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https://github.com/chipsec/chipsec
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CHIPSEC
ac2ca7264f
UEFI shell. 2. Decompression of images in SPI flash parsing is only supported in Windows. 3. UEFI - Support for IA32 and i586 (Quark) 4. Added capability to use modules from an arbitrary path with the -I / --import command line option 5. Module functionality encapsulated in class inheriting BaseModule 6. Fixed loading platform specific configuration 7. Fixed issue with modules which run on multiple logical CPUs hanging on Bay Trail (Windows/Linux). The issue still exist when running from UEFI shell 8. Added template for a module - module_template.py 9. Added options to flush log files 10. Added ability to define custom platforms Driver changes: 1. Windows - Added IOCTL_ALLOC_PHYSMEM to allocate physical memory buffer 2. Linux - Fix wrpci defect
103 lines
3.1 KiB
Python
103 lines
3.1 KiB
Python
#!/usr/local/bin/python
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#CHIPSEC: Platform Security Assessment Framework
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#Copyright (c) 2010-2014, Intel Corporation
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#
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#This program is free software; you can redistribute it and/or
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#modify it under the terms of the GNU General Public License
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#as published by the Free Software Foundation; Version 2.
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#
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#This program is distributed in the hope that it will be useful,
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#but WITHOUT ANY WARRANTY; without even the implied warranty of
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#MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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#GNU General Public License for more details.
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#
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#You should have received a copy of the GNU General Public License
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#along with this program; if not, write to the Free Software
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#Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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#
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#Contact information:
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#chipsec@intel.com
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#
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#
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# usage as a standalone utility:
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#
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## \addtogroup standalone
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#chipsec_util msr
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#-----
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#~~~
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#chipsec_util msr <msr> [eax] [edx] [cpu_id]
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#''
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# Examples:
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#''
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# chipsec_util msr 0x3A
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# chipsec_util msr 0x8B 0x0 0x0 0
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#~~~
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__version__ = '1.0'
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import os
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import sys
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import time
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import chipsec_util
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from chipsec_util import chipsec_util_commands, _cs
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from chipsec.logger import *
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from chipsec.file import *
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from chipsec.hal.msr import Msr
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#_cs = cs()
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usage = "chipsec_util msr <msr> [eax] [edx] [cpu_id]\n" + \
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"Examples:\n" + \
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" chipsec_util msr 0x3A\n" + \
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" chipsec_util msr 0x8B 0x0 0x0 0\n\n"
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chipsec_util.global_usage += usage
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# ###################################################################
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#
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# CPU Model Specific Registers
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#
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# ###################################################################
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def msr(argv):
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if 3 > len(argv):
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print usage
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return
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#msr = Msr( os_helper )
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msr_addr = int(argv[2],16)
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if (3 == len(argv)):
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for tid in range(_cs.msr.get_cpu_thread_count()):
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(eax, edx) = _cs.msr.read_msr( tid, msr_addr )
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val64 = ((edx << 32) | eax)
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logger().log( "[CHIPSEC] CPU%d: RDMSR( 0x%x ) = %016X (EAX=%08X, EDX=%08X)" % (tid, msr_addr, val64, eax, edx) )
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elif (4 == len(argv)):
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cpu_thread_id = int(argv[3], 16)
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(eax, edx) = _cs.msr.read_msr( cpu_thread_id, msr_addr )
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val64 = ((edx << 32) | eax)
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logger().log( "[CHIPSEC] CPU%d: RDMSR( 0x%x ) = %016X (EAX=%08X, EDX=%08X)" % (cpu_thread_id, msr_addr, val64, eax, edx) )
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else:
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eax = int(argv[3], 16)
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edx = int(argv[4], 16)
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val64 = ((edx << 32) | eax)
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if (5 == len(argv)):
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logger().log( "[CHIPSEC] All CPUs: WRMSR( 0x%x ) = %016X" % (msr_addr, val64) )
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for tid in range(_cs.msr.get_cpu_thread_count()):
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_cs.msr.write_msr( tid, msr_addr, eax, edx )
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elif (6 == len(argv)):
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cpu_thread_id = int(argv[5], 16)
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logger().log( "[CHIPSEC] CPU%d: WRMSR( 0x%x ) = %016X" % (cpu_thread_id, msr_addr, val64) )
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_cs.msr.write_msr( cpu_thread_id, msr_addr, eax, edx )
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chipsec_util_commands['msr'] = {'func' : msr , 'start_driver' : True }
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