mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
brentholtsclaw
f7fe1be074
E231, E201, E226 Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
78 lines
3.5 KiB
Python
78 lines
3.5 KiB
Python
#CHIPSEC: Platform Security Assessment Framework
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#Copyright (c) 2010-2020, Intel Corporation
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#
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#This program is free software; you can redistribute it and/or
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#modify it under the terms of the GNU General Public License
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#as published by the Free Software Foundation; Version 2.
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#
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#This program is distributed in the hope that it will be useful,
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#but WITHOUT ANY WARRANTY; without even the implied warranty of
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#MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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#GNU General Public License for more details.
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#
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#You should have received a copy of the GNU General Public License
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#along with this program; if not, write to the Free Software
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#Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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#
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#Contact information:
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#chipsec@intel.com
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#
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"""
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In 2006, `Security Issues Related to Pentium System Management Mode <http://www.ssi.gouv.fr/archive/fr/sciences/fichiers/lti/cansecwest2006-duflot.pdf>`_ outlined a configuration issue where compatibility SMRAM was not locked on some platforms. This means that ring 0 software was able to modify System Management Mode (SMM) code and data that should have been protected.
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In Compatability SMRAM (CSEG), access to memory is defined by the SMRAMC register. When SMRAMC[D_LCK] is not set by the BIOS, SMRAM can be accessed even when the CPU is not in SMM. Such attacks were also described in `Using CPU SMM to Circumvent OS Security Functions <http://fawlty.cs.usfca.edu/~cruse/cs630f06/duflot.pdf>`_ and `Using SMM for Other Purposes <http://phrack.org/issues/65/7.html>`_.
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This CHIPSEC module simply reads SMRAMC and checks that D_LCK is set.
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"""
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from collections import namedtuple
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from chipsec.module_common import BaseModule, ModuleResult, MTAG_BIOS, MTAG_SMM
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TAGS = [MTAG_BIOS, MTAG_SMM]
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class smm(BaseModule):
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def __init__(self):
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BaseModule.__init__(self)
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def is_supported(self):
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if self.cs.is_core() and self.cs.is_register_defined('PCI0.0.0_SMRAMC'):
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return True
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self.res = ModuleResult.NOTAPPLICABLE
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return False
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def check_SMRAMC(self):
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self.logger.start_test( "Compatible SMM memory (SMRAM) Protection" )
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regval = self.cs.read_register( 'PCI0.0.0_SMRAMC' )
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g_smrame = self.cs.get_register_field( 'PCI0.0.0_SMRAMC', regval, 'G_SMRAME' )
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d_open = self.cs.get_register_field( 'PCI0.0.0_SMRAMC', regval, 'D_OPEN' )
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d_lock = self.cs.get_register_field( 'PCI0.0.0_SMRAMC', regval, 'D_LCK' )
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self.cs.print_register( 'PCI0.0.0_SMRAMC', regval )
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if 1 == g_smrame:
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self.logger.log( "[*] Compatible SMRAM is enabled" )
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# When D_LCK is set HW clears D_OPEN so generally no need to check for D_OPEN but doesn't hurt double checking
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if 1 == d_lock and 0 == d_open:
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res = ModuleResult.PASSED
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self.logger.log_passed_check( "Compatible SMRAM is locked down" )
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else:
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res = ModuleResult.FAILED
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self.logger.log_failed_check( "Compatible SMRAM is not properly locked. Expected ( D_LCK = 1, D_OPEN = 0 )" )
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else:
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res = ModuleResult.SKIPPED
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self.logger.log( "[*] Compatible SMRAM is not enabled. Skipping.." )
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return res
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# --------------------------------------------------------------------------
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# run( module_argv )
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# Required function: run here all tests from this module
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# --------------------------------------------------------------------------
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def run( self, module_argv ):
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return self.check_SMRAMC()
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