mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
d9a8265fc5
Signed-off-by: Sara Batllori <sara.batllori@intel.com>
129 lines
4.6 KiB
Python
129 lines
4.6 KiB
Python
# CHIPSEC: Platform Security Assessment Framework
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# Copyright (c) 2010-2020, Intel Corporation
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; Version 2.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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#
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# Contact information:
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# chipsec@intel.com
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#
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"""
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This module verifies memory map secure configuration,
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that memory map registers are correctly configured and locked down.
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Usage:
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``chipsec_main -m common.memconfig``
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Example:
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>>> chipsec_main.py -m common.memconfig
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.. note::
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- This module will only run on Core (client) platforms.
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"""
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from chipsec.module_common import BaseModule, HWCONFIG
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from chipsec.library.returncode import ModuleResult
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from typing import List
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_MODULE_NAME = 'memconfig'
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TAGS = [HWCONFIG]
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METADATA_TAGS = ['OPENSOURCE', 'IA', 'COMMON', 'MEMCONFIG']
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class memconfig(BaseModule):
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def __init__(self):
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BaseModule.__init__(self)
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self.memmap_registers = {
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"8086.HOSTCTL.GGC": 'GGCLOCK',
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"8086.HOSTCTL.PAVPC": 'PAVPLCK',
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"8086.HOSTCTL.DPR": 'LOCK',
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"8086.HOSTCTL.MESEG_MASK": 'MELCK',
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"8086.HOSTCTL.REMAPBASE": 'LOCK',
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"8086.HOSTCTL.REMAPLIMIT": 'LOCK',
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"8086.HOSTCTL.TOM": 'LOCK',
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"8086.HOSTCTL.TOUUD": 'LOCK',
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"8086.HOSTCTL.BDSM": 'LOCK',
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"8086.HOSTCTL.BGSM": 'LOCK',
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"8086.HOSTCTL.TSEGMB": 'LOCK',
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"8086.HOSTCTL.TOLUD": 'LOCK'
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}
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self.cs.set_scope({
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"MSR_BIOS_DONE": "8086.MSR",
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})
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def is_supported(self) -> bool:
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if self.cs.is_intel():
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if self.cs.is_core():
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return True
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self.logger.log_important("Not a 'Core' (Desktop) platform. Skipping test.")
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else:
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self.logger.log_important('Not an Intel platform. Skipping test.')
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return False
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def check_memmap_locks(self) -> int:
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ia_untrusted = None
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if self.cs.register.has_field('MSR_BIOS_DONE', 'IA_UNTRUSTED'):
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bios_done = self.cs.register.get_list_by_name('MSR_BIOS_DONE')
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ia_untrusted = bios_done.read_field('IA_UNTRUSTED')
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regs = sorted(self.memmap_registers.keys())
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all_locked = True
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self.logger.log('[*]')
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if ia_untrusted is not None:
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self.logger.log('[*] Checking legacy register lock state:')
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else:
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self.logger.log('[*] Checking register lock state:')
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for reg in regs:
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if not self.cs.register.has_field(reg, self.memmap_registers[reg]):
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self.logger.log_important(f'{reg}.{self.memmap_registers[reg]} not defined for platform. Skipping register.')
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continue
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reglist = self.cs.register.get_list_by_name(reg)
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description = reglist[0].desc
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reglist.read_and_verbose_print()
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if reglist.is_all_field_value(1, self.memmap_registers[reg]):
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self.logger.log_good(f'{reg:20} - LOCKED - {description}')
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else:
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all_locked = False
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self.logger.log_bad(f'{reg:20} - UNLOCKED - {description}')
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if ia_untrusted is not None:
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self.logger.log('[*]')
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self.logger.log('[*] Checking if IA Untrusted mode is used to lock registers')
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if all(data == 1 for data in ia_untrusted):
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self.logger.log_good('IA Untrusted mode set')
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all_locked = True
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else:
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self.logger.log_bad('IA Untrusted mode not set')
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self.logger.log('[*]')
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if all_locked:
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res = ModuleResult.PASSED
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self.logger.log_passed('All memory map registers seem to be locked down')
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else:
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res = ModuleResult.FAILED
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self.logger.log_failed('Not all memory map registers are locked down')
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self.result.setStatusBit(self.result.status.LOCKS)
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return res
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def run(self, module_argv: List[str]) -> int:
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self.logger.start_test('Host Bridge Memory Map Locks')
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self.res = self.check_memmap_locks()
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return self.result.getReturnCode(self.res)
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