mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
Nathaniel Mitchell
230 lines
8.8 KiB
Python
230 lines
8.8 KiB
Python
# CHIPSEC: Platform Security Assessment Framework
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# Copyright (c) 2010-2021, Intel Corporation
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; Version 2.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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#
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# Contact information:
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# chipsec@intel.com
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#
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"""
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Access to message bus (IOSF sideband) interface registers on Intel SoCs
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References:
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- Intel(R) Atom(TM) Processor D2000 and N2000 Series Datasheet, Volume 2, July 2012, Revision 003
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http://www.intel.com/content/dam/doc/datasheet/atom-d2000-n2000-vol-2-datasheet.pdf (section 1.10.2)
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usage:
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>>> msgbus_reg_read( port, register )
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>>> msgbus_reg_write( port, register, data )
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>>> msgbus_read_message( port, register, opcode )
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>>> msgbus_write_message( port, register, opcode, data )
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>>> msgbus_send_message( port, register, opcode, data )
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"""
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from chipsec.hal import hal_base
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from chipsec.exceptions import RegisterNotFoundError
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#
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# IOSF Message bus message opcodes
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# Reference: http://lxr.free-electrons.com/source/arch/x86/include/asm/iosf_mbi.h
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#
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class MessageBusOpcode:
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MB_OPCODE_MMIO_READ = 0x00
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MB_OPCODE_MMIO_WRITE = 0x01
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MB_OPCODE_IO_READ = 0x02
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MB_OPCODE_IO_WRITE = 0x03
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MB_OPCODE_CFG_READ = 0x04
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MB_OPCODE_CFG_WRITE = 0x05
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MB_OPCODE_CR_READ = 0x06
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MB_OPCODE_CR_WRITE = 0x07
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MB_OPCODE_REG_READ = 0x10
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MB_OPCODE_REG_WRITE = 0x11
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MB_OPCODE_ESRAM_READ = 0x12
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MB_OPCODE_ESRAM_WRITE = 0x13
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#
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# IOSF Message bus unit ports
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# Reference: http://lxr.free-electrons.com/source/arch/x86/include/asm/iosf_mbi.h
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# @TODO: move these to per-platform XML config?
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#
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class MessageBusPort_Atom:
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UNIT_AUNIT = 0x00
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UNIT_SMC = 0x01
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UNIT_CPU = 0x02
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UNIT_BUNIT = 0x03
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UNIT_PMC = 0x04
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UNIT_GFX = 0x06
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UNIT_SMI = 0x0C
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UNIT_USB = 0x43
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UNIT_SATA = 0xA3
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UNIT_PCIE = 0xA6
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class MessageBusPort_Quark:
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UNIT_HBA = 0x00
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UNIT_HB = 0x03
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UNIT_RMU = 0x04
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UNIT_MM = 0x05
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UNIT_SOC = 0x31
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class MsgBus(hal_base.HALBase):
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def __init__(self, cs):
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super(MsgBus, self).__init__(cs)
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self.helper = cs.helper
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self.p2sbHide = None
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def __MB_MESSAGE_MCR(self, port, reg, opcode):
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mcr = 0x0
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mcr = self.cs.set_register_field('MSG_CTRL_REG', mcr, 'MESSAGE_WR_BYTE_ENABLES', 0xF)
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mcr = self.cs.set_register_field('MSG_CTRL_REG', mcr, 'MESSAGE_ADDRESS_OFFSET', reg)
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mcr = self.cs.set_register_field('MSG_CTRL_REG', mcr, 'MESSAGE_PORT', port)
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mcr = self.cs.set_register_field('MSG_CTRL_REG', mcr, 'MESSAGE_OPCODE', opcode)
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return mcr
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def __MB_MESSAGE_MCRX(self, reg):
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mcrx = 0x0
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mcrx = self.cs.set_register_field('MSG_CTRL_REG_EXT', mcrx, 'MESSAGE_ADDRESS_OFFSET_EXT', (reg >> 8), preserve_field_position=True)
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return mcrx
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def __MB_MESSAGE_MDR(self, data):
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mdr = 0x0
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mdr = self.cs.set_register_field('MSG_DATA_REG', mdr, 'MESSAGE_DATA', data)
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return mdr
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def __hide_p2sb(self, hide):
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if not self.p2sbHide:
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if self.cs.register_has_field("P2SBC", "HIDE"):
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self.p2sbHide = {'reg': 'P2SBC', 'field': 'HIDE'}
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elif self.cs.register_has_field("P2SB_HIDE", "HIDE"):
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self.p2sbHide = {'reg': 'P2SB_HIDE', 'field': 'HIDE'}
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else:
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raise RegisterNotFoundError('RegisterNotFound: P2SBC')
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hidden = not self.cs.is_device_enabled('P2SBC')
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if hide:
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self.cs.write_register_field(self.p2sbHide['reg'], self.p2sbHide['field'], 1)
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else:
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self.cs.write_register_field(self.p2sbHide['reg'], self.p2sbHide['field'], 0)
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return hidden
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#
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# Issues read message on the message bus
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#
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def msgbus_read_message(self, port, register, opcode):
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mcr = self.__MB_MESSAGE_MCR(port, register, opcode)
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mcrx = self.__MB_MESSAGE_MCRX(register)
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if self.logger.HAL:
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self.logger.log("[msgbus] read: port 0x{:02X} + 0x{:08X} (op = 0x{:02X})".format(port, register, opcode))
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self.logger.log("[msgbus] MCR = 0x{:08X}, MCRX = 0x{:08X}".format(mcr, mcrx))
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mdr_out = self.helper.msgbus_send_read_message(mcr, mcrx)
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if self.logger.HAL:
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self.logger.log("[msgbus] < 0x{:08X}".format(mdr_out))
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return mdr_out
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#
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# Issues write message on the message bus
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#
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def msgbus_write_message(self, port, register, opcode, data):
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mcr = self.__MB_MESSAGE_MCR(port, register, opcode)
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mcrx = self.__MB_MESSAGE_MCRX(register)
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mdr = self.__MB_MESSAGE_MDR(data)
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if self.logger.HAL:
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self.logger.log("[msgbus] write: port 0x{:02X} + 0x{:08X} (op = 0x{:02X}) < data = 0x{:08X}".format(port, register, opcode, data))
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self.logger.log("[msgbus] MCR = 0x{:08X}, MCRX = 0x{:08X}, MDR = 0x{:08X}".format(mcr, mcrx, mdr))
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return self.helper.msgbus_send_write_message(mcr, mcrx, mdr)
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#
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# Issues generic message on the message bus
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#
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def msgbus_send_message(self, port, register, opcode, data=None):
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mcr = self.__MB_MESSAGE_MCR(port, register, opcode)
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mcrx = self.__MB_MESSAGE_MCRX(register)
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mdr = None if data is None else self.__MB_MESSAGE_MDR(data)
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if self.logger.HAL:
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self.logger.log("[msgbus] message: port 0x{:02X} + 0x{:08X} (op = 0x{:02X})".format(port, register, opcode))
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if data is not None:
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self.logger.log("[msgbus] data = 0x{:08X}".format(data))
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self.logger.log("[msgbus] MCR = 0x{:08X}, MCRX = 0x{:08X}, MDR = 0x{:08X}".format(mcr, mcrx, mdr))
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mdr_out = self.helper.msgbus_send_message(mcr, mcrx, mdr)
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if self.logger.HAL:
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self.logger.log("[msgbus] < 0x{:08X}".format(mdr_out))
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return mdr_out
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#
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# Message bus register read/write
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#
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def msgbus_reg_read(self, port, register):
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return self.msgbus_read_message(port, register, MessageBusOpcode.MB_OPCODE_REG_READ)
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def msgbus_reg_write(self, port, register, data):
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return self.msgbus_write_message(port, register, MessageBusOpcode.MB_OPCODE_REG_WRITE, data)
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def mm_msgbus_reg_read(self, port, register):
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was_hidden = False
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if self.cs.is_register_defined('P2SBC'):
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was_hidden = self.__hide_p2sb(False)
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mmio_addr = self.cs.mmio.get_MMIO_BAR_base_address('SBREGBAR')[0]
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reg_val = self.cs.mmio.read_MMIO_reg_dword(mmio_addr, ((port & 0xFF) << 16) | (register & 0xFFFF))
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if self.cs.is_register_defined('P2SBC') and was_hidden:
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self.__hide_p2sb(True)
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return reg_val
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def mm_msgbus_reg_write(self, port, register, data):
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was_hidden = False
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if self.cs.is_register_defined('P2SBC'):
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was_hidden = self.__hide_p2sb(False)
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mmio_addr = self.cs.mmio.get_MMIO_BAR_base_address('SBREGBAR')[0]
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reg_val = self.cs.mmio.write_MMIO_reg_dword(mmio_addr, ((port & 0xFF) << 16) | (register & 0xFFFF), data)
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if self.cs.is_register_defined('P2SBC') and was_hidden:
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self.__hide_p2sb(True)
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return reg_val
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"""
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# py implementation of msgbus -- doesn't seem to work properly becaise it's not atomic
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def msgbus_send_message( self, port, register, opcode, data=None ):
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if self.logger.HAL:
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self.logger.log( "[msgbus] message - port: 0x{:02X}, reg: 0x{:08X} (op: 0x{:02X})".format(port, register, opcode) )
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if data is not None: self.logger.log( "[msgbus] message - data: 0x{:08X}".format(data) )
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if (register & 0xFFFFFF00):
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# write extended register address (bits [31:08]) to Message Control Register Extension (MCRX)
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chipsec.chipset.write_register_field( self.cs, 'MSG_CTRL_REG_EXT', 'MESSAGE_ADDRESS_OFFSET_EXT', register, preserve_field_position=True )
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res = None
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# write data to Message Data Register (MDR) for writes
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if data is not None: chipsec.chipset.write_register( self.cs, 'MSG_DATA_REG', data )
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# write message (byte enables, address bits [08:00], port and opcode) to Message Control Register (MCR)
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chipsec.chipset.write_register( self.cs, 'MSG_CTRL_REG', MB_MESSAGE(self.cs, port, register, opcode) )
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# read the data from Message Data Register (MDR) for reads
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if data is None: res = chipsec.chipset.read_register( self.cs, 'MSG_DATA_REG' )
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return res
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"""
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