mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
8137240092
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
182 lines
6.0 KiB
Python
182 lines
6.0 KiB
Python
# CHIPSEC: Platform Security Assessment Framework
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; Version 2.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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#
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#
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import os
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import tempfile
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import unittest
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from tests.software import mock_helper
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from chipsec.library import logger
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from chipsec import chipset
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class TestChipsecCs(unittest.TestCase):
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"""Test the commands exposed by chipsec_utils.
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Each test may define its virtual helper and then call the _chipsec_util
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method with the command line arguments.
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"""
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def setUp(self):
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"""Setup the environment for the utils tests.
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We mock the helper registry to only contain our emulated helper.
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"""
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fileno, self.log_file = tempfile.mkstemp()
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os.close(fileno)
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chipset._chipset = None
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def tearDown(self):
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os.remove(self.log_file)
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chipset._chipset = None
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def _chipsec_cs(self, arg, helper_class=mock_helper.TestHelper, platform=None, pch=None):
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"""Run the chipsec chipset commands
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Each test may setup a virtual helper to emulate the expected behaviour
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from the hardware. If no helper is provided, TestHelper will be used.
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It verifies that no error is being reported. self.log will be populated
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with the output.
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"""
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_cs = chipset.cs()
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logger.logger().HAL = True
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logger.logger().VERBOSE = True
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logger.logger().set_log_file(self.log_file)
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try:
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_cs.init(platform, pch, helper_class())
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ret = getattr(_cs.Cfg, arg.split()[0])()
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finally:
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logger.logger().close()
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with open(self.log_file, 'rb') as log:
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self.log = log.read()
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return ret
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from chipsec.library.register import RegisterType
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class DummyCS:
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class DummyCfg:
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REGISTERS = {
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'TEST_MSR': {
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'type': RegisterType.MSR,
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'msr': 0x123,
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'size': 4,
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'desc': "Test MSR Register",
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'FIELDS': {
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'FIELD1': {'bit': 0, 'size': 8, 'desc': "Test Field 1"},
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}
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},
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'TEST_PCI': {
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'type': RegisterType.PCICFG,
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'device': 'DEV1',
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'dev': 1,
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'fun': 0,
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'offset': 0x10,
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'size': 4,
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'desc': "Test PCI Register",
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'FIELDS': {
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'FIELD2': {'bit': 8, 'size': 8, 'desc': "Test PCI Field 2"}
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}
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},
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'TEST_MMIO': {
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'type': RegisterType.MMIO,
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'bar': 'TEST_MMIO_BAR',
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'offset': 0x20,
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'size': 4,
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'desc': "Test MMIO Register",
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'FIELDS': {
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'FIELD3': {'bit': 16, 'size': 8, 'desc': "Test MMIO Field 3"}
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}
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},
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'TEST_BAD_MMIO': {
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'type': RegisterType.MMIO,
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'bar': 'BAD',
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'offset': 0x20,
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'size': 4,
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'desc': "Test MMIO Register",
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'FIELDS': {
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'FIELD3': {'bit': 16, 'size': 8, 'desc': "Test MMIO Field 3"}
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}
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}
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}
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MMIO_BARS = {
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'TEST_MMIO_BAR': {
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'device': 'DEV1',
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'bar': 0,
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'desc': "Test MMIO BAR"
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}
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}
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CONFIG_PCI = {
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'DEV1': {'dev': 1, 'fun': 0}
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}
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MEMORY_RANGES = {}
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IMA_REGISTERS = {}
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class DummyDevice:
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def get_bus(self, device): return [0]
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def get_first_bus(self, reg): return 0
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def get_first(self, bus): return bus
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class DummyMMIO:
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def get_MMIO_BAR_base_address(self, bar, bus=None): return (0,) if bar == "BAD" else (1, )
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def read_MMIO_BAR_reg(self, bar, offset, size, bus): return 0xDEADBEEF
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def read_MMIO_reg(self, address, offset, size): return 0xBEEF
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def read_mmcfg_reg(self, b, d, f, o, size): return 0xFEED
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def write_MMIO_BAR_reg(self, bar, offset, value, size, bus): pass
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def write_MMIO_reg(self, address, offset, value, size): pass
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def write_mmcfg_reg(self, b, d, f, o, size, value): pass
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class DummyMSR:
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def read_msr(self, cpu_thread, msr): return (0xABCD, 0x1234)
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def write_msr(self, cpu_thread, msr, eax, edx): pass
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class DummyIO:
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def _read_port(self, port, size): return 0xFF
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def _write_port(self, port, value, size): pass
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class DummyIOBAR:
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def get_IO_BAR_base_address(self, bar): return (1, )
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def read_IO_BAR_reg(self, bar, offset, size): return 0xCAFE
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def write_IO_BAR_reg(self, bar, offset, size, value): pass
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class DummyMsgBus:
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def msgbus_reg_read(self, port, offset): return 0xAABB
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def mm_msgbus_reg_read(self, port, offset): return 0xCCDD
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def msgbus_reg_write(self, port, offset, value): pass
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def mm_msgbus_reg_write(self, port, offset, value): pass
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class DummyMem:
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def write_physical_mem(self, address, size, value): pass
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class DummyCPU:
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def get_cpu_topology(self):
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return {'packages': {0: [0]}, 'cores': {0: [0]}}
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class DummyHelper:
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def get_threads_count(self): return 1
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def __init__(self):
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self.Cfg = self.DummyCfg()
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self.device = self.DummyDevice()
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self.mmio = self.DummyMMIO()
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self.msr = self.DummyMSR()
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self.io = self.DummyIO()
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self.iobar = self.DummyIOBAR()
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self.msgbus = self.DummyMsgBus()
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self.mem = self.DummyMem()
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self.cpu = self.DummyCPU()
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self.helper = self.DummyHelper()
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self.consistency_checking = False |