From e1bee9f8e8d15fd9e8252e4aac2edfe57d5ca2fc Mon Sep 17 00:00:00 2001
From: Clement Rouault <clement.rouault@sogeti.com>
Date: Fri, 26 Jun 2015 11:08:53 +0200
Subject: [PATCH] Commit simple_x86 before full rewriting

---
 native_exec/simple_x64.py | 29 ++++++++++++++++++++---------
 native_exec/simple_x86.py | 27 +++++++++++++++++++++------
 2 files changed, 41 insertions(+), 15 deletions(-)

diff --git a/native_exec/simple_x64.py b/native_exec/simple_x64.py
index f970e6e..7199bed 100644
--- a/native_exec/simple_x64.py
+++ b/native_exec/simple_x64.py
@@ -3,7 +3,8 @@
 
 import struct
 import sys
-from simple_x86 import MultipleInstr
+import codecs
+from .simple_x86 import MultipleInstr
 
 # This code should really be rewritten..
 
@@ -11,6 +12,8 @@ this_module = sys.modules[__name__]
    
 generated_instruction = []
 
+long = int
+
 def add_instruction(name, instruction):
     generated_instruction.append((name, instruction))
     setattr(this_module, name, instruction)
@@ -22,6 +25,12 @@ def generate_module_doc():
         
     this_module.__doc__ = "\n".join(doc_lines)
     
+def decode_hex(s):
+    return codecs.decode(s.encode(), "hex").decode()
+ 
+def encode_hex(s):
+    return codecs.encode(s.encode(), "hex").decode()
+    
 reg_order = ['EAX', 'ECX', 'EDX', 'EBX', 'ESP', 'EBP', 'ESI', 'EDI']
 reg_opcode = {v : format(i, "03b") for i, v in enumerate(reg_order)}    
     
@@ -52,12 +61,14 @@ class X64Instruction(object):
                 raise ValueError("{0} bindings must be between 0 and 0xffffffffffffffff".format(self.__class__.__name__))
                 
     def get_unbinded_code(self):
-        return self.code.replace(" ", "").decode('hex')
+        return decode_hex(self.code.replace(" ", ""))
         
     def get_code(self):
         code = self.get_unbinded_code()
         for i in range(self.biding):
-            code = code.replace((str(i + 1) * 16).decode('hex'), struct.pack("<Q", self.bind_values[i]))
+            to_search = codecs.decode(str(i + 1) * 16, 'hex')
+            import pdb;pdb.set_trace()
+            code = code.replace(to_search, struct.pack("<Q", self.bind_values[i]))
         return code
         
     def get_mnemo(self):
@@ -151,7 +162,7 @@ def generate_reg_instruction_onebind(instr_cls):
     for reg_name, reg_bits in reg_opcode.items():
         class OneBindRegInstruction(OneBindX64Instruction):
             mnemo = instr_cls.mnemo.format(reg_name)
-            code = chr(int(instr_cls.instruction_bits + reg_bits, 2)).encode('hex')  + '11 11 11 11 11 11 11 11' # the biding
+            code = encode_hex(chr(int(instr_cls.instruction_bits + reg_bits, 2)))  + '11 11 11 11 11 11 11 11' # the biding
             if instr_cls.prefix_bin_h48:
                 code = "48" + code
         OneBindRegInstruction.__name__ = instr_cls.name.format(reg_name)
@@ -168,12 +179,12 @@ generate_reg_instruction_onebind(Mov_Reg_X)
 def get_immediat_modr_byte(register_bits):
     "Generate a modr-reg-r/m indicating a register and an immediat"
     str_bits = "11000{0}".format(register_bits)
-    return chr(int(str_bits, 2)).encode('hex')
+    return encode_hex(chr(int(str_bits, 2)))
   
 def get_simple_modr_byte(register_bits):
     "Generate a simple modr-reg-r/m for a displacement only mode"
     str_bits = "00{0}101".format(register_bits)
-    return chr(int(str_bits, 2)).encode('hex')
+    return encode_hex(chr(int(str_bits, 2)))
  
 
 #def generate_reg_indirect_modr_byte(reg_dst_bits, reg_src_bits):
@@ -204,9 +215,9 @@ def get_simple_modr_byte(register_bits):
 def generate_reg_indirect_modr_byte(reg_dst_bits, reg_src_bits, deref_first):
     # reg, [reg] or [reg], reg
     if deref_first:
-        return chr(int("00{0}{1}".format(reg_dst_bits, reg_src_bits), 2)).encode('hex')
+        return encode_hex(chr(int("00{0}{1}".format(reg_dst_bits, reg_src_bits), 2)))
     else:
-        return chr(int("00{0}{1}".format(reg_src_bits, reg_dst_bits), 2)).encode('hex')
+        return encode_hex(chr(int("00{0}{1}".format(reg_src_bits, reg_dst_bits), 2)))
     
 def generate_reg_reg_deref():
     for reg1_name, reg1_bits in all_regs.items():
@@ -216,7 +227,7 @@ def generate_reg_reg_deref():
             is_reg1_new = reg1_name in new_reg_opcode
             is_reg2_new = reg2_name in new_reg_opcode
             
-            first_byte = chr(int("1001{0}0{1}".format(int(is_reg1_new), int(is_reg2_new)), 2)).encode('hex')
+            first_byte = encode_hex(chr(int("1001{0}0{1}".format(int(is_reg1_new), int(is_reg2_new)), 2)))
             
             class DReg_Reg_instruction(X64Instruction):
                 mnemo = "mov [{0}], {1}".format(reg1_name, reg2_name)
diff --git a/native_exec/simple_x86.py b/native_exec/simple_x86.py
index 2871fda..70f9761 100644
--- a/native_exec/simple_x86.py
+++ b/native_exec/simple_x86.py
@@ -1,11 +1,14 @@
 import struct
 import sys
+import codecs
 # This code should really be rewritten..
 
 this_module = sys.modules[__name__]
 
 generated_instruction = []
 
+long = int
+
 
 def add_instruction(name, instruction):
     generated_instruction.append((name, instruction))
@@ -18,6 +21,12 @@ def generate_module_doc():
         
     this_module.__doc__ = "\n".join(doc_lines)
     
+def decode_hex(s):
+    return codecs.decode(s.encode(), "hex").decode()
+ 
+def encode_hex(s):
+    return codecs.encode(s.encode(), "hex").decode()
+    
 reg_order = ['EAX', 'ECX', 'EDX', 'EBX', 'ESP', 'EBP', 'ESI', 'EDI']
 reg_opcode = {v : format(i, "03b") for i, v in enumerate(reg_order)}
 
@@ -38,12 +47,14 @@ class X86Instruction(object):
                 raise ValueError("{0} bindings must be between 0 and 0xffffffff".format(self.__class__.__name__))
                 
     def get_unbinded_code(self):
-        return self.code.replace(" ", "").decode('hex')
+        print(self.code)
+        return codecs.decode(self.code.replace(" ", ""), 'hex')
         
     def get_code(self):
         code = self.get_unbinded_code()
         for i in range(self.biding):
-            code = code.replace((str(i + 1) * 8).decode('hex'), struct.pack("<I", self.bind_values[i]))
+            to_search = codecs.decode(str(i + 1) * 8, 'hex')
+            code = code.replace(to_search, struct.pack("<I", self.bind_values[i]))
         return code
         
     def get_mnemo(self):
@@ -114,7 +125,11 @@ def generate_reg_instruction_onebind(instr_cls):
     for reg_name, reg_bits in reg_opcode.items():
         class OneBindRegInstruction(OneBindX86Instruction):
             mnemo = instr_cls.mnemo.format(reg_name)
-            code = chr(int(instr_cls.instruction_bits + reg_bits, 2)).encode('hex')  + '11 11 11 11' # the biding
+            
+            i = int(instr_cls.instruction_bits + reg_bits, 2)
+            code = bytes([i]) + b'11 11 11 11' # the biding
+            #import pdb;pdb.set_trace()
+            #code = encode_hex(chr(int(instr_cls.instruction_bits + reg_bits, 2)))  + b'11 11 11 11' # the biding
             
         OneBindRegInstruction.__name__ = instr_cls.name.format(reg_name)
         add_instruction(OneBindRegInstruction.__name__, OneBindRegInstruction)
@@ -129,7 +144,7 @@ generate_reg_instruction_onebind(Mov_Reg_X)
 def get_immediat_modr_byte(register_bits):
     "Generate a modr-reg-r/m indicating a register and an immediat"
     str_bits = "11000{0}".format(register_bits)
-    return chr(int(str_bits, 2)).encode('hex')
+    return encode_hex(chr(int(str_bits, 2)))
     
 def generate_reg_immediat_modr(instr_cls):
     for reg_name, reg_bits in reg_opcode.items():
@@ -151,7 +166,7 @@ generate_reg_immediat_modr(Add_Reg_X)
 def get_simple_modr_byte(register_bits):
     "Generate a simple modr-reg-r/m for a displacement only mode"
     str_bits = "00{0}101".format(register_bits)
-    return chr(int(str_bits, 2)).encode('hex')
+    return encode_hex(chr(int(str_bits, 2)))
 
 
 def generate_reg_modr(instr_cls):
@@ -198,7 +213,7 @@ def generate_reg_reg_deref(instr_cls, src_first=True):
                     modr_code = generate_reg_indirect_modr_byte(reg_src_bits, reg_dst_bits)
                 else:
                     modr_code = generate_reg_indirect_modr_byte(reg_dst_bits, reg_src_bits)
-                code = instr_cls.instruction_bits + chr(int(modr_code, 2)).encode("hex")
+                code = encode_hex(instr_cls.instruction_bits + chr(int(modr_code, 2)))
             Reg_DReg_instruction.__name__ = Reg_DReg_instruction.name
             add_instruction(Reg_DReg_instruction.__name__, Reg_DReg_instruction)