# RV64D  Standard Extension (in addition to RV32D)

# fcvt.d.l D,s,m d2200053 fff0007f SIMPLE (64, 0) 
:fcvt.d.l frd,rs1L,FRM is frd & FRM & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x69 & op2024=0x2
{
	local tmp:8 = int2float(rs1L);
	frd = tmp;
}


# fcvt.d.lu D,s,m d2300053 fff0007f SIMPLE (64, 0) 
:fcvt.d.lu frd,rs1L,FRM is frd & FRM & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x69 & op2024=0x3
{
	#ATTN  unsigned can be an issue here
	local u64:$(XLEN2) = zext(rs1L);
	local tmp:8 = int2float(u64);
	frd = tmp;
}


# fcvt.l.d d,S,m c2200053 fff0007f SIMPLE (64, 0) 
:fcvt.l.d rdL,frs1D,FRM is frs1D & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x2
{
	rdL = trunc(frs1D);
}


# fcvt.lu.d d,S,m c2300053 fff0007f SIMPLE (64, 0) 
:fcvt.lu.d rdL,frs1D,FRM is frs1D & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x3
{
	#TODO  unsigned
	rdL = trunc(frs1D);
}


# fmv.d.x D,s f2000053 fff0707f SIMPLE (64, 0) 
:fmv.d.x frd,rs1L is frd & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x79 & op2024=0x0
{
	frd = rs1L;
}

:fmv.x.d rdL,frs1D is frs1D & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x71 & op2024=0x0
{
	local tmpreg:4 = &frs1D;
	local tmp:8 = *[register]:8 tmpreg;
	rdL = tmp;
}
