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Update the Ghidra processors

Browse Source 
https://github.com/icicle-emu/ghidra/commit/50230050fa58bd40d5a96cab9c167fc55bc92a76
This commit is contained in:
Duncan Ogilvie
2023-10-20 17:50:33 +02:00
parent f1e1245459
commit 21be341c59
608 changed files with 259459 additions and 255126 deletions
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python/icicle/Ghidra/Processors/6502/data/languages/6502.cspec
+34 -34
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@@ -1,34 +1,34 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<global>
<range space="RAM"/>
</global>
<stackpointer register="SP" space="RAM" growth="negative"/>
<returnaddress>
<varnode space="stack" offset="1" size="2"/>
</returnaddress>
<default_proto>
<prototype name="__stdcall" extrapop="2" stackshift="2" strategy="register">
<input>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="X"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="Y"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
</unaffected>
</prototype>
</default_proto>
</compiler_spec>
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<global>
<range space="RAM"/>
</global>
<stackpointer register="SP" space="RAM" growth="negative"/>
<returnaddress>
<varnode space="stack" offset="1" size="2"/>
</returnaddress>
<default_proto>
<prototype name="__stdcall" extrapop="2" stackshift="2" strategy="register">
<input>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="X"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="Y"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
</unaffected>
</prototype>
</default_proto>
</compiler_spec>
python/icicle/Ghidra/Processors/6502/data/languages/6502.ldefs
+33 -33
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@@ -1,33 +1,33 @@
<?xml version="1.0" encoding="UTF-8"?>
<language_definitions>
<language processor="6502"
endian="little"
size="16"
variant="default"
version="1.0"
slafile="6502.sla"
processorspec="6502.pspec"
manualindexfile="../manuals/6502.idx"
id="6502:LE:16:default">
<description>6502 Microcontroller Family</description>
<compiler name="default" spec="6502.cspec" id="default"/>
<external_name tool="IDA-PRO" name="m6502"/>
</language>
<language processor="65C02"
endian="little"
size="16"
variant="default"
version="1.0"
slafile="65c02.sla"
processorspec="6502.pspec"
manualindexfile="../manuals/65c02.idx"
id="65C02:LE:16:default">
<description>65C02 Microcontroller Family</description>
<compiler name="default" spec="6502.cspec" id="default"/>
<external_name tool="IDA-PRO" name="m65c02"/>
</language>
</language_definitions>
<?xml version="1.0" encoding="UTF-8"?>
<language_definitions>
<language processor="6502"
endian="little"
size="16"
variant="default"
version="1.0"
slafile="6502.sla"
processorspec="6502.pspec"
manualindexfile="../manuals/6502.idx"
id="6502:LE:16:default">
<description>6502 Microcontroller Family</description>
<compiler name="default" spec="6502.cspec" id="default"/>
<external_name tool="IDA-PRO" name="m6502"/>
</language>
<language processor="65C02"
endian="little"
size="16"
variant="default"
version="1.0"
slafile="65c02.sla"
processorspec="6502.pspec"
manualindexfile="../manuals/65c02.idx"
id="65C02:LE:16:default">
<description>65C02 Microcontroller Family</description>
<compiler name="default" spec="6502.cspec" id="default"/>
<external_name tool="IDA-PRO" name="m65c02"/>
</language>
</language_definitions>
python/icicle/Ghidra/Processors/6502/data/languages/6502.pspec
+16 -16
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@@ -1,16 +1,16 @@
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="PC"/>
<default_symbols>
<symbol name="NMI" address="FFFA" entry="true" type="code_ptr"/>
<symbol name="RES" address="FFFC" entry="true" type="code_ptr"/>
<symbol name="IRQ" address="FFFE" entry="true" type="code_ptr"/>
</default_symbols>
<default_memory_blocks>
<memory_block name="ZERO_PAGE" start_address="0x0000" length="0x0100" initialized="false"/>
<memory_block name="STACK" start_address="0x0100" length="0x0100" initialized="false"/>
</default_memory_blocks>
</processor_spec>
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="PC"/>
<default_symbols>
<symbol name="NMI" address="FFFA" entry="true" type="code_ptr"/>
<symbol name="RES" address="FFFC" entry="true" type="code_ptr"/>
<symbol name="IRQ" address="FFFE" entry="true" type="code_ptr"/>
</default_symbols>
<default_memory_blocks>
<memory_block name="ZERO_PAGE" start_address="0x0000" length="0x0100" initialized="false"/>
<memory_block name="STACK" start_address="0x0100" length="0x0100" initialized="false"/>
</default_memory_blocks>
</processor_spec>
python/icicle/Ghidra/Processors/6502/data/languages/6502.slaspec
+500 -499
View File
@@ -1,499 +1,500 @@
# sleigh specification file for MOS 6502
define endian=little;
define alignment=1;
define space RAM type=ram_space size=2 default;
define space register type=register_space size=1;
define register offset=0x00 size=1 [ A X Y P ];
define register offset=0x20 size=2 [ PC SP ];
define register offset=0x20 size=1 [ PCL PCH S SH ];
define register offset=0x30 size=1 [ N V B D I Z C ]; # status bits
#TOKENS
define token opbyte (8)
op = (0,7)
aaa = (5,7)
bbb = (2,4)
cc = (0,1)
;
define token data8 (8)
imm8 = (0,7)
rel = (0,7) signed
;
define token data (16)
imm16 = (0,15)
;
macro popSR() {
SP = SP + 1;
local ccr = *:1 SP;
N = ccr[7,1];
V = ccr[6,1];
B = ccr[4,1];
D = ccr[3,1];
I = ccr[2,1];
Z = ccr[1,1];
C = ccr[0,1];
}
macro pushSR() {
local ccr:1 = 0xff;
ccr[7,1] = N;
ccr[6,1] = V;
ccr[4,1] = B;
ccr[3,1] = D;
ccr[2,1] = I;
ccr[1,1] = Z;
ccr[0,1] = C;
*:1 (SP) = ccr;
SP = SP -1;
}
macro resultFlags(value) {
Z = (value == 0);
N = (value s< 0);
}
macro subtraction_flags1(register, operand, result) {
local complement_register = ~register;
V = ( ((register & ~operand & ~result) | (complement_register & operand & result)) & 0b10000000 ) != 0;
N = (result s< 0);
Z = (result == 0);
C = ( ((complement_register & operand) | (operand & result) | (result & complement_register)) & 0b10000000 ) != 0;
}
################################################################
# Pseudo Instructions
################################################################
define pcodeop readIRQ;
################################################################
REL: reloc is rel [ reloc = inst_next + rel; ] { export *:2 reloc; }
# Immediate
OP1: "#"imm8 is bbb=2; imm8 { tmp:1 = imm8; export tmp; }
# Zero Page
OP1: imm8 is bbb=1; imm8 { export *:1 imm8; }
# Zero Page Indexed X
OP1: imm8,X is bbb=5 & X; imm8 { tmp:2 = zext(imm8 + X); export *:1 tmp; }
# Absolute
OP1: imm16 is bbb=3; imm16 { export *:1 imm16; }
# Absolute Indexed X
OP1: imm16,X is bbb=7 & X; imm16 { tmp:2 = imm16 + zext(X); export *:1 tmp; }
# Absolute Indexed Y
OP1: imm16,Y is bbb=6 & Y; imm16 { tmp:2 = imm16 + zext(Y); export *:1 tmp; }
# Indirect X
OP1: (imm8,X) is bbb=0 & X; imm8 { addr:2 = zext(imm8 + X); tmp:2 = *:2 addr; export *:1 tmp; }
# Indirect Y
OP1: (imm8),Y is bbb=4 & Y; imm8 { addr:2 = imm8; tmp:2 = *:2 addr; tmp = tmp + zext(Y); export *:1 tmp; }
# Immediate
OP2: "#"imm8 is bbb=0; imm8 { tmp:1 = imm8; export tmp; }
# Zero Page
OP2: imm8 is bbb=1; imm8 { export *:1 imm8; }
OP2: A is bbb=2 & A { export A; }
# Absolute
OP2: imm16 is bbb=3; imm16 { export *:1 imm16; }
# Zero Page Indexed X
OP2: imm8,X is bbb=5 & X; imm8 { tmp:2 = zext(imm8 + X); export *:1 tmp; }
# Absolute Indexed X
OP2: imm16,X is bbb=7 & X; imm16 { tmp:2 = imm16 + zext(X); export *:1 tmp; }
OP2ST: OP2 is OP2 { export OP2; }
OP2ST: imm8,Y is bbb=5 & Y; imm8 { tmp:2 = zext(imm8 + Y); export *:1 tmp; }
OP2LD: OP2 is OP2 { export OP2; }
OP2LD: imm8,Y is bbb=5 & Y; imm8 { tmp:2 = zext(imm8 + Y); export *:1 tmp; }
OP2LD: imm16,Y is bbb=7 & Y; imm16 { tmp:2 = imm16 + zext(Y); export *:1 tmp; }
ADDR8: imm8 is imm8 { export *:1 imm8; }
ADDR16: imm16 is imm16 { export *:1 imm16; }
ADDRI: (imm16) is imm16 { tmp:2 = imm16; export *:2 tmp; }
# Instructions
:ADC OP1 is (cc=1 & aaa=3) ... & OP1
{
local op1 = OP1;
local tmpC = C;
C = carry(A, op1);
A = A + op1 + tmpC;
resultFlags(A);
V = C;
}
:AND OP1 is (cc=1 & aaa=1) ... & OP1
{
A = A & OP1;
resultFlags(A);
}
:ASL OP2 is (op=0x06 | op=0x0A | op=0x0E | op=0x16 | op=0x1E) ... & OP2
{
local tmp = OP2;
C = tmp >> 7;
tmp = tmp << 1;
OP2 = tmp;
resultFlags(tmp);
}
:BCC REL is op=0x90; REL
{
if (C == 0) goto REL;
}
:BCS REL is op=0xB0; REL
{
if (C) goto REL;
}
:BEQ REL is op=0xF0; REL
{
if (Z) goto REL;
}
:BIT OP2 is (op=0x24 | op=0x2C) ... & OP2
{
N = (OP2 & 0x80) == 0x80;
V = (OP2 & 0x40) == 0x40;
local value = A & OP2;
Z = (value == 0);
}
:BMI REL is op=0x30; REL
{
if (N) goto REL;
}
:BNE REL is op=0xD0; REL
{
if (Z == 0) goto REL;
}
:BPL REL is op=0x10; REL
{
if (N == 0) goto REL;
}
:BRK is op=0x00
{
*:2 (SP - 1) = inst_next;
SP = SP - 2;
B = 1;
pushSR();
I = 1;
local target:2 = 0xFFFE;
goto [*:2 target];
}
:BVC REL is op=0x50; REL
{
if (V == 0) goto REL;
}
:BVS REL is op=0x70; REL
{
if (V) goto REL;
}
:CLC is op=0x18
{
C = 0;
}
:CLD is op=0xD8
{
D = 0;
}
:CLI is op=0x58
{
I = 0;
}
:CLV is op=0xB8
{
V = 0;
}
:CMP OP1 is (cc=1 & aaa=6) ... & OP1
{
local op1 = OP1;
local tmp = A - op1;
resultFlags(tmp);
C = (A >= op1);
}
:CPX OP2 is (op=0xE0 | op=0xE4 | op=0xEC) ... & OP2
{
local op1 = OP2;
local tmp = X - op1;
resultFlags(tmp);
C = (X >= op1);
}
:CPY OP2 is (op=0xC0 | op=0xC4 | op=0xCC) ... & OP2
{
local op1 = OP2;
local tmp = Y - op1;
resultFlags(tmp);
C = (Y >= op1);
}
:DEC OP2 is (op=0xC6 | op=0xCE | op=0xD6 | op=0xDE) ... & OP2
{
local tmp = OP2 - 1;
OP2 = tmp;
resultFlags(tmp);
}
:DEX is op=0xCA
{
X = X - 1;
resultFlags(X);
}
:DEY is op=0x88
{
Y = Y -1;
resultFlags(Y);
}
:EOR OP1 is (cc=1 & aaa=2) ... & OP1
{
local op1 = OP1;
A = A ^ op1;
resultFlags(A);
}
:INC OP2 is (op=0xE6 | op=0xEE | op=0xF6 | op=0xFE) ... & OP2
{
local tmp = OP2 + 1;
OP2 = tmp;
resultFlags(tmp);
}
:INY is op=0xC8
{
Y = Y + 1;
resultFlags(Y);
}
:INX is op=0xE8
{
X = X + 1;
resultFlags(X);
}
:JMP ADDR16 is (op=0x4C); ADDR16
{
goto ADDR16;
}
:JMP ADDRI is (op=0x6c); ADDRI
{
goto [ADDRI];
}
:JSR ADDR16 is op=0x20; ADDR16
{
*:2 (SP-1) = inst_next;
SP=SP-2;
call ADDR16;
}
:LDA OP1 is (cc=1 & aaa=5) ... & OP1
{
A = OP1;
resultFlags(A);
}
:LDY OP2 is (op=0xA0 | op=0xA4 | op=0xAC | op=0xB4 | op=0xBC) ... & OP2
{
Y = OP2;
resultFlags(Y);
}
:LDX OP2LD is (op=0xA2 | op=0xA6 | op=0xAE | op=0xB6 | op=0xBE) ... & OP2LD
{
X = OP2LD;
resultFlags(X);
}
:LSR OP2 is (op=0x46 | op=0x4A | op=0x4E | op=0x56 | op=0x5E) ... & OP2
{
local tmp = OP2;
C = tmp & 1;
tmp = tmp >> 1;
OP2 = tmp;
Z = (tmp == 0);
N = 0;
}
:NOP is op=0xEA
{
}
:ORA OP1 is (cc=1 & aaa=0) ... & OP1
{
A = A | OP1;
resultFlags(A);
}
:PHP is op=0x8
{
pushSR();
}
:PLP is op=0x28
{
popSR();
}
:PHA is op=0x48
{
*:1 (SP) = A;
SP = SP - 1;
}
:PLA is op=0x68
{
SP = SP + 1;
A = *:1 (SP);
resultFlags(A);
}
:ROL OP2 is (op=0x26 | op=0x2A | op=0x2E | op=0x36 | op=0x3E) ... & OP2
{
local tmpC = C;
local op2 = OP2;
C = op2 >> 7;
local result = op2 << 1;
result = result | tmpC;
OP2 = result;
resultFlags(result);
}
:ROR OP2 is (op=0x66 | op=0x6A | op=0x6E | op=0x76 | op=0x7E) ... & OP2
{
local tmpC = C << 7;
local tmp = OP2;
C = tmp & 1;
tmp = tmp >> 1;
tmp = tmp | tmpC;
OP2 = tmp;
resultFlags(tmp);
}
:RTI is op=0x40
{
popSR();
SP = SP+1;
tmp:2 = *:2 SP;
SP = SP+1;
return [tmp];
}
:RTS is op=0x60
{
SP = SP+1;
tmp:2 = *:2 SP;
SP = SP+1;
return [tmp];
}
:SBC OP1 is (cc=1 & aaa=7) ... & OP1
{
local op1 = OP1;
local result = A - op1 - !C;
subtraction_flags1(A, op1, result);
A = result;
# resultFlags(tmp);
# C = ((A <= op1) * C) | (A < op1);
# A = tmp;
}
:SEC is op=0x38
{
C = 1;
}
:SED is op=0xF8
{
D = 1;
}
:SEI is op=0x78
{
I = 1;
}
:STA OP1 is (cc=1 & aaa=4) ... & OP1
{
OP1 = A;
}
:STX OP2ST is (op=0x86 | op=0x8E | op=0x96) ... & OP2ST
{
OP2ST = X;
}
:STY OP2 is (op=0x84 | op=0x8C | op=0x94) ... & OP2
{
OP2 = Y;
}
:TAX is op=0xAA
{
X = A;
resultFlags(X);
}
:TAY is op=0xA8
{
Y = A;
resultFlags(Y);
}
:TSX is op=0xBA
{
X = S;
}
:TXA is op=0x8A
{
A = X;
resultFlags(A);
}
:TXS is op=0x9A
{
S = X;
}
:TYA is op=0x98
{
A = Y;
resultFlags(A);
}
# sleigh specification file for MOS 6502
define endian=little;
define alignment=1;
define space RAM type=ram_space size=2 default;
define space register type=register_space size=1;
define register offset=0x00 size=1 [ A X Y P ];
define register offset=0x20 size=2 [ PC SP ];
define register offset=0x20 size=1 [ PCL PCH S SH ];
define register offset=0x30 size=1 [ N V B D I Z C ]; # status bits
#TOKENS
define token opbyte (8)
op = (0,7)
aaa = (5,7)
bbb = (2,4)
cc = (0,1)
;
define token data8 (8)
imm8 = (0,7)
rel = (0,7) signed
;
define token data (16)
imm16 = (0,15)
;
macro popSR() {
SP = SP + 1;
local ccr = *:1 SP;
N = ccr[7,1];
V = ccr[6,1];
B = ccr[4,1];
D = ccr[3,1];
I = ccr[2,1];
Z = ccr[1,1];
C = ccr[0,1];
}
macro pushSR() {
local ccr:1 = 0xff;
ccr[7,1] = N;
ccr[6,1] = V;
ccr[4,1] = B;
ccr[3,1] = D;
ccr[2,1] = I;
ccr[1,1] = Z;
ccr[0,1] = C;
*:1 (SP) = ccr;
SP = SP -1;
}
macro resultFlags(value) {
Z = (value == 0);
N = (value s< 0);
}
macro subtraction_flags1(register, operand, result) {
local complement_register = ~register;
V = ( ((register & ~operand & ~result) | (complement_register & operand & result)) & 0b10000000 ) != 0;
N = (result s< 0);
Z = (result == 0);
C = ( ((complement_register & operand) | (operand & result) | (result & complement_register)) & 0b10000000 ) != 0;
}
################################################################
# Pseudo Instructions
################################################################
define pcodeop readIRQ;
################################################################
REL: reloc is rel [ reloc = inst_next + rel; ] { export *:2 reloc; }
# Immediate
OP1: "#"imm8 is bbb=2; imm8 { tmp:1 = imm8; export tmp; }
# Zero Page
OP1: imm8 is bbb=1; imm8 { export *:1 imm8; }
# Zero Page Indexed X
OP1: imm8,X is bbb=5 & X; imm8 { tmp:2 = zext(imm8 + X); export *:1 tmp; }
# Absolute
OP1: imm16 is bbb=3; imm16 { export *:1 imm16; }
# Absolute Indexed X
OP1: imm16,X is bbb=7 & X; imm16 { tmp:2 = imm16 + zext(X); export *:1 tmp; }
# Absolute Indexed Y
OP1: imm16,Y is bbb=6 & Y; imm16 { tmp:2 = imm16 + zext(Y); export *:1 tmp; }
# Indirect X
OP1: (imm8,X) is bbb=0 & X; imm8 { addr:2 = zext(imm8 + X); tmp:2 = *:2 addr; export *:1 tmp; }
# Indirect Y
OP1: (imm8),Y is bbb=4 & Y; imm8 { addr:2 = imm8; tmp:2 = *:2 addr; tmp = tmp + zext(Y); export *:1 tmp; }
# Immediate
OP2: "#"imm8 is bbb=0; imm8 { tmp:1 = imm8; export tmp; }
# Zero Page
OP2: imm8 is bbb=1; imm8 { export *:1 imm8; }
OP2: A is bbb=2 & A { export A; }
# Absolute
OP2: imm16 is bbb=3; imm16 { export *:1 imm16; }
# Zero Page Indexed X
OP2: imm8,X is bbb=5 & X; imm8 { tmp:2 = zext(imm8 + X); export *:1 tmp; }
# Absolute Indexed X
OP2: imm16,X is bbb=7 & X; imm16 { tmp:2 = imm16 + zext(X); export *:1 tmp; }
OP2ST: OP2 is OP2 { export OP2; }
OP2ST: imm8,Y is bbb=5 & Y; imm8 { tmp:2 = zext(imm8 + Y); export *:1 tmp; }
OP2LD: OP2 is OP2 { export OP2; }
OP2LD: imm8,Y is bbb=5 & Y; imm8 { tmp:2 = zext(imm8 + Y); export *:1 tmp; }
OP2LD: imm16,Y is bbb=7 & Y; imm16 { tmp:2 = imm16 + zext(Y); export *:1 tmp; }
ADDR8: imm8 is imm8 { export *:1 imm8; }
ADDR16: imm16 is imm16 { export *:1 imm16; }
ADDRI: (imm16) is imm16 { tmp:2 = imm16; export *:2 tmp; }
# Instructions
:ADC OP1 is (cc=1 & aaa=3) ... & OP1
{
local op1 = OP1;
local tmpC = C;
C = carry(A, op1);
A = A + op1 + tmpC;
resultFlags(A);
V = C;
}
:AND OP1 is (cc=1 & aaa=1) ... & OP1
{
A = A & OP1;
resultFlags(A);
}
:ASL OP2 is (op=0x06 | op=0x0A | op=0x0E | op=0x16 | op=0x1E) ... & OP2
{
local tmp = OP2;
C = tmp >> 7;
tmp = tmp << 1;
OP2 = tmp;
resultFlags(tmp);
}
:BCC REL is op=0x90; REL
{
if (C == 0) goto REL;
}
:BCS REL is op=0xB0; REL
{
if (C) goto REL;
}
:BEQ REL is op=0xF0; REL
{
if (Z) goto REL;
}
:BIT OP2 is (op=0x24 | op=0x2C) ... & OP2
{
N = (OP2 & 0x80) == 0x80;
V = (OP2 & 0x40) == 0x40;
local value = A & OP2;
Z = (value == 0);
}
:BMI REL is op=0x30; REL
{
if (N) goto REL;
}
:BNE REL is op=0xD0; REL
{
if (Z == 0) goto REL;
}
:BPL REL is op=0x10; REL
{
if (N == 0) goto REL;
}
:BRK is op=0x00
{
*:2 (SP - 1) = inst_next;
SP = SP - 2;
B = 1;
pushSR();
I = 1;
local target:2 = 0xFFFE;
goto [*:2 target];
}
:BVC REL is op=0x50; REL
{
if (V == 0) goto REL;
}
:BVS REL is op=0x70; REL
{
if (V) goto REL;
}
:CLC is op=0x18
{
C = 0;
}
:CLD is op=0xD8
{
D = 0;
}
:CLI is op=0x58
{
I = 0;
}
:CLV is op=0xB8
{
V = 0;
}
:CMP OP1 is (cc=1 & aaa=6) ... & OP1
{
local op1 = OP1;
local tmp = A - op1;
resultFlags(tmp);
C = (A >= op1);
}
:CPX OP2 is (op=0xE0 | op=0xE4 | op=0xEC) ... & OP2
{
local op1 = OP2;
local tmp = X - op1;
resultFlags(tmp);
C = (X >= op1);
}
:CPY OP2 is (op=0xC0 | op=0xC4 | op=0xCC) ... & OP2
{
local op1 = OP2;
local tmp = Y - op1;
resultFlags(tmp);
C = (Y >= op1);
}
:DEC OP2 is (op=0xC6 | op=0xCE | op=0xD6 | op=0xDE) ... & OP2
{
local tmp = OP2 - 1;
OP2 = tmp;
resultFlags(tmp);
}
:DEX is op=0xCA
{
X = X - 1;
resultFlags(X);
}
:DEY is op=0x88
{
Y = Y -1;
resultFlags(Y);
}
:EOR OP1 is (cc=1 & aaa=2) ... & OP1
{
local op1 = OP1;
A = A ^ op1;
resultFlags(A);
}
:INC OP2 is (op=0xE6 | op=0xEE | op=0xF6 | op=0xFE) ... & OP2
{
local tmp = OP2 + 1;
OP2 = tmp;
resultFlags(tmp);
}
:INY is op=0xC8
{
Y = Y + 1;
resultFlags(Y);
}
:INX is op=0xE8
{
X = X + 1;
resultFlags(X);
}
:JMP ADDR16 is (op=0x4C); ADDR16
{
goto ADDR16;
}
:JMP ADDRI is (op=0x6c); ADDRI
{
goto [ADDRI];
}
:JSR ADDR16 is op=0x20; ADDR16
{
*:2 (SP-1) = inst_next;
SP=SP-2;
call ADDR16;
}
:LDA OP1 is (cc=1 & aaa=5) ... & OP1
{
A = OP1;
resultFlags(A);
}
:LDY OP2 is (op=0xA0 | op=0xA4 | op=0xAC | op=0xB4 | op=0xBC) ... & OP2
{
Y = OP2;
resultFlags(Y);
}
:LDX OP2LD is (op=0xA2 | op=0xA6 | op=0xAE | op=0xB6 | op=0xBE) ... & OP2LD
{
X = OP2LD;
resultFlags(X);
}
:LSR OP2 is (op=0x46 | op=0x4A | op=0x4E | op=0x56 | op=0x5E) ... & OP2
{
local tmp = OP2;
C = tmp & 1;
tmp = tmp >> 1;
OP2 = tmp;
Z = (tmp == 0);
N = 0;
}
:NOP is op=0xEA
{
}
:ORA OP1 is (cc=1 & aaa=0) ... & OP1
{
A = A | OP1;
resultFlags(A);
}
:PHP is op=0x8
{
pushSR();
}
:PLP is op=0x28
{
popSR();
}
:PHA is op=0x48
{
*:1 (SP) = A;
SP = SP - 1;
}
:PLA is op=0x68
{
SP = SP + 1;
A = *:1 (SP);
resultFlags(A);
}
:ROL OP2 is (op=0x26 | op=0x2A | op=0x2E | op=0x36 | op=0x3E) ... & OP2
{
local tmpC = C;
local op2 = OP2;
C = op2 >> 7;
local result = op2 << 1;
result = result | tmpC;
OP2 = result;
resultFlags(result);
}
:ROR OP2 is (op=0x66 | op=0x6A | op=0x6E | op=0x76 | op=0x7E) ... & OP2
{
local tmpC = C << 7;
local tmp = OP2;
C = tmp & 1;
tmp = tmp >> 1;
tmp = tmp | tmpC;
OP2 = tmp;
resultFlags(tmp);
}
:RTI is op=0x40
{
popSR();
SP = SP+1;
tmp:2 = *:2 SP;
SP = SP+1;
return [tmp];
}
:RTS is op=0x60
{
SP = SP+1;
tmp:2 = *:2 SP;
SP = SP+1;
return [tmp];
}
:SBC OP1 is (cc=1 & aaa=7) ... & OP1
{
local op1 = OP1;
local result = A - op1 - !C;
subtraction_flags1(A, op1, result);
A = result;
# resultFlags(tmp);
# C = ((A <= op1) * C) | (A < op1);
# A = tmp;
}
:SEC is op=0x38
{
C = 1;
}
:SED is op=0xF8
{
D = 1;
}
:SEI is op=0x78
{
I = 1;
}
:STA OP1 is (cc=1 & aaa=4) ... & OP1
{
OP1 = A;
}
:STX OP2ST is (op=0x86 | op=0x8E | op=0x96) ... & OP2ST
{
OP2ST = X;
}
:STY OP2 is (op=0x84 | op=0x8C | op=0x94) ... & OP2
{
OP2 = Y;
}
:TAX is op=0xAA
{
X = A;
resultFlags(X);
}
:TAY is op=0xA8
{
Y = A;
resultFlags(Y);
}
:TSX is op=0xBA
{
X = S;
resultFlags(X);
}
:TXA is op=0x8A
{
A = X;
resultFlags(A);
}
:TXS is op=0x9A
{
S = X;
}
:TYA is op=0x98
{
A = Y;
resultFlags(A);
}
python/icicle/Ghidra/Processors/6502/data/languages/65c02.slaspec
+222 -222
View File
@@ -1,222 +1,222 @@
@include "6502.slaspec"
define token bitopbyte (8)
bitop = (0,7)
action = (7,7)
bitindex = (4,6) dec
optype = (0,3)
;
define token testopbyte (8)
top = (0, 7)
taaa = (5, 7)
td = (4, 4)
tbb = (2, 3)
tcc = (0, 1)
;
################################################################
# Zero Page Indirect
ZIOP: (imm8) is bbb=4; imm8 { addr:2 = imm8; tmp:2 = *:2 addr; export *:1 tmp; }
OPTB: imm8 is tbb=1; imm8 { export *:1 imm8; }
OPTB: imm16 is tbb=3; imm16 { export *:1 imm16; }
# Absolute Indexed Indirect
ADDRIX: (imm16,X) is X; imm16 { addr:2 = imm16 + zext(X); tmp:2 = *:2 addr; export tmp; }
# Instructions
:ADC ZIOP is (cc=2 & aaa=3) ... & ZIOP
{
local op1 = ZIOP;
local tmpC = C;
C = carry(A, op1);
A = A + op1 + tmpC;
resultFlags(A);
V = C;
}
:AND ZIOP is (cc=2 & aaa=1) ... & ZIOP
{
A = A & ZIOP;
resultFlags(A);
}
:BBR "#"bitindex, imm8, REL is (action=0 & optype=0xF) & bitindex ; imm8 ; REL {
local ptr:2 = imm8;
local value:1 = *:1 ptr;
local jump = (value & (1 << bitindex)) == 0;
if (jump) goto REL;
}
:BBS "#"bitindex, imm8, REL is (action=1 & optype=0xF) & bitindex ; imm8 ; REL {
local ptr:2 = imm8;
local value:1 = *:1 ptr;
local jump = (value & (1 << bitindex)) != 0;
if (jump) goto REL;
}
:BIT "#"imm8 is op=0x89; imm8
{
local value:1 = imm8;
N = (value & 0x80) == 0x80;
V = (value & 0x40) == 0x40;
value = A & value;
Z = (value == 0);
}
:BIT OP2 is (op=0x34 | op=0x3C) ... & OP2
{
N = (OP2 & 0x80) == 0x80;
V = (OP2 & 0x40) == 0x40;
local value = A & OP2;
Z = (value == 0);
}
:BRA REL is op=0x80; REL
{
goto REL;
}
:CMP ZIOP is (cc=2 & aaa=6) ... & ZIOP
{
local op1 = ZIOP;
local tmp = A - op1;
resultFlags(tmp);
C = (A >= op1);
}
:DEC A is op=0x3A & A
{
local tmp = A - 1;
A = tmp;
resultFlags(tmp);
}
:EOR ZIOP is (cc=2 & aaa=2) ... & ZIOP
{
local op1 = ZIOP;
A = A ^ op1;
resultFlags(A);
}
:INC A is op=0x1A & A
{
A = A + 1;
resultFlags(A);
}
:JMP ADDRIX is (op=0x7C); ADDRIX
{
goto [ADDRIX];
}
:LDA ZIOP is (cc=2 & aaa=5) ... & ZIOP
{
A = ZIOP;
resultFlags(A);
}
:ORA ZIOP is (cc=2 & aaa=0) ... & ZIOP
{
A = A | ZIOP;
resultFlags(A);
}
:PHX is op=0xDA
{
*:1 (SP) = X;
SP = SP - 1;
}
:PLX is op=0xFA
{
SP = SP + 1;
X = *:1 (SP);
resultFlags(X);
}
:PHY is op=0x5A
{
*:1 (SP) = Y;
SP = SP - 1;
}
:PLY is op=0x7A
{
SP = SP + 1;
Y = *:1 (SP);
resultFlags(Y);
}
:RMB "#"bitindex, imm8 is (action=0 & optype=7) & bitindex ; imm8 {
local ptr:2 = imm8;
local value:1 = *:1 ptr;
value = value & ~(1 << bitindex);
*:1 ptr = value;
}
:SBC ZIOP is (cc=2 & aaa=7) ... & ZIOP
{
local op1 = ZIOP;
local result = A - op1 - !C;
subtraction_flags1(A, op1, result);
A = result;
}
:SMB "#"bitindex, imm8 is (action=1 & optype=7) & bitindex ; imm8 {
local ptr:2 = imm8;
local value:1 = *:1 ptr;
value = value | (1 << bitindex);
*:1 ptr = value;
}
:STA ZIOP is (cc=2 & aaa=4) ... & ZIOP
{
ZIOP = A;
}
:STZ imm8 is op=0x64 ; imm8
{
local tmp:2 = imm8;
*:1 tmp = 0;
}
:STZ imm8,X is op=0x74 & X ; imm8
{
local tmp:2 = zext(imm8 + X);
*:1 tmp = 0;
}
:STZ imm16 is op=0x9C ; imm16
{
local tmp:2 = imm16;
*:1 tmp = 0;
}
:STZ imm16,X is op=0x9E & X ; imm16
{
local tmp:2 = imm16 + zext(X);
*:1 tmp = 0;
}
:TRB OPTB is (tcc=0 & taaa=0 & td=1) ... & OPTB
{
local op1 = OPTB;
local result = (~A) & op1;
OPTB = result;
Z = result == 0;
}
:TSB OPTB is (tcc=0 & taaa=0 & td=0) ... & OPTB
{
local op1 = OPTB;
local result = A | op1;
OPTB = result;
Z = result == 0;
}
@include "6502.slaspec"
define token bitopbyte (8)
bitop = (0,7)
action = (7,7)
bitindex = (4,6) dec
optype = (0,3)
;
define token testopbyte (8)
top = (0, 7)
taaa = (5, 7)
td = (4, 4)
tbb = (2, 3)
tcc = (0, 1)
;
################################################################
# Zero Page Indirect
ZIOP: (imm8) is bbb=4; imm8 { addr:2 = imm8; tmp:2 = *:2 addr; export *:1 tmp; }
OPTB: imm8 is tbb=1; imm8 { export *:1 imm8; }
OPTB: imm16 is tbb=3; imm16 { export *:1 imm16; }
# Absolute Indexed Indirect
ADDRIX: (imm16,X) is X; imm16 { addr:2 = imm16 + zext(X); tmp:2 = *:2 addr; export tmp; }
# Instructions
:ADC ZIOP is (cc=2 & aaa=3) ... & ZIOP
{
local op1 = ZIOP;
local tmpC = C;
C = carry(A, op1);
A = A + op1 + tmpC;
resultFlags(A);
V = C;
}
:AND ZIOP is (cc=2 & aaa=1) ... & ZIOP
{
A = A & ZIOP;
resultFlags(A);
}
:BBR "#"bitindex, imm8, REL is (action=0 & optype=0xF) & bitindex ; imm8 ; REL {
local ptr:2 = imm8;
local value:1 = *:1 ptr;
local jump = (value & (1 << bitindex)) == 0;
if (jump) goto REL;
}
:BBS "#"bitindex, imm8, REL is (action=1 & optype=0xF) & bitindex ; imm8 ; REL {
local ptr:2 = imm8;
local value:1 = *:1 ptr;
local jump = (value & (1 << bitindex)) != 0;
if (jump) goto REL;
}
:BIT "#"imm8 is op=0x89; imm8
{
local value:1 = imm8;
N = (value & 0x80) == 0x80;
V = (value & 0x40) == 0x40;
value = A & value;
Z = (value == 0);
}
:BIT OP2 is (op=0x34 | op=0x3C) ... & OP2
{
N = (OP2 & 0x80) == 0x80;
V = (OP2 & 0x40) == 0x40;
local value = A & OP2;
Z = (value == 0);
}
:BRA REL is op=0x80; REL
{
goto REL;
}
:CMP ZIOP is (cc=2 & aaa=6) ... & ZIOP
{
local op1 = ZIOP;
local tmp = A - op1;
resultFlags(tmp);
C = (A >= op1);
}
:DEC A is op=0x3A & A
{
local tmp = A - 1;
A = tmp;
resultFlags(tmp);
}
:EOR ZIOP is (cc=2 & aaa=2) ... & ZIOP
{
local op1 = ZIOP;
A = A ^ op1;
resultFlags(A);
}
:INC A is op=0x1A & A
{
A = A + 1;
resultFlags(A);
}
:JMP ADDRIX is (op=0x7C); ADDRIX
{
goto [ADDRIX];
}
:LDA ZIOP is (cc=2 & aaa=5) ... & ZIOP
{
A = ZIOP;
resultFlags(A);
}
:ORA ZIOP is (cc=2 & aaa=0) ... & ZIOP
{
A = A | ZIOP;
resultFlags(A);
}
:PHX is op=0xDA
{
*:1 (SP) = X;
SP = SP - 1;
}
:PLX is op=0xFA
{
SP = SP + 1;
X = *:1 (SP);
resultFlags(X);
}
:PHY is op=0x5A
{
*:1 (SP) = Y;
SP = SP - 1;
}
:PLY is op=0x7A
{
SP = SP + 1;
Y = *:1 (SP);
resultFlags(Y);
}
:RMB "#"bitindex, imm8 is (action=0 & optype=7) & bitindex ; imm8 {
local ptr:2 = imm8;
local value:1 = *:1 ptr;
value = value & ~(1 << bitindex);
*:1 ptr = value;
}
:SBC ZIOP is (cc=2 & aaa=7) ... & ZIOP
{
local op1 = ZIOP;
local result = A - op1 - !C;
subtraction_flags1(A, op1, result);
A = result;
}
:SMB "#"bitindex, imm8 is (action=1 & optype=7) & bitindex ; imm8 {
local ptr:2 = imm8;
local value:1 = *:1 ptr;
value = value | (1 << bitindex);
*:1 ptr = value;
}
:STA ZIOP is (cc=2 & aaa=4) ... & ZIOP
{
ZIOP = A;
}
:STZ imm8 is op=0x64 ; imm8
{
local tmp:2 = imm8;
*:1 tmp = 0;
}
:STZ imm8,X is op=0x74 & X ; imm8
{
local tmp:2 = zext(imm8 + X);
*:1 tmp = 0;
}
:STZ imm16 is op=0x9C ; imm16
{
local tmp:2 = imm16;
*:1 tmp = 0;
}
:STZ imm16,X is op=0x9E & X ; imm16
{
local tmp:2 = imm16 + zext(X);
*:1 tmp = 0;
}
:TRB OPTB is (tcc=0 & taaa=0 & td=1) ... & OPTB
{
local op1 = OPTB;
local result = (~A) & op1;
OPTB = result;
Z = result == 0;
}
:TSB OPTB is (tcc=0 & taaa=0 & td=0) ... & OPTB
{
local op1 = OPTB;
local result = A | op1;
OPTB = result;
Z = result == 0;
}
python/icicle/Ghidra/Processors/68000/data/languages/68000.cspec
+67 -69
View File
@@ -1,69 +1,67 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<data_organization>
<absolute_max_alignment value="0" />
<machine_alignment value="8" />
<default_alignment value="1" />
<default_pointer_alignment value="4" />
<pointer_size value="4" />
<wchar_size value="4" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="10" /> <!-- aligned-length=12 -->
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="4" />
</size_alignment_map>
</data_organization>
<global>
<range space="ram"/>
</global>
<stackpointer register="SP" space="ram"/>
<default_proto>
<prototype name="__stdcall" extrapop="4" stackshift="4" strategy="register">
<input>
<pentry minsize="1" maxsize="4" metatype="ptr">
<register name="A0"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="ptr">
<register name="A1"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="D0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="D1"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4">
<register name="D0"/>
</pentry>
</output>
<unaffected>
<register name="D2"/>
<register name="D3"/>
<register name="D4"/>
<register name="D5"/>
<register name="D6"/>
<register name="D7"/>
<register name="A2"/>
<register name="A3"/>
<register name="A4"/>
<register name="A5"/>
<register name="A6"/>
<register name="SP"/>
</unaffected>
</prototype>
</default_proto>
</compiler_spec>
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<data_organization>
<absolute_max_alignment value="0" />
<machine_alignment value="8" />
<default_alignment value="1" />
<default_pointer_alignment value="4" />
<pointer_size value="4" />
<wchar_size value="4" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="10" /> <!-- aligned-length=12 -->
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="4" />
</size_alignment_map>
</data_organization>
<global>
<range space="ram"/>
</global>
<stackpointer register="SP" space="ram"/>
<default_proto>
<prototype name="__stdcall" extrapop="4" stackshift="4">
<input>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4">
<register name="D0"/>
</pentry>
</output>
<unaffected>
<register name="D2"/>
<register name="D3"/>
<register name="D4"/>
<register name="D5"/>
<register name="D6"/>
<register name="D7"/>
<register name="A2"/>
<register name="A3"/>
<register name="A4"/>
<register name="A5"/>
<register name="A6"/>
<register name="SP"/>
</unaffected>
<killedbycall>
<register name="D0"/>
<register name="D1"/>
<register name="A0"/>
<register name="A1"/>
</killedbycall>
</prototype>
</default_proto>
</compiler_spec>
python/icicle/Ghidra/Processors/68000/data/languages/68000.dwarf
+10 -10
View File
@@ -1,10 +1,10 @@
<dwarf>
<register_mappings>
<register_mapping dwarf="0" ghidra="D0" auto_count="8"/> <!-- D0..D7 -->
<register_mapping dwarf="8" ghidra="A0" auto_count="7"/> <!-- A0..A6 -->
<register_mapping dwarf="15" ghidra="SP" stackpointer="true"/>
<register_mapping dwarf="16" ghidra="FP0" auto_count="8"/> <!-- FP0..FP7 -->
</register_mappings>
</dwarf>
<dwarf>
<register_mappings>
<register_mapping dwarf="0" ghidra="D0" auto_count="8"/> <!-- D0..D7 -->
<register_mapping dwarf="8" ghidra="A0" auto_count="7"/> <!-- A0..A6 -->
<register_mapping dwarf="15" ghidra="SP" stackpointer="true"/>
<register_mapping dwarf="16" ghidra="FP0" auto_count="8"/> <!-- FP0..FP7 -->
</register_mappings>
</dwarf>
python/icicle/Ghidra/Processors/68000/data/languages/68000.ldefs
+68 -67
View File
@@ -1,67 +1,68 @@
<?xml version="1.0" encoding="UTF-8"?>
<language_definitions>
<language processor="68000"
endian="big"
size="32"
variant="default"
version="1.1"
slafile="68040.sla"
processorspec="68000.pspec"
manualindexfile="../manuals/68000.idx"
id="68000:BE:32:default">
<description>Motorola 32-bit 68040</description>
<compiler name="default" spec="68000.cspec" id="default"/>
<external_name tool="gnu" name="m68k"/>
<external_name tool="IDA-PRO" name="68000"/>
<external_name tool="IDA-PRO" name="68040"/>
<external_name tool="IDA-PRO" name="68K"/>
<external_name tool="DWARF.register.mapping.file" name="68000.dwarf"/>
</language>
<language processor="68000"
endian="big"
size="32"
variant="MC68030"
version="1.1"
slafile="68030.sla"
processorspec="68000.pspec"
manualindexfile="../manuals/68000.idx"
id="68000:BE:32:MC68030">
<description>Motorola 32-bit 68030</description>
<compiler name="default" spec="68000.cspec" id="default"/>
<external_name tool="gnu" name="m68k:68030"/>
<external_name tool="IDA-PRO" name="68030"/>
<external_name tool="DWARF.register.mapping.file" name="68000.dwarf"/>
</language>
<language processor="68000"
endian="big"
size="32"
variant="MC68020"
version="1.1"
slafile="68020.sla"
processorspec="68000.pspec"
manualindexfile="../manuals/68000.idx"
id="68000:BE:32:MC68020">
<description>Motorola 32-bit 68020</description>
<compiler name="default" spec="68000.cspec" id="default"/>
<external_name tool="gnu" name="m68k:68020"/>
<external_name tool="IDA-PRO" name="68010"/>
<external_name tool="IDA-PRO" name="68020"/>
<external_name tool="IDA-PRO" name="68020EX"/>
<external_name tool="DWARF.register.mapping.file" name="68000.dwarf"/>
</language>
<language processor="68000"
endian="big"
size="32"
variant="Coldfire"
version="1.1"
slafile="coldfire.sla"
processorspec="68000.pspec"
manualindexfile="../manuals/68000.idx"
id="68000:BE:32:Coldfire">
<description>Motorola 32-bit Coldfire</description>
<compiler name="default" spec="68000.cspec" id="default"/>
<external_name tool="IDA-PRO" name="colfire"/>
<external_name tool="DWARF.register.mapping.file" name="68000.dwarf"/>
</language>
</language_definitions>
<?xml version="1.0" encoding="UTF-8"?>
<language_definitions>
<language processor="68000"
endian="big"
size="32"
variant="default"
version="1.1"
slafile="68040.sla"
processorspec="68000.pspec"
manualindexfile="../manuals/68000.idx"
id="68000:BE:32:default">
<description>Motorola 32-bit 68040</description>
<compiler name="default" spec="68000.cspec" id="default"/>
<external_name tool="gnu" name="m68k"/>
<external_name tool="IDA-PRO" name="68000"/>
<external_name tool="IDA-PRO" name="68040"/>
<external_name tool="IDA-PRO" name="68K"/>
<external_name tool="DWARF.register.mapping.file" name="68000.dwarf"/>
</language>
<language processor="68000"
endian="big"
size="32"
variant="MC68030"
version="1.1"
slafile="68030.sla"
processorspec="68000.pspec"
manualindexfile="../manuals/68000.idx"
id="68000:BE:32:MC68030">
<description>Motorola 32-bit 68030</description>
<compiler name="default" spec="68000.cspec" id="default"/>
<external_name tool="gnu" name="m68k:68030"/>
<external_name tool="IDA-PRO" name="68030"/>
<external_name tool="DWARF.register.mapping.file" name="68000.dwarf"/>
</language>
<language processor="68000"
endian="big"
size="32"
variant="MC68020"
version="1.1"
slafile="68020.sla"
processorspec="68000.pspec"
manualindexfile="../manuals/68000.idx"
id="68000:BE:32:MC68020">
<description>Motorola 32-bit 68020</description>
<compiler name="default" spec="68000.cspec" id="default"/>
<external_name tool="gnu" name="m68k:68020"/>
<external_name tool="IDA-PRO" name="68010"/>
<external_name tool="IDA-PRO" name="68020"/>
<external_name tool="IDA-PRO" name="68020EX"/>
<external_name tool="DWARF.register.mapping.file" name="68000.dwarf"/>
</language>
<language processor="68000"
endian="big"
size="32"
variant="Coldfire"
version="1.1"
slafile="coldfire.sla"
processorspec="68000.pspec"
manualindexfile="../manuals/68000.idx"
id="68000:BE:32:Coldfire">
<description>Motorola 32-bit Coldfire</description>
<compiler name="default" spec="68000.cspec" id="default"/>
<compiler name="register" spec="68000_register.cspec" id="register"/>
<external_name tool="IDA-PRO" name="colfire"/>
<external_name tool="DWARF.register.mapping.file" name="68000.dwarf"/>
</language>
</language_definitions>
python/icicle/Ghidra/Processors/68000/data/languages/68000.opinion
+17 -17
View File
@@ -1,17 +1,17 @@
<opinions>
<constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default">
<constraint primary="4" processor="68000" endian="big" size="32" />
</constraint>
<constraint loader="Preferred Executable Format (PEF)" compilerSpecID="default">
<constraint primary="m68k" processor="68000" endian="big" size="32" />
</constraint>
<constraint loader="Palm Pilot Program (Palm)" compilerSpecID="default">
<constraint primary="0" processor="68000" endian="big" size="32" />
</constraint>
<constraint loader="Assembler Output (AOUT)" compilerSpecID="default">
<constraint primary="1" processor="68000" endian="big" size="32" />
<constraint primary="2" processor="68000" endian="big" size="32" />
<constraint primary="200" processor="68000" endian="big" size="32" />
<constraint primary="300" processor="68000" endian="big" size="32" />
</constraint>
</opinions>
<opinions>
<constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default">
<constraint primary="4" processor="68000" endian="big" size="32" />
</constraint>
<constraint loader="Preferred Executable Format (PEF)" compilerSpecID="default">
<constraint primary="m68k" processor="68000" endian="big" size="32" />
</constraint>
<constraint loader="Palm Pilot Program (Palm)" compilerSpecID="default">
<constraint primary="0" processor="68000" endian="big" size="32" />
</constraint>
<constraint loader="Assembler Output (AOUT)" compilerSpecID="default">
<constraint primary="1" processor="68000" endian="big" size="32" />
<constraint primary="2" processor="68000" endian="big" size="32" />
<constraint primary="200" processor="68000" endian="big" size="32" />
<constraint primary="300" processor="68000" endian="big" size="32" />
</constraint>
</opinions>
python/icicle/Ghidra/Processors/68000/data/languages/68000.pspec
+9 -9
View File
@@ -1,9 +1,9 @@
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<properties>
<property key="emulateInstructionStateModifierClass" value="ghidra.program.emulation.m68kEmulateInstructionStateModifier"/>
<property key="assemblyRating:68000:BE:32:default" value="PLATINUM"/>
</properties>
<programcounter register="PC"/>
</processor_spec>
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<properties>
<property key="emulateInstructionStateModifierClass" value="ghidra.program.emulation.m68kEmulateInstructionStateModifier"/>
<property key="assemblyRating:68000:BE:32:default" value="PLATINUM"/>
</properties>
<programcounter register="PC"/>
</processor_spec>
python/icicle/Ghidra/Processors/68000/data/languages/68000.sinc
+3173 -2954
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python/icicle/Ghidra/Processors/68000/data/languages/68000_register.cspec
+118
View File
@@ -0,0 +1,118 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<data_organization>
<absolute_max_alignment value="0" />
<machine_alignment value="8" />
<default_alignment value="1" />
<default_pointer_alignment value="4" />
<pointer_size value="4" />
<wchar_size value="4" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="10" /> <!-- aligned-length=12 -->
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="4" />
</size_alignment_map>
</data_organization>
<global>
<range space="ram"/>
</global>
<stackpointer register="SP" space="ram"/>
<default_proto>
<prototype name="register" extrapop="4" stackshift="4" strategy="register">
<input>
<pentry minsize="1" maxsize="4" metatype="ptr">
<register name="A0"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="ptr">
<register name="A1"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="FP0"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="FP1"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="D0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="D1"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4" metatype="ptr">
<register name="A0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="D0"/>
</pentry>
</output>
<unaffected>
<register name="D2"/>
<register name="D3"/>
<register name="D4"/>
<register name="D5"/>
<register name="D6"/>
<register name="D7"/>
<register name="A2"/>
<register name="A3"/>
<register name="A4"/>
<register name="A5"/>
<register name="A6"/>
<register name="SP"/>
</unaffected>
</prototype>
</default_proto>
<prototype name="standard" extrapop="4" stackshift="4">
<input>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4" metatype="ptr">
<register name="A0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="D0"/>
</pentry>
</output>
<unaffected>
<register name="D2"/>
<register name="D3"/>
<register name="D4"/>
<register name="D5"/>
<register name="D6"/>
<register name="D7"/>
<register name="A2"/>
<register name="A3"/>
<register name="A4"/>
<register name="A5"/>
<register name="A6"/>
<register name="SP"/>
</unaffected>
<killedbycall>
<register name="D0"/>
<register name="D1"/>
<register name="A0"/>
<register name="A1"/>
</killedbycall>
</prototype>
</compiler_spec>
python/icicle/Ghidra/Processors/68000/data/languages/68020.slaspec
+1 -1
View File
@@ -1 +1 @@
@include "68000.sinc"
@include "68000.sinc"
python/icicle/Ghidra/Processors/68000/data/languages/68030.slaspec
+2 -2
View File
@@ -1,2 +1,2 @@
@define MC68030 ""
@include "68000.sinc"
@define MC68030 ""
@include "68000.sinc"
python/icicle/Ghidra/Processors/68000/data/languages/68040.slaspec
+2 -2
View File
@@ -1,2 +1,2 @@
@define MC68040 ""
@include "68000.sinc"
@define MC68040 ""
@include "68000.sinc"
python/icicle/Ghidra/Processors/68000/data/languages/coldfire.slaspec
+6 -6
View File
@@ -1,6 +1,6 @@
# Motorola's Coldfire processor
@define COLDFIRE ""
@define MC68040 ""
@include "68000.sinc"
# Motorola's Coldfire processor
@define COLDFIRE ""
@define MC68040 ""
@include "68000.sinc"
python/icicle/Ghidra/Processors/8048/data/languages/8048.cspec
+31 -31
View File
@@ -1,31 +1,31 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<global>
<range space="CODE"/>
<range space="INTMEM"/>
<range space="EXTMEM"/>
<range space="PORT"/>
</global>
<stackpointer register="SP" space="INTMEM" growth="positive"/>
<returnaddress>
<varnode space="stack" offset="-2" size="2"/>
</returnaddress>
<default_proto>
<prototype name="__stdcall" extrapop="-2" stackshift="-2" strategy="register">
<input>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
</unaffected>
</prototype>
</default_proto>
</compiler_spec>
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<global>
<range space="CODE"/>
<range space="INTMEM"/>
<range space="EXTMEM"/>
<range space="PORT"/>
</global>
<stackpointer register="SP" space="INTMEM" growth="positive"/>
<returnaddress>
<varnode space="stack" offset="-2" size="2"/>
</returnaddress>
<default_proto>
<prototype name="__stdcall" extrapop="-2" stackshift="-2" strategy="register">
<input>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
</unaffected>
</prototype>
</default_proto>
</compiler_spec>
python/icicle/Ghidra/Processors/8048/data/languages/8048.ldefs
+18 -18
View File
@@ -1,18 +1,18 @@
<?xml version="1.0" encoding="UTF-8"?>
<language_definitions>
<language processor="8048"
endian="little"
size="16"
variant="default"
version="1.0"
slafile="8048.sla"
processorspec="8048.pspec"
manualindexfile="../manuals/8048.idx"
id="8048:LE:16:default">
<description>8048 Microcontroller Family</description>
<compiler name="default" spec="8048.cspec" id="default"/>
</language>
</language_definitions>
<?xml version="1.0" encoding="UTF-8"?>
<language_definitions>
<language processor="8048"
endian="little"
size="16"
variant="default"
version="1.0"
slafile="8048.sla"
processorspec="8048.pspec"
manualindexfile="../manuals/8048.idx"
id="8048:LE:16:default">
<description>8048 Microcontroller Family</description>
<compiler name="default" spec="8048.cspec" id="default"/>
</language>
</language_definitions>
python/icicle/Ghidra/Processors/8048/data/languages/8048.pspec
+59 -49
View File
@@ -1,49 +1,59 @@
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="PC"/>
<default_symbols>
<symbol name="BANK0_R0" address="INTMEM:00"/>
<symbol name="BANK0_R1" address="INTMEM:01"/>
<symbol name="BANK0_R2" address="INTMEM:02"/>
<symbol name="BANK0_R3" address="INTMEM:03"/>
<symbol name="BANK0_R4" address="INTMEM:04"/>
<symbol name="BANK0_R5" address="INTMEM:05"/>
<symbol name="BANK0_R6" address="INTMEM:06"/>
<symbol name="BANK0_R7" address="INTMEM:07"/>
<symbol name="BANK1_R0" address="INTMEM:18"/>
<symbol name="BANK1_R1" address="INTMEM:19"/>
<symbol name="BANK1_R2" address="INTMEM:1a"/>
<symbol name="BANK1_R3" address="INTMEM:1b"/>
<symbol name="BANK1_R4" address="INTMEM:1c"/>
<symbol name="BANK1_R5" address="INTMEM:1d"/>
<symbol name="BANK1_R6" address="INTMEM:1e"/>
<symbol name="BANK1_R7" address="INTMEM:1f"/>
<symbol name="BUS" address="PORT:0"/>
<symbol name="P1" address="PORT:1"/>
<symbol name="P2" address="PORT:2"/>
<symbol name="P4" address="PORT:4"/>
<symbol name="P5" address="PORT:5"/>
<symbol name="P6" address="PORT:6"/>
<symbol name="P7" address="PORT:7"/>
<symbol name="RESET" address="CODE:0" entry="true"/>
<symbol name="EXTIRQ" address="CODE:3" entry="true"/>
<symbol name="TIMIRQ" address="CODE:7" entry="true"/>
</default_symbols>
<default_memory_blocks>
<memory_block name="REG_BANK_0" start_address="INTMEM:0" length="0x8" initialized="false"/>
<memory_block name="STACK" start_address="INTMEM:8" length="0x10" initialized="false"/>
<memory_block name="REG_BANK_1" start_address="INTMEM:18" length="0x8" initialized="false"/>
<memory_block name="INTMEM" start_address="INTMEM:20" length="0xe0" initialized="false"/>
<memory_block name="PORT" start_address="PORT:0" length="0x8" initialized="false"/>
</default_memory_blocks>
</processor_spec>
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="PC"/>
<default_symbols>
<symbol name="BANK0_R0" address="INTMEM:00"/>
<symbol name="BANK0_R1" address="INTMEM:01"/>
<symbol name="BANK0_R2" address="INTMEM:02"/>
<symbol name="BANK0_R3" address="INTMEM:03"/>
<symbol name="BANK0_R4" address="INTMEM:04"/>
<symbol name="BANK0_R5" address="INTMEM:05"/>
<symbol name="BANK0_R6" address="INTMEM:06"/>
<symbol name="BANK0_R7" address="INTMEM:07"/>
<symbol name="BANK1_R0" address="INTMEM:18"/>
<symbol name="BANK1_R1" address="INTMEM:19"/>
<symbol name="BANK1_R2" address="INTMEM:1a"/>
<symbol name="BANK1_R3" address="INTMEM:1b"/>
<symbol name="BANK1_R4" address="INTMEM:1c"/>
<symbol name="BANK1_R5" address="INTMEM:1d"/>
<symbol name="BANK1_R6" address="INTMEM:1e"/>
<symbol name="BANK1_R7" address="INTMEM:1f"/>
<symbol name="BUS" address="PORT:0" volatile="true" />
<symbol name="P1" address="PORT:1" volatile="true" />
<symbol name="P2" address="PORT:2" volatile="true" />
<symbol name="P4" address="PORT:4" volatile="true" />
<symbol name="P5" address="PORT:5" volatile="true" />
<symbol name="P6" address="PORT:6" volatile="true" />
<symbol name="P7" address="PORT:7" volatile="true" />
<symbol name="RESET" address="CODE:0" entry="true"/>
<symbol name="EXTIRQ" address="CODE:3" entry="true"/>
<symbol name="TIMIRQ" address="CODE:7" entry="true"/>
</default_symbols>
<default_memory_blocks>
<memory_block name="REG_BANK_0" start_address="INTMEM:0" length="0x8" initialized="false"/>
<memory_block name="STACK" start_address="INTMEM:8" length="0x10" initialized="false"/>
<memory_block name="REG_BANK_1" start_address="INTMEM:18" length="0x8" initialized="false"/>
<memory_block name="INTMEM" start_address="INTMEM:20" length="0xe0" initialized="false"/>
<memory_block name="PORT" start_address="PORT:0" length="0x8" initialized="false"/>
</default_memory_blocks>
<context_data>
<context_set space="CODE" first="0x0" last="0x7ff">
<set name="DBF" val="0"/>
</context_set>
<context_set space="CODE" first="0x800" last="0xfff">
<set name="DBF" val="1"/>
</context_set>
</context_data>
</processor_spec>
python/icicle/Ghidra/Processors/8048/data/languages/8048.slaspec
+561 -539
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python/icicle/Ghidra/Processors/8051/data/languages/80251.cspec
+54 -54
View File
@@ -1,54 +1,54 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<global>
<range space="RAM"/>
<range space="SFR"/>
<range space="BITS"/>
</global>
<stackpointer register="SPX" space="RAM" growth="positive"/>
<default_proto>
<prototype name="__stdcall" extrapop="-2" stackshift="-2">
<input>
<pentry minsize="1" maxsize="1">
<register name="R0"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R1"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R2"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R3"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R4"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R5"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R6"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R7"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="ACC"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="1">
<register name="ACC"/>
</pentry>
</output>
<unaffected>
<register name="SPX"/>
</unaffected>
<localrange>
<range space="stack" first="0x0" last="0xfffc"/>
</localrange>
</prototype>
</default_proto>
</compiler_spec>
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<global>
<range space="RAM"/>
<range space="SFR"/>
<range space="BITS"/>
</global>
<stackpointer register="SPX" space="RAM" growth="positive"/>
<default_proto>
<prototype name="__stdcall" extrapop="-2" stackshift="-2">
<input>
<pentry minsize="1" maxsize="1">
<register name="R0"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R1"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R2"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R3"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R4"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R5"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R6"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R7"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="ACC"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="1">
<register name="ACC"/>
</pentry>
</output>
<unaffected>
<register name="SPX"/>
</unaffected>
<localrange>
<range space="stack" first="0x0" last="0xfffc"/>
</localrange>
</prototype>
</default_proto>
</compiler_spec>
python/icicle/Ghidra/Processors/8051/data/languages/80251.pspec
+1070 -1070
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python/icicle/Ghidra/Processors/8051/data/languages/80251.sinc
+662 -662
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python/icicle/Ghidra/Processors/8051/data/languages/80251.slaspec
+5 -5
View File
@@ -1,5 +1,5 @@
@define MCS251 ""
@include "8051_main.sinc"
@include "80251.sinc"
@define MCS251 ""
@include "8051_main.sinc"
@include "80251.sinc"
python/icicle/Ghidra/Processors/8051/data/languages/80390.cspec
+62 -62
View File
@@ -1,62 +1,62 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<global>
<range space="CODE"/>
<range space="INTMEM"/>
<range space="SFR"/>
<range space="EXTMEM"/>
<range space="BITS"/>
</global>
<stackpointer register="SP" space="INTMEM" growth="positive"/>
<default_proto>
<prototype name="__stdcall" extrapop="-3" stackshift="-3" strategy="register">
<input>
<pentry minsize="1" maxsize="1">
<register name="ACC"/>
</pentry>
<pentry minsize="1" maxsize="3">
<register name="DPTR"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="B"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R0"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R1"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R2"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R3"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R4"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R5"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R6"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R7"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="1">
<register name="ACC"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
</unaffected>
<localrange>
<range space="stack" first="0x0" last="0xf"/>
</localrange>
</prototype>
</default_proto>
</compiler_spec>
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<global>
<range space="CODE"/>
<range space="INTMEM"/>
<range space="SFR"/>
<range space="EXTMEM"/>
<range space="BITS"/>
</global>
<stackpointer register="SP" space="INTMEM" growth="positive"/>
<default_proto>
<prototype name="__stdcall" extrapop="-3" stackshift="-3" strategy="register">
<input>
<pentry minsize="1" maxsize="1">
<register name="ACC"/>
</pentry>
<pentry minsize="1" maxsize="3">
<register name="DPTR"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="B"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R0"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R1"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R2"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R3"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R4"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R5"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R6"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R7"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="1">
<register name="ACC"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
</unaffected>
<localrange>
<range space="stack" first="0x0" last="0xf"/>
</localrange>
</prototype>
</default_proto>
</compiler_spec>
python/icicle/Ghidra/Processors/8051/data/languages/80390.slaspec
+3 -3
View File
@@ -1,3 +1,3 @@
@define MCS80390 ""
@include "8051_main.sinc"
@define MCS80390 ""
@include "8051_main.sinc"
python/icicle/Ghidra/Processors/8051/data/languages/8051.cspec
+72 -72
View File
@@ -1,72 +1,72 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<global>
<range space="CODE"/>
<range space="INTMEM"/>
<range space="SFR"/>
<range space="EXTMEM"/>
<range space="BITS"/>
</global>
<stackpointer register="SP" space="INTMEM" growth="positive"/>
<default_proto>
<prototype name="__stdcall" extrapop="-2" stackshift="-2" strategy="register">
<input>
<pentry minsize="1" maxsize="1">
<register name="ACC"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="DPTR"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="B"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R0"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R1"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R2"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R3"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R4"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R5"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R6"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R7"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="1">
<register name="ACC"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
</unaffected>
<localrange>
<range space="stack" first="0x0" last="0xf"/>
</localrange>
</prototype>
</default_proto>
<callfixup name="switch_override_ACC">
<pcode>
<body><![CDATA[
PC = inst_next + zext(ACC) * 3;
goto [PC];
]]></body>
</pcode>
</callfixup>
</compiler_spec>
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<global>
<range space="CODE"/>
<range space="INTMEM"/>
<range space="SFR"/>
<range space="EXTMEM"/>
<range space="BITS"/>
</global>
<stackpointer register="SP" space="INTMEM" growth="positive"/>
<default_proto>
<prototype name="__stdcall" extrapop="-2" stackshift="-2" strategy="register">
<input>
<pentry minsize="1" maxsize="1">
<register name="ACC"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="DPTR"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="B"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R0"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R1"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R2"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R3"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R4"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R5"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R6"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="R7"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="1">
<register name="ACC"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
</unaffected>
<localrange>
<range space="stack" first="0x0" last="0xf"/>
</localrange>
</prototype>
</default_proto>
<callfixup name="switch_override_ACC">
<pcode>
<body><![CDATA[
PC = inst_next + zext(ACC) * 3;
goto [PC];
]]></body>
</pcode>
</callfixup>
</compiler_spec>
python/icicle/Ghidra/Processors/8051/data/languages/8051.ldefs
+53 -53
View File
@@ -1,53 +1,53 @@
<?xml version="1.0" encoding="UTF-8"?>
<language_definitions>
<language processor="8051"
endian="big"
size="16"
variant="default"
version="2.0"
slafile="8051.sla"
processorspec="8051.pspec"
manualindexfile="../manuals/8051.idx"
id="8051:BE:16:default">
<description>8051 Microcontroller Family</description>
<compiler name="default" spec="8051.cspec" id="default"/>
<compiler name="Archimedes" spec="8051_archimedes.cspec" id="Archimedes"/>
<external_name tool="IDA-PRO" name="8051"/>
</language>
<language processor="80251"
endian="big"
size="16"
variant="default"
version="2.0"
slafile="80251.sla"
processorspec="80251.pspec"
id="80251:BE:24:default">
<description>80251 Microcontroller Family</description>
<compiler name="default" spec="80251.cspec" id="default"/>
</language>
<language processor="80390"
endian="big"
size="16"
variant="default"
version="1.0"
slafile="80390.sla"
processorspec="8051.pspec"
id="80390:BE:24:default">
<description>80390 in flat mode</description>
<compiler name="default" spec="80390.cspec" id="default"/>
</language>
<language processor="8051"
endian="big"
size="16"
variant="mx51"
version="2.0"
slafile="mx51.sla"
processorspec="mx51.pspec"
manualindexfile="../manuals/8051.idx"
id="8051:BE:24:mx51">
<description>NXP/Phillips MX51</description>
<compiler name="default" spec="mx51.cspec" id="default"/>
<external_name tool="IDA-PRO" name="8051"/>
</language>
</language_definitions>
<?xml version="1.0" encoding="UTF-8"?>
<language_definitions>
<language processor="8051"
endian="big"
size="16"
variant="default"
version="2.0"
slafile="8051.sla"
processorspec="8051.pspec"
manualindexfile="../manuals/8051.idx"
id="8051:BE:16:default">
<description>8051 Microcontroller Family</description>
<compiler name="default" spec="8051.cspec" id="default"/>
<compiler name="Archimedes" spec="8051_archimedes.cspec" id="Archimedes"/>
<external_name tool="IDA-PRO" name="8051"/>
</language>
<language processor="80251"
endian="big"
size="16"
variant="default"
version="2.0"
slafile="80251.sla"
processorspec="80251.pspec"
id="80251:BE:24:default">
<description>80251 Microcontroller Family</description>
<compiler name="default" spec="80251.cspec" id="default"/>
</language>
<language processor="80390"
endian="big"
size="16"
variant="default"
version="1.0"
slafile="80390.sla"
processorspec="8051.pspec"
id="80390:BE:24:default">
<description>80390 in flat mode</description>
<compiler name="default" spec="80390.cspec" id="default"/>
</language>
<language processor="8051"
endian="big"
size="16"
variant="mx51"
version="2.0"
slafile="mx51.sla"
processorspec="mx51.pspec"
manualindexfile="../manuals/8051.idx"
id="8051:BE:24:mx51">
<description>NXP/Phillips MX51</description>
<compiler name="default" spec="mx51.cspec" id="default"/>
<external_name tool="IDA-PRO" name="8051"/>
</language>
</language_definitions>
python/icicle/Ghidra/Processors/8051/data/languages/8051.pspec
+413 -413
View File
@@ -1,413 +1,413 @@
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="PC"/>
<volatile outputop="write_volatile" inputop="read_volatile">
<range space="SFR" first="0x0" last="0xFF"/>
<range space="BITS" first="0x80" last="0xFF"/>
</volatile>
<default_symbols>
<symbol name="BANK0_R0" address="INTMEM:00"/>
<symbol name="BANK0_R1" address="INTMEM:01"/>
<symbol name="BANK0_R2" address="INTMEM:02"/>
<symbol name="BANK0_R3" address="INTMEM:03"/>
<symbol name="BANK0_R4" address="INTMEM:04"/>
<symbol name="BANK0_R5" address="INTMEM:05"/>
<symbol name="BANK0_R6" address="INTMEM:06"/>
<symbol name="BANK0_R7" address="INTMEM:07"/>
<symbol name="BANK1_R0" address="INTMEM:08"/>
<symbol name="BANK1_R1" address="INTMEM:09"/>
<symbol name="BANK1_R2" address="INTMEM:0a"/>
<symbol name="BANK1_R3" address="INTMEM:0b"/>
<symbol name="BANK1_R4" address="INTMEM:0c"/>
<symbol name="BANK1_R5" address="INTMEM:0d"/>
<symbol name="BANK1_R6" address="INTMEM:0e"/>
<symbol name="BANK1_R7" address="INTMEM:0f"/>
<symbol name="BANK2_R0" address="INTMEM:10"/>
<symbol name="BANK2_R1" address="INTMEM:11"/>
<symbol name="BANK2_R2" address="INTMEM:12"/>
<symbol name="BANK2_R3" address="INTMEM:13"/>
<symbol name="BANK2_R4" address="INTMEM:14"/>
<symbol name="BANK2_R5" address="INTMEM:15"/>
<symbol name="BANK2_R6" address="INTMEM:16"/>
<symbol name="BANK2_R7" address="INTMEM:17"/>
<symbol name="BANK3_R0" address="INTMEM:18"/>
<symbol name="BANK3_R1" address="INTMEM:19"/>
<symbol name="BANK3_R2" address="INTMEM:1a"/>
<symbol name="BANK3_R3" address="INTMEM:1b"/>
<symbol name="BANK3_R4" address="INTMEM:1c"/>
<symbol name="BANK3_R5" address="INTMEM:1d"/>
<symbol name="BANK3_R6" address="INTMEM:1e"/>
<symbol name="BANK3_R7" address="INTMEM:1f"/>
<symbol name="P0" address="SFR:80"/>
<symbol name="SP" address="SFR:81"/>
<symbol name="DPL" address="SFR:82"/>
<symbol name="DPH" address="SFR:83"/>
<symbol name="DPXL" address="SFR:84"/>
<symbol name="PCON" address="SFR:87"/>
<symbol name="TCON" address="SFR:88"/>
<symbol name="TMOD" address="SFR:89"/>
<symbol name="TL0" address="SFR:8a"/>
<symbol name="TL1" address="SFR:8b"/>
<symbol name="TH0" address="SFR:8c"/>
<symbol name="TH1" address="SFR:8d"/>
<symbol name="FADDR" address="SFR:8f"/>
<symbol name="P1" address="SFR:90"/>
<symbol name="DPX" address="SFR:93"/>
<symbol name="HADDR" address="SFR:97"/>
<symbol name="SCON" address="SFR:98"/>
<symbol name="SBUF" address="SFR:99"/>
<symbol name="P2" address="SFR:a0"/>
<symbol name="HIE" address="SFR:a1"/>
<symbol name="FIE" address="SFR:a2"/>
<symbol name="FIE1" address="SFR:a3"/>
<symbol name="WDTRST" address="SFR:a6"/>
<symbol name="WCON" address="SFR:a7"/>
<symbol name="IE" address="SFR:a8"/>
<symbol name="SADDR" address="SFR:a9"/>
<symbol name="HSTAT" address="SFR:ae"/>
<symbol name="P3" address="SFR:b0"/>
<symbol name="IEN1" address="SFR:b1"/>
<symbol name="IPL1" address="SFR:b2"/>
<symbol name="IPH1" address="SFR:b3"/>
<symbol name="IPH0" address="SFR:b7"/>
<symbol name="IP" address="SFR:b8"/>
<symbol name="SADEN" address="SFR:b9"/>
<symbol name="SPH" address="SFR:be"/>
<symbol name="FIFLG" address="SFR:c0"/>
<symbol name="FIFLG1" address="SFR:c1"/>
<symbol name="EPCONFIG" address="SFR:c7"/>
<symbol name="T2CON" address="SFR:c8"/>
<symbol name="T2MOD" address="SFR:c9"/>
<symbol name="RCAP2L" address="SFR:ca"/>
<symbol name="RCAP2H" address="SFR:cb"/>
<symbol name="TL2" address="SFR:cc"/>
<symbol name="TH2" address="SFR:cd"/>
<symbol name="HPCON" address="SFR:cf"/>
<symbol name="PSW" address="SFR:d0"/>
<symbol name="PSW1" address="SFR:d1"/>
<symbol name="SOFL" address="SFR:d2"/>
<symbol name="HPINDEX" address="SFR:d4"/>
<symbol name="HPSC" address="SFR:d5"/>
<symbol name="HPSTAT" address="SFR:d7"/>
<symbol name="CCON" address="SFR:d8"/>
<symbol name="CMOD" address="SFR:d9"/>
<symbol name="CCAPM0" address="SFR:da"/>
<symbol name="CCAPM1" address="SFR:db"/>
<symbol name="CCAPM2" address="SFR:dc"/>
<symbol name="CCAPM3" address="SFR:dd"/>
<symbol name="CCAPM4" address="SFR:de"/>
<symbol name="PCON1" address="SFR:df"/>
<symbol name="ACC" address="SFR:e0"/>
<symbol name="EPCON" address="SFR:e1"/>
<symbol name="RXSTAT" address="SFR:e2"/>
<symbol name="RXDAT" address="SFR:e3"/>
<symbol name="RXCON" address="SFR:e4"/>
<symbol name="RXFLG" address="SFR:e5"/>
<symbol name="RXCNTL" address="SFR:e6"/>
<symbol name="RXCNTH" address="SFR:e7"/>
<symbol name="HIFLG" address="SFR:e8"/>
<symbol name="CL" address="SFR:e9"/>
<symbol name="CCAP0L" address="SFR:ea"/>
<symbol name="CCAP1L" address="SFR:eb"/>
<symbol name="CCAP2L" address="SFR:ec"/>
<symbol name="CCAP3L" address="SFR:ed"/>
<symbol name="CCAP4L" address="SFR:ee"/>
<symbol name="B" address="SFR:f0"/>
<symbol name="EPINDEX" address="SFR:f1"/>
<symbol name="TXSTAT" address="SFR:f2"/>
<symbol name="TXDAT" address="SFR:f3"/>
<symbol name="TXCON" address="SFR:f4"/>
<symbol name="TXFLG" address="SFR:f5"/>
<symbol name="TXCNTL" address="SFR:f6"/>
<symbol name="TXCNTH" address="SFR:f7"/>
<symbol name="CH" address="SFR:f9"/>
<symbol name="CCAP0H" address="SFR:fa"/>
<symbol name="CCAP1H" address="SFR:fb"/>
<symbol name="CCAP2H" address="SFR:fc"/>
<symbol name="CCAP3H" address="SFR:fd"/>
<symbol name="CCAP4H" address="SFR:fe"/>
<symbol name="20.0" address="BITS:00"/>
<symbol name="20.1" address="BITS:01"/>
<symbol name="20.2" address="BITS:02"/>
<symbol name="20.3" address="BITS:03"/>
<symbol name="20.4" address="BITS:04"/>
<symbol name="20.5" address="BITS:05"/>
<symbol name="20.6" address="BITS:06"/>
<symbol name="20.7" address="BITS:07"/>
<symbol name="21.0" address="BITS:08"/>
<symbol name="21.1" address="BITS:09"/>
<symbol name="21.2" address="BITS:0a"/>
<symbol name="21.3" address="BITS:0b"/>
<symbol name="21.4" address="BITS:0c"/>
<symbol name="21.5" address="BITS:0d"/>
<symbol name="21.6" address="BITS:0e"/>
<symbol name="21.7" address="BITS:0f"/>
<symbol name="22.0" address="BITS:10"/>
<symbol name="22.1" address="BITS:11"/>
<symbol name="22.2" address="BITS:12"/>
<symbol name="22.3" address="BITS:13"/>
<symbol name="22.4" address="BITS:14"/>
<symbol name="22.5" address="BITS:15"/>
<symbol name="22.6" address="BITS:16"/>
<symbol name="22.7" address="BITS:17"/>
<symbol name="23.0" address="BITS:18"/>
<symbol name="23.1" address="BITS:19"/>
<symbol name="23.2" address="BITS:1a"/>
<symbol name="23.3" address="BITS:1b"/>
<symbol name="23.4" address="BITS:1c"/>
<symbol name="23.5" address="BITS:1d"/>
<symbol name="23.6" address="BITS:1e"/>
<symbol name="23.7" address="BITS:1f"/>
<symbol name="24.0" address="BITS:20"/>
<symbol name="24.1" address="BITS:21"/>
<symbol name="24.2" address="BITS:22"/>
<symbol name="24.3" address="BITS:23"/>
<symbol name="24.4" address="BITS:24"/>
<symbol name="24.5" address="BITS:25"/>
<symbol name="24.6" address="BITS:26"/>
<symbol name="24.7" address="BITS:27"/>
<symbol name="25.0" address="BITS:28"/>
<symbol name="25.1" address="BITS:29"/>
<symbol name="25.2" address="BITS:2a"/>
<symbol name="25.3" address="BITS:2b"/>
<symbol name="25.4" address="BITS:2c"/>
<symbol name="25.5" address="BITS:2d"/>
<symbol name="25.6" address="BITS:2e"/>
<symbol name="25.7" address="BITS:2f"/>
<symbol name="26.0" address="BITS:30"/>
<symbol name="26.1" address="BITS:31"/>
<symbol name="26.2" address="BITS:32"/>
<symbol name="26.3" address="BITS:33"/>
<symbol name="26.4" address="BITS:34"/>
<symbol name="26.5" address="BITS:35"/>
<symbol name="26.6" address="BITS:36"/>
<symbol name="26.7" address="BITS:37"/>
<symbol name="27.0" address="BITS:38"/>
<symbol name="27.1" address="BITS:39"/>
<symbol name="27.2" address="BITS:3a"/>
<symbol name="27.3" address="BITS:3b"/>
<symbol name="27.4" address="BITS:3c"/>
<symbol name="27.5" address="BITS:3d"/>
<symbol name="27.6" address="BITS:3e"/>
<symbol name="27.7" address="BITS:3f"/>
<symbol name="28.0" address="BITS:40"/>
<symbol name="28.1" address="BITS:41"/>
<symbol name="28.2" address="BITS:42"/>
<symbol name="28.3" address="BITS:43"/>
<symbol name="28.4" address="BITS:44"/>
<symbol name="28.5" address="BITS:45"/>
<symbol name="28.6" address="BITS:46"/>
<symbol name="28.7" address="BITS:47"/>
<symbol name="29.0" address="BITS:48"/>
<symbol name="29.1" address="BITS:49"/>
<symbol name="29.2" address="BITS:4a"/>
<symbol name="29.3" address="BITS:4b"/>
<symbol name="29.4" address="BITS:4c"/>
<symbol name="29.5" address="BITS:4d"/>
<symbol name="29.6" address="BITS:4e"/>
<symbol name="29.7" address="BITS:4f"/>
<symbol name="2a.0" address="BITS:50"/>
<symbol name="2a.1" address="BITS:51"/>
<symbol name="2a.2" address="BITS:52"/>
<symbol name="2a.3" address="BITS:53"/>
<symbol name="2a.4" address="BITS:54"/>
<symbol name="2a.5" address="BITS:55"/>
<symbol name="2a.6" address="BITS:56"/>
<symbol name="2a.7" address="BITS:57"/>
<symbol name="2b.0" address="BITS:58"/>
<symbol name="2b.1" address="BITS:59"/>
<symbol name="2b.2" address="BITS:5a"/>
<symbol name="2b.3" address="BITS:5b"/>
<symbol name="2b.4" address="BITS:5c"/>
<symbol name="2b.5" address="BITS:5d"/>
<symbol name="2b.6" address="BITS:5e"/>
<symbol name="2b.7" address="BITS:5f"/>
<symbol name="2c.0" address="BITS:60"/>
<symbol name="2c.1" address="BITS:61"/>
<symbol name="2c.2" address="BITS:62"/>
<symbol name="2c.3" address="BITS:63"/>
<symbol name="2c.4" address="BITS:64"/>
<symbol name="2c.5" address="BITS:65"/>
<symbol name="2c.6" address="BITS:66"/>
<symbol name="2c.7" address="BITS:67"/>
<symbol name="2d.0" address="BITS:68"/>
<symbol name="2d.1" address="BITS:69"/>
<symbol name="2d.2" address="BITS:6a"/>
<symbol name="2d.3" address="BITS:6b"/>
<symbol name="2d.4" address="BITS:6c"/>
<symbol name="2d.5" address="BITS:6d"/>
<symbol name="2d.6" address="BITS:6e"/>
<symbol name="2d.7" address="BITS:6f"/>
<symbol name="2e.0" address="BITS:70"/>
<symbol name="2e.1" address="BITS:71"/>
<symbol name="2e.2" address="BITS:72"/>
<symbol name="2e.3" address="BITS:73"/>
<symbol name="2e.4" address="BITS:74"/>
<symbol name="2e.5" address="BITS:75"/>
<symbol name="2e.6" address="BITS:76"/>
<symbol name="2e.7" address="BITS:77"/>
<symbol name="2f.0" address="BITS:78"/>
<symbol name="2f.1" address="BITS:79"/>
<symbol name="2f.2" address="BITS:7a"/>
<symbol name="2f.3" address="BITS:7b"/>
<symbol name="2f.4" address="BITS:7c"/>
<symbol name="2f.5" address="BITS:7d"/>
<symbol name="2f.6" address="BITS:7e"/>
<symbol name="2f.7" address="BITS:7f"/>
<symbol name="P0.0" address="BITS:80"/>
<symbol name="P0.1" address="BITS:81"/>
<symbol name="P0.2" address="BITS:82"/>
<symbol name="P0.3" address="BITS:83"/>
<symbol name="P0.4" address="BITS:84"/>
<symbol name="P0.5" address="BITS:85"/>
<symbol name="P0.6" address="BITS:86"/>
<symbol name="P0.7" address="BITS:87"/>
<symbol name="IT0" address="BITS:88"/>
<symbol name="IE0" address="BITS:89"/>
<symbol name="IT1" address="BITS:8a"/>
<symbol name="IE1" address="BITS:8b"/>
<symbol name="TR0" address="BITS:8c"/>
<symbol name="TF0" address="BITS:8d"/>
<symbol name="TR1" address="BITS:8e"/>
<symbol name="TF1" address="BITS:8f"/>
<symbol name="P1.0" address="BITS:90"/>
<symbol name="P1.1" address="BITS:91"/>
<symbol name="P1.2" address="BITS:92"/>
<symbol name="P1.3" address="BITS:93"/>
<symbol name="P1.4" address="BITS:94"/>
<symbol name="P1.5" address="BITS:95"/>
<symbol name="P1.6" address="BITS:96"/>
<symbol name="P1.7" address="BITS:97"/>
<symbol name="RI" address="BITS:98"/>
<symbol name="TI" address="BITS:99"/>
<symbol name="RB8" address="BITS:9a"/>
<symbol name="TB8" address="BITS:9b"/>
<symbol name="REN" address="BITS:9c"/>
<symbol name="SM2" address="BITS:9d"/>
<symbol name="SM1" address="BITS:9e"/>
<symbol name="SM0" address="BITS:9f"/>
<symbol name="P2.0" address="BITS:a0"/>
<symbol name="P2.1" address="BITS:a1"/>
<symbol name="P2.2" address="BITS:a2"/>
<symbol name="P2.3" address="BITS:a3"/>
<symbol name="P2.4" address="BITS:a4"/>
<symbol name="P2.5" address="BITS:a5"/>
<symbol name="P2.6" address="BITS:a6"/>
<symbol name="P2.7" address="BITS:a7"/>
<symbol name="EX0" address="BITS:a8"/>
<symbol name="ET0" address="BITS:a9"/>
<symbol name="EX1" address="BITS:aa"/>
<symbol name="ET1" address="BITS:ab"/>
<symbol name="ES" address="BITS:ac"/>
<symbol name="ET2" address="BITS:ad"/>
<symbol name="EC" address="BITS:ae"/>
<symbol name="EA" address="BITS:af"/>
<symbol name="RXD" address="BITS:b0"/>
<symbol name="TXD" address="BITS:b1"/>
<symbol name="INT0" address="BITS:b2"/>
<symbol name="INT1" address="BITS:b3"/>
<symbol name="T0" address="BITS:b4"/>
<symbol name="T1" address="BITS:b5"/>
<symbol name="WR" address="BITS:b6"/>
<symbol name="RD" address="BITS:b7"/>
<symbol name="PX0" address="BITS:b8"/>
<symbol name="PT0" address="BITS:b9"/>
<symbol name="PX1" address="BITS:ba"/>
<symbol name="PT1" address="BITS:bb"/>
<symbol name="PS" address="BITS:bc"/>
<symbol name="PT2" address="BITS:bd"/>
<symbol name="PC" address="BITS:be"/>
<symbol name="IP.7" address="BITS:bf"/>
<symbol name="FIFLG.0" address="BITS:c0"/>
<symbol name="FIFLG.1" address="BITS:c1"/>
<symbol name="FIFLG.2" address="BITS:c2"/>
<symbol name="FIFLG.3" address="BITS:c3"/>
<symbol name="FIFLG.4" address="BITS:c4"/>
<symbol name="FIFLG.5" address="BITS:c5"/>
<symbol name="FIFLG.6" address="BITS:c6"/>
<symbol name="FIFLG.7" address="BITS:c7"/>
<symbol name="CPRL2" address="BITS:c8"/>
<symbol name="CT2" address="BITS:c9"/>
<symbol name="TR2" address="BITS:ca"/>
<symbol name="EXEN2" address="BITS:cb"/>
<symbol name="TCLK" address="BITS:cc"/>
<symbol name="RCLK" address="BITS:cd"/>
<symbol name="EXF2" address="BITS:ce"/>
<symbol name="TF2" address="BITS:cf"/>
<symbol name="P" address="BITS:d0"/>
<symbol name="UD" address="BITS:d1"/>
<symbol name="OV" address="BITS:d2"/>
<symbol name="RS0" address="BITS:d3"/>
<symbol name="RS1" address="BITS:d4"/>
<symbol name="F0" address="BITS:d5"/>
<symbol name="AC" address="BITS:d6"/>
<symbol name="C" address="BITS:d7"/>
<symbol name="CCF.0" address="BITS:d8"/>
<symbol name="CCF.1" address="BITS:d9"/>
<symbol name="CCF.2" address="BITS:da"/>
<symbol name="CCF.3" address="BITS:db"/>
<symbol name="CCF.4" address="BITS:dc"/>
<symbol name="CCON.5" address="BITS:dd"/>
<symbol name="CR" address="BITS:de"/>
<symbol name="CF" address="BITS:df"/>
<symbol name="ACC.0" address="BITS:e0"/>
<symbol name="ACC.1" address="BITS:e1"/>
<symbol name="ACC.2" address="BITS:e2"/>
<symbol name="ACC.3" address="BITS:e3"/>
<symbol name="ACC.4" address="BITS:e4"/>
<symbol name="ACC.5" address="BITS:e5"/>
<symbol name="ACC.6" address="BITS:e6"/>
<symbol name="ACC.7" address="BITS:e7"/>
<symbol name="HIFLG.0" address="BITS:e8"/>
<symbol name="HIFLG.1" address="BITS:e9"/>
<symbol name="HIFLG.2" address="BITS:ea"/>
<symbol name="HIFLG.3" address="BITS:eb"/>
<symbol name="HIFLG.4" address="BITS:ec"/>
<symbol name="HIFLG.5" address="BITS:ed"/>
<symbol name="HIFLG.6" address="BITS:ee"/>
<symbol name="HIFLG.7" address="BITS:ef"/>
<symbol name="B.0" address="BITS:f0"/>
<symbol name="B.1" address="BITS:f1"/>
<symbol name="B.2" address="BITS:f2"/>
<symbol name="B.3" address="BITS:f3"/>
<symbol name="B.4" address="BITS:f4"/>
<symbol name="B.5" address="BITS:f5"/>
<symbol name="B.6" address="BITS:f6"/>
<symbol name="B.7" address="BITS:f7"/>
<symbol name="F8.0" address="BITS:f8"/>
<symbol name="F8.1" address="BITS:f9"/>
<symbol name="F8.2" address="BITS:fa"/>
<symbol name="F8.3" address="BITS:fb"/>
<symbol name="F8.4" address="BITS:fc"/>
<symbol name="F8.5" address="BITS:fd"/>
<symbol name="F8.6" address="BITS:fe"/>
<symbol name="F8.7" address="BITS:ff"/>
</default_symbols>
<default_memory_blocks>
<memory_block name="REG_BANK_1" start_address="INTMEM:0" length="0x8" initialized="false"/>
<memory_block name="REG_BANK_2" start_address="INTMEM:8" length="0x8" initialized="false"/>
<memory_block name="REG_BANK_3" start_address="INTMEM:10" length="0x8" initialized="false"/>
<memory_block name="REG_BANK_4" start_address="INTMEM:18" length="0x8" initialized="false"/>
<memory_block name="INTMEM" start_address="INTMEM:20" length="0xe0" initialized="false"/>
<memory_block name="BITS" start_address="BITS:00" bit_mapped_address="INTMEM:20" length="0x80"/>
<memory_block name="SFR" start_address="SFR:80" length="0x80" initialized="false"/>
<!-- BUG: SFR-BITS do not map properly since only every 8th SFR register is mapped (e.g., 0x80, 0x88, 0x90 ... 0xF0, 0xF8) -->
<memory_block name="SFR-BITS" start_address="BITS:80" bit_mapped_address="SFR:80" length="0x80"/>
</default_memory_blocks>
</processor_spec>
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="PC"/>
<volatile outputop="write_volatile" inputop="read_volatile">
<range space="SFR" first="0x0" last="0xFF"/>
<range space="BITS" first="0x80" last="0xFF"/>
</volatile>
<default_symbols>
<symbol name="BANK0_R0" address="INTMEM:00"/>
<symbol name="BANK0_R1" address="INTMEM:01"/>
<symbol name="BANK0_R2" address="INTMEM:02"/>
<symbol name="BANK0_R3" address="INTMEM:03"/>
<symbol name="BANK0_R4" address="INTMEM:04"/>
<symbol name="BANK0_R5" address="INTMEM:05"/>
<symbol name="BANK0_R6" address="INTMEM:06"/>
<symbol name="BANK0_R7" address="INTMEM:07"/>
<symbol name="BANK1_R0" address="INTMEM:08"/>
<symbol name="BANK1_R1" address="INTMEM:09"/>
<symbol name="BANK1_R2" address="INTMEM:0a"/>
<symbol name="BANK1_R3" address="INTMEM:0b"/>
<symbol name="BANK1_R4" address="INTMEM:0c"/>
<symbol name="BANK1_R5" address="INTMEM:0d"/>
<symbol name="BANK1_R6" address="INTMEM:0e"/>
<symbol name="BANK1_R7" address="INTMEM:0f"/>
<symbol name="BANK2_R0" address="INTMEM:10"/>
<symbol name="BANK2_R1" address="INTMEM:11"/>
<symbol name="BANK2_R2" address="INTMEM:12"/>
<symbol name="BANK2_R3" address="INTMEM:13"/>
<symbol name="BANK2_R4" address="INTMEM:14"/>
<symbol name="BANK2_R5" address="INTMEM:15"/>
<symbol name="BANK2_R6" address="INTMEM:16"/>
<symbol name="BANK2_R7" address="INTMEM:17"/>
<symbol name="BANK3_R0" address="INTMEM:18"/>
<symbol name="BANK3_R1" address="INTMEM:19"/>
<symbol name="BANK3_R2" address="INTMEM:1a"/>
<symbol name="BANK3_R3" address="INTMEM:1b"/>
<symbol name="BANK3_R4" address="INTMEM:1c"/>
<symbol name="BANK3_R5" address="INTMEM:1d"/>
<symbol name="BANK3_R6" address="INTMEM:1e"/>
<symbol name="BANK3_R7" address="INTMEM:1f"/>
<symbol name="P0" address="SFR:80"/>
<symbol name="SP" address="SFR:81"/>
<symbol name="DPL" address="SFR:82"/>
<symbol name="DPH" address="SFR:83"/>
<symbol name="DPXL" address="SFR:84"/>
<symbol name="PCON" address="SFR:87"/>
<symbol name="TCON" address="SFR:88"/>
<symbol name="TMOD" address="SFR:89"/>
<symbol name="TL0" address="SFR:8a"/>
<symbol name="TL1" address="SFR:8b"/>
<symbol name="TH0" address="SFR:8c"/>
<symbol name="TH1" address="SFR:8d"/>
<symbol name="FADDR" address="SFR:8f"/>
<symbol name="P1" address="SFR:90"/>
<symbol name="DPX" address="SFR:93"/>
<symbol name="HADDR" address="SFR:97"/>
<symbol name="SCON" address="SFR:98"/>
<symbol name="SBUF" address="SFR:99"/>
<symbol name="P2" address="SFR:a0"/>
<symbol name="HIE" address="SFR:a1"/>
<symbol name="FIE" address="SFR:a2"/>
<symbol name="FIE1" address="SFR:a3"/>
<symbol name="WDTRST" address="SFR:a6"/>
<symbol name="WCON" address="SFR:a7"/>
<symbol name="IE" address="SFR:a8"/>
<symbol name="SADDR" address="SFR:a9"/>
<symbol name="HSTAT" address="SFR:ae"/>
<symbol name="P3" address="SFR:b0"/>
<symbol name="IEN1" address="SFR:b1"/>
<symbol name="IPL1" address="SFR:b2"/>
<symbol name="IPH1" address="SFR:b3"/>
<symbol name="IPH0" address="SFR:b7"/>
<symbol name="IP" address="SFR:b8"/>
<symbol name="SADEN" address="SFR:b9"/>
<symbol name="SPH" address="SFR:be"/>
<symbol name="FIFLG" address="SFR:c0"/>
<symbol name="FIFLG1" address="SFR:c1"/>
<symbol name="EPCONFIG" address="SFR:c7"/>
<symbol name="T2CON" address="SFR:c8"/>
<symbol name="T2MOD" address="SFR:c9"/>
<symbol name="RCAP2L" address="SFR:ca"/>
<symbol name="RCAP2H" address="SFR:cb"/>
<symbol name="TL2" address="SFR:cc"/>
<symbol name="TH2" address="SFR:cd"/>
<symbol name="HPCON" address="SFR:cf"/>
<symbol name="PSW" address="SFR:d0"/>
<symbol name="PSW1" address="SFR:d1"/>
<symbol name="SOFL" address="SFR:d2"/>
<symbol name="HPINDEX" address="SFR:d4"/>
<symbol name="HPSC" address="SFR:d5"/>
<symbol name="HPSTAT" address="SFR:d7"/>
<symbol name="CCON" address="SFR:d8"/>
<symbol name="CMOD" address="SFR:d9"/>
<symbol name="CCAPM0" address="SFR:da"/>
<symbol name="CCAPM1" address="SFR:db"/>
<symbol name="CCAPM2" address="SFR:dc"/>
<symbol name="CCAPM3" address="SFR:dd"/>
<symbol name="CCAPM4" address="SFR:de"/>
<symbol name="PCON1" address="SFR:df"/>
<symbol name="ACC" address="SFR:e0"/>
<symbol name="EPCON" address="SFR:e1"/>
<symbol name="RXSTAT" address="SFR:e2"/>
<symbol name="RXDAT" address="SFR:e3"/>
<symbol name="RXCON" address="SFR:e4"/>
<symbol name="RXFLG" address="SFR:e5"/>
<symbol name="RXCNTL" address="SFR:e6"/>
<symbol name="RXCNTH" address="SFR:e7"/>
<symbol name="HIFLG" address="SFR:e8"/>
<symbol name="CL" address="SFR:e9"/>
<symbol name="CCAP0L" address="SFR:ea"/>
<symbol name="CCAP1L" address="SFR:eb"/>
<symbol name="CCAP2L" address="SFR:ec"/>
<symbol name="CCAP3L" address="SFR:ed"/>
<symbol name="CCAP4L" address="SFR:ee"/>
<symbol name="B" address="SFR:f0"/>
<symbol name="EPINDEX" address="SFR:f1"/>
<symbol name="TXSTAT" address="SFR:f2"/>
<symbol name="TXDAT" address="SFR:f3"/>
<symbol name="TXCON" address="SFR:f4"/>
<symbol name="TXFLG" address="SFR:f5"/>
<symbol name="TXCNTL" address="SFR:f6"/>
<symbol name="TXCNTH" address="SFR:f7"/>
<symbol name="CH" address="SFR:f9"/>
<symbol name="CCAP0H" address="SFR:fa"/>
<symbol name="CCAP1H" address="SFR:fb"/>
<symbol name="CCAP2H" address="SFR:fc"/>
<symbol name="CCAP3H" address="SFR:fd"/>
<symbol name="CCAP4H" address="SFR:fe"/>
<symbol name="20.0" address="BITS:00"/>
<symbol name="20.1" address="BITS:01"/>
<symbol name="20.2" address="BITS:02"/>
<symbol name="20.3" address="BITS:03"/>
<symbol name="20.4" address="BITS:04"/>
<symbol name="20.5" address="BITS:05"/>
<symbol name="20.6" address="BITS:06"/>
<symbol name="20.7" address="BITS:07"/>
<symbol name="21.0" address="BITS:08"/>
<symbol name="21.1" address="BITS:09"/>
<symbol name="21.2" address="BITS:0a"/>
<symbol name="21.3" address="BITS:0b"/>
<symbol name="21.4" address="BITS:0c"/>
<symbol name="21.5" address="BITS:0d"/>
<symbol name="21.6" address="BITS:0e"/>
<symbol name="21.7" address="BITS:0f"/>
<symbol name="22.0" address="BITS:10"/>
<symbol name="22.1" address="BITS:11"/>
<symbol name="22.2" address="BITS:12"/>
<symbol name="22.3" address="BITS:13"/>
<symbol name="22.4" address="BITS:14"/>
<symbol name="22.5" address="BITS:15"/>
<symbol name="22.6" address="BITS:16"/>
<symbol name="22.7" address="BITS:17"/>
<symbol name="23.0" address="BITS:18"/>
<symbol name="23.1" address="BITS:19"/>
<symbol name="23.2" address="BITS:1a"/>
<symbol name="23.3" address="BITS:1b"/>
<symbol name="23.4" address="BITS:1c"/>
<symbol name="23.5" address="BITS:1d"/>
<symbol name="23.6" address="BITS:1e"/>
<symbol name="23.7" address="BITS:1f"/>
<symbol name="24.0" address="BITS:20"/>
<symbol name="24.1" address="BITS:21"/>
<symbol name="24.2" address="BITS:22"/>
<symbol name="24.3" address="BITS:23"/>
<symbol name="24.4" address="BITS:24"/>
<symbol name="24.5" address="BITS:25"/>
<symbol name="24.6" address="BITS:26"/>
<symbol name="24.7" address="BITS:27"/>
<symbol name="25.0" address="BITS:28"/>
<symbol name="25.1" address="BITS:29"/>
<symbol name="25.2" address="BITS:2a"/>
<symbol name="25.3" address="BITS:2b"/>
<symbol name="25.4" address="BITS:2c"/>
<symbol name="25.5" address="BITS:2d"/>
<symbol name="25.6" address="BITS:2e"/>
<symbol name="25.7" address="BITS:2f"/>
<symbol name="26.0" address="BITS:30"/>
<symbol name="26.1" address="BITS:31"/>
<symbol name="26.2" address="BITS:32"/>
<symbol name="26.3" address="BITS:33"/>
<symbol name="26.4" address="BITS:34"/>
<symbol name="26.5" address="BITS:35"/>
<symbol name="26.6" address="BITS:36"/>
<symbol name="26.7" address="BITS:37"/>
<symbol name="27.0" address="BITS:38"/>
<symbol name="27.1" address="BITS:39"/>
<symbol name="27.2" address="BITS:3a"/>
<symbol name="27.3" address="BITS:3b"/>
<symbol name="27.4" address="BITS:3c"/>
<symbol name="27.5" address="BITS:3d"/>
<symbol name="27.6" address="BITS:3e"/>
<symbol name="27.7" address="BITS:3f"/>
<symbol name="28.0" address="BITS:40"/>
<symbol name="28.1" address="BITS:41"/>
<symbol name="28.2" address="BITS:42"/>
<symbol name="28.3" address="BITS:43"/>
<symbol name="28.4" address="BITS:44"/>
<symbol name="28.5" address="BITS:45"/>
<symbol name="28.6" address="BITS:46"/>
<symbol name="28.7" address="BITS:47"/>
<symbol name="29.0" address="BITS:48"/>
<symbol name="29.1" address="BITS:49"/>
<symbol name="29.2" address="BITS:4a"/>
<symbol name="29.3" address="BITS:4b"/>
<symbol name="29.4" address="BITS:4c"/>
<symbol name="29.5" address="BITS:4d"/>
<symbol name="29.6" address="BITS:4e"/>
<symbol name="29.7" address="BITS:4f"/>
<symbol name="2a.0" address="BITS:50"/>
<symbol name="2a.1" address="BITS:51"/>
<symbol name="2a.2" address="BITS:52"/>
<symbol name="2a.3" address="BITS:53"/>
<symbol name="2a.4" address="BITS:54"/>
<symbol name="2a.5" address="BITS:55"/>
<symbol name="2a.6" address="BITS:56"/>
<symbol name="2a.7" address="BITS:57"/>
<symbol name="2b.0" address="BITS:58"/>
<symbol name="2b.1" address="BITS:59"/>
<symbol name="2b.2" address="BITS:5a"/>
<symbol name="2b.3" address="BITS:5b"/>
<symbol name="2b.4" address="BITS:5c"/>
<symbol name="2b.5" address="BITS:5d"/>
<symbol name="2b.6" address="BITS:5e"/>
<symbol name="2b.7" address="BITS:5f"/>
<symbol name="2c.0" address="BITS:60"/>
<symbol name="2c.1" address="BITS:61"/>
<symbol name="2c.2" address="BITS:62"/>
<symbol name="2c.3" address="BITS:63"/>
<symbol name="2c.4" address="BITS:64"/>
<symbol name="2c.5" address="BITS:65"/>
<symbol name="2c.6" address="BITS:66"/>
<symbol name="2c.7" address="BITS:67"/>
<symbol name="2d.0" address="BITS:68"/>
<symbol name="2d.1" address="BITS:69"/>
<symbol name="2d.2" address="BITS:6a"/>
<symbol name="2d.3" address="BITS:6b"/>
<symbol name="2d.4" address="BITS:6c"/>
<symbol name="2d.5" address="BITS:6d"/>
<symbol name="2d.6" address="BITS:6e"/>
<symbol name="2d.7" address="BITS:6f"/>
<symbol name="2e.0" address="BITS:70"/>
<symbol name="2e.1" address="BITS:71"/>
<symbol name="2e.2" address="BITS:72"/>
<symbol name="2e.3" address="BITS:73"/>
<symbol name="2e.4" address="BITS:74"/>
<symbol name="2e.5" address="BITS:75"/>
<symbol name="2e.6" address="BITS:76"/>
<symbol name="2e.7" address="BITS:77"/>
<symbol name="2f.0" address="BITS:78"/>
<symbol name="2f.1" address="BITS:79"/>
<symbol name="2f.2" address="BITS:7a"/>
<symbol name="2f.3" address="BITS:7b"/>
<symbol name="2f.4" address="BITS:7c"/>
<symbol name="2f.5" address="BITS:7d"/>
<symbol name="2f.6" address="BITS:7e"/>
<symbol name="2f.7" address="BITS:7f"/>
<symbol name="P0.0" address="BITS:80"/>
<symbol name="P0.1" address="BITS:81"/>
<symbol name="P0.2" address="BITS:82"/>
<symbol name="P0.3" address="BITS:83"/>
<symbol name="P0.4" address="BITS:84"/>
<symbol name="P0.5" address="BITS:85"/>
<symbol name="P0.6" address="BITS:86"/>
<symbol name="P0.7" address="BITS:87"/>
<symbol name="IT0" address="BITS:88"/>
<symbol name="IE0" address="BITS:89"/>
<symbol name="IT1" address="BITS:8a"/>
<symbol name="IE1" address="BITS:8b"/>
<symbol name="TR0" address="BITS:8c"/>
<symbol name="TF0" address="BITS:8d"/>
<symbol name="TR1" address="BITS:8e"/>
<symbol name="TF1" address="BITS:8f"/>
<symbol name="P1.0" address="BITS:90"/>
<symbol name="P1.1" address="BITS:91"/>
<symbol name="P1.2" address="BITS:92"/>
<symbol name="P1.3" address="BITS:93"/>
<symbol name="P1.4" address="BITS:94"/>
<symbol name="P1.5" address="BITS:95"/>
<symbol name="P1.6" address="BITS:96"/>
<symbol name="P1.7" address="BITS:97"/>
<symbol name="RI" address="BITS:98"/>
<symbol name="TI" address="BITS:99"/>
<symbol name="RB8" address="BITS:9a"/>
<symbol name="TB8" address="BITS:9b"/>
<symbol name="REN" address="BITS:9c"/>
<symbol name="SM2" address="BITS:9d"/>
<symbol name="SM1" address="BITS:9e"/>
<symbol name="SM0" address="BITS:9f"/>
<symbol name="P2.0" address="BITS:a0"/>
<symbol name="P2.1" address="BITS:a1"/>
<symbol name="P2.2" address="BITS:a2"/>
<symbol name="P2.3" address="BITS:a3"/>
<symbol name="P2.4" address="BITS:a4"/>
<symbol name="P2.5" address="BITS:a5"/>
<symbol name="P2.6" address="BITS:a6"/>
<symbol name="P2.7" address="BITS:a7"/>
<symbol name="EX0" address="BITS:a8"/>
<symbol name="ET0" address="BITS:a9"/>
<symbol name="EX1" address="BITS:aa"/>
<symbol name="ET1" address="BITS:ab"/>
<symbol name="ES" address="BITS:ac"/>
<symbol name="ET2" address="BITS:ad"/>
<symbol name="EC" address="BITS:ae"/>
<symbol name="EA" address="BITS:af"/>
<symbol name="RXD" address="BITS:b0"/>
<symbol name="TXD" address="BITS:b1"/>
<symbol name="INT0" address="BITS:b2"/>
<symbol name="INT1" address="BITS:b3"/>
<symbol name="T0" address="BITS:b4"/>
<symbol name="T1" address="BITS:b5"/>
<symbol name="WR" address="BITS:b6"/>
<symbol name="RD" address="BITS:b7"/>
<symbol name="PX0" address="BITS:b8"/>
<symbol name="PT0" address="BITS:b9"/>
<symbol name="PX1" address="BITS:ba"/>
<symbol name="PT1" address="BITS:bb"/>
<symbol name="PS" address="BITS:bc"/>
<symbol name="PT2" address="BITS:bd"/>
<symbol name="PC" address="BITS:be"/>
<symbol name="IP.7" address="BITS:bf"/>
<symbol name="FIFLG.0" address="BITS:c0"/>
<symbol name="FIFLG.1" address="BITS:c1"/>
<symbol name="FIFLG.2" address="BITS:c2"/>
<symbol name="FIFLG.3" address="BITS:c3"/>
<symbol name="FIFLG.4" address="BITS:c4"/>
<symbol name="FIFLG.5" address="BITS:c5"/>
<symbol name="FIFLG.6" address="BITS:c6"/>
<symbol name="FIFLG.7" address="BITS:c7"/>
<symbol name="CPRL2" address="BITS:c8"/>
<symbol name="CT2" address="BITS:c9"/>
<symbol name="TR2" address="BITS:ca"/>
<symbol name="EXEN2" address="BITS:cb"/>
<symbol name="TCLK" address="BITS:cc"/>
<symbol name="RCLK" address="BITS:cd"/>
<symbol name="EXF2" address="BITS:ce"/>
<symbol name="TF2" address="BITS:cf"/>
<symbol name="P" address="BITS:d0"/>
<symbol name="UD" address="BITS:d1"/>
<symbol name="OV" address="BITS:d2"/>
<symbol name="RS0" address="BITS:d3"/>
<symbol name="RS1" address="BITS:d4"/>
<symbol name="F0" address="BITS:d5"/>
<symbol name="AC" address="BITS:d6"/>
<symbol name="C" address="BITS:d7"/>
<symbol name="CCF.0" address="BITS:d8"/>
<symbol name="CCF.1" address="BITS:d9"/>
<symbol name="CCF.2" address="BITS:da"/>
<symbol name="CCF.3" address="BITS:db"/>
<symbol name="CCF.4" address="BITS:dc"/>
<symbol name="CCON.5" address="BITS:dd"/>
<symbol name="CR" address="BITS:de"/>
<symbol name="CF" address="BITS:df"/>
<symbol name="ACC.0" address="BITS:e0"/>
<symbol name="ACC.1" address="BITS:e1"/>
<symbol name="ACC.2" address="BITS:e2"/>
<symbol name="ACC.3" address="BITS:e3"/>
<symbol name="ACC.4" address="BITS:e4"/>
<symbol name="ACC.5" address="BITS:e5"/>
<symbol name="ACC.6" address="BITS:e6"/>
<symbol name="ACC.7" address="BITS:e7"/>
<symbol name="HIFLG.0" address="BITS:e8"/>
<symbol name="HIFLG.1" address="BITS:e9"/>
<symbol name="HIFLG.2" address="BITS:ea"/>
<symbol name="HIFLG.3" address="BITS:eb"/>
<symbol name="HIFLG.4" address="BITS:ec"/>
<symbol name="HIFLG.5" address="BITS:ed"/>
<symbol name="HIFLG.6" address="BITS:ee"/>
<symbol name="HIFLG.7" address="BITS:ef"/>
<symbol name="B.0" address="BITS:f0"/>
<symbol name="B.1" address="BITS:f1"/>
<symbol name="B.2" address="BITS:f2"/>
<symbol name="B.3" address="BITS:f3"/>
<symbol name="B.4" address="BITS:f4"/>
<symbol name="B.5" address="BITS:f5"/>
<symbol name="B.6" address="BITS:f6"/>
<symbol name="B.7" address="BITS:f7"/>
<symbol name="F8.0" address="BITS:f8"/>
<symbol name="F8.1" address="BITS:f9"/>
<symbol name="F8.2" address="BITS:fa"/>
<symbol name="F8.3" address="BITS:fb"/>
<symbol name="F8.4" address="BITS:fc"/>
<symbol name="F8.5" address="BITS:fd"/>
<symbol name="F8.6" address="BITS:fe"/>
<symbol name="F8.7" address="BITS:ff"/>
</default_symbols>
<default_memory_blocks>
<memory_block name="REG_BANK_1" start_address="INTMEM:0" length="0x8" initialized="false"/>
<memory_block name="REG_BANK_2" start_address="INTMEM:8" length="0x8" initialized="false"/>
<memory_block name="REG_BANK_3" start_address="INTMEM:10" length="0x8" initialized="false"/>
<memory_block name="REG_BANK_4" start_address="INTMEM:18" length="0x8" initialized="false"/>
<memory_block name="INTMEM" start_address="INTMEM:20" length="0xe0" initialized="false"/>
<memory_block name="BITS" start_address="BITS:00" bit_mapped_address="INTMEM:20" length="0x80"/>
<memory_block name="SFR" start_address="SFR:80" length="0x80" initialized="false"/>
<!-- BUG: SFR-BITS do not map properly since only every 8th SFR register is mapped (e.g., 0x80, 0x88, 0x90 ... 0xF0, 0xF8) -->
<memory_block name="SFR-BITS" start_address="BITS:80" bit_mapped_address="SFR:80" length="0x80"/>
</default_memory_blocks>
</processor_spec>
python/icicle/Ghidra/Processors/8051/data/languages/8051.slaspec
+3 -3
View File
@@ -1,3 +1,3 @@
@define MCS51 ""
@include "8051_main.sinc"
@define MCS51 ""
@include "8051_main.sinc"
python/icicle/Ghidra/Processors/8051/data/languages/8051_archimedes.cspec
+99 -99
View File
@@ -1,99 +1,99 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<global>
<range space="CODE"/>
<range space="INTMEM"/>
<range space="SFR"/>
<range space="EXTMEM"/>
<range space="BITS"/>
</global>
<stackpointer register="SP" space="INTMEM" growth="positive"/>
<default_proto>
<prototype name="ret_in_r7" extrapop="-2" stackshift="-2" strategy="register">
<input>
<pentry maxsize="1" minsize="1">
<register name="R1"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="R2"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="R3"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="R4"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="R5"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="R6"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="R7"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="ACC"/>
</pentry>
</input>
<output>
<pentry maxsize="1" minsize="1">
<register name="R7"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
</unaffected>
<!-- This first range lists the permissible stack offsets
that can be used as scratch and/or local variables -->
<localrange>
<range space="stack" first="0x0" last="0xf"/>
</localrange>
</prototype>
</default_proto>
<prototype name="ret_in_a" extrapop="-2" stackshift="-2" strategy="register">
<input>
<pentry maxsize="1" minsize="1">
<register name="R1"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="R2"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="R3"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="R4"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="R5"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="R6"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="R7"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="ACC"/>
</pentry>
</input>
<output>
<pentry maxsize="1" minsize="1">
<register name="ACC"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
</unaffected>
<!-- This first range lists the permissible stack offsets
that can be used as scratch and/or local variables -->
<localrange>
<range space="stack" first="0x0" last="0xf"/>
</localrange>
</prototype>
</compiler_spec>
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<global>
<range space="CODE"/>
<range space="INTMEM"/>
<range space="SFR"/>
<range space="EXTMEM"/>
<range space="BITS"/>
</global>
<stackpointer register="SP" space="INTMEM" growth="positive"/>
<default_proto>
<prototype name="ret_in_r7" extrapop="-2" stackshift="-2" strategy="register">
<input>
<pentry maxsize="1" minsize="1">
<register name="R1"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="R2"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="R3"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="R4"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="R5"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="R6"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="R7"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="ACC"/>
</pentry>
</input>
<output>
<pentry maxsize="1" minsize="1">
<register name="R7"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
</unaffected>
<!-- This first range lists the permissible stack offsets
that can be used as scratch and/or local variables -->
<localrange>
<range space="stack" first="0x0" last="0xf"/>
</localrange>
</prototype>
</default_proto>
<prototype name="ret_in_a" extrapop="-2" stackshift="-2" strategy="register">
<input>
<pentry maxsize="1" minsize="1">
<register name="R1"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="R2"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="R3"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="R4"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="R5"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="R6"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="R7"/>
</pentry>
<pentry maxsize="1" minsize="1">
<register name="ACC"/>
</pentry>
</input>
<output>
<pentry maxsize="1" minsize="1">
<register name="ACC"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
</unaffected>
<!-- This first range lists the permissible stack offsets
that can be used as scratch and/or local variables -->
<localrange>
<range space="stack" first="0x0" last="0xf"/>
</localrange>
</prototype>
</compiler_spec>
python/icicle/Ghidra/Processors/8051/data/languages/8051_main.sinc
+917 -917
View File
File diff suppressed because it is too large Load Diff
python/icicle/Ghidra/Processors/8051/data/languages/mx51.cspec
+73 -73
View File
@@ -1,73 +1,73 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<global>
<range space="RAM"/>
<range space="SFR"/>
<range space="ESFR"/>
<range space="BITS"/>
<range space="EBITS"/>
</global>
<stackpointer register="SP" space="RAM" growth="positive"/>
<default_proto>
<!-- Removed push / pop around calls to clear up decompilation -->
<prototype name="__keilmxs3" extrapop="0" stackshift="0" strategy="register">
<input>
<pentry minsize="1" maxsize="2">
<register name="R6R7"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="R4R5"/>
</pentry>
<pentry minsize="1" maxsize="2">
<!-- Expect to see R3R2R1 as an endian swapped pointer a lot -->
<register name="R2R3"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="2">
<register name="R6R7"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
</unaffected>
<localrange>
<range space="stack" first="0x1" last="0x0fc"/>
</localrange>
<!-- <localrange> -->
<!-- <range space="stack" first="0x0" last="0xf"/> -->
<!-- </localrange> -->
</prototype>
</default_proto>
<!-- Add in additional Keil prototypes -->
<prototype name="__keilmxs2p1" extrapop="0" stackshift="0" strategy="register">
<input>
<pentry minsize="1" maxsize="2">
<register name="R6R7"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="R4R5"/>
</pentry>
<pentry minsize="3" maxsize="3">
<!-- Technically will be endian swapped -->
<register name="R1R2R3"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="2">
<register name="R6R7"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
</unaffected>
<localrange>
<range space="stack" first="0x1" last="0x0fc"/>
</localrange>
<!-- <localrange> -->
<!-- <range space="stack" first="0x0" last="0xf"/> -->
<!-- </localrange> -->
</prototype>
</compiler_spec>
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<global>
<range space="RAM"/>
<range space="SFR"/>
<range space="ESFR"/>
<range space="BITS"/>
<range space="EBITS"/>
</global>
<stackpointer register="SP" space="RAM" growth="positive"/>
<default_proto>
<!-- Removed push / pop around calls to clear up decompilation -->
<prototype name="__keilmxs3" extrapop="0" stackshift="0" strategy="register">
<input>
<pentry minsize="1" maxsize="2">
<register name="R6R7"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="R4R5"/>
</pentry>
<pentry minsize="1" maxsize="2">
<!-- Expect to see R3R2R1 as an endian swapped pointer a lot -->
<register name="R2R3"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="2">
<register name="R6R7"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
</unaffected>
<localrange>
<range space="stack" first="0x1" last="0x0fc"/>
</localrange>
<!-- <localrange> -->
<!-- <range space="stack" first="0x0" last="0xf"/> -->
<!-- </localrange> -->
</prototype>
</default_proto>
<!-- Add in additional Keil prototypes -->
<prototype name="__keilmxs2p1" extrapop="0" stackshift="0" strategy="register">
<input>
<pentry minsize="1" maxsize="2">
<register name="R6R7"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="R4R5"/>
</pentry>
<pentry minsize="3" maxsize="3">
<!-- Technically will be endian swapped -->
<register name="R1R2R3"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="2">
<register name="R6R7"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
</unaffected>
<localrange>
<range space="stack" first="0x1" last="0x0fc"/>
</localrange>
<!-- <localrange> -->
<!-- <range space="stack" first="0x0" last="0xf"/> -->
<!-- </localrange> -->
</prototype>
</compiler_spec>
python/icicle/Ghidra/Processors/8051/data/languages/mx51.pspec
+423 -423
View File
@@ -1,423 +1,423 @@
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="PC"/>
<volatile outputop="write_volatile" inputop="read_volatile">
<range space="SFR" first="0x0" last="0xFF"/>
<range space="BITS" first="0x80" last="0xFF"/>
</volatile>
<default_symbols>
<symbol name="BANK0_R0" address="RAM:7f0000"/>
<symbol name="BANK0_R1" address="RAM:7f0001"/>
<symbol name="BANK0_R2" address="RAM:7f0002"/>
<symbol name="BANK0_R3" address="RAM:7f0003"/>
<symbol name="BANK0_R4" address="RAM:7f0004"/>
<symbol name="BANK0_R5" address="RAM:7f0005"/>
<symbol name="BANK0_R6" address="RAM:7f0006"/>
<symbol name="BANK0_R7" address="RAM:7f0007"/>
<symbol name="BANK1_R0" address="RAM:7f0008"/>
<symbol name="BANK1_R1" address="RAM:7f0009"/>
<symbol name="BANK1_R2" address="RAM:7f000a"/>
<symbol name="BANK1_R3" address="RAM:7f000b"/>
<symbol name="BANK1_R4" address="RAM:7f000c"/>
<symbol name="BANK1_R5" address="RAM:7f000d"/>
<symbol name="BANK1_R6" address="RAM:7f000e"/>
<symbol name="BANK1_R7" address="RAM:7f000f"/>
<symbol name="BANK2_R0" address="RAM:7f0010"/>
<symbol name="BANK2_R1" address="RAM:7f0011"/>
<symbol name="BANK2_R2" address="RAM:7f0012"/>
<symbol name="BANK2_R3" address="RAM:7f0013"/>
<symbol name="BANK2_R4" address="RAM:7f0014"/>
<symbol name="BANK2_R5" address="RAM:7f0015"/>
<symbol name="BANK2_R6" address="RAM:7f0016"/>
<symbol name="BANK2_R7" address="RAM:7f0017"/>
<symbol name="BANK3_R0" address="RAM:7f0018"/>
<symbol name="BANK3_R1" address="RAM:7f0019"/>
<symbol name="BANK3_R2" address="RAM:7f001a"/>
<symbol name="BANK3_R3" address="RAM:7f001b"/>
<symbol name="BANK3_R4" address="RAM:7f001c"/>
<symbol name="BANK3_R5" address="RAM:7f001d"/>
<symbol name="BANK3_R6" address="RAM:7f001e"/>
<symbol name="BANK3_R7" address="RAM:7f001f"/>
<symbol name="P0" address="SFR:80"/>
<symbol name="SP" address="SFR:81"/>
<symbol name="DPL" address="SFR:82"/>
<symbol name="DPH" address="SFR:83"/>
<symbol name="DPXL" address="SFR:84"/>
<symbol name="PCON" address="SFR:87"/>
<symbol name="TCON" address="SFR:88"/>
<symbol name="TMOD" address="SFR:89"/>
<symbol name="TL0" address="SFR:8a"/>
<symbol name="TL1" address="SFR:8b"/>
<symbol name="TH0" address="SFR:8c"/>
<symbol name="TH1" address="SFR:8d"/>
<symbol name="FADDR" address="SFR:8f"/>
<symbol name="P1" address="SFR:90"/>
<symbol name="DPX" address="SFR:93"/>
<symbol name="HADDR" address="SFR:97"/>
<symbol name="SCON" address="SFR:98"/>
<symbol name="SBUF" address="SFR:99"/>
<symbol name="P2" address="SFR:a0"/>
<symbol name="HIE" address="SFR:a1"/>
<symbol name="FIE" address="SFR:a2"/>
<symbol name="FIE1" address="SFR:a3"/>
<symbol name="WDTRST" address="SFR:a6"/>
<symbol name="WCON" address="SFR:a7"/>
<symbol name="IE" address="SFR:a8"/>
<symbol name="SADDR" address="SFR:a9"/>
<symbol name="HSTAT" address="SFR:ae"/>
<symbol name="P3" address="SFR:b0"/>
<symbol name="IEN1" address="SFR:b1"/>
<symbol name="IPL1" address="SFR:b2"/>
<symbol name="IPH1" address="SFR:b3"/>
<symbol name="IPH0" address="SFR:b7"/>
<symbol name="IP" address="SFR:b8"/>
<symbol name="SADEN" address="SFR:b9"/>
<symbol name="SPH" address="SFR:be"/>
<symbol name="FIFLG" address="SFR:c0"/>
<symbol name="FIFLG1" address="SFR:c1"/>
<symbol name="EPCONFIG" address="SFR:c7"/>
<symbol name="T2CON" address="SFR:c8"/>
<symbol name="T2MOD" address="SFR:c9"/>
<symbol name="RCAP2L" address="SFR:ca"/>
<symbol name="RCAP2H" address="SFR:cb"/>
<symbol name="TL2" address="SFR:cc"/>
<symbol name="TH2" address="SFR:cd"/>
<symbol name="HPCON" address="SFR:cf"/>
<symbol name="PSW" address="SFR:d0"/>
<symbol name="PSW1" address="SFR:d1"/>
<symbol name="SOFL" address="SFR:d2"/>
<symbol name="HPINDEX" address="SFR:d4"/>
<symbol name="HPSC" address="SFR:d5"/>
<symbol name="HPSTAT" address="SFR:d7"/>
<symbol name="CCON" address="SFR:d8"/>
<symbol name="CMOD" address="SFR:d9"/>
<symbol name="CCAPM0" address="SFR:da"/>
<symbol name="CCAPM1" address="SFR:db"/>
<symbol name="CCAPM2" address="SFR:dc"/>
<symbol name="CCAPM3" address="SFR:dd"/>
<symbol name="CCAPM4" address="SFR:de"/>
<symbol name="PCON1" address="SFR:df"/>
<symbol name="ACC" address="SFR:e0"/>
<symbol name="EPCON" address="SFR:e1"/>
<symbol name="RXSTAT" address="SFR:e2"/>
<symbol name="RXDAT" address="SFR:e3"/>
<symbol name="RXCON" address="SFR:e4"/>
<symbol name="RXFLG" address="SFR:e5"/>
<symbol name="RXCNTL" address="SFR:e6"/>
<symbol name="RXCNTH" address="SFR:e7"/>
<symbol name="HIFLG" address="SFR:e8"/>
<symbol name="CL" address="SFR:e9"/>
<symbol name="CCAP0L" address="SFR:ea"/>
<symbol name="CCAP1L" address="SFR:eb"/>
<symbol name="CCAP2L" address="SFR:ec"/>
<symbol name="CCAP3L" address="SFR:ed"/>
<symbol name="CCAP4L" address="SFR:ee"/>
<symbol name="B" address="SFR:f0"/>
<symbol name="EPINDEX" address="SFR:f1"/>
<symbol name="TXSTAT" address="SFR:f2"/>
<symbol name="TXDAT" address="SFR:f3"/>
<symbol name="TXCON" address="SFR:f4"/>
<symbol name="TXFLG" address="SFR:f5"/>
<symbol name="TXCNTL" address="SFR:f6"/>
<symbol name="TXCNTH" address="SFR:f7"/>
<symbol name="CH" address="SFR:f9"/>
<symbol name="CCAP0H" address="SFR:fa"/>
<symbol name="CCAP1H" address="SFR:fb"/>
<symbol name="CCAP2H" address="SFR:fc"/>
<symbol name="CCAP3H" address="SFR:fd"/>
<symbol name="CCAP4H" address="SFR:fe"/>
<symbol name="SPE" address="ESFR:fb"/>
<symbol name="EPL" address="ESFR:fc"/>
<symbol name="EPM" address="ESFR:fd"/>
<symbol name="EPH" address="ESFR:fe"/>
<symbol name="MXCON" address="ESFR:ff"/>
<symbol name="20.0" address="BITS:00"/>
<symbol name="20.1" address="BITS:01"/>
<symbol name="20.2" address="BITS:02"/>
<symbol name="20.3" address="BITS:03"/>
<symbol name="20.4" address="BITS:04"/>
<symbol name="20.5" address="BITS:05"/>
<symbol name="20.6" address="BITS:06"/>
<symbol name="20.7" address="BITS:07"/>
<symbol name="21.0" address="BITS:08"/>
<symbol name="21.1" address="BITS:09"/>
<symbol name="21.2" address="BITS:0a"/>
<symbol name="21.3" address="BITS:0b"/>
<symbol name="21.4" address="BITS:0c"/>
<symbol name="21.5" address="BITS:0d"/>
<symbol name="21.6" address="BITS:0e"/>
<symbol name="21.7" address="BITS:0f"/>
<symbol name="22.0" address="BITS:10"/>
<symbol name="22.1" address="BITS:11"/>
<symbol name="22.2" address="BITS:12"/>
<symbol name="22.3" address="BITS:13"/>
<symbol name="22.4" address="BITS:14"/>
<symbol name="22.5" address="BITS:15"/>
<symbol name="22.6" address="BITS:16"/>
<symbol name="22.7" address="BITS:17"/>
<symbol name="23.0" address="BITS:18"/>
<symbol name="23.1" address="BITS:19"/>
<symbol name="23.2" address="BITS:1a"/>
<symbol name="23.3" address="BITS:1b"/>
<symbol name="23.4" address="BITS:1c"/>
<symbol name="23.5" address="BITS:1d"/>
<symbol name="23.6" address="BITS:1e"/>
<symbol name="23.7" address="BITS:1f"/>
<symbol name="24.0" address="BITS:20"/>
<symbol name="24.1" address="BITS:21"/>
<symbol name="24.2" address="BITS:22"/>
<symbol name="24.3" address="BITS:23"/>
<symbol name="24.4" address="BITS:24"/>
<symbol name="24.5" address="BITS:25"/>
<symbol name="24.6" address="BITS:26"/>
<symbol name="24.7" address="BITS:27"/>
<symbol name="25.0" address="BITS:28"/>
<symbol name="25.1" address="BITS:29"/>
<symbol name="25.2" address="BITS:2a"/>
<symbol name="25.3" address="BITS:2b"/>
<symbol name="25.4" address="BITS:2c"/>
<symbol name="25.5" address="BITS:2d"/>
<symbol name="25.6" address="BITS:2e"/>
<symbol name="25.7" address="BITS:2f"/>
<symbol name="26.0" address="BITS:30"/>
<symbol name="26.1" address="BITS:31"/>
<symbol name="26.2" address="BITS:32"/>
<symbol name="26.3" address="BITS:33"/>
<symbol name="26.4" address="BITS:34"/>
<symbol name="26.5" address="BITS:35"/>
<symbol name="26.6" address="BITS:36"/>
<symbol name="26.7" address="BITS:37"/>
<symbol name="27.0" address="BITS:38"/>
<symbol name="27.1" address="BITS:39"/>
<symbol name="27.2" address="BITS:3a"/>
<symbol name="27.3" address="BITS:3b"/>
<symbol name="27.4" address="BITS:3c"/>
<symbol name="27.5" address="BITS:3d"/>
<symbol name="27.6" address="BITS:3e"/>
<symbol name="27.7" address="BITS:3f"/>
<symbol name="28.0" address="BITS:40"/>
<symbol name="28.1" address="BITS:41"/>
<symbol name="28.2" address="BITS:42"/>
<symbol name="28.3" address="BITS:43"/>
<symbol name="28.4" address="BITS:44"/>
<symbol name="28.5" address="BITS:45"/>
<symbol name="28.6" address="BITS:46"/>
<symbol name="28.7" address="BITS:47"/>
<symbol name="29.0" address="BITS:48"/>
<symbol name="29.1" address="BITS:49"/>
<symbol name="29.2" address="BITS:4a"/>
<symbol name="29.3" address="BITS:4b"/>
<symbol name="29.4" address="BITS:4c"/>
<symbol name="29.5" address="BITS:4d"/>
<symbol name="29.6" address="BITS:4e"/>
<symbol name="29.7" address="BITS:4f"/>
<symbol name="2a.0" address="BITS:50"/>
<symbol name="2a.1" address="BITS:51"/>
<symbol name="2a.2" address="BITS:52"/>
<symbol name="2a.3" address="BITS:53"/>
<symbol name="2a.4" address="BITS:54"/>
<symbol name="2a.5" address="BITS:55"/>
<symbol name="2a.6" address="BITS:56"/>
<symbol name="2a.7" address="BITS:57"/>
<symbol name="2b.0" address="BITS:58"/>
<symbol name="2b.1" address="BITS:59"/>
<symbol name="2b.2" address="BITS:5a"/>
<symbol name="2b.3" address="BITS:5b"/>
<symbol name="2b.4" address="BITS:5c"/>
<symbol name="2b.5" address="BITS:5d"/>
<symbol name="2b.6" address="BITS:5e"/>
<symbol name="2b.7" address="BITS:5f"/>
<symbol name="2c.0" address="BITS:60"/>
<symbol name="2c.1" address="BITS:61"/>
<symbol name="2c.2" address="BITS:62"/>
<symbol name="2c.3" address="BITS:63"/>
<symbol name="2c.4" address="BITS:64"/>
<symbol name="2c.5" address="BITS:65"/>
<symbol name="2c.6" address="BITS:66"/>
<symbol name="2c.7" address="BITS:67"/>
<symbol name="2d.0" address="BITS:68"/>
<symbol name="2d.1" address="BITS:69"/>
<symbol name="2d.2" address="BITS:6a"/>
<symbol name="2d.3" address="BITS:6b"/>
<symbol name="2d.4" address="BITS:6c"/>
<symbol name="2d.5" address="BITS:6d"/>
<symbol name="2d.6" address="BITS:6e"/>
<symbol name="2d.7" address="BITS:6f"/>
<symbol name="2e.0" address="BITS:70"/>
<symbol name="2e.1" address="BITS:71"/>
<symbol name="2e.2" address="BITS:72"/>
<symbol name="2e.3" address="BITS:73"/>
<symbol name="2e.4" address="BITS:74"/>
<symbol name="2e.5" address="BITS:75"/>
<symbol name="2e.6" address="BITS:76"/>
<symbol name="2e.7" address="BITS:77"/>
<symbol name="2f.0" address="BITS:78"/>
<symbol name="2f.1" address="BITS:79"/>
<symbol name="2f.2" address="BITS:7a"/>
<symbol name="2f.3" address="BITS:7b"/>
<symbol name="2f.4" address="BITS:7c"/>
<symbol name="2f.5" address="BITS:7d"/>
<symbol name="2f.6" address="BITS:7e"/>
<symbol name="2f.7" address="BITS:7f"/>
<symbol name="P0.0" address="BITS:80"/>
<symbol name="P0.1" address="BITS:81"/>
<symbol name="P0.2" address="BITS:82"/>
<symbol name="P0.3" address="BITS:83"/>
<symbol name="P0.4" address="BITS:84"/>
<symbol name="P0.5" address="BITS:85"/>
<symbol name="P0.6" address="BITS:86"/>
<symbol name="P0.7" address="BITS:87"/>
<symbol name="IT0" address="BITS:88"/>
<symbol name="IE0" address="BITS:89"/>
<symbol name="IT1" address="BITS:8a"/>
<symbol name="IE1" address="BITS:8b"/>
<symbol name="TR0" address="BITS:8c"/>
<symbol name="TF0" address="BITS:8d"/>
<symbol name="TR1" address="BITS:8e"/>
<symbol name="TF1" address="BITS:8f"/>
<symbol name="P1.0" address="BITS:90"/>
<symbol name="P1.1" address="BITS:91"/>
<symbol name="P1.2" address="BITS:92"/>
<symbol name="P1.3" address="BITS:93"/>
<symbol name="P1.4" address="BITS:94"/>
<symbol name="P1.5" address="BITS:95"/>
<symbol name="P1.6" address="BITS:96"/>
<symbol name="P1.7" address="BITS:97"/>
<symbol name="RI" address="BITS:98"/>
<symbol name="TI" address="BITS:99"/>
<symbol name="RB8" address="BITS:9a"/>
<symbol name="TB8" address="BITS:9b"/>
<symbol name="REN" address="BITS:9c"/>
<symbol name="SM2" address="BITS:9d"/>
<symbol name="SM1" address="BITS:9e"/>
<symbol name="SM0" address="BITS:9f"/>
<symbol name="P2.0" address="BITS:a0"/>
<symbol name="P2.1" address="BITS:a1"/>
<symbol name="P2.2" address="BITS:a2"/>
<symbol name="P2.3" address="BITS:a3"/>
<symbol name="P2.4" address="BITS:a4"/>
<symbol name="P2.5" address="BITS:a5"/>
<symbol name="P2.6" address="BITS:a6"/>
<symbol name="P2.7" address="BITS:a7"/>
<symbol name="EX0" address="BITS:a8"/>
<symbol name="ET0" address="BITS:a9"/>
<symbol name="EX1" address="BITS:aa"/>
<symbol name="ET1" address="BITS:ab"/>
<symbol name="ES" address="BITS:ac"/>
<symbol name="ET2" address="BITS:ad"/>
<symbol name="EC" address="BITS:ae"/>
<symbol name="EA" address="BITS:af"/>
<symbol name="RXD" address="BITS:b0"/>
<symbol name="TXD" address="BITS:b1"/>
<symbol name="INT0" address="BITS:b2"/>
<symbol name="INT1" address="BITS:b3"/>
<symbol name="T0" address="BITS:b4"/>
<symbol name="T1" address="BITS:b5"/>
<symbol name="WR" address="BITS:b6"/>
<symbol name="RD" address="BITS:b7"/>
<symbol name="PX0" address="BITS:b8"/>
<symbol name="PT0" address="BITS:b9"/>
<symbol name="PX1" address="BITS:ba"/>
<symbol name="PT1" address="BITS:bb"/>
<symbol name="PS" address="BITS:bc"/>
<symbol name="PT2" address="BITS:bd"/>
<symbol name="PC" address="BITS:be"/>
<symbol name="IP.7" address="BITS:bf"/>
<symbol name="FIFLG.0" address="BITS:c0"/>
<symbol name="FIFLG.1" address="BITS:c1"/>
<symbol name="FIFLG.2" address="BITS:c2"/>
<symbol name="FIFLG.3" address="BITS:c3"/>
<symbol name="FIFLG.4" address="BITS:c4"/>
<symbol name="FIFLG.5" address="BITS:c5"/>
<symbol name="FIFLG.6" address="BITS:c6"/>
<symbol name="FIFLG.7" address="BITS:c7"/>
<symbol name="CPRL2" address="BITS:c8"/>
<symbol name="CT2" address="BITS:c9"/>
<symbol name="TR2" address="BITS:ca"/>
<symbol name="EXEN2" address="BITS:cb"/>
<symbol name="TCLK" address="BITS:cc"/>
<symbol name="RCLK" address="BITS:cd"/>
<symbol name="EXF2" address="BITS:ce"/>
<symbol name="TF2" address="BITS:cf"/>
<symbol name="P" address="BITS:d0"/>
<symbol name="UD" address="BITS:d1"/>
<symbol name="OV" address="BITS:d2"/>
<symbol name="RS0" address="BITS:d3"/>
<symbol name="RS1" address="BITS:d4"/>
<symbol name="F0" address="BITS:d5"/>
<symbol name="AC" address="BITS:d6"/>
<symbol name="C" address="BITS:d7"/>
<symbol name="CCF.0" address="BITS:d8"/>
<symbol name="CCF.1" address="BITS:d9"/>
<symbol name="CCF.2" address="BITS:da"/>
<symbol name="CCF.3" address="BITS:db"/>
<symbol name="CCF.4" address="BITS:dc"/>
<symbol name="CCON.5" address="BITS:dd"/>
<symbol name="CR" address="BITS:de"/>
<symbol name="CF" address="BITS:df"/>
<symbol name="ACC.0" address="BITS:e0"/>
<symbol name="ACC.1" address="BITS:e1"/>
<symbol name="ACC.2" address="BITS:e2"/>
<symbol name="ACC.3" address="BITS:e3"/>
<symbol name="ACC.4" address="BITS:e4"/>
<symbol name="ACC.5" address="BITS:e5"/>
<symbol name="ACC.6" address="BITS:e6"/>
<symbol name="ACC.7" address="BITS:e7"/>
<symbol name="HIFLG.0" address="BITS:e8"/>
<symbol name="HIFLG.1" address="BITS:e9"/>
<symbol name="HIFLG.2" address="BITS:ea"/>
<symbol name="HIFLG.3" address="BITS:eb"/>
<symbol name="HIFLG.4" address="BITS:ec"/>
<symbol name="HIFLG.5" address="BITS:ed"/>
<symbol name="HIFLG.6" address="BITS:ee"/>
<symbol name="HIFLG.7" address="BITS:ef"/>
<symbol name="B.0" address="BITS:f0"/>
<symbol name="B.1" address="BITS:f1"/>
<symbol name="B.2" address="BITS:f2"/>
<symbol name="B.3" address="BITS:f3"/>
<symbol name="B.4" address="BITS:f4"/>
<symbol name="B.5" address="BITS:f5"/>
<symbol name="B.6" address="BITS:f6"/>
<symbol name="B.7" address="BITS:f7"/>
<symbol name="F8.0" address="BITS:f8"/>
<symbol name="F8.1" address="BITS:f9"/>
<symbol name="F8.2" address="BITS:fa"/>
<symbol name="F8.3" address="BITS:fb"/>
<symbol name="F8.4" address="BITS:fc"/>
<symbol name="F8.5" address="BITS:fd"/>
<symbol name="F8.6" address="BITS:fe"/>
<symbol name="F8.7" address="BITS:ff"/>
</default_symbols>
<default_memory_blocks>
<memory_block name="REG_BANK_1" start_address="RAM:7f0000" length="0x8" initialized="false"/>
<memory_block name="REG_BANK_2" start_address="RAM:7f0008" length="0x8" initialized="false"/>
<memory_block name="REG_BANK_3" start_address="RAM:7f0010" length="0x8" initialized="false"/>
<memory_block name="REG_BANK_4" start_address="RAM:7f0018" length="0x8" initialized="false"/>
<memory_block name="INTMEM" start_address="RAM:7f0020" length="0xe0" initialized="false"/>
<memory_block name="EXTMEM" start_address="RAM:0" length="0x1000" initialized="false"/>
<memory_block name="BITS" start_address="BITS:00" bit_mapped_address="RAM:7f0020" length="0x80"/>
<memory_block name="SFR" start_address="SFR:80" length="0x80" initialized="false"/>
<memory_block name="ESFR" start_address="ESFR:80" length="0x80" initialized="false"/>
<memory_block name="EBITS" start_address="EBITS:00" bit_mapped_address="RAM:7f0020" length="0x80"/>
<!-- BUG: SFR-BITS do not map properly since only every 8th SFR register is mapped (e.g., 0x80, 0x88, 0x90 ... 0xF0, 0xF8) -->
<memory_block name="SFR-BITS" start_address="BITS:80" bit_mapped_address="SFR:80" length="0x80"/>
<memory_block name="ESFR-BITS" start_address="EBITS:80" bit_mapped_address="ESFR:80" length="0x80"/>
</default_memory_blocks>
</processor_spec>
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="PC"/>
<volatile outputop="write_volatile" inputop="read_volatile">
<range space="SFR" first="0x0" last="0xFF"/>
<range space="BITS" first="0x80" last="0xFF"/>
</volatile>
<default_symbols>
<symbol name="BANK0_R0" address="RAM:7f0000"/>
<symbol name="BANK0_R1" address="RAM:7f0001"/>
<symbol name="BANK0_R2" address="RAM:7f0002"/>
<symbol name="BANK0_R3" address="RAM:7f0003"/>
<symbol name="BANK0_R4" address="RAM:7f0004"/>
<symbol name="BANK0_R5" address="RAM:7f0005"/>
<symbol name="BANK0_R6" address="RAM:7f0006"/>
<symbol name="BANK0_R7" address="RAM:7f0007"/>
<symbol name="BANK1_R0" address="RAM:7f0008"/>
<symbol name="BANK1_R1" address="RAM:7f0009"/>
<symbol name="BANK1_R2" address="RAM:7f000a"/>
<symbol name="BANK1_R3" address="RAM:7f000b"/>
<symbol name="BANK1_R4" address="RAM:7f000c"/>
<symbol name="BANK1_R5" address="RAM:7f000d"/>
<symbol name="BANK1_R6" address="RAM:7f000e"/>
<symbol name="BANK1_R7" address="RAM:7f000f"/>
<symbol name="BANK2_R0" address="RAM:7f0010"/>
<symbol name="BANK2_R1" address="RAM:7f0011"/>
<symbol name="BANK2_R2" address="RAM:7f0012"/>
<symbol name="BANK2_R3" address="RAM:7f0013"/>
<symbol name="BANK2_R4" address="RAM:7f0014"/>
<symbol name="BANK2_R5" address="RAM:7f0015"/>
<symbol name="BANK2_R6" address="RAM:7f0016"/>
<symbol name="BANK2_R7" address="RAM:7f0017"/>
<symbol name="BANK3_R0" address="RAM:7f0018"/>
<symbol name="BANK3_R1" address="RAM:7f0019"/>
<symbol name="BANK3_R2" address="RAM:7f001a"/>
<symbol name="BANK3_R3" address="RAM:7f001b"/>
<symbol name="BANK3_R4" address="RAM:7f001c"/>
<symbol name="BANK3_R5" address="RAM:7f001d"/>
<symbol name="BANK3_R6" address="RAM:7f001e"/>
<symbol name="BANK3_R7" address="RAM:7f001f"/>
<symbol name="P0" address="SFR:80"/>
<symbol name="SP" address="SFR:81"/>
<symbol name="DPL" address="SFR:82"/>
<symbol name="DPH" address="SFR:83"/>
<symbol name="DPXL" address="SFR:84"/>
<symbol name="PCON" address="SFR:87"/>
<symbol name="TCON" address="SFR:88"/>
<symbol name="TMOD" address="SFR:89"/>
<symbol name="TL0" address="SFR:8a"/>
<symbol name="TL1" address="SFR:8b"/>
<symbol name="TH0" address="SFR:8c"/>
<symbol name="TH1" address="SFR:8d"/>
<symbol name="FADDR" address="SFR:8f"/>
<symbol name="P1" address="SFR:90"/>
<symbol name="DPX" address="SFR:93"/>
<symbol name="HADDR" address="SFR:97"/>
<symbol name="SCON" address="SFR:98"/>
<symbol name="SBUF" address="SFR:99"/>
<symbol name="P2" address="SFR:a0"/>
<symbol name="HIE" address="SFR:a1"/>
<symbol name="FIE" address="SFR:a2"/>
<symbol name="FIE1" address="SFR:a3"/>
<symbol name="WDTRST" address="SFR:a6"/>
<symbol name="WCON" address="SFR:a7"/>
<symbol name="IE" address="SFR:a8"/>
<symbol name="SADDR" address="SFR:a9"/>
<symbol name="HSTAT" address="SFR:ae"/>
<symbol name="P3" address="SFR:b0"/>
<symbol name="IEN1" address="SFR:b1"/>
<symbol name="IPL1" address="SFR:b2"/>
<symbol name="IPH1" address="SFR:b3"/>
<symbol name="IPH0" address="SFR:b7"/>
<symbol name="IP" address="SFR:b8"/>
<symbol name="SADEN" address="SFR:b9"/>
<symbol name="SPH" address="SFR:be"/>
<symbol name="FIFLG" address="SFR:c0"/>
<symbol name="FIFLG1" address="SFR:c1"/>
<symbol name="EPCONFIG" address="SFR:c7"/>
<symbol name="T2CON" address="SFR:c8"/>
<symbol name="T2MOD" address="SFR:c9"/>
<symbol name="RCAP2L" address="SFR:ca"/>
<symbol name="RCAP2H" address="SFR:cb"/>
<symbol name="TL2" address="SFR:cc"/>
<symbol name="TH2" address="SFR:cd"/>
<symbol name="HPCON" address="SFR:cf"/>
<symbol name="PSW" address="SFR:d0"/>
<symbol name="PSW1" address="SFR:d1"/>
<symbol name="SOFL" address="SFR:d2"/>
<symbol name="HPINDEX" address="SFR:d4"/>
<symbol name="HPSC" address="SFR:d5"/>
<symbol name="HPSTAT" address="SFR:d7"/>
<symbol name="CCON" address="SFR:d8"/>
<symbol name="CMOD" address="SFR:d9"/>
<symbol name="CCAPM0" address="SFR:da"/>
<symbol name="CCAPM1" address="SFR:db"/>
<symbol name="CCAPM2" address="SFR:dc"/>
<symbol name="CCAPM3" address="SFR:dd"/>
<symbol name="CCAPM4" address="SFR:de"/>
<symbol name="PCON1" address="SFR:df"/>
<symbol name="ACC" address="SFR:e0"/>
<symbol name="EPCON" address="SFR:e1"/>
<symbol name="RXSTAT" address="SFR:e2"/>
<symbol name="RXDAT" address="SFR:e3"/>
<symbol name="RXCON" address="SFR:e4"/>
<symbol name="RXFLG" address="SFR:e5"/>
<symbol name="RXCNTL" address="SFR:e6"/>
<symbol name="RXCNTH" address="SFR:e7"/>
<symbol name="HIFLG" address="SFR:e8"/>
<symbol name="CL" address="SFR:e9"/>
<symbol name="CCAP0L" address="SFR:ea"/>
<symbol name="CCAP1L" address="SFR:eb"/>
<symbol name="CCAP2L" address="SFR:ec"/>
<symbol name="CCAP3L" address="SFR:ed"/>
<symbol name="CCAP4L" address="SFR:ee"/>
<symbol name="B" address="SFR:f0"/>
<symbol name="EPINDEX" address="SFR:f1"/>
<symbol name="TXSTAT" address="SFR:f2"/>
<symbol name="TXDAT" address="SFR:f3"/>
<symbol name="TXCON" address="SFR:f4"/>
<symbol name="TXFLG" address="SFR:f5"/>
<symbol name="TXCNTL" address="SFR:f6"/>
<symbol name="TXCNTH" address="SFR:f7"/>
<symbol name="CH" address="SFR:f9"/>
<symbol name="CCAP0H" address="SFR:fa"/>
<symbol name="CCAP1H" address="SFR:fb"/>
<symbol name="CCAP2H" address="SFR:fc"/>
<symbol name="CCAP3H" address="SFR:fd"/>
<symbol name="CCAP4H" address="SFR:fe"/>
<symbol name="SPE" address="ESFR:fb"/>
<symbol name="EPL" address="ESFR:fc"/>
<symbol name="EPM" address="ESFR:fd"/>
<symbol name="EPH" address="ESFR:fe"/>
<symbol name="MXCON" address="ESFR:ff"/>
<symbol name="20.0" address="BITS:00"/>
<symbol name="20.1" address="BITS:01"/>
<symbol name="20.2" address="BITS:02"/>
<symbol name="20.3" address="BITS:03"/>
<symbol name="20.4" address="BITS:04"/>
<symbol name="20.5" address="BITS:05"/>
<symbol name="20.6" address="BITS:06"/>
<symbol name="20.7" address="BITS:07"/>
<symbol name="21.0" address="BITS:08"/>
<symbol name="21.1" address="BITS:09"/>
<symbol name="21.2" address="BITS:0a"/>
<symbol name="21.3" address="BITS:0b"/>
<symbol name="21.4" address="BITS:0c"/>
<symbol name="21.5" address="BITS:0d"/>
<symbol name="21.6" address="BITS:0e"/>
<symbol name="21.7" address="BITS:0f"/>
<symbol name="22.0" address="BITS:10"/>
<symbol name="22.1" address="BITS:11"/>
<symbol name="22.2" address="BITS:12"/>
<symbol name="22.3" address="BITS:13"/>
<symbol name="22.4" address="BITS:14"/>
<symbol name="22.5" address="BITS:15"/>
<symbol name="22.6" address="BITS:16"/>
<symbol name="22.7" address="BITS:17"/>
<symbol name="23.0" address="BITS:18"/>
<symbol name="23.1" address="BITS:19"/>
<symbol name="23.2" address="BITS:1a"/>
<symbol name="23.3" address="BITS:1b"/>
<symbol name="23.4" address="BITS:1c"/>
<symbol name="23.5" address="BITS:1d"/>
<symbol name="23.6" address="BITS:1e"/>
<symbol name="23.7" address="BITS:1f"/>
<symbol name="24.0" address="BITS:20"/>
<symbol name="24.1" address="BITS:21"/>
<symbol name="24.2" address="BITS:22"/>
<symbol name="24.3" address="BITS:23"/>
<symbol name="24.4" address="BITS:24"/>
<symbol name="24.5" address="BITS:25"/>
<symbol name="24.6" address="BITS:26"/>
<symbol name="24.7" address="BITS:27"/>
<symbol name="25.0" address="BITS:28"/>
<symbol name="25.1" address="BITS:29"/>
<symbol name="25.2" address="BITS:2a"/>
<symbol name="25.3" address="BITS:2b"/>
<symbol name="25.4" address="BITS:2c"/>
<symbol name="25.5" address="BITS:2d"/>
<symbol name="25.6" address="BITS:2e"/>
<symbol name="25.7" address="BITS:2f"/>
<symbol name="26.0" address="BITS:30"/>
<symbol name="26.1" address="BITS:31"/>
<symbol name="26.2" address="BITS:32"/>
<symbol name="26.3" address="BITS:33"/>
<symbol name="26.4" address="BITS:34"/>
<symbol name="26.5" address="BITS:35"/>
<symbol name="26.6" address="BITS:36"/>
<symbol name="26.7" address="BITS:37"/>
<symbol name="27.0" address="BITS:38"/>
<symbol name="27.1" address="BITS:39"/>
<symbol name="27.2" address="BITS:3a"/>
<symbol name="27.3" address="BITS:3b"/>
<symbol name="27.4" address="BITS:3c"/>
<symbol name="27.5" address="BITS:3d"/>
<symbol name="27.6" address="BITS:3e"/>
<symbol name="27.7" address="BITS:3f"/>
<symbol name="28.0" address="BITS:40"/>
<symbol name="28.1" address="BITS:41"/>
<symbol name="28.2" address="BITS:42"/>
<symbol name="28.3" address="BITS:43"/>
<symbol name="28.4" address="BITS:44"/>
<symbol name="28.5" address="BITS:45"/>
<symbol name="28.6" address="BITS:46"/>
<symbol name="28.7" address="BITS:47"/>
<symbol name="29.0" address="BITS:48"/>
<symbol name="29.1" address="BITS:49"/>
<symbol name="29.2" address="BITS:4a"/>
<symbol name="29.3" address="BITS:4b"/>
<symbol name="29.4" address="BITS:4c"/>
<symbol name="29.5" address="BITS:4d"/>
<symbol name="29.6" address="BITS:4e"/>
<symbol name="29.7" address="BITS:4f"/>
<symbol name="2a.0" address="BITS:50"/>
<symbol name="2a.1" address="BITS:51"/>
<symbol name="2a.2" address="BITS:52"/>
<symbol name="2a.3" address="BITS:53"/>
<symbol name="2a.4" address="BITS:54"/>
<symbol name="2a.5" address="BITS:55"/>
<symbol name="2a.6" address="BITS:56"/>
<symbol name="2a.7" address="BITS:57"/>
<symbol name="2b.0" address="BITS:58"/>
<symbol name="2b.1" address="BITS:59"/>
<symbol name="2b.2" address="BITS:5a"/>
<symbol name="2b.3" address="BITS:5b"/>
<symbol name="2b.4" address="BITS:5c"/>
<symbol name="2b.5" address="BITS:5d"/>
<symbol name="2b.6" address="BITS:5e"/>
<symbol name="2b.7" address="BITS:5f"/>
<symbol name="2c.0" address="BITS:60"/>
<symbol name="2c.1" address="BITS:61"/>
<symbol name="2c.2" address="BITS:62"/>
<symbol name="2c.3" address="BITS:63"/>
<symbol name="2c.4" address="BITS:64"/>
<symbol name="2c.5" address="BITS:65"/>
<symbol name="2c.6" address="BITS:66"/>
<symbol name="2c.7" address="BITS:67"/>
<symbol name="2d.0" address="BITS:68"/>
<symbol name="2d.1" address="BITS:69"/>
<symbol name="2d.2" address="BITS:6a"/>
<symbol name="2d.3" address="BITS:6b"/>
<symbol name="2d.4" address="BITS:6c"/>
<symbol name="2d.5" address="BITS:6d"/>
<symbol name="2d.6" address="BITS:6e"/>
<symbol name="2d.7" address="BITS:6f"/>
<symbol name="2e.0" address="BITS:70"/>
<symbol name="2e.1" address="BITS:71"/>
<symbol name="2e.2" address="BITS:72"/>
<symbol name="2e.3" address="BITS:73"/>
<symbol name="2e.4" address="BITS:74"/>
<symbol name="2e.5" address="BITS:75"/>
<symbol name="2e.6" address="BITS:76"/>
<symbol name="2e.7" address="BITS:77"/>
<symbol name="2f.0" address="BITS:78"/>
<symbol name="2f.1" address="BITS:79"/>
<symbol name="2f.2" address="BITS:7a"/>
<symbol name="2f.3" address="BITS:7b"/>
<symbol name="2f.4" address="BITS:7c"/>
<symbol name="2f.5" address="BITS:7d"/>
<symbol name="2f.6" address="BITS:7e"/>
<symbol name="2f.7" address="BITS:7f"/>
<symbol name="P0.0" address="BITS:80"/>
<symbol name="P0.1" address="BITS:81"/>
<symbol name="P0.2" address="BITS:82"/>
<symbol name="P0.3" address="BITS:83"/>
<symbol name="P0.4" address="BITS:84"/>
<symbol name="P0.5" address="BITS:85"/>
<symbol name="P0.6" address="BITS:86"/>
<symbol name="P0.7" address="BITS:87"/>
<symbol name="IT0" address="BITS:88"/>
<symbol name="IE0" address="BITS:89"/>
<symbol name="IT1" address="BITS:8a"/>
<symbol name="IE1" address="BITS:8b"/>
<symbol name="TR0" address="BITS:8c"/>
<symbol name="TF0" address="BITS:8d"/>
<symbol name="TR1" address="BITS:8e"/>
<symbol name="TF1" address="BITS:8f"/>
<symbol name="P1.0" address="BITS:90"/>
<symbol name="P1.1" address="BITS:91"/>
<symbol name="P1.2" address="BITS:92"/>
<symbol name="P1.3" address="BITS:93"/>
<symbol name="P1.4" address="BITS:94"/>
<symbol name="P1.5" address="BITS:95"/>
<symbol name="P1.6" address="BITS:96"/>
<symbol name="P1.7" address="BITS:97"/>
<symbol name="RI" address="BITS:98"/>
<symbol name="TI" address="BITS:99"/>
<symbol name="RB8" address="BITS:9a"/>
<symbol name="TB8" address="BITS:9b"/>
<symbol name="REN" address="BITS:9c"/>
<symbol name="SM2" address="BITS:9d"/>
<symbol name="SM1" address="BITS:9e"/>
<symbol name="SM0" address="BITS:9f"/>
<symbol name="P2.0" address="BITS:a0"/>
<symbol name="P2.1" address="BITS:a1"/>
<symbol name="P2.2" address="BITS:a2"/>
<symbol name="P2.3" address="BITS:a3"/>
<symbol name="P2.4" address="BITS:a4"/>
<symbol name="P2.5" address="BITS:a5"/>
<symbol name="P2.6" address="BITS:a6"/>
<symbol name="P2.7" address="BITS:a7"/>
<symbol name="EX0" address="BITS:a8"/>
<symbol name="ET0" address="BITS:a9"/>
<symbol name="EX1" address="BITS:aa"/>
<symbol name="ET1" address="BITS:ab"/>
<symbol name="ES" address="BITS:ac"/>
<symbol name="ET2" address="BITS:ad"/>
<symbol name="EC" address="BITS:ae"/>
<symbol name="EA" address="BITS:af"/>
<symbol name="RXD" address="BITS:b0"/>
<symbol name="TXD" address="BITS:b1"/>
<symbol name="INT0" address="BITS:b2"/>
<symbol name="INT1" address="BITS:b3"/>
<symbol name="T0" address="BITS:b4"/>
<symbol name="T1" address="BITS:b5"/>
<symbol name="WR" address="BITS:b6"/>
<symbol name="RD" address="BITS:b7"/>
<symbol name="PX0" address="BITS:b8"/>
<symbol name="PT0" address="BITS:b9"/>
<symbol name="PX1" address="BITS:ba"/>
<symbol name="PT1" address="BITS:bb"/>
<symbol name="PS" address="BITS:bc"/>
<symbol name="PT2" address="BITS:bd"/>
<symbol name="PC" address="BITS:be"/>
<symbol name="IP.7" address="BITS:bf"/>
<symbol name="FIFLG.0" address="BITS:c0"/>
<symbol name="FIFLG.1" address="BITS:c1"/>
<symbol name="FIFLG.2" address="BITS:c2"/>
<symbol name="FIFLG.3" address="BITS:c3"/>
<symbol name="FIFLG.4" address="BITS:c4"/>
<symbol name="FIFLG.5" address="BITS:c5"/>
<symbol name="FIFLG.6" address="BITS:c6"/>
<symbol name="FIFLG.7" address="BITS:c7"/>
<symbol name="CPRL2" address="BITS:c8"/>
<symbol name="CT2" address="BITS:c9"/>
<symbol name="TR2" address="BITS:ca"/>
<symbol name="EXEN2" address="BITS:cb"/>
<symbol name="TCLK" address="BITS:cc"/>
<symbol name="RCLK" address="BITS:cd"/>
<symbol name="EXF2" address="BITS:ce"/>
<symbol name="TF2" address="BITS:cf"/>
<symbol name="P" address="BITS:d0"/>
<symbol name="UD" address="BITS:d1"/>
<symbol name="OV" address="BITS:d2"/>
<symbol name="RS0" address="BITS:d3"/>
<symbol name="RS1" address="BITS:d4"/>
<symbol name="F0" address="BITS:d5"/>
<symbol name="AC" address="BITS:d6"/>
<symbol name="C" address="BITS:d7"/>
<symbol name="CCF.0" address="BITS:d8"/>
<symbol name="CCF.1" address="BITS:d9"/>
<symbol name="CCF.2" address="BITS:da"/>
<symbol name="CCF.3" address="BITS:db"/>
<symbol name="CCF.4" address="BITS:dc"/>
<symbol name="CCON.5" address="BITS:dd"/>
<symbol name="CR" address="BITS:de"/>
<symbol name="CF" address="BITS:df"/>
<symbol name="ACC.0" address="BITS:e0"/>
<symbol name="ACC.1" address="BITS:e1"/>
<symbol name="ACC.2" address="BITS:e2"/>
<symbol name="ACC.3" address="BITS:e3"/>
<symbol name="ACC.4" address="BITS:e4"/>
<symbol name="ACC.5" address="BITS:e5"/>
<symbol name="ACC.6" address="BITS:e6"/>
<symbol name="ACC.7" address="BITS:e7"/>
<symbol name="HIFLG.0" address="BITS:e8"/>
<symbol name="HIFLG.1" address="BITS:e9"/>
<symbol name="HIFLG.2" address="BITS:ea"/>
<symbol name="HIFLG.3" address="BITS:eb"/>
<symbol name="HIFLG.4" address="BITS:ec"/>
<symbol name="HIFLG.5" address="BITS:ed"/>
<symbol name="HIFLG.6" address="BITS:ee"/>
<symbol name="HIFLG.7" address="BITS:ef"/>
<symbol name="B.0" address="BITS:f0"/>
<symbol name="B.1" address="BITS:f1"/>
<symbol name="B.2" address="BITS:f2"/>
<symbol name="B.3" address="BITS:f3"/>
<symbol name="B.4" address="BITS:f4"/>
<symbol name="B.5" address="BITS:f5"/>
<symbol name="B.6" address="BITS:f6"/>
<symbol name="B.7" address="BITS:f7"/>
<symbol name="F8.0" address="BITS:f8"/>
<symbol name="F8.1" address="BITS:f9"/>
<symbol name="F8.2" address="BITS:fa"/>
<symbol name="F8.3" address="BITS:fb"/>
<symbol name="F8.4" address="BITS:fc"/>
<symbol name="F8.5" address="BITS:fd"/>
<symbol name="F8.6" address="BITS:fe"/>
<symbol name="F8.7" address="BITS:ff"/>
</default_symbols>
<default_memory_blocks>
<memory_block name="REG_BANK_1" start_address="RAM:7f0000" length="0x8" initialized="false"/>
<memory_block name="REG_BANK_2" start_address="RAM:7f0008" length="0x8" initialized="false"/>
<memory_block name="REG_BANK_3" start_address="RAM:7f0010" length="0x8" initialized="false"/>
<memory_block name="REG_BANK_4" start_address="RAM:7f0018" length="0x8" initialized="false"/>
<memory_block name="INTMEM" start_address="RAM:7f0020" length="0xe0" initialized="false"/>
<memory_block name="EXTMEM" start_address="RAM:0" length="0x1000" initialized="false"/>
<memory_block name="BITS" start_address="BITS:00" bit_mapped_address="RAM:7f0020" length="0x80"/>
<memory_block name="SFR" start_address="SFR:80" length="0x80" initialized="false"/>
<memory_block name="ESFR" start_address="ESFR:80" length="0x80" initialized="false"/>
<memory_block name="EBITS" start_address="EBITS:00" bit_mapped_address="RAM:7f0020" length="0x80"/>
<!-- BUG: SFR-BITS do not map properly since only every 8th SFR register is mapped (e.g., 0x80, 0x88, 0x90 ... 0xF0, 0xF8) -->
<memory_block name="SFR-BITS" start_address="BITS:80" bit_mapped_address="SFR:80" length="0x80"/>
<memory_block name="ESFR-BITS" start_address="EBITS:80" bit_mapped_address="ESFR:80" length="0x80"/>
</default_memory_blocks>
</processor_spec>
python/icicle/Ghidra/Processors/8051/data/languages/mx51.sinc
+332 -332
View File
@@ -1,332 +1,332 @@
# Extended mx51 instructions live here, so as to avoid further
# complicating the main 8051 file.
# All have 0xa5 as prefix, so subtract one
define token TwoByteOp (8)
b2op = (0,7)
;
define token ThreeByteOp (16)
b3op = (8,15)
;
define token FourByteOp (24)
b4op = (16,23)
;
define token EcallDispTok (24)
imm24 = (0,23)
;
####################
# Note that PRi is used in little endian format, as R3 is the MSB
attach variables PRi_revend [ R1R2R3 R5R6R7 ];
@define ENDIANSWAPFUNC ""
@if defined(ENDIANSWAPFUNC)
define pcodeop endian_swap;
PRi: PRi_revend is PRi_revend { tmp:3 = endian_swap(PRi_revend); export tmp; }
@else
PRi: PRi_revend is PRi_sel=0 & PRi_revend { tmp:3 = (zext(R3) << 16) | (zext(R2) << 8) | zext(R1); export tmp; }
PRi: PRi_revend is PRi_sel=1 & PRi_revend { tmp:3 = (zext(R7) << 16) | (zext(R6) << 8) | zext(R5); export tmp; }
@endif
####################
@ifdef OMIT_RETADDR
macro push24(val) { val = val; }
macro pop24(val) { val = val; }
@else
# stack grows up.
macro push24(val) {
ptr:3 = zext(SP) + 1 + $(STACKBASE);
*[RAM]:3 ptr = val;
SP = SP + 2;
}
macro pop24(val) {
ptr:3 = zext(SP - 2) + $(STACKBASE);
val = *[RAM]:3 ptr;
SP = SP - 3;
}
@endif
####################
eptrReg: EPTR is EPTR { export EPTR; }
APlusEptr: "@"Areg"+"eptrReg is Areg & eptrReg { tmp:3 = EPTR + zext(ACC); export tmp; }
ecallImmAddr: imm24 is imm24 { export *:1 imm24; }
add_with_pr_const: emov_delta is emov_delta { tmp:1 = emov_delta; export tmp; }
add_with_pr_const: "4" is emov_delta = 0 { tmp:1 = 4; export tmp; }
EDirect: mainreg is bank=0 & mainreg { tmp:3 = mainreg + 0x7f0000; export *[RAM]:1 tmp; }
EDirect: direct is bank=1 & direct { export *[ESFR]:1 direct; }
EDirect: EPL is bank=1 & direct=0xfc & EPL { export EPL; }
EDirect: EPM is bank=1 & direct=0xfd & EPM { export EPM; }
EDirect: EPH is bank=1 & direct=0xfe & EPH { export EPH; }
EDirect2: mainreg2 is bank2=0 & mainreg2 { tmp:3 = mainreg2 + 0x7f0000; export *[RAM]:1 tmp; }
EDirect2: direct2 is bank2=1 & direct2 { export *[ESFR]:1 direct2; }
EDirect2: EPL is bank2=1 & direct2=0xfc & EPL { export EPL; }
EDirect2: EPM is bank2=1 & direct2=0xfd & EPM { export EPM; }
EDirect2: EPH is bank2=1 & direct2=0xfe & EPH { export EPH; }
# Continuing with pattern via copying from stock 8051 sleighspec.
# Note that there is a known bug with the Bit addressing of the SFR.
EBitAddr: bitaddr is bitbank=1 & sfrbyte & sfrbit [ bitaddr =(sfrbyte << 3)+sfrbit; ] { export *[EBITS]:1 bitaddr; }
EBitAddr: bitaddr is bitbank=0 & lowbyte & sfrbit [ bitaddr =(lowbyte << 3)+sfrbit; ] { export *[EBITS]:1 bitaddr; }
EBitAddr2: "/"bitaddr is bitbank=1 & sfrbyte & sfrbit [ bitaddr =(sfrbyte << 3)+sfrbit; ] { export *[EBITS]:1 bitaddr; }
EBitAddr2: "/"bitaddr is bitbank=0 & lowbyte & sfrbit [ bitaddr =(lowbyte << 3)+sfrbit; ] { export *[EBITS]:1 bitaddr; }
EBitByteAddr: byteaddr is bitbank=1 & sfrbyte & sfrbit [ byteaddr =(sfrbyte << 3); ] { export *[ESFR]:1 byteaddr; }
EBitByteAddr: byteaddr is bitbank=0 & lowbyte & sfrbit [ byteaddr = lowbyte + 0x20; ] { tmp:3 = byteaddr + 0x7f0000; export *[RAM]:1 tmp; }
####################
:inc EDirect is opfull=0xa5; ophi=0 & oplo=5; EDirect {
EDirect = EDirect + 1;
}
:dec EDirect is opfull=0xa5; opfull=0x15; EDirect {
EDirect = EDirect - 1;
}
:add Areg,EDirect is opfull=0xa5; opfull=0x25 & Areg; EDirect {
addflags(ACC,EDirect); ACC = ACC + EDirect; resultflags(ACC);
}
:addc Areg,EDirect is opfull=0xa5; opfull=0x35 & Areg; EDirect {
tmp:1 =$(CY)+ EDirect; addflags(ACC,tmp); ACC = ACC + tmp; resultflags(ACC);
}
:orl Areg,EDirect is opfull=0xa5; opfull=0x45 & Areg; EDirect {
ACC = ACC | EDirect;
}
:anl Areg,EDirect is opfull=0xa5; opfull=0x55 & Areg; EDirect {
ACC = ACC & EDirect; resultflags(ACC);
}
:xrl Areg,EDirect is opfull=0xa5; opfull=0x65 & Areg; EDirect {
ACC = ACC ^ EDirect;
}
:subb Areg,EDirect is opfull=0xa5; opfull=0x95 & Areg; EDirect {
tmp:1 = EDirect+$(CY); subflags(ACC,tmp); ACC = ACC - tmp;
}
:xch Areg,EDirect is opfull=0xa5; opfull=0xc5 & Areg; EDirect {
tmp:1 = ACC; ACC = EDirect; EDirect = tmp;
}
:mov Areg,EDirect is opfull=0xa5; opfull=0xe5 & Areg; EDirect {
ACC = EDirect;
}
:mov EDirect,Areg is opfull=0xa5; opfull=0xf5 & Areg; EDirect {
EDirect = ACC;
}
:mov EDirect,rn is opfull=0xa5; ophi=0x8 & rnfill=1 & rn; EDirect {
EDirect = rn;
}
:mov rn,EDirect is opfull=0xa5; ophi=0xa & rnfill=1 & rn; EDirect {
rn = EDirect;
}
:mov EDirect2,EDirect is opfull=0xa5; ophi=8 & oplo=5; EDirect; EDirect2 {
EDirect2 = EDirect;
}
:mov EDirect,Data is opfull=0xa5; ophi=7 & oplo=5; EDirect; Data {
EDirect = Data;
}
:mov EDirect,Ri is opfull=0xa5; ophi=8 & rifill=3 & Ri; EDirect {
EDirect = Ri;
}
:mov Ri,EDirect is opfull=0xa5; ophi=10 & rifill=3 & Ri; EDirect {
Ri = EDirect;
}
:orl EDirect,Areg is opfull=0xa5; ophi=4 & oplo=2 & Areg; EDirect {
EDirect = EDirect | ACC;
}
:anl EDirect,Areg is opfull=0xa5; ophi=5 & oplo=2 & Areg; EDirect {
tmp:1 = EDirect & ACC; EDirect = tmp; resultflags(tmp);
}
:xrl EDirect,Areg is opfull=0xa5; ophi=6 & oplo=2 & Areg; EDirect {
EDirect = EDirect ^ ACC;
}
:xrl EDirect,Data is opfull=0xa5; ophi=6 & oplo=3; EDirect; Data {
EDirect = EDirect ^ Data;
}
:anl EDirect,Data is opfull=0xa5; ophi=5 & oplo=3; EDirect; Data {
tmp:1 = EDirect & Data; EDirect = tmp; resultflags(tmp);
}
:orl EDirect,Data is opfull=0xa5; ophi=4 & oplo=3 & Areg; EDirect; Data {
EDirect = EDirect | Data;
}
:push EDirect is opfull=0xa5; opfull=0xc0; EDirect {
push8(EDirect);
}
:pop EDirect is opfull=0xa5; opfull=0xd0; EDirect {
pop8(EDirect);
}
:cjne Areg,EDirect,Rel8 is opfull=0xa5; ophi=11 & oplo=5 & Areg; EDirect; Rel8 {
compflags(ACC,EDirect); if (ACC!=EDirect) goto Rel8;
}
:djnz EDirect,Rel8 is opfull=0xa5; ophi=13 & oplo=5; EDirect; Rel8 {
EDirect = EDirect - 1;
if (EDirect!=0) goto Rel8;
}
# EPTR operations
:ejmp ecallImmAddr is opfull=0xa5; opfull=0x02; ecallImmAddr {
goto ecallImmAddr;
}
:ecall ecallImmAddr is opfull=0xa5; opfull=0x12; ecallImmAddr {
ret:3 = inst_next; push24(ret); call ecallImmAddr;
}
:mov eptrReg,ecallImmAddr is opfull=0xa5; opfull=0x90; ecallImmAddr & eptrReg & imm24 {
EPTR = imm24;
}
:eret is opfull=0xa5; opfull=0x22 {
pc:3 = 0; pop24(pc); return[pc];
}
:jmp APlusEptr is opfull=0xa5; opfull=0x73 & APlusEptr {
# this is correct, but causes disassembler problems
# goto APlusEptr;
# added additional indirection to stop disassembler problems.
goto [APlusEptr];
}
:movx Areg",@"eptrReg is opfull=0xa5; opfull=0xe0 & Areg & eptrReg {
ACC = *:1 EPTR;
}
:movx "@"eptrReg,Areg is opfull=0xa5; opfull=0xf0 & Areg & eptrReg {
*:1 EPTR = ACC;
}
:movc Areg,APlusEptr is opfull=0xa5; opfull=0x93 & Areg & APlusEptr {
ACC = *:1 APlusEptr;
}
:inc EPTR is opfull=0xa5; opfull=0xa3 & EPTR {
EPTR = EPTR + 1;
}
# PRi operations
:emov Areg",@"PRi"+"emov_delta is opfull=0xa5; ophi=4 & PRi & emov_delta & Areg {
tmp:3 = zext(PRi) + emov_delta;
ACC = *:1 tmp;
}
:emov "@"PRi"+"emov_delta,Areg is opfull=0xa5; ophi=5 & PRi & emov_delta & Areg {
tmp:3 = PRi + emov_delta;
*:1 tmp = ACC;
}
:add PRi_revend,add_with_pr_const is opfull=0xa5; ophi=6 & PRi_revend & PRi & add_with_pr_const {
x:3 = zext(add_with_pr_const);
tmp:3 = PRi + x;
@if defined(ENDIANSWAPFUNC)
y:3 = endian_swap(tmp);
@else
y:3 = (tmp << 16) | (tmp & 0x00ff00) | zext(tmp >> 16);
@endif
PRi_revend = y;
}
# bit operations
:anl CY,EBitAddr is opfull=0xa5; CY & ophi=8 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr {tmp:1 = EBitByteAddr; $(CY)=$(CY)& ((tmp>>sfrbit)&1); resultflags(tmp); }
:anl CY,EBitAddr2 is opfull=0xa5; CY & ophi=11 & oplo=0; EBitAddr2 & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr {tmp:1 = EBitByteAddr; $(CY)=$(CY)& (~((tmp>>sfrbit)&1)); }
@if BIT_OPS == "BIT_ADDRS"
:anl CY,EBitAddr is opfull=0xa5; CY & ophi=8 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)& EBitAddr; }
:anl CY,EBitAddr2 is opfull=0xa5; CY & ophi=11 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)& ~EBitAddr2; }
@elif BIT_OPS == "PCODEOPS"
:anl CY,EBitAddr is opfull=0xa5; CY & ophi=8 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)& get(EBitAddr, EBitByteAddr); }
:anl CY,EBitAddr2 is opfull=0xa5; CY & ophi=11 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)& (get(EBitAddr2, EBitByteAddr)^1); }
@elif BIT_OPS == "SHIFTS"
:anl CY,EBitAddr is opfull=0xa5; CY & ophi=8 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)& ((EBitByteAddr>>sfrbit)&1); }
:anl CY,EBitAddr2 is opfull=0xa5; CY & ophi=11 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)& (~((EBitByteAddr>>sfrbit)&1)); }
@endif
:clr EBitAddr is opfull=0xa5; ophi=12 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr { tmp:1 = ~(1<<sfrbit); EBitByteAddr = EBitByteAddr & tmp; }
@if BIT_OPS == "BIT_ADDRS"
:clr EBitAddr is opfull=0xa5; ophi=12 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { EBitAddr = 0; }
@elif BIT_OPS == "PCODEOPS"
:clr EBitAddr is opfull=0xa5; ophi=12 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { EBitByteAddr = clr(EBitAddr, EBitByteAddr); }
#:CLR PortBit is opfull=0xa5; ophi=12 & oplo=2; PortBit & sfrbit & EBitByteAddr { outp(PortBit, 0:1, EBitByteAddr); }
@elif BIT_OPS == "SHIFTS"
:clr EBitAddr is opfull=0xa5; ophi=12 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { tmp:1 = ~(1<<sfrbit); EBitByteAddr = EBitByteAddr & tmp; }
@endif
:cpl EBitAddr is opfull=0xa5; ophi=11 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr { tmp:1 = (1<<sfrbit); EBitByteAddr = EBitByteAddr ^ tmp; }
@if BIT_OPS == "BIT_ADDRS"
:cpl EBitAddr is opfull=0xa5; ophi=11 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { EBitAddr = EBitAddr ^ 1; }
@elif BIT_OPS == "PCODEOPS"
:cpl EBitAddr is opfull=0xa5; ophi=11 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { tmp:1 = get(EBitAddr, EBitByteAddr) ^ 1; EBitByteAddr = set_bit_value(EBitAddr, tmp, EBitByteAddr); }
@elif BIT_OPS == "SHIFTS"
:cpl EBitAddr is opfull=0xa5; ophi=11 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { tmp:1 = (1<<sfrbit); EBitByteAddr = EBitByteAddr ^ tmp; }
@endif
:jb EBitAddr,Rel8 is opfull=0xa5; ophi=2 & oplo=0; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr; Rel8 { if (((EBitByteAddr>>sfrbit)&1) == 1:1) goto Rel8; }
:jbc EBitAddr,Rel8 is opfull=0xa5; ophi=1 & oplo=0; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr; Rel8 { tmp:1 = 1<<sfrbit; if ((EBitByteAddr & tmp)==0) goto inst_next; EBitByteAddr = EBitByteAddr & ~tmp; goto Rel8; }
@if BIT_OPS == "BIT_ADDRS"
:jb EBitAddr,Rel8 is opfull=0xa5; ophi=2 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { if (EBitAddr == 1:1) goto Rel8; }
:jbc EBitAddr,Rel8 is opfull=0xa5; ophi=1 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { if (EBitAddr == 0:1) goto inst_next; EBitAddr = 0; goto Rel8; }
@elif BIT_OPS == "PCODEOPS"
:jb EBitAddr,Rel8 is opfull=0xa5; ophi=2 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { if (get(EBitAddr, EBitByteAddr)==1:1) goto Rel8; }
:jbc EBitAddr,Rel8 is opfull=0xa5; ophi=1 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { tmp:1 = get(EBitAddr, EBitByteAddr); if (tmp==0) goto inst_next; EBitByteAddr = clr(EBitAddr, EBitByteAddr); goto Rel8; }
@elif BIT_OPS == "SHIFTS"
:jb EBitAddr,Rel8 is opfull=0xa5; ophi=2 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { if (((EBitByteAddr>>sfrbit)&1) == 1:1) goto Rel8; }
:jbc EBitAddr,Rel8 is opfull=0xa5; ophi=1 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { tmp:1 = 1<<sfrbit; if ((EBitByteAddr & tmp)==0) goto inst_next; EBitByteAddr = EBitByteAddr & ~tmp; goto Rel8; }
@endif
:jnb EBitAddr,Rel8 is opfull=0xa5; ophi=3 & oplo=0; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr; Rel8 { if (((EBitByteAddr>>sfrbit)&1)==0:1) goto Rel8; }
@if BIT_OPS == "BIT_ADDRS"
:jnb EBitAddr,Rel8 is opfull=0xa5; ophi=3 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { if (EBitAddr == 0:1) goto Rel8; }
@elif BIT_OPS == "PCODEOPS"
:jnb EBitAddr,Rel8 is opfull=0xa5; ophi=3 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { if (get(EBitAddr, EBitByteAddr)==0:1) goto Rel8; }
@elif BIT_OPS == "SHIFTS"
:jnb EBitAddr,Rel8 is opfull=0xa5; ophi=3 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { if (((EBitByteAddr>>sfrbit)&1)==0:1) goto Rel8; }
@endif
:mov CY,EBitAddr is opfull=0xa5; CY & ophi=10 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr {$(CY)= (EBitByteAddr>>sfrbit)&1; }
:mov EBitAddr,CY is opfull=0xa5; CY & ophi=9 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr { EBitByteAddr = EBitByteAddr & (~(1<<sfrbit)); EBitByteAddr = EBitByteAddr | ($(CY)<<sfrbit); }
@if BIT_OPS == "BIT_ADDRS"
:mov CY,EBitAddr is opfull=0xa5; CY & ophi=10 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)= EBitAddr; }
:mov EBitAddr,CY is opfull=0xa5; CY & ophi=9 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { EBitAddr = $(CY); }
@elif BIT_OPS == "PCODEOPS"
:mov CY,EBitAddr is opfull=0xa5; CY & ophi=10 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY) = get(EBitAddr, EBitByteAddr); }
:mov EBitAddr,CY is opfull=0xa5; CY & ophi=9 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { EBitByteAddr = set_bit_value(EBitAddr, $(CY), EBitByteAddr); }
@elif BIT_OPS == "SHIFTS"
:mov CY,EBitAddr is opfull=0xa5; CY & ophi=10 & oplo=2; EBitAddr & sfrbit & EBitByteAddr{$(CY)= (EBitByteAddr>>sfrbit)&1; }
:mov EBitAddr,CY is opfull=0xa5; CY & ophi=9 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { EBitByteAddr = EBitByteAddr & (~(1<<sfrbit)); EBitByteAddr = EBitByteAddr | ($(CY)<<sfrbit); }
@endif
:orl CY,EBitAddr is opfull=0xa5; CY & ophi=7 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr {$(CY)=$(CY)| ((EBitByteAddr>>sfrbit)&1); }
:orl CY,EBitAddr2 is opfull=0xa5; CY & ophi=10 & oplo=0; EBitAddr2 & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr {$(CY)=$(CY)| (((EBitByteAddr>>sfrbit)&1)^1); }
@if BIT_OPS == "BIT_ADDRS"
:orl CY,EBitAddr is opfull=0xa5; CY & ophi=7 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)| EBitAddr; }
:orl CY,EBitAddr2 is opfull=0xa5; CY & ophi=10 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)| (EBitAddr2^1); }
@elif BIT_OPS == "PCODEOPS"
:orl CY,EBitAddr is opfull=0xa5; CY & ophi=7 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)| get(EBitAddr, EBitByteAddr); }
:orl CY,EBitAddr2 is opfull=0xa5; CY & ophi=10 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)| (get(EBitAddr2, EBitByteAddr)^1); }
@elif BIT_OPS == "SHIFTS"
:orl CY,EBitAddr is opfull=0xa5; CY & ophi=7 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)| ((EBitByteAddr>>sfrbit)&1); }
:orl CY,EBitAddr2 is opfull=0xa5; CY & ophi=10 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)| (((EBitByteAddr>>sfrbit)&1)^1); }
@endif
:setb EBitAddr is opfull=0xa5; ophi=13 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr { EBitByteAddr = EBitByteAddr | (1<<sfrbit); }
@if BIT_OPS == "BIT_ADDRS"
:setb EBitAddr is opfull=0xa5; ophi=13 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { EBitAddr = 1; }
@elif BIT_OPS == "PCODEOPS"
:setb EBitAddr is opfull=0xa5; ophi=13 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { EBitByteAddr = set(EBitAddr, EBitByteAddr); }
@elif BIT_OPS == "SHIFTS"
:setb EBitAddr is opfull=0xa5; ophi=13 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { EBitByteAddr = EBitByteAddr | (1<<sfrbit); }
@endif
########################################################################
@if defined(INS_FUSION)
# Eventually, it is hoped that the decompiler will just handle these.
# In the meantime, lets try to rewrite so to help the decompiler out.
#
# Due to compiler optimizations, this can sometimes lead to bad results
# on 8051 derivatives. E.g, jumps to the middle of the fused instruction.
define token Fuse4ByteToken (32)
f4op1 = (24,31)
f4op1imm8 = (16,23)
f4op2 = (8,15)
f4op2imm8 = (0,7)
;
f4imm16: val is f4op1imm8 & f4op2imm8 [ val = (f4op2imm8 << 8) | f4op1imm8; ] { tmp:2 = val; export tmp; }
# Just do r7 r6 for now
:mov_fused R6R7,"#"f4imm16 is f4op1=0x7f & f4op2=0x7e & R6R7 & f4imm16 {
R6R7 = f4imm16;
}
@endif
# Extended mx51 instructions live here, so as to avoid further
# complicating the main 8051 file.
# All have 0xa5 as prefix, so subtract one
define token TwoByteOp (8)
b2op = (0,7)
;
define token ThreeByteOp (16)
b3op = (8,15)
;
define token FourByteOp (24)
b4op = (16,23)
;
define token EcallDispTok (24)
imm24 = (0,23)
;
####################
# Note that PRi is used in little endian format, as R3 is the MSB
attach variables PRi_revend [ R1R2R3 R5R6R7 ];
@define ENDIANSWAPFUNC ""
@if defined(ENDIANSWAPFUNC)
define pcodeop endian_swap;
PRi: PRi_revend is PRi_revend { tmp:3 = endian_swap(PRi_revend); export tmp; }
@else
PRi: PRi_revend is PRi_sel=0 & PRi_revend { tmp:3 = (zext(R3) << 16) | (zext(R2) << 8) | zext(R1); export tmp; }
PRi: PRi_revend is PRi_sel=1 & PRi_revend { tmp:3 = (zext(R7) << 16) | (zext(R6) << 8) | zext(R5); export tmp; }
@endif
####################
@ifdef OMIT_RETADDR
macro push24(val) { val = val; }
macro pop24(val) { val = val; }
@else
# stack grows up.
macro push24(val) {
ptr:3 = zext(SP) + 1 + $(STACKBASE);
*[RAM]:3 ptr = val;
SP = SP + 2;
}
macro pop24(val) {
ptr:3 = zext(SP - 2) + $(STACKBASE);
val = *[RAM]:3 ptr;
SP = SP - 3;
}
@endif
####################
eptrReg: EPTR is EPTR { export EPTR; }
APlusEptr: "@"Areg"+"eptrReg is Areg & eptrReg { tmp:3 = EPTR + zext(ACC); export tmp; }
ecallImmAddr: imm24 is imm24 { export *:1 imm24; }
add_with_pr_const: emov_delta is emov_delta { tmp:1 = emov_delta; export tmp; }
add_with_pr_const: "4" is emov_delta = 0 { tmp:1 = 4; export tmp; }
EDirect: mainreg is bank=0 & mainreg { tmp:3 = mainreg + 0x7f0000; export *[RAM]:1 tmp; }
EDirect: direct is bank=1 & direct { export *[ESFR]:1 direct; }
EDirect: EPL is bank=1 & direct=0xfc & EPL { export EPL; }
EDirect: EPM is bank=1 & direct=0xfd & EPM { export EPM; }
EDirect: EPH is bank=1 & direct=0xfe & EPH { export EPH; }
EDirect2: mainreg2 is bank2=0 & mainreg2 { tmp:3 = mainreg2 + 0x7f0000; export *[RAM]:1 tmp; }
EDirect2: direct2 is bank2=1 & direct2 { export *[ESFR]:1 direct2; }
EDirect2: EPL is bank2=1 & direct2=0xfc & EPL { export EPL; }
EDirect2: EPM is bank2=1 & direct2=0xfd & EPM { export EPM; }
EDirect2: EPH is bank2=1 & direct2=0xfe & EPH { export EPH; }
# Continuing with pattern via copying from stock 8051 sleighspec.
# Note that there is a known bug with the Bit addressing of the SFR.
EBitAddr: bitaddr is bitbank=1 & sfrbyte & sfrbit [ bitaddr =(sfrbyte << 3)+sfrbit; ] { export *[EBITS]:1 bitaddr; }
EBitAddr: bitaddr is bitbank=0 & lowbyte & sfrbit [ bitaddr =(lowbyte << 3)+sfrbit; ] { export *[EBITS]:1 bitaddr; }
EBitAddr2: "/"bitaddr is bitbank=1 & sfrbyte & sfrbit [ bitaddr =(sfrbyte << 3)+sfrbit; ] { export *[EBITS]:1 bitaddr; }
EBitAddr2: "/"bitaddr is bitbank=0 & lowbyte & sfrbit [ bitaddr =(lowbyte << 3)+sfrbit; ] { export *[EBITS]:1 bitaddr; }
EBitByteAddr: byteaddr is bitbank=1 & sfrbyte & sfrbit [ byteaddr =(sfrbyte << 3); ] { export *[ESFR]:1 byteaddr; }
EBitByteAddr: byteaddr is bitbank=0 & lowbyte & sfrbit [ byteaddr = lowbyte + 0x20; ] { tmp:3 = byteaddr + 0x7f0000; export *[RAM]:1 tmp; }
####################
:inc EDirect is opfull=0xa5; ophi=0 & oplo=5; EDirect {
EDirect = EDirect + 1;
}
:dec EDirect is opfull=0xa5; opfull=0x15; EDirect {
EDirect = EDirect - 1;
}
:add Areg,EDirect is opfull=0xa5; opfull=0x25 & Areg; EDirect {
addflags(ACC,EDirect); ACC = ACC + EDirect; resultflags(ACC);
}
:addc Areg,EDirect is opfull=0xa5; opfull=0x35 & Areg; EDirect {
tmp:1 =$(CY)+ EDirect; addflags(ACC,tmp); ACC = ACC + tmp; resultflags(ACC);
}
:orl Areg,EDirect is opfull=0xa5; opfull=0x45 & Areg; EDirect {
ACC = ACC | EDirect;
}
:anl Areg,EDirect is opfull=0xa5; opfull=0x55 & Areg; EDirect {
ACC = ACC & EDirect; resultflags(ACC);
}
:xrl Areg,EDirect is opfull=0xa5; opfull=0x65 & Areg; EDirect {
ACC = ACC ^ EDirect;
}
:subb Areg,EDirect is opfull=0xa5; opfull=0x95 & Areg; EDirect {
tmp:1 = EDirect+$(CY); subflags(ACC,tmp); ACC = ACC - tmp;
}
:xch Areg,EDirect is opfull=0xa5; opfull=0xc5 & Areg; EDirect {
tmp:1 = ACC; ACC = EDirect; EDirect = tmp;
}
:mov Areg,EDirect is opfull=0xa5; opfull=0xe5 & Areg; EDirect {
ACC = EDirect;
}
:mov EDirect,Areg is opfull=0xa5; opfull=0xf5 & Areg; EDirect {
EDirect = ACC;
}
:mov EDirect,rn is opfull=0xa5; ophi=0x8 & rnfill=1 & rn; EDirect {
EDirect = rn;
}
:mov rn,EDirect is opfull=0xa5; ophi=0xa & rnfill=1 & rn; EDirect {
rn = EDirect;
}
:mov EDirect2,EDirect is opfull=0xa5; ophi=8 & oplo=5; EDirect; EDirect2 {
EDirect2 = EDirect;
}
:mov EDirect,Data is opfull=0xa5; ophi=7 & oplo=5; EDirect; Data {
EDirect = Data;
}
:mov EDirect,Ri is opfull=0xa5; ophi=8 & rifill=3 & Ri; EDirect {
EDirect = Ri;
}
:mov Ri,EDirect is opfull=0xa5; ophi=10 & rifill=3 & Ri; EDirect {
Ri = EDirect;
}
:orl EDirect,Areg is opfull=0xa5; ophi=4 & oplo=2 & Areg; EDirect {
EDirect = EDirect | ACC;
}
:anl EDirect,Areg is opfull=0xa5; ophi=5 & oplo=2 & Areg; EDirect {
tmp:1 = EDirect & ACC; EDirect = tmp; resultflags(tmp);
}
:xrl EDirect,Areg is opfull=0xa5; ophi=6 & oplo=2 & Areg; EDirect {
EDirect = EDirect ^ ACC;
}
:xrl EDirect,Data is opfull=0xa5; ophi=6 & oplo=3; EDirect; Data {
EDirect = EDirect ^ Data;
}
:anl EDirect,Data is opfull=0xa5; ophi=5 & oplo=3; EDirect; Data {
tmp:1 = EDirect & Data; EDirect = tmp; resultflags(tmp);
}
:orl EDirect,Data is opfull=0xa5; ophi=4 & oplo=3 & Areg; EDirect; Data {
EDirect = EDirect | Data;
}
:push EDirect is opfull=0xa5; opfull=0xc0; EDirect {
push8(EDirect);
}
:pop EDirect is opfull=0xa5; opfull=0xd0; EDirect {
pop8(EDirect);
}
:cjne Areg,EDirect,Rel8 is opfull=0xa5; ophi=11 & oplo=5 & Areg; EDirect; Rel8 {
compflags(ACC,EDirect); if (ACC!=EDirect) goto Rel8;
}
:djnz EDirect,Rel8 is opfull=0xa5; ophi=13 & oplo=5; EDirect; Rel8 {
EDirect = EDirect - 1;
if (EDirect!=0) goto Rel8;
}
# EPTR operations
:ejmp ecallImmAddr is opfull=0xa5; opfull=0x02; ecallImmAddr {
goto ecallImmAddr;
}
:ecall ecallImmAddr is opfull=0xa5; opfull=0x12; ecallImmAddr {
ret:3 = inst_next; push24(ret); call ecallImmAddr;
}
:mov eptrReg,ecallImmAddr is opfull=0xa5; opfull=0x90; ecallImmAddr & eptrReg & imm24 {
EPTR = imm24;
}
:eret is opfull=0xa5; opfull=0x22 {
pc:3 = 0; pop24(pc); return[pc];
}
:jmp APlusEptr is opfull=0xa5; opfull=0x73 & APlusEptr {
# this is correct, but causes disassembler problems
# goto APlusEptr;
# added additional indirection to stop disassembler problems.
goto [APlusEptr];
}
:movx Areg",@"eptrReg is opfull=0xa5; opfull=0xe0 & Areg & eptrReg {
ACC = *:1 EPTR;
}
:movx "@"eptrReg,Areg is opfull=0xa5; opfull=0xf0 & Areg & eptrReg {
*:1 EPTR = ACC;
}
:movc Areg,APlusEptr is opfull=0xa5; opfull=0x93 & Areg & APlusEptr {
ACC = *:1 APlusEptr;
}
:inc EPTR is opfull=0xa5; opfull=0xa3 & EPTR {
EPTR = EPTR + 1;
}
# PRi operations
:emov Areg",@"PRi"+"emov_delta is opfull=0xa5; ophi=4 & PRi & emov_delta & Areg {
tmp:3 = zext(PRi) + emov_delta;
ACC = *:1 tmp;
}
:emov "@"PRi"+"emov_delta,Areg is opfull=0xa5; ophi=5 & PRi & emov_delta & Areg {
tmp:3 = PRi + emov_delta;
*:1 tmp = ACC;
}
:add PRi_revend,add_with_pr_const is opfull=0xa5; ophi=6 & PRi_revend & PRi & add_with_pr_const {
x:3 = zext(add_with_pr_const);
tmp:3 = PRi + x;
@if defined(ENDIANSWAPFUNC)
y:3 = endian_swap(tmp);
@else
y:3 = (tmp << 16) | (tmp & 0x00ff00) | zext(tmp >> 16);
@endif
PRi_revend = y;
}
# bit operations
:anl CY,EBitAddr is opfull=0xa5; CY & ophi=8 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr {tmp:1 = EBitByteAddr; $(CY)=$(CY)& ((tmp>>sfrbit)&1); resultflags(tmp); }
:anl CY,EBitAddr2 is opfull=0xa5; CY & ophi=11 & oplo=0; EBitAddr2 & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr {tmp:1 = EBitByteAddr; $(CY)=$(CY)& (~((tmp>>sfrbit)&1)); }
@if BIT_OPS == "BIT_ADDRS"
:anl CY,EBitAddr is opfull=0xa5; CY & ophi=8 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)& EBitAddr; }
:anl CY,EBitAddr2 is opfull=0xa5; CY & ophi=11 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)& ~EBitAddr2; }
@elif BIT_OPS == "PCODEOPS"
:anl CY,EBitAddr is opfull=0xa5; CY & ophi=8 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)& get(EBitAddr, EBitByteAddr); }
:anl CY,EBitAddr2 is opfull=0xa5; CY & ophi=11 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)& (get(EBitAddr2, EBitByteAddr)^1); }
@elif BIT_OPS == "SHIFTS"
:anl CY,EBitAddr is opfull=0xa5; CY & ophi=8 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)& ((EBitByteAddr>>sfrbit)&1); }
:anl CY,EBitAddr2 is opfull=0xa5; CY & ophi=11 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)& (~((EBitByteAddr>>sfrbit)&1)); }
@endif
:clr EBitAddr is opfull=0xa5; ophi=12 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr { tmp:1 = ~(1<<sfrbit); EBitByteAddr = EBitByteAddr & tmp; }
@if BIT_OPS == "BIT_ADDRS"
:clr EBitAddr is opfull=0xa5; ophi=12 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { EBitAddr = 0; }
@elif BIT_OPS == "PCODEOPS"
:clr EBitAddr is opfull=0xa5; ophi=12 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { EBitByteAddr = clr(EBitAddr, EBitByteAddr); }
#:CLR PortBit is opfull=0xa5; ophi=12 & oplo=2; PortBit & sfrbit & EBitByteAddr { outp(PortBit, 0:1, EBitByteAddr); }
@elif BIT_OPS == "SHIFTS"
:clr EBitAddr is opfull=0xa5; ophi=12 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { tmp:1 = ~(1<<sfrbit); EBitByteAddr = EBitByteAddr & tmp; }
@endif
:cpl EBitAddr is opfull=0xa5; ophi=11 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr { tmp:1 = (1<<sfrbit); EBitByteAddr = EBitByteAddr ^ tmp; }
@if BIT_OPS == "BIT_ADDRS"
:cpl EBitAddr is opfull=0xa5; ophi=11 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { EBitAddr = EBitAddr ^ 1; }
@elif BIT_OPS == "PCODEOPS"
:cpl EBitAddr is opfull=0xa5; ophi=11 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { tmp:1 = get(EBitAddr, EBitByteAddr) ^ 1; EBitByteAddr = set_bit_value(EBitAddr, tmp, EBitByteAddr); }
@elif BIT_OPS == "SHIFTS"
:cpl EBitAddr is opfull=0xa5; ophi=11 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { tmp:1 = (1<<sfrbit); EBitByteAddr = EBitByteAddr ^ tmp; }
@endif
:jb EBitAddr,Rel8 is opfull=0xa5; ophi=2 & oplo=0; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr; Rel8 { if (((EBitByteAddr>>sfrbit)&1) == 1:1) goto Rel8; }
:jbc EBitAddr,Rel8 is opfull=0xa5; ophi=1 & oplo=0; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr; Rel8 { tmp:1 = 1<<sfrbit; if ((EBitByteAddr & tmp)==0) goto inst_next; EBitByteAddr = EBitByteAddr & ~tmp; goto Rel8; }
@if BIT_OPS == "BIT_ADDRS"
:jb EBitAddr,Rel8 is opfull=0xa5; ophi=2 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { if (EBitAddr == 1:1) goto Rel8; }
:jbc EBitAddr,Rel8 is opfull=0xa5; ophi=1 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { if (EBitAddr == 0:1) goto inst_next; EBitAddr = 0; goto Rel8; }
@elif BIT_OPS == "PCODEOPS"
:jb EBitAddr,Rel8 is opfull=0xa5; ophi=2 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { if (get(EBitAddr, EBitByteAddr)==1:1) goto Rel8; }
:jbc EBitAddr,Rel8 is opfull=0xa5; ophi=1 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { tmp:1 = get(EBitAddr, EBitByteAddr); if (tmp==0) goto inst_next; EBitByteAddr = clr(EBitAddr, EBitByteAddr); goto Rel8; }
@elif BIT_OPS == "SHIFTS"
:jb EBitAddr,Rel8 is opfull=0xa5; ophi=2 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { if (((EBitByteAddr>>sfrbit)&1) == 1:1) goto Rel8; }
:jbc EBitAddr,Rel8 is opfull=0xa5; ophi=1 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { tmp:1 = 1<<sfrbit; if ((EBitByteAddr & tmp)==0) goto inst_next; EBitByteAddr = EBitByteAddr & ~tmp; goto Rel8; }
@endif
:jnb EBitAddr,Rel8 is opfull=0xa5; ophi=3 & oplo=0; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr; Rel8 { if (((EBitByteAddr>>sfrbit)&1)==0:1) goto Rel8; }
@if BIT_OPS == "BIT_ADDRS"
:jnb EBitAddr,Rel8 is opfull=0xa5; ophi=3 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { if (EBitAddr == 0:1) goto Rel8; }
@elif BIT_OPS == "PCODEOPS"
:jnb EBitAddr,Rel8 is opfull=0xa5; ophi=3 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { if (get(EBitAddr, EBitByteAddr)==0:1) goto Rel8; }
@elif BIT_OPS == "SHIFTS"
:jnb EBitAddr,Rel8 is opfull=0xa5; ophi=3 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { if (((EBitByteAddr>>sfrbit)&1)==0:1) goto Rel8; }
@endif
:mov CY,EBitAddr is opfull=0xa5; CY & ophi=10 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr {$(CY)= (EBitByteAddr>>sfrbit)&1; }
:mov EBitAddr,CY is opfull=0xa5; CY & ophi=9 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr { EBitByteAddr = EBitByteAddr & (~(1<<sfrbit)); EBitByteAddr = EBitByteAddr | ($(CY)<<sfrbit); }
@if BIT_OPS == "BIT_ADDRS"
:mov CY,EBitAddr is opfull=0xa5; CY & ophi=10 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)= EBitAddr; }
:mov EBitAddr,CY is opfull=0xa5; CY & ophi=9 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { EBitAddr = $(CY); }
@elif BIT_OPS == "PCODEOPS"
:mov CY,EBitAddr is opfull=0xa5; CY & ophi=10 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY) = get(EBitAddr, EBitByteAddr); }
:mov EBitAddr,CY is opfull=0xa5; CY & ophi=9 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { EBitByteAddr = set_bit_value(EBitAddr, $(CY), EBitByteAddr); }
@elif BIT_OPS == "SHIFTS"
:mov CY,EBitAddr is opfull=0xa5; CY & ophi=10 & oplo=2; EBitAddr & sfrbit & EBitByteAddr{$(CY)= (EBitByteAddr>>sfrbit)&1; }
:mov EBitAddr,CY is opfull=0xa5; CY & ophi=9 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { EBitByteAddr = EBitByteAddr & (~(1<<sfrbit)); EBitByteAddr = EBitByteAddr | ($(CY)<<sfrbit); }
@endif
:orl CY,EBitAddr is opfull=0xa5; CY & ophi=7 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr {$(CY)=$(CY)| ((EBitByteAddr>>sfrbit)&1); }
:orl CY,EBitAddr2 is opfull=0xa5; CY & ophi=10 & oplo=0; EBitAddr2 & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr {$(CY)=$(CY)| (((EBitByteAddr>>sfrbit)&1)^1); }
@if BIT_OPS == "BIT_ADDRS"
:orl CY,EBitAddr is opfull=0xa5; CY & ophi=7 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)| EBitAddr; }
:orl CY,EBitAddr2 is opfull=0xa5; CY & ophi=10 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)| (EBitAddr2^1); }
@elif BIT_OPS == "PCODEOPS"
:orl CY,EBitAddr is opfull=0xa5; CY & ophi=7 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)| get(EBitAddr, EBitByteAddr); }
:orl CY,EBitAddr2 is opfull=0xa5; CY & ophi=10 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)| (get(EBitAddr2, EBitByteAddr)^1); }
@elif BIT_OPS == "SHIFTS"
:orl CY,EBitAddr is opfull=0xa5; CY & ophi=7 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)| ((EBitByteAddr>>sfrbit)&1); }
:orl CY,EBitAddr2 is opfull=0xa5; CY & ophi=10 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)| (((EBitByteAddr>>sfrbit)&1)^1); }
@endif
:setb EBitAddr is opfull=0xa5; ophi=13 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr { EBitByteAddr = EBitByteAddr | (1<<sfrbit); }
@if BIT_OPS == "BIT_ADDRS"
:setb EBitAddr is opfull=0xa5; ophi=13 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { EBitAddr = 1; }
@elif BIT_OPS == "PCODEOPS"
:setb EBitAddr is opfull=0xa5; ophi=13 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { EBitByteAddr = set(EBitAddr, EBitByteAddr); }
@elif BIT_OPS == "SHIFTS"
:setb EBitAddr is opfull=0xa5; ophi=13 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { EBitByteAddr = EBitByteAddr | (1<<sfrbit); }
@endif
########################################################################
@if defined(INS_FUSION)
# Eventually, it is hoped that the decompiler will just handle these.
# In the meantime, lets try to rewrite so to help the decompiler out.
#
# Due to compiler optimizations, this can sometimes lead to bad results
# on 8051 derivatives. E.g, jumps to the middle of the fused instruction.
define token Fuse4ByteToken (32)
f4op1 = (24,31)
f4op1imm8 = (16,23)
f4op2 = (8,15)
f4op2imm8 = (0,7)
;
f4imm16: val is f4op1imm8 & f4op2imm8 [ val = (f4op2imm8 << 8) | f4op1imm8; ] { tmp:2 = val; export tmp; }
# Just do r7 r6 for now
:mov_fused R6R7,"#"f4imm16 is f4op1=0x7f & f4op2=0x7e & R6R7 & f4imm16 {
R6R7 = f4imm16;
}
@endif
python/icicle/Ghidra/Processors/8051/data/languages/mx51.slaspec
+7 -7
View File
@@ -1,7 +1,7 @@
@define MX51 ""
@define OMIT_RETADDR 1
@define DUAL_DPTR ""
@define DPS_REG_NUM 0xa2
@include "8051_main.sinc"
@include "mx51.sinc"
@define MX51 ""
@define OMIT_RETADDR 1
@define DUAL_DPTR ""
@define DPS_REG_NUM 0xa2
@include "8051_main.sinc"
@include "mx51.sinc"
python/icicle/Ghidra/Processors/8051/data/languages/old/8051v1.lang
+44 -44
View File
@@ -1,44 +1,44 @@
<?xml version="1.0" encoding="UTF-8"?>
<language version="1" endian="big">
<description>
<id>8051:BE:16:default</id>
<processor>8051</processor>
<variant>default</variant>
<size>16</size>
</description>
<compiler name="default" id="default" />
<compiler name="Archimedes" id="Archimedes" />
<spaces>
<space name="CODE" type="ram" size="2" default="yes" />
<space name="INTMEM" type="ram" size="1" />
<space name="BITS" type="ram" size="1" />
<space name="SFR" type="ram" size="1" />
<space name="EXTMEM" type="ram" size="2" />
<space name="register" type="register" size="1" />
</spaces>
<registers>
<register name="R0" offset="0x0" bitsize="8" />
<register name="R1" offset="0x1" bitsize="8" />
<register name="R2" offset="0x2" bitsize="8" />
<register name="R3" offset="0x3" bitsize="8" />
<register name="R4" offset="0x4" bitsize="8" />
<register name="R5" offset="0x5" bitsize="8" />
<register name="R6" offset="0x6" bitsize="8" />
<register name="R7" offset="0x7" bitsize="8" />
<register name="R3R2R1" offset="0x1" bitsize="24" />
<register name="R2R1" offset="0x1" bitsize="16" />
<register name="R5R4" offset="0x4" bitsize="16" />
<register name="R7R6" offset="0x6" bitsize="16" />
<register name="R7R6R5R4" offset="0x4" bitsize="32" />
<register name="ACC" offset="0xe0" bitsize="8" />
<register name="B" offset="0xf0" bitsize="8" />
<register name="C" offset="0x22" bitsize="8" />
<register name="DPTR" offset="0x82" bitsize="16" />
<register name="DPH" offset="0x82" bitsize="8" />
<register name="DPL" offset="0x83" bitsize="8" />
<register name="PC" offset="0x20" bitsize="16" />
<register name="SP" offset="0x81" bitsize="8" />
<register name="PSW" address="SFR:d0" bitsize="8" />
</registers>
</language>
<?xml version="1.0" encoding="UTF-8"?>
<language version="1" endian="big">
<description>
<id>8051:BE:16:default</id>
<processor>8051</processor>
<variant>default</variant>
<size>16</size>
</description>
<compiler name="default" id="default" />
<compiler name="Archimedes" id="Archimedes" />
<spaces>
<space name="CODE" type="ram" size="2" default="yes" />
<space name="INTMEM" type="ram" size="1" />
<space name="BITS" type="ram" size="1" />
<space name="SFR" type="ram" size="1" />
<space name="EXTMEM" type="ram" size="2" />
<space name="register" type="register" size="1" />
</spaces>
<registers>
<register name="R0" offset="0x0" bitsize="8" />
<register name="R1" offset="0x1" bitsize="8" />
<register name="R2" offset="0x2" bitsize="8" />
<register name="R3" offset="0x3" bitsize="8" />
<register name="R4" offset="0x4" bitsize="8" />
<register name="R5" offset="0x5" bitsize="8" />
<register name="R6" offset="0x6" bitsize="8" />
<register name="R7" offset="0x7" bitsize="8" />
<register name="R3R2R1" offset="0x1" bitsize="24" />
<register name="R2R1" offset="0x1" bitsize="16" />
<register name="R5R4" offset="0x4" bitsize="16" />
<register name="R7R6" offset="0x6" bitsize="16" />
<register name="R7R6R5R4" offset="0x4" bitsize="32" />
<register name="ACC" offset="0xe0" bitsize="8" />
<register name="B" offset="0xf0" bitsize="8" />
<register name="C" offset="0x22" bitsize="8" />
<register name="DPTR" offset="0x82" bitsize="16" />
<register name="DPH" offset="0x82" bitsize="8" />
<register name="DPL" offset="0x83" bitsize="8" />
<register name="PC" offset="0x20" bitsize="16" />
<register name="SP" offset="0x81" bitsize="8" />
<register name="PSW" address="SFR:d0" bitsize="8" />
</registers>
</language>
python/icicle/Ghidra/Processors/8051/data/languages/old/8051v1.trans
+8 -8
View File
@@ -1,8 +1,8 @@
<?xml version="1.0" encoding="UTF-8"?>
<language_translation>
<from_language version="1">8051:BE:16:default</from_language>
<to_language version="2">8051:BE:16:default</to_language>
<map_compiler_spec from="default" to="default" />
<map_compiler_spec from="Archimedes" to="Archimedes" />
</language_translation>
<?xml version="1.0" encoding="UTF-8"?>
<language_translation>
<from_language version="1">8051:BE:16:default</from_language>
<to_language version="2">8051:BE:16:default</to_language>
<map_compiler_spec from="default" to="default" />
<map_compiler_spec from="Archimedes" to="Archimedes" />
</language_translation>
python/icicle/Ghidra/Processors/8085/data/languages/8085.cspec
+28 -28
View File
@@ -1,28 +1,28 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<global>
<range space="ram"/>
</global>
<stackpointer register="SP" space="ram" growth="negative"/>
<default_proto>
<prototype name="__stdcall" extrapop="2" stackshift="2">
<input>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="B"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
</unaffected>
</prototype>
</default_proto>
</compiler_spec>
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<global>
<range space="ram"/>
</global>
<stackpointer register="SP" space="ram" growth="negative"/>
<default_proto>
<prototype name="__stdcall" extrapop="2" stackshift="2">
<input>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
<pentry minsize="1" maxsize="1">
<register name="B"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
</unaffected>
</prototype>
</default_proto>
</compiler_spec>
python/icicle/Ghidra/Processors/8085/data/languages/8085.ldefs
+15 -15
View File
@@ -1,15 +1,15 @@
<?xml version="1.0" encoding="UTF-8"?>
<language_definitions>
<language processor="8085"
endian="little"
size="16"
variant="default"
version="1.0"
slafile="8085.sla"
processorspec="8085.pspec"
id="8085:LE:16:default">
<description>Intel 8085</description>
<compiler name="default" spec="8085.cspec" id="default"/>
</language>
</language_definitions>
<?xml version="1.0" encoding="UTF-8"?>
<language_definitions>
<language processor="8085"
endian="little"
size="16"
variant="default"
version="1.0"
slafile="8085.sla"
processorspec="8085.pspec"
id="8085:LE:16:default">
<description>Intel 8085</description>
<compiler name="default" spec="8085.cspec" id="default"/>
</language>
</language_definitions>
python/icicle/Ghidra/Processors/8085/data/languages/8085.pspec
+30 -30
View File
@@ -1,30 +1,30 @@
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="PC"/>
<register_data>
<register name="CY_flag" group="Flags"/>
<register name="P_flag" group="Flags"/>
<register name="AC_flag" group="Flags"/>
<register name="Z_flag" group="Flags"/>
<register name="S_flag" group="Flags"/>
<register name="AF_" group="Alt"/>
<register name="BC_" group="Alt"/>
<register name="DE_" group="Alt"/>
<register name="HL_" group="Alt"/>
</register_data>
<default_symbols>
<symbol name="RST0" address="ram:0000" entry="true"/>
<symbol name="RST1" address="ram:0008" entry="false"/>
<symbol name="RST2" address="ram:0010" entry="false"/>
<symbol name="RST3" address="ram:0018" entry="false"/>
<symbol name="RST4" address="ram:0020" entry="false"/>
<symbol name="RST5" address="ram:0028" entry="false"/>
<symbol name="RST6" address="ram:0030" entry="false"/>
<symbol name="RST7" address="ram:0038" entry="false"/>
<symbol name="RST5.5" address="ram:002c" entry="false"/>
<symbol name="RST6.5" address="ram:0034" entry="false"/>
<symbol name="RST7.5" address="ram:003c" entry="false"/>
<symbol name="TRAP" address="ram:0024" entry="false"/>
</default_symbols>
</processor_spec>
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="PC"/>
<register_data>
<register name="CY_flag" group="Flags"/>
<register name="P_flag" group="Flags"/>
<register name="AC_flag" group="Flags"/>
<register name="Z_flag" group="Flags"/>
<register name="S_flag" group="Flags"/>
<register name="AF_" group="Alt"/>
<register name="BC_" group="Alt"/>
<register name="DE_" group="Alt"/>
<register name="HL_" group="Alt"/>
</register_data>
<default_symbols>
<symbol name="RST0" address="ram:0000" entry="true"/>
<symbol name="RST1" address="ram:0008" entry="false"/>
<symbol name="RST2" address="ram:0010" entry="false"/>
<symbol name="RST3" address="ram:0018" entry="false"/>
<symbol name="RST4" address="ram:0020" entry="false"/>
<symbol name="RST5" address="ram:0028" entry="false"/>
<symbol name="RST6" address="ram:0030" entry="false"/>
<symbol name="RST7" address="ram:0038" entry="false"/>
<symbol name="RST5.5" address="ram:002c" entry="false"/>
<symbol name="RST6.5" address="ram:0034" entry="false"/>
<symbol name="RST7.5" address="ram:003c" entry="false"/>
<symbol name="TRAP" address="ram:0024" entry="false"/>
</default_symbols>
</processor_spec>
python/icicle/Ghidra/Processors/8085/data/languages/8085.slaspec
+551 -551
View File
File diff suppressed because it is too large Load Diff
python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.cspec
+202 -205
View File
@@ -1,205 +1,202 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<data_organization>
<absolute_max_alignment value="0" />
<machine_alignment value="4" />
<default_alignment value="1" />
<default_pointer_alignment value="8" />
<pointer_size value="8" />
<wchar_size value="4" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="8" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="8" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="8" />
</size_alignment_map>
</data_organization>
<global>
<range space="ram"/>
<!-- The decompiler will treat registers in this range as global variables.
ie: tmp_ldWn, tmp_ldXn, tmp_stWn, tmp_stXn -->
<range space="register" first="0x3000" last="0x3fff"/>
</global>
<stackpointer register="sp" space="ram"/>
<funcptr align="4"/> <!-- Function pointers are word aligned and leastsig bit may encode otherstuff -->
<prefersplit style="inhalf">
<register name="q0"/>
<register name="q1"/>
<register name="q2"/>
<register name="q3"/>
<register name="q4"/>
<register name="q5"/>
<register name="q6"/>
<register name="q7"/>
<register name="q8"/>
<register name="q9"/>
<register name="q10"/>
<register name="q11"/>
<register name="q12"/>
<register name="q13"/>
<register name="q14"/>
<register name="q15"/>
<register name="q16"/>
<register name="q17"/>
<register name="q18"/>
<register name="q19"/>
<register name="q20"/>
<register name="q21"/>
<register name="q22"/>
<register name="q23"/>
<register name="q24"/>
<register name="q25"/>
<register name="q26"/>
<register name="q27"/>
<register name="q28"/>
<register name="q29"/>
<register name="q30"/>
</prefersplit>
<default_proto>
<prototype name="__cdecl" extrapop="0" stackshift="0">
<input>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d0"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d1"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d2"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d3"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d4"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d5"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d6"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d7"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x0"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x1"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x2"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x3"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x4"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x5"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x6"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x7"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="0" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d0"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x0"/>
</pentry>
<pentry minsize="9" maxsize="16" extension="zero">
<addr space="join" piece1="x1" piece2="x0"/>
</pentry>
</output>
<unaffected>
<register name="x19"/>
<register name="x20"/>
<register name="x21"/>
<register name="x22"/>
<register name="x23"/>
<register name="x24"/>
<register name="x25"/>
<register name="x26"/>
<register name="x27"/>
<register name="x28"/>
<register name="x29"/>
<register name="x30"/>
<register name="sp"/>
<!-- vectors -->
<register name="d8"/>
<register name="d9"/>
<register name="d10"/>
<register name="d11"/>
<register name="d12"/>
<register name="d13"/>
<register name="d14"/>
<register name="d15"/>
</unaffected>
<killedbycall>
<!-- x8: indirect result location register, which is not
reflected in the pentry list -->
<register name="x8"/>
<register name="x9"/>
<register name="x10"/>
<register name="x11"/>
<register name="x12"/>
<register name="x13"/>
<register name="x14"/>
<register name="x15"/>
<register name="x16"/>
<register name="x17"/>
<register name="x18"/>
<!-- vectors -->
<register name="d16"/>
<register name="d17"/>
<register name="d18"/>
<register name="d19"/>
<register name="d20"/>
<register name="d21"/>
<register name="d22"/>
<register name="d23"/>
<register name="d24"/>
<register name="d25"/>
<register name="d26"/>
<register name="d27"/>
<register name="d28"/>
<register name="d29"/>
<register name="d30"/>
<register name="d31"/>
</killedbycall>
</prototype>
</default_proto>
<callfixup name="PlaceHolderCallFixup"> <!-- This is here just to force call fixup and NoReturn fixup. Will be fixed in Ghidra V6.0 -->
<target name="___NotARealFunctionName___"/>
<pcode>
<body><![CDATA[
tmpptr:4 = 0;
]]></body>
</pcode>
</callfixup>
</compiler_spec>
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<data_organization>
<absolute_max_alignment value="0" />
<machine_alignment value="4" />
<default_alignment value="1" />
<default_pointer_alignment value="8" />
<pointer_size value="8" />
<wchar_size value="4" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="8" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="8" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="8" />
</size_alignment_map>
</data_organization>
<global>
<range space="ram"/>
</global>
<stackpointer register="sp" space="ram"/>
<funcptr align="4"/> <!-- Function pointers are word aligned and leastsig bit may encode otherstuff -->
<prefersplit style="inhalf">
<register name="q0"/>
<register name="q1"/>
<register name="q2"/>
<register name="q3"/>
<register name="q4"/>
<register name="q5"/>
<register name="q6"/>
<register name="q7"/>
<register name="q8"/>
<register name="q9"/>
<register name="q10"/>
<register name="q11"/>
<register name="q12"/>
<register name="q13"/>
<register name="q14"/>
<register name="q15"/>
<register name="q16"/>
<register name="q17"/>
<register name="q18"/>
<register name="q19"/>
<register name="q20"/>
<register name="q21"/>
<register name="q22"/>
<register name="q23"/>
<register name="q24"/>
<register name="q25"/>
<register name="q26"/>
<register name="q27"/>
<register name="q28"/>
<register name="q29"/>
<register name="q30"/>
</prefersplit>
<default_proto>
<prototype name="__cdecl" extrapop="0" stackshift="0">
<input>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d0"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d1"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d2"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d3"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d4"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d5"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d6"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d7"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x0"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x1"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x2"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x3"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x4"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x5"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x6"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x7"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="0" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d0"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x0"/>
</pentry>
<pentry minsize="9" maxsize="16" extension="zero">
<addr space="join" piece1="x1" piece2="x0"/>
</pentry>
</output>
<unaffected>
<register name="x19"/>
<register name="x20"/>
<register name="x21"/>
<register name="x22"/>
<register name="x23"/>
<register name="x24"/>
<register name="x25"/>
<register name="x26"/>
<register name="x27"/>
<register name="x28"/>
<register name="x29"/>
<register name="x30"/>
<register name="sp"/>
<!-- vectors -->
<register name="d8"/>
<register name="d9"/>
<register name="d10"/>
<register name="d11"/>
<register name="d12"/>
<register name="d13"/>
<register name="d14"/>
<register name="d15"/>
</unaffected>
<killedbycall>
<!-- x8: indirect result location register, which is not
reflected in the pentry list -->
<register name="x8"/>
<register name="x9"/>
<register name="x10"/>
<register name="x11"/>
<register name="x12"/>
<register name="x13"/>
<register name="x14"/>
<register name="x15"/>
<register name="x16"/>
<register name="x17"/>
<register name="x18"/>
<!-- vectors -->
<register name="d16"/>
<register name="d17"/>
<register name="d18"/>
<register name="d19"/>
<register name="d20"/>
<register name="d21"/>
<register name="d22"/>
<register name="d23"/>
<register name="d24"/>
<register name="d25"/>
<register name="d26"/>
<register name="d27"/>
<register name="d28"/>
<register name="d29"/>
<register name="d30"/>
<register name="d31"/>
</killedbycall>
</prototype>
</default_proto>
<callfixup name="PlaceHolderCallFixup"> <!-- This is here just to force call fixup and NoReturn fixup. Will be fixed in Ghidra V6.0 -->
<target name="___NotARealFunctionName___"/>
<pcode>
<body><![CDATA[
tmpptr:4 = 0;
]]></body>
</pcode>
</callfixup>
</compiler_spec>
python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.dwarf
+8 -8
View File
@@ -1,8 +1,8 @@
<dwarf>
<register_mappings>
<register_mapping dwarf="0" ghidra="x0" auto_count="31"/> <!-- x0..x30 -->
<register_mapping dwarf="31" ghidra="xzr" stackpointer="true"/>
<register_mapping dwarf="64" ghidra="q0" auto_count="32"/> <!-- q0..q31 -->
</register_mappings>
<call_frame_cfa value="0"/>
</dwarf>
<dwarf>
<register_mappings>
<register_mapping dwarf="0" ghidra="x0" auto_count="31"/> <!-- x0..x30 -->
<register_mapping dwarf="31" ghidra="xzr" stackpointer="true"/>
<register_mapping dwarf="64" ghidra="q0" auto_count="32"/> <!-- q0..q31 -->
</register_mappings>
<call_frame_cfa value="0"/>
</dwarf>
python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.ldefs
+64 -64
View File
@@ -1,64 +1,64 @@
<?xml version="1.1" encoding="UTF-8"?>
<language_definitions>
<language processor="AARCH64"
endian="little"
size="64"
variant="v8A"
version="1.6"
slafile="AARCH64.sla"
processorspec="AARCH64.pspec"
manualindexfile="../manuals/AARCH64.idx"
id="AARCH64:LE:64:v8A">
<description>Generic ARM64 v8.5-A LE instructions, LE data, missing some 8.5 vector</description>
<compiler name="default" spec="AARCH64.cspec" id="default"/>
<compiler name="Visual Studio" spec="AARCH64_win.cspec" id="windows"/>
<external_name tool="gnu" name="aarch64"/>
<external_name tool="DWARF.register.mapping.file" name="AARCH64.dwarf"/>
</language>
<language processor="AARCH64"
endian="big"
instructionEndian="little"
size="64"
variant="v8A"
version="1.6"
slafile="AARCH64BE.sla"
processorspec="AARCH64.pspec"
manualindexfile="../manuals/AARCH64.idx"
id="AARCH64:BE:64:v8A">
<description>Generic ARM64 v8.5-A LE instructions, BE data, missing some 8.5 vector</description>
<compiler name="default" spec="AARCH64.cspec" id="default"/>
<external_name tool="gnu" name="aarch64"/>
<external_name tool="DWARF.register.mapping.file" name="AARCH64.dwarf"/>
</language>
<language processor="AARCH64"
endian="little"
size="32"
variant="ilp32"
version="1.5"
slafile="AARCH64.sla"
processorspec="AARCH64.pspec"
manualindexfile="../manuals/AARCH64.idx"
id="AARCH64:LE:32:ilp32">
<description>Generic ARM64 v8.5-A LE instructions, LE data, ilp32</description>
<truncate_space space="ram" size="4"/>
<compiler name="default" spec="AARCH64_ilp32.cspec" id="default"/>
<external_name tool="gnu" name="aarch64:ilp32"/>
<external_name tool="DWARF.register.mapping.file" name="AARCH64.dwarf"/>
</language>
<language processor="AARCH64"
endian="big"
instructionEndian="little"
size="32"
variant="ilp32"
version="1.5"
slafile="AARCH64BE.sla"
processorspec="AARCH64.pspec"
manualindexfile="../manuals/AARCH64.idx"
id="AARCH64:BE:32:ilp32">
<description>Generic ARM64 v8.5-A LE instructions, BE data, ilp32</description>
<truncate_space space="ram" size="4"/>
<compiler name="default" spec="AARCH64_ilp32.cspec" id="default"/>
<external_name tool="gnu" name="aarch64:ilp32"/>
<external_name tool="DWARF.register.mapping.file" name="AARCH64.dwarf"/>
</language>
</language_definitions>
<?xml version="1.1" encoding="UTF-8"?>
<language_definitions>
<language processor="AARCH64"
endian="little"
size="64"
variant="v8A"
version="1.6"
slafile="AARCH64.sla"
processorspec="AARCH64.pspec"
manualindexfile="../manuals/AARCH64.idx"
id="AARCH64:LE:64:v8A">
<description>Generic ARM64 v8.5-A LE instructions, LE data, missing some 8.5 vector</description>
<compiler name="default" spec="AARCH64.cspec" id="default"/>
<compiler name="Visual Studio" spec="AARCH64_win.cspec" id="windows"/>
<external_name tool="gnu" name="aarch64"/>
<external_name tool="DWARF.register.mapping.file" name="AARCH64.dwarf"/>
</language>
<language processor="AARCH64"
endian="big"
instructionEndian="little"
size="64"
variant="v8A"
version="1.6"
slafile="AARCH64BE.sla"
processorspec="AARCH64.pspec"
manualindexfile="../manuals/AARCH64.idx"
id="AARCH64:BE:64:v8A">
<description>Generic ARM64 v8.5-A LE instructions, BE data, missing some 8.5 vector</description>
<compiler name="default" spec="AARCH64.cspec" id="default"/>
<external_name tool="gnu" name="aarch64"/>
<external_name tool="DWARF.register.mapping.file" name="AARCH64.dwarf"/>
</language>
<language processor="AARCH64"
endian="little"
size="32"
variant="ilp32"
version="1.5"
slafile="AARCH64.sla"
processorspec="AARCH64.pspec"
manualindexfile="../manuals/AARCH64.idx"
id="AARCH64:LE:32:ilp32">
<description>Generic ARM64 v8.5-A LE instructions, LE data, ilp32</description>
<truncate_space space="ram" size="4"/>
<compiler name="default" spec="AARCH64_ilp32.cspec" id="default"/>
<external_name tool="gnu" name="aarch64:ilp32"/>
<external_name tool="DWARF.register.mapping.file" name="AARCH64.dwarf"/>
</language>
<language processor="AARCH64"
endian="big"
instructionEndian="little"
size="32"
variant="ilp32"
version="1.5"
slafile="AARCH64BE.sla"
processorspec="AARCH64.pspec"
manualindexfile="../manuals/AARCH64.idx"
id="AARCH64:BE:32:ilp32">
<description>Generic ARM64 v8.5-A LE instructions, BE data, ilp32</description>
<truncate_space space="ram" size="4"/>
<compiler name="default" spec="AARCH64_ilp32.cspec" id="default"/>
<external_name tool="gnu" name="aarch64:ilp32"/>
<external_name tool="DWARF.register.mapping.file" name="AARCH64.dwarf"/>
</language>
</language_definitions>
python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.opinion
+19 -17
View File
@@ -1,17 +1,19 @@
<opinions>
<constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default">
<constraint primary="183" processor="AARCH64" size="64" variant="v8A" />
</constraint>
<constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default">
<constraint primary="183" processor="AARCH64" size="32" variant="ilp32" />
</constraint>
<constraint loader="Mac OS X Mach-O" compilerSpecID="default">
<constraint primary="16777228" processor="AARCH64" endian="little" size="64" variant="AppleSilicon" />
</constraint>
<constraint loader="DYLD Cache" compilerSpecID="default">
<constraint primary="AARCH64" processor="AARCH64" endian="little" size="64" variant="AppleSilicon" />
</constraint>
<constraint loader="Portable Executable (PE)" compilerSpecID="windows">
<constraint primary="43620" processor="AARCH64" endian="little" size="64" variant="v8A" />
</constraint>
</opinions>
<opinions>
<constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default">
<constraint primary="183" processor="AARCH64" size="64" variant="v8A" />
</constraint>
<constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default">
<constraint primary="183" processor="AARCH64" size="32" variant="ilp32" />
</constraint>
<constraint loader="Mac OS X Mach-O" compilerSpecID="default">
<constraint primary="16777228" processor="AARCH64" endian="little" size="64" variant="AppleSilicon" />
<constraint primary="33554444" processor="AARCH64" endian="little" size="32" variant="ilp32" />
</constraint>
<constraint loader="DYLD Cache" compilerSpecID="default">
<constraint primary="AARCH64" processor="AARCH64" endian="little" size="64" variant="AppleSilicon" />
<constraint primary="ARM64_32" processor="AARCH64" endian="little" size="32" variant="ilp32" />
</constraint>
<constraint loader="Portable Executable (PE)" compilerSpecID="windows">
<constraint primary="43620" processor="AARCH64" endian="little" size="64" variant="v8A" />
</constraint>
</opinions>
python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.pspec
+101 -101
View File
@@ -1,101 +1,101 @@
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<properties>
<property key="addressesDoNotAppearDirectlyInCode" value="true"/>
<property key="allowOffcutReferencesToFunctionStarts" value="false"/>
<property key="useNewFunctionStackAnalysis" value="true"/>
<property key="emulateInstructionStateModifierClass"
value="ghidra.program.emulation.AARCH64EmulateInstructionStateModifier"/>
<property key="assemblyRating:AARCH64:BE:64:v8A" value="PLATINUM"/>
<property key="assemblyRating:AARCH64:LE:64:v8A" value="PLATINUM"/>
</properties>
<programcounter register="pc"/>
<!-- The context_data's context_set initializes the given registers to the given values. -->
<context_data>
<context_set space="ram">
<!-- These context registers are only modified by the user, e.g. with the "Set Registers..." command. -->
<set name="ShowPAC" val="0" description="1 to show PAC operations in decompiler"/>
<set name="PAC_clobber" val="0" description="1 to let PAC operations overwrite their operands in decompiler"/>
<set name="ShowBTI" val="0" description="1 to show BTI effects in decompiler"/>
<set name="ShowMemTag" val="0" description="1 to show memory tag checks in decompiler"/>
</context_set>
</context_data>
<default_symbols>
<symbol name="Reset" address="ram:0x0" entry="true"/>
</default_symbols>
<volatile outputop="cWrite" inputop="cRead">
<range space="register" first="0x1000" last="0x3fff"/>
</volatile>
<register_data>
<register name="z0" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z1" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z2" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z3" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z4" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z5" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z6" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z7" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z8" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z9" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z10" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z11" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z12" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z13" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z14" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z15" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z16" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z17" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z18" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z19" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z20" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z21" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z22" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z23" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z24" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z25" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z26" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z27" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z28" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z29" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z30" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z31" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="q0" vector_lane_sizes="1,2,4,8"/>
<register name="q1" vector_lane_sizes="1,2,4,8"/>
<register name="q2" vector_lane_sizes="1,2,4,8"/>
<register name="q3" vector_lane_sizes="1,2,4,8"/>
<register name="q4" vector_lane_sizes="1,2,4,8"/>
<register name="q5" vector_lane_sizes="1,2,4,8"/>
<register name="q6" vector_lane_sizes="1,2,4,8"/>
<register name="q7" vector_lane_sizes="1,2,4,8"/>
<register name="q8" vector_lane_sizes="1,2,4,8"/>
<register name="q9" vector_lane_sizes="1,2,4,8"/>
<register name="q10" vector_lane_sizes="1,2,4,8"/>
<register name="q11" vector_lane_sizes="1,2,4,8"/>
<register name="q12" vector_lane_sizes="1,2,4,8"/>
<register name="q13" vector_lane_sizes="1,2,4,8"/>
<register name="q14" vector_lane_sizes="1,2,4,8"/>
<register name="q15" vector_lane_sizes="1,2,4,8"/>
<register name="q16" vector_lane_sizes="1,2,4,8"/>
<register name="q17" vector_lane_sizes="1,2,4,8"/>
<register name="q18" vector_lane_sizes="1,2,4,8"/>
<register name="q19" vector_lane_sizes="1,2,4,8"/>
<register name="q20" vector_lane_sizes="1,2,4,8"/>
<register name="q21" vector_lane_sizes="1,2,4,8"/>
<register name="q22" vector_lane_sizes="1,2,4,8"/>
<register name="q23" vector_lane_sizes="1,2,4,8"/>
<register name="q24" vector_lane_sizes="1,2,4,8"/>
<register name="q25" vector_lane_sizes="1,2,4,8"/>
<register name="q26" vector_lane_sizes="1,2,4,8"/>
<register name="q27" vector_lane_sizes="1,2,4,8"/>
<register name="q28" vector_lane_sizes="1,2,4,8"/>
<register name="q29" vector_lane_sizes="1,2,4,8"/>
<register name="q30" vector_lane_sizes="1,2,4,8"/>
<register name="q31" vector_lane_sizes="1,2,4,8"/>
</register_data>
</processor_spec>
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<properties>
<property key="addressesDoNotAppearDirectlyInCode" value="true"/>
<property key="allowOffcutReferencesToFunctionStarts" value="false"/>
<property key="useNewFunctionStackAnalysis" value="true"/>
<property key="emulateInstructionStateModifierClass"
value="ghidra.program.emulation.AARCH64EmulateInstructionStateModifier"/>
<property key="assemblyRating:AARCH64:BE:64:v8A" value="PLATINUM"/>
<property key="assemblyRating:AARCH64:LE:64:v8A" value="PLATINUM"/>
</properties>
<programcounter register="pc"/>
<!-- The context_data's context_set initializes the given registers to the given values. -->
<context_data>
<context_set space="ram">
<!-- These context registers are only modified by the user, e.g. with the "Set Registers..." command. -->
<set name="ShowPAC" val="0" description="1 to show PAC operations in decompiler"/>
<set name="PAC_clobber" val="0" description="1 to let PAC operations overwrite their operands in decompiler"/>
<set name="ShowBTI" val="0" description="1 to show BTI effects in decompiler"/>
<set name="ShowMemTag" val="0" description="1 to show memory tag checks in decompiler"/>
</context_set>
</context_data>
<default_symbols>
<symbol name="Reset" address="ram:0x0" entry="true"/>
</default_symbols>
<volatile outputop="cWrite" inputop="cRead">
<range space="register" first="0x1000" last="0x2fff"/>
</volatile>
<register_data>
<register name="z0" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z1" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z2" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z3" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z4" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z5" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z6" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z7" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z8" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z9" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z10" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z11" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z12" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z13" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z14" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z15" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z16" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z17" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z18" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z19" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z20" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z21" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z22" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z23" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z24" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z25" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z26" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z27" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z28" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z29" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z30" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="z31" group="SVE" vector_lane_sizes="1,2,4,8"/>
<register name="q0" vector_lane_sizes="1,2,4,8"/>
<register name="q1" vector_lane_sizes="1,2,4,8"/>
<register name="q2" vector_lane_sizes="1,2,4,8"/>
<register name="q3" vector_lane_sizes="1,2,4,8"/>
<register name="q4" vector_lane_sizes="1,2,4,8"/>
<register name="q5" vector_lane_sizes="1,2,4,8"/>
<register name="q6" vector_lane_sizes="1,2,4,8"/>
<register name="q7" vector_lane_sizes="1,2,4,8"/>
<register name="q8" vector_lane_sizes="1,2,4,8"/>
<register name="q9" vector_lane_sizes="1,2,4,8"/>
<register name="q10" vector_lane_sizes="1,2,4,8"/>
<register name="q11" vector_lane_sizes="1,2,4,8"/>
<register name="q12" vector_lane_sizes="1,2,4,8"/>
<register name="q13" vector_lane_sizes="1,2,4,8"/>
<register name="q14" vector_lane_sizes="1,2,4,8"/>
<register name="q15" vector_lane_sizes="1,2,4,8"/>
<register name="q16" vector_lane_sizes="1,2,4,8"/>
<register name="q17" vector_lane_sizes="1,2,4,8"/>
<register name="q18" vector_lane_sizes="1,2,4,8"/>
<register name="q19" vector_lane_sizes="1,2,4,8"/>
<register name="q20" vector_lane_sizes="1,2,4,8"/>
<register name="q21" vector_lane_sizes="1,2,4,8"/>
<register name="q22" vector_lane_sizes="1,2,4,8"/>
<register name="q23" vector_lane_sizes="1,2,4,8"/>
<register name="q24" vector_lane_sizes="1,2,4,8"/>
<register name="q25" vector_lane_sizes="1,2,4,8"/>
<register name="q26" vector_lane_sizes="1,2,4,8"/>
<register name="q27" vector_lane_sizes="1,2,4,8"/>
<register name="q28" vector_lane_sizes="1,2,4,8"/>
<register name="q29" vector_lane_sizes="1,2,4,8"/>
<register name="q30" vector_lane_sizes="1,2,4,8"/>
<register name="q31" vector_lane_sizes="1,2,4,8"/>
</register_data>
</processor_spec>
python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.slaspec
+5 -5
View File
@@ -1,5 +1,5 @@
@define DATA_ENDIAN "little"
@include "AARCH64instructions.sinc"
@define DATA_ENDIAN "little"
@include "AARCH64instructions.sinc"
python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64BE.slaspec
+5 -5
View File
@@ -1,5 +1,5 @@
@define DATA_ENDIAN "big"
@include "AARCH64instructions.sinc"
@define DATA_ENDIAN "big"
@include "AARCH64instructions.sinc"
python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_AMXext.sinc
+170 -170
View File
@@ -1,171 +1,171 @@
#
# Apple AARCH64 extended matrix instructions
# Contents based on evolving information published on Web
#
#
define pcodeop __amx_ldx;
define pcodeop __amx_ldy;
define pcodeop __amx_stx;
define pcodeop __amx_sty;
define pcodeop __amx_ldz;
define pcodeop __amx_stz;
define pcodeop __amx_ldzi;
define pcodeop __amx_stzi;
define pcodeop __amx_extrx;
define pcodeop __amx_extry;
define pcodeop __amx_fma64;
define pcodeop __amx_fms64;
define pcodeop __amx_fma32;
define pcodeop __amx_fms32;
define pcodeop __amx_mac16;
define pcodeop __amx_fma16;
define pcodeop __amx_fms16;
define pcodeop __amx_enable;
define pcodeop __amx_disable;
define pcodeop __amx_vecint;
define pcodeop __amx_vecfp;
define pcodeop __amx_matint;
define pcodeop __amx_matfp;
define pcodeop __amx_genlut;
with : ImmS_ImmR_TestSet=1 {
AMXAddr: is Rd_GPR64 {
addr:8 = Rd_GPR64 & 0x00FFFFFFFFFFFFFF;
export addr;
}
AMXRegOff: is Rd_GPR64 {
registerOff:8 = (Rd_GPR64 >> 56) & 0x1F;
export registerOff;
}
AMXSize: is Rd_GPR64 {
local size = ((Rd_GPR64 >> 62) & 1);
size = zext(size == 0) * 0x40 | zext(size ==1 ) * 0x80;
export size;
}
:__amx_ldx Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=0 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
{
__amx_ldx(Rd_GPR64);
}
:__amx_ldy Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=1 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
{
__amx_ldy(Rd_GPR64);
}
:__amx_stx Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=2 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
{
__amx_stx(Rd_GPR64);
}
:__amx_sty Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=3 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
{
__amx_sty(Rd_GPR64);
}
:__amx_ldz Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=4 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
{
__amx_ldz(Rd_GPR64);
}
:__amx_stz Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=5 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
{
__amx_stz(Rd_GPR64);
}
:__amx_ldzi Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=6 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
{
__amx_ldzi(Rd_GPR64);
}
:__amx_stzi Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=7 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
{
__amx_stzi(Rd_GPR64);
}
:__amx_extrx Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=8 & Rd_GPR64
{
__amx_extrx(Rd_GPR64);
}
:__amx_extry Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=9 & Rd_GPR64
{
__amx_extry(Rd_GPR64);
}
:__amx_fma64 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=10 & Rd_GPR64
{
__amx_fma64(Rd_GPR64);
}
:__amx_fms64 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=11 & Rd_GPR64
{
__amx_fms64(Rd_GPR64);
}
:__amx_fma32 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=12 & Rd_GPR64
{
__amx_fma32(Rd_GPR64);
}
:__amx_fms32 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=13 & Rd_GPR64
{
__amx_fms32(Rd_GPR64);
}
:__amx_mac16 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=14 & Rd_GPR64
{
__amx_mac16(Rd_GPR64);
}
:__amx_fma16 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=15 & Rd_GPR64
{
__amx_fma16(Rd_GPR64);
}
:__amx_fms16 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=16 & Rd_GPR64
{
__amx_fms16(Rd_GPR64);
}
:__amxdisable is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=17 & b_0004=1
{
__amx_disable();
}
:__amxenable is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=17 & b_0004=0
{
__amx_enable();
}
:__amx_vecint Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=18 & Rd_GPR64
{
__amx_vecint(Rd_GPR64);
}
:__amx_vecfp Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=19 & Rd_GPR64
{
__amx_vecfp(Rd_GPR64);
}
:__amx_matint Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=20 & Rd_GPR64
{
__amx_matint(Rd_GPR64);
}
:__amx_matfp Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=21 & Rd_GPR64
{
__amx_matfp(Rd_GPR64);
}
:__amx_genlut Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=22 & Rd_GPR64
{
__amx_genlut(Rd_GPR64);
}
#
# Apple AARCH64 extended matrix instructions
# Contents based on evolving information published on Web
#
#
define pcodeop __amx_ldx;
define pcodeop __amx_ldy;
define pcodeop __amx_stx;
define pcodeop __amx_sty;
define pcodeop __amx_ldz;
define pcodeop __amx_stz;
define pcodeop __amx_ldzi;
define pcodeop __amx_stzi;
define pcodeop __amx_extrx;
define pcodeop __amx_extry;
define pcodeop __amx_fma64;
define pcodeop __amx_fms64;
define pcodeop __amx_fma32;
define pcodeop __amx_fms32;
define pcodeop __amx_mac16;
define pcodeop __amx_fma16;
define pcodeop __amx_fms16;
define pcodeop __amx_enable;
define pcodeop __amx_disable;
define pcodeop __amx_vecint;
define pcodeop __amx_vecfp;
define pcodeop __amx_matint;
define pcodeop __amx_matfp;
define pcodeop __amx_genlut;
with : ImmS_ImmR_TestSet=1 {
AMXAddr: is Rd_GPR64 {
addr:8 = Rd_GPR64 & 0x00FFFFFFFFFFFFFF;
export addr;
}
AMXRegOff: is Rd_GPR64 {
registerOff:8 = (Rd_GPR64 >> 56) & 0x1F;
export registerOff;
}
AMXSize: is Rd_GPR64 {
local size = ((Rd_GPR64 >> 62) & 1);
size = zext(size == 0) * 0x40 | zext(size ==1 ) * 0x80;
export size;
}
:__amx_ldx Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=0 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
{
__amx_ldx(Rd_GPR64);
}
:__amx_ldy Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=1 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
{
__amx_ldy(Rd_GPR64);
}
:__amx_stx Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=2 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
{
__amx_stx(Rd_GPR64);
}
:__amx_sty Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=3 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
{
__amx_sty(Rd_GPR64);
}
:__amx_ldz Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=4 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
{
__amx_ldz(Rd_GPR64);
}
:__amx_stz Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=5 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
{
__amx_stz(Rd_GPR64);
}
:__amx_ldzi Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=6 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
{
__amx_ldzi(Rd_GPR64);
}
:__amx_stzi Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=7 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
{
__amx_stzi(Rd_GPR64);
}
:__amx_extrx Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=8 & Rd_GPR64
{
__amx_extrx(Rd_GPR64);
}
:__amx_extry Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=9 & Rd_GPR64
{
__amx_extry(Rd_GPR64);
}
:__amx_fma64 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=10 & Rd_GPR64
{
__amx_fma64(Rd_GPR64);
}
:__amx_fms64 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=11 & Rd_GPR64
{
__amx_fms64(Rd_GPR64);
}
:__amx_fma32 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=12 & Rd_GPR64
{
__amx_fma32(Rd_GPR64);
}
:__amx_fms32 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=13 & Rd_GPR64
{
__amx_fms32(Rd_GPR64);
}
:__amx_mac16 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=14 & Rd_GPR64
{
__amx_mac16(Rd_GPR64);
}
:__amx_fma16 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=15 & Rd_GPR64
{
__amx_fma16(Rd_GPR64);
}
:__amx_fms16 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=16 & Rd_GPR64
{
__amx_fms16(Rd_GPR64);
}
:__amxdisable is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=17 & b_0004=1
{
__amx_disable();
}
:__amxenable is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=17 & b_0004=0
{
__amx_enable();
}
:__amx_vecint Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=18 & Rd_GPR64
{
__amx_vecint(Rd_GPR64);
}
:__amx_vecfp Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=19 & Rd_GPR64
{
__amx_vecfp(Rd_GPR64);
}
:__amx_matint Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=20 & Rd_GPR64
{
__amx_matint(Rd_GPR64);
}
:__amx_matfp Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=21 & Rd_GPR64
{
__amx_matfp(Rd_GPR64);
}
:__amx_genlut Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=22 & Rd_GPR64
{
__amx_genlut(Rd_GPR64);
}
}
python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_AppleSilicon.slaspec
+6 -6
View File
@@ -1,6 +1,6 @@
@define DATA_ENDIAN "little"
@include "AARCH64instructions.sinc"
@include "AARCH64_AMXext.sinc"
@define DATA_ENDIAN "little"
@include "AARCH64instructions.sinc"
@include "AARCH64_AMXext.sinc"
python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_base_PACoptions.sinc
+164 -164
View File
@@ -1,164 +1,164 @@
autda__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = AuthDA(Rd_GPR64, Rn_GPR64xsp); }
autda__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { AuthDA(Rd_GPR64, Rn_GPR64xsp); }
autda__PACpart: "hide" is ShowPAC=0 { }
autdza__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = AuthDA(Rd_GPR64, xzr); }
autdza__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { AuthDA(Rd_GPR64, xzr); }
autdza__PACpart: "hide" is ShowPAC=0 { }
autdb__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = AuthDB(Rd_GPR64, Rn_GPR64xsp); }
autdb__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { AuthDB(Rd_GPR64, Rn_GPR64xsp); }
autdb__PACpart: "hide" is ShowPAC=0 { }
autdzb__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = AuthDB(Rd_GPR64, xzr); }
autdzb__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { AuthDB(Rd_GPR64, xzr); }
autdzb__PACpart: "hide" is ShowPAC=0 { }
autia__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = AuthIA(Rd_GPR64, Rn_GPR64xsp); }
autia__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { AuthIA(Rd_GPR64, Rn_GPR64xsp); }
autia__PACpart: "hide" is ShowPAC=0 { }
autiza__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = AuthIA(Rd_GPR64, xzr); }
autiza__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { AuthIA(Rd_GPR64, xzr); }
autiza__PACpart: "hide" is ShowPAC=0 { }
autia1716__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x17 = AuthIA(x17, x16); }
autia1716__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIA(x17, x16); }
autia1716__PACpart: "hide" is ShowPAC=0 { }
autiasp__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = AuthIA(x30, sp); }
autiasp__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIA(x30, sp); }
autiasp__PACpart: "hide" is ShowPAC=0 { }
autiaz__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = AuthIA(x30, xzr); }
autiaz__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIA(x30, xzr); }
autiaz__PACpart: "hide" is ShowPAC=0 { }
autib__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = AuthIB(Rd_GPR64, Rn_GPR64xsp); }
autib__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { AuthIB(Rd_GPR64, Rn_GPR64xsp); }
autib__PACpart: "hide" is ShowPAC=0 { }
autizb__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = AuthIB(Rd_GPR64, xzr); }
autizb__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { AuthIB(Rd_GPR64, xzr); }
autizb__PACpart: "hide" is ShowPAC=0 { }
autib1716__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x17 = AuthIB(x17, x16); }
autib1716__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIB(x17, x16); }
autib1716__PACpart: "hide" is ShowPAC=0 { }
autibsp__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = AuthIB(x30, sp); }
autibsp__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIB(x30, sp); }
autibsp__PACpart: "hide" is ShowPAC=0 { }
autibz__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = AuthIB(x30, xzr); }
autibz__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIB(x30, xzr); }
autibz__PACpart: "hide" is ShowPAC=0 { }
b_blinkop__raaz___PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64 { AuthIA(Rn_GPR64, xzr); }
b_blinkop__raaz___PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64 { AuthIA(Rn_GPR64, xzr); }
b_blinkop__raaz___PACpart: "hide" is ShowPAC=0 { }
b_blinkop__raa___PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64xsp & Rn_GPR64 { AuthIA(Rn_GPR64, Rd_GPR64xsp); }
b_blinkop__raa___PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64xsp & Rn_GPR64 { AuthIA(Rn_GPR64, Rd_GPR64xsp); }
b_blinkop__raa___PACpart: "hide" is ShowPAC=0 { }
b_blinkop__rabz___PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64 { AuthIB(Rn_GPR64, xzr); }
b_blinkop__rabz___PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64 { AuthIB(Rn_GPR64, xzr); }
b_blinkop__rabz___PACpart: "hide" is ShowPAC=0 { }
b_blinkop__rab___PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64xsp & Rn_GPR64 { AuthIB(Rn_GPR64, Rd_GPR64xsp); }
b_blinkop__rab___PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64xsp & Rn_GPR64 { AuthIB(Rn_GPR64, Rd_GPR64xsp); }
b_blinkop__rab___PACpart: "hide" is ShowPAC=0 { }
eretaa__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { AuthIA(pc, sp); }
eretaa__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIA(pc, sp); }
eretaa__PACpart: "hide" is ShowPAC=0 { }
eretab__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { AuthIB(pc, sp); }
eretab__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIB(pc, sp); }
eretab__PACpart: "hide" is ShowPAC=0 { }
ldraa__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp { AuthDA(Rn_GPR64xsp, xzr); }
ldraa__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp { AuthDA(Rn_GPR64xsp, xzr); }
ldraa__PACpart: "hide" is ShowPAC=0 { }
ldrab__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp { AuthDB(Rn_GPR64xsp, xzr); }
ldrab__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp { AuthDB(Rn_GPR64xsp, xzr); }
ldrab__PACpart: "hide" is ShowPAC=0 { }
pacda__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = pacda(Rd_GPR64, Rn_GPR64xsp); }
pacda__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { pacda(Rd_GPR64, Rn_GPR64xsp); }
pacda__PACpart: "hide" is ShowPAC=0 { }
pacdza__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = pacdza(Rd_GPR64); }
pacdza__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { pacdza(Rd_GPR64); }
pacdza__PACpart: "hide" is ShowPAC=0 { }
pacdb__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = pacdb(Rd_GPR64, Rn_GPR64xsp); }
pacdb__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { pacdb(Rd_GPR64, Rn_GPR64xsp); }
pacdb__PACpart: "hide" is ShowPAC=0 { }
pacdzb__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = pacdzb(Rd_GPR64); }
pacdzb__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { pacdzb(Rd_GPR64); }
pacdzb__PACpart: "hide" is ShowPAC=0 { }
pacia__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = pacia(Rd_GPR64, Rn_GPR64xsp); }
pacia__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { pacia(Rd_GPR64, Rn_GPR64xsp); }
pacia__PACpart: "hide" is ShowPAC=0 { }
paciza__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = paciza(Rd_GPR64); }
paciza__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { paciza(Rd_GPR64); }
paciza__PACpart: "hide" is ShowPAC=0 { }
pacia1716__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x17 = pacia(x17, x16); }
pacia1716__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { pacia(x17, x16); }
pacia1716__PACpart: "hide" is ShowPAC=0 { }
paciasp__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = pacia(x30, sp); }
paciasp__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { pacia(x30, sp); }
paciasp__PACpart: "hide" is ShowPAC=0 { }
paciaz__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = paciza(x30); }
paciaz__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { paciza(x30); }
paciaz__PACpart: "hide" is ShowPAC=0 { }
pacib__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = pacib(Rd_GPR64, Rn_GPR64xsp); }
pacib__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { pacib(Rd_GPR64, Rn_GPR64xsp); }
pacib__PACpart: "hide" is ShowPAC=0 { }
pacizb__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = pacizb(Rd_GPR64); }
pacizb__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { pacizb(Rd_GPR64); }
pacizb__PACpart: "hide" is ShowPAC=0 { }
pacib1716__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x17 = pacib(x17, x16); }
pacib1716__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { pacib(x17, x16); }
pacib1716__PACpart: "hide" is ShowPAC=0 { }
pacibsp__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = pacib(x30, sp); }
pacibsp__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { pacib(x30, sp); }
pacibsp__PACpart: "hide" is ShowPAC=0 { }
pacibz__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = pacizb(x30); }
pacibz__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { pacizb(x30); }
pacibz__PACpart: "hide" is ShowPAC=0 { }
retaa__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { AuthIA(x30, sp); }
retaa__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIA(x30, sp); }
retaa__PACpart: "hide" is ShowPAC=0 { }
retab__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { AuthIB(x30, sp); }
retab__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIB(x30, sp); }
retab__PACpart: "hide" is ShowPAC=0 { }
xpacd__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = xpac(Rd_GPR64, 1:1); }
xpacd__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { xpac(Rd_GPR64, 1:1); }
xpacd__PACpart: "hide" is ShowPAC=0 { }
xpaci__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = xpac(Rd_GPR64, 0:1); }
xpaci__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { xpac(Rd_GPR64, 0:1); }
xpaci__PACpart: "hide" is ShowPAC=0 { }
xpaclri__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = xpac(x30, 0:1); }
xpaclri__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { xpac(x30, 0:1); }
xpaclri__PACpart: "hide" is ShowPAC=0 { }
autda__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = AuthDA(Rd_GPR64, Rn_GPR64xsp); }
autda__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { AuthDA(Rd_GPR64, Rn_GPR64xsp); }
autda__PACpart: "hide" is ShowPAC=0 { }
autdza__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = AuthDA(Rd_GPR64, xzr); }
autdza__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { AuthDA(Rd_GPR64, xzr); }
autdza__PACpart: "hide" is ShowPAC=0 { }
autdb__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = AuthDB(Rd_GPR64, Rn_GPR64xsp); }
autdb__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { AuthDB(Rd_GPR64, Rn_GPR64xsp); }
autdb__PACpart: "hide" is ShowPAC=0 { }
autdzb__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = AuthDB(Rd_GPR64, xzr); }
autdzb__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { AuthDB(Rd_GPR64, xzr); }
autdzb__PACpart: "hide" is ShowPAC=0 { }
autia__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = AuthIA(Rd_GPR64, Rn_GPR64xsp); }
autia__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { AuthIA(Rd_GPR64, Rn_GPR64xsp); }
autia__PACpart: "hide" is ShowPAC=0 { }
autiza__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = AuthIA(Rd_GPR64, xzr); }
autiza__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { AuthIA(Rd_GPR64, xzr); }
autiza__PACpart: "hide" is ShowPAC=0 { }
autia1716__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x17 = AuthIA(x17, x16); }
autia1716__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIA(x17, x16); }
autia1716__PACpart: "hide" is ShowPAC=0 { }
autiasp__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = AuthIA(x30, sp); }
autiasp__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIA(x30, sp); }
autiasp__PACpart: "hide" is ShowPAC=0 { }
autiaz__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = AuthIA(x30, xzr); }
autiaz__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIA(x30, xzr); }
autiaz__PACpart: "hide" is ShowPAC=0 { }
autib__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = AuthIB(Rd_GPR64, Rn_GPR64xsp); }
autib__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { AuthIB(Rd_GPR64, Rn_GPR64xsp); }
autib__PACpart: "hide" is ShowPAC=0 { }
autizb__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = AuthIB(Rd_GPR64, xzr); }
autizb__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { AuthIB(Rd_GPR64, xzr); }
autizb__PACpart: "hide" is ShowPAC=0 { }
autib1716__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x17 = AuthIB(x17, x16); }
autib1716__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIB(x17, x16); }
autib1716__PACpart: "hide" is ShowPAC=0 { }
autibsp__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = AuthIB(x30, sp); }
autibsp__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIB(x30, sp); }
autibsp__PACpart: "hide" is ShowPAC=0 { }
autibz__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = AuthIB(x30, xzr); }
autibz__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIB(x30, xzr); }
autibz__PACpart: "hide" is ShowPAC=0 { }
b_blinkop__raaz___PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64 { AuthIA(Rn_GPR64, xzr); }
b_blinkop__raaz___PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64 { AuthIA(Rn_GPR64, xzr); }
b_blinkop__raaz___PACpart: "hide" is ShowPAC=0 { }
b_blinkop__raa___PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64xsp & Rn_GPR64 { AuthIA(Rn_GPR64, Rd_GPR64xsp); }
b_blinkop__raa___PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64xsp & Rn_GPR64 { AuthIA(Rn_GPR64, Rd_GPR64xsp); }
b_blinkop__raa___PACpart: "hide" is ShowPAC=0 { }
b_blinkop__rabz___PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64 { AuthIB(Rn_GPR64, xzr); }
b_blinkop__rabz___PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64 { AuthIB(Rn_GPR64, xzr); }
b_blinkop__rabz___PACpart: "hide" is ShowPAC=0 { }
b_blinkop__rab___PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64xsp & Rn_GPR64 { AuthIB(Rn_GPR64, Rd_GPR64xsp); }
b_blinkop__rab___PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64xsp & Rn_GPR64 { AuthIB(Rn_GPR64, Rd_GPR64xsp); }
b_blinkop__rab___PACpart: "hide" is ShowPAC=0 { }
eretaa__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { AuthIA(pc, sp); }
eretaa__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIA(pc, sp); }
eretaa__PACpart: "hide" is ShowPAC=0 { }
eretab__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { AuthIB(pc, sp); }
eretab__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIB(pc, sp); }
eretab__PACpart: "hide" is ShowPAC=0 { }
ldraa__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp { AuthDA(Rn_GPR64xsp, xzr); }
ldraa__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp { AuthDA(Rn_GPR64xsp, xzr); }
ldraa__PACpart: "hide" is ShowPAC=0 { }
ldrab__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp { AuthDB(Rn_GPR64xsp, xzr); }
ldrab__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp { AuthDB(Rn_GPR64xsp, xzr); }
ldrab__PACpart: "hide" is ShowPAC=0 { }
pacda__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = pacda(Rd_GPR64, Rn_GPR64xsp); }
pacda__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { pacda(Rd_GPR64, Rn_GPR64xsp); }
pacda__PACpart: "hide" is ShowPAC=0 { }
pacdza__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = pacdza(Rd_GPR64); }
pacdza__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { pacdza(Rd_GPR64); }
pacdza__PACpart: "hide" is ShowPAC=0 { }
pacdb__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = pacdb(Rd_GPR64, Rn_GPR64xsp); }
pacdb__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { pacdb(Rd_GPR64, Rn_GPR64xsp); }
pacdb__PACpart: "hide" is ShowPAC=0 { }
pacdzb__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = pacdzb(Rd_GPR64); }
pacdzb__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { pacdzb(Rd_GPR64); }
pacdzb__PACpart: "hide" is ShowPAC=0 { }
pacia__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = pacia(Rd_GPR64, Rn_GPR64xsp); }
pacia__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { pacia(Rd_GPR64, Rn_GPR64xsp); }
pacia__PACpart: "hide" is ShowPAC=0 { }
paciza__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = paciza(Rd_GPR64); }
paciza__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { paciza(Rd_GPR64); }
paciza__PACpart: "hide" is ShowPAC=0 { }
pacia1716__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x17 = pacia(x17, x16); }
pacia1716__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { pacia(x17, x16); }
pacia1716__PACpart: "hide" is ShowPAC=0 { }
paciasp__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = pacia(x30, sp); }
paciasp__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { pacia(x30, sp); }
paciasp__PACpart: "hide" is ShowPAC=0 { }
paciaz__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = paciza(x30); }
paciaz__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { paciza(x30); }
paciaz__PACpart: "hide" is ShowPAC=0 { }
pacib__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = pacib(Rd_GPR64, Rn_GPR64xsp); }
pacib__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { pacib(Rd_GPR64, Rn_GPR64xsp); }
pacib__PACpart: "hide" is ShowPAC=0 { }
pacizb__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = pacizb(Rd_GPR64); }
pacizb__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { pacizb(Rd_GPR64); }
pacizb__PACpart: "hide" is ShowPAC=0 { }
pacib1716__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x17 = pacib(x17, x16); }
pacib1716__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { pacib(x17, x16); }
pacib1716__PACpart: "hide" is ShowPAC=0 { }
pacibsp__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = pacib(x30, sp); }
pacibsp__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { pacib(x30, sp); }
pacibsp__PACpart: "hide" is ShowPAC=0 { }
pacibz__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = pacizb(x30); }
pacibz__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { pacizb(x30); }
pacibz__PACpart: "hide" is ShowPAC=0 { }
retaa__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { AuthIA(x30, sp); }
retaa__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIA(x30, sp); }
retaa__PACpart: "hide" is ShowPAC=0 { }
retab__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { AuthIB(x30, sp); }
retab__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIB(x30, sp); }
retab__PACpart: "hide" is ShowPAC=0 { }
xpacd__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = xpac(Rd_GPR64, 1:1); }
xpacd__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { xpac(Rd_GPR64, 1:1); }
xpacd__PACpart: "hide" is ShowPAC=0 { }
xpaci__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = xpac(Rd_GPR64, 0:1); }
xpaci__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { xpac(Rd_GPR64, 0:1); }
xpaci__PACpart: "hide" is ShowPAC=0 { }
xpaclri__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = xpac(x30, 0:1); }
xpaclri__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { xpac(x30, 0:1); }
xpaclri__PACpart: "hide" is ShowPAC=0 { }
python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_ilp32.cspec
+204 -207
View File
@@ -1,207 +1,204 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<data_organization>
<absolute_max_alignment value="0" />
<machine_alignment value="4" />
<default_alignment value="1" />
<default_pointer_alignment value="8" />
<pointer_size value="4" />
<wchar_size value="4" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="8" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="8" />
</size_alignment_map>
</data_organization>
<global>
<range space="ram"/>
<!-- The decompiler will treat registers in this range as global variables.
ie: tmp_ldWn, tmp_ldXn, tmp_stWn, tmp_stXn -->
<range space="register" first="0x3000" last="0x3fff"/>
</global>
<aggressivetrim signext="true"/> <!-- Aggressively try to eliminate sign extensions -->
<stackpointer register="sp" space="ram"/>
<funcptr align="4"/> <!-- Function pointers are word aligned and leastsig bit may encode otherstuff -->
<prefersplit style="inhalf">
<register name="q0"/>
<register name="q1"/>
<register name="q2"/>
<register name="q3"/>
<register name="q4"/>
<register name="q5"/>
<register name="q6"/>
<register name="q7"/>
<register name="q8"/>
<register name="q9"/>
<register name="q10"/>
<register name="q11"/>
<register name="q12"/>
<register name="q13"/>
<register name="q14"/>
<register name="q15"/>
<register name="q16"/>
<register name="q17"/>
<register name="q18"/>
<register name="q19"/>
<register name="q20"/>
<register name="q21"/>
<register name="q22"/>
<register name="q23"/>
<register name="q24"/>
<register name="q25"/>
<register name="q26"/>
<register name="q27"/>
<register name="q28"/>
<register name="q29"/>
<register name="q30"/>
</prefersplit>
<default_proto>
<prototype name="__cdecl" extrapop="0" stackshift="0">
<input>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d0"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d1"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d2"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d3"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d4"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d5"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d6"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d7"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x0"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x1"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x2"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x3"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x4"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x5"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x6"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x7"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="0" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d0"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x0"/>
</pentry>
<pentry minsize="9" maxsize="16" extension="zero">
<addr space="join" piece1="x1" piece2="x0"/>
</pentry>
</output>
<unaffected>
<register name="x19"/>
<register name="x20"/>
<register name="x21"/>
<register name="x22"/>
<register name="x23"/>
<register name="x24"/>
<register name="x25"/>
<register name="x26"/>
<register name="x27"/>
<register name="x28"/>
<register name="x29"/>
<register name="x30"/>
<register name="sp"/>
<!-- vectors -->
<register name="d8"/>
<register name="d9"/>
<register name="d10"/>
<register name="d11"/>
<register name="d12"/>
<register name="d13"/>
<register name="d14"/>
<register name="d15"/>
</unaffected>
<killedbycall>
<!-- x8: indirect result location register, which is not
reflected in the pentry list -->
<register name="x8"/>
<register name="x9"/>
<register name="x10"/>
<register name="x11"/>
<register name="x12"/>
<register name="x13"/>
<register name="x14"/>
<register name="x15"/>
<register name="x16"/>
<register name="x17"/>
<register name="x18"/>
<!-- vectors -->
<register name="d16"/>
<register name="d17"/>
<register name="d18"/>
<register name="d19"/>
<register name="d20"/>
<register name="d21"/>
<register name="d22"/>
<register name="d23"/>
<register name="d24"/>
<register name="d25"/>
<register name="d26"/>
<register name="d27"/>
<register name="d28"/>
<register name="d29"/>
<register name="d30"/>
<register name="d31"/>
</killedbycall>
</prototype>
</default_proto>
<callfixup name="PlaceHolderCallFixup"> <!-- This is here just to force call fixup and NoReturn fixup. Will be fixed in Ghidra V6.0 -->
<target name="___NotARealFunctionName___"/>
<pcode>
<body><![CDATA[
tmpptr:4 = 0;
]]></body>
</pcode>
</callfixup>
</compiler_spec>
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<data_organization>
<absolute_max_alignment value="0" />
<machine_alignment value="4" />
<default_alignment value="1" />
<default_pointer_alignment value="8" />
<pointer_size value="4" />
<wchar_size value="4" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="8" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="8" />
</size_alignment_map>
</data_organization>
<global>
<range space="ram"/>
</global>
<aggressivetrim signext="true"/> <!-- Aggressively try to eliminate sign extensions -->
<stackpointer register="sp" space="ram"/>
<funcptr align="4"/> <!-- Function pointers are word aligned and leastsig bit may encode otherstuff -->
<prefersplit style="inhalf">
<register name="q0"/>
<register name="q1"/>
<register name="q2"/>
<register name="q3"/>
<register name="q4"/>
<register name="q5"/>
<register name="q6"/>
<register name="q7"/>
<register name="q8"/>
<register name="q9"/>
<register name="q10"/>
<register name="q11"/>
<register name="q12"/>
<register name="q13"/>
<register name="q14"/>
<register name="q15"/>
<register name="q16"/>
<register name="q17"/>
<register name="q18"/>
<register name="q19"/>
<register name="q20"/>
<register name="q21"/>
<register name="q22"/>
<register name="q23"/>
<register name="q24"/>
<register name="q25"/>
<register name="q26"/>
<register name="q27"/>
<register name="q28"/>
<register name="q29"/>
<register name="q30"/>
</prefersplit>
<default_proto>
<prototype name="__cdecl" extrapop="0" stackshift="0">
<input>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d0"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d1"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d2"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d3"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d4"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d5"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d6"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d7"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x0"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x1"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x2"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x3"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x4"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x5"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x6"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x7"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="0" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d0"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x0"/>
</pentry>
<pentry minsize="9" maxsize="16" extension="zero">
<addr space="join" piece1="x1" piece2="x0"/>
</pentry>
</output>
<unaffected>
<register name="x19"/>
<register name="x20"/>
<register name="x21"/>
<register name="x22"/>
<register name="x23"/>
<register name="x24"/>
<register name="x25"/>
<register name="x26"/>
<register name="x27"/>
<register name="x28"/>
<register name="x29"/>
<register name="x30"/>
<register name="sp"/>
<!-- vectors -->
<register name="d8"/>
<register name="d9"/>
<register name="d10"/>
<register name="d11"/>
<register name="d12"/>
<register name="d13"/>
<register name="d14"/>
<register name="d15"/>
</unaffected>
<killedbycall>
<!-- x8: indirect result location register, which is not
reflected in the pentry list -->
<register name="x8"/>
<register name="x9"/>
<register name="x10"/>
<register name="x11"/>
<register name="x12"/>
<register name="x13"/>
<register name="x14"/>
<register name="x15"/>
<register name="x16"/>
<register name="x17"/>
<register name="x18"/>
<!-- vectors -->
<register name="d16"/>
<register name="d17"/>
<register name="d18"/>
<register name="d19"/>
<register name="d20"/>
<register name="d21"/>
<register name="d22"/>
<register name="d23"/>
<register name="d24"/>
<register name="d25"/>
<register name="d26"/>
<register name="d27"/>
<register name="d28"/>
<register name="d29"/>
<register name="d30"/>
<register name="d31"/>
</killedbycall>
</prototype>
</default_proto>
<callfixup name="PlaceHolderCallFixup"> <!-- This is here just to force call fixup and NoReturn fixup. Will be fixed in Ghidra V6.0 -->
<target name="___NotARealFunctionName___"/>
<pcode>
<body><![CDATA[
tmpptr:4 = 0;
]]></body>
</pcode>
</callfixup>
</compiler_spec>
python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_win.cspec
+215 -214
View File
@@ -1,214 +1,215 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<!-- Copied from AARCH.cspec and modified...
See: https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions?view=vs-2019
The AARCH64 ABI refers to Windows ABI as LLP64 data model -->
<data_organization>
<absolute_max_alignment value="0" />
<machine_alignment value="4" />
<default_alignment value="1" />
<default_pointer_alignment value="8" />
<pointer_size value="8" />
<wchar_size value="2" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="16" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="8" />
<entry size="16" alignment="16" />
</size_alignment_map>
<bitfield_packing>
<use_MS_convention value="true"/>
</bitfield_packing>
</data_organization>
<global>
<range space="ram"/>
</global>
<stackpointer register="sp" space="ram"/>
<funcptr align="4"/> <!-- Function pointers are word aligned and leastsig bit may encode otherstuff -->
<prefersplit style="inhalf">
<register name="q0"/>
<register name="q1"/>
<register name="q2"/>
<register name="q3"/>
<register name="q4"/>
<register name="q5"/>
<register name="q6"/>
<register name="q7"/>
<register name="q8"/>
<register name="q9"/>
<register name="q10"/>
<register name="q11"/>
<register name="q12"/>
<register name="q13"/>
<register name="q14"/>
<register name="q15"/>
<register name="q16"/>
<register name="q17"/>
<register name="q18"/>
<register name="q19"/>
<register name="q20"/>
<register name="q21"/>
<register name="q22"/>
<register name="q23"/>
<register name="q24"/>
<register name="q25"/>
<register name="q26"/>
<register name="q27"/>
<register name="q28"/>
<register name="q29"/>
<register name="q30"/>
</prefersplit>
<default_proto>
<prototype name="__cdecl" extrapop="0" stackshift="0">
<input>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d0"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d1"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d2"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d3"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d4"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d5"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d6"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d7"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x0"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x1"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x2"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x3"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x4"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x5"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x6"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x7"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="0" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d0"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x0"/>
</pentry>
</output>
<unaffected>
<register name="x19"/>
<register name="x20"/>
<register name="x21"/>
<register name="x22"/>
<register name="x23"/>
<register name="x24"/>
<register name="x25"/>
<register name="x26"/>
<register name="x27"/>
<register name="x28"/>
<register name="x29"/>
<register name="x30"/>
<register name="sp"/>
<!-- vectors -->
<register name="d8"/>
<register name="d9"/>
<register name="d10"/>
<register name="d11"/>
<register name="d12"/>
<register name="d13"/>
<register name="d14"/>
<register name="d15"/>
</unaffected>
<killedbycall>
<!-- x8: indirect result location register, which is not
reflected in the pentry list -->
<register name="x8"/>
<register name="x9"/>
<register name="x10"/>
<register name="x11"/>
<register name="x12"/>
<register name="x13"/>
<register name="x14"/>
<register name="x15"/>
<register name="x16"/>
<register name="x17"/>
<register name="x18"/>
<!-- vectors -->
<register name="d16"/>
<register name="d17"/>
<register name="d18"/>
<register name="d19"/>
<register name="d20"/>
<register name="d21"/>
<register name="d22"/>
<register name="d23"/>
<register name="d24"/>
<register name="d25"/>
<register name="d26"/>
<register name="d27"/>
<register name="d28"/>
<register name="d29"/>
<register name="d30"/>
<register name="d31"/>
</killedbycall>
</prototype>
</default_proto>
<callfixup name="security_push_cookie">
<target name="__security_push_cookie"/>
<pcode>
<body><![CDATA[
sp = sp - 16;
]]></body>
</pcode>
</callfixup>
<callfixup name="security_pop_cookie">
<target name="__security_pop_cookie"/>
<pcode>
<body><![CDATA[
sp = sp + 16;
]]></body>
</pcode>
</callfixup>
</compiler_spec>
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<!-- Copied from AARCH.cspec and modified...
See: https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions?view=vs-2019
The AARCH64 ABI refers to Windows ABI as LLP64 data model -->
<data_organization>
<absolute_max_alignment value="0" />
<machine_alignment value="4" />
<default_alignment value="1" />
<default_pointer_alignment value="8" />
<pointer_size value="8" />
<wchar_size value="2" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="16" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="8" />
<entry size="16" alignment="16" />
</size_alignment_map>
<bitfield_packing>
<use_MS_convention value="true"/>
</bitfield_packing>
</data_organization>
<global>
<range space="ram"/>
</global>
<stackpointer register="sp" space="ram"/>
<funcptr align="4"/> <!-- Function pointers are word aligned and leastsig bit may encode otherstuff -->
<prefersplit style="inhalf">
<register name="q0"/>
<register name="q1"/>
<register name="q2"/>
<register name="q3"/>
<register name="q4"/>
<register name="q5"/>
<register name="q6"/>
<register name="q7"/>
<register name="q8"/>
<register name="q9"/>
<register name="q10"/>
<register name="q11"/>
<register name="q12"/>
<register name="q13"/>
<register name="q14"/>
<register name="q15"/>
<register name="q16"/>
<register name="q17"/>
<register name="q18"/>
<register name="q19"/>
<register name="q20"/>
<register name="q21"/>
<register name="q22"/>
<register name="q23"/>
<register name="q24"/>
<register name="q25"/>
<register name="q26"/>
<register name="q27"/>
<register name="q28"/>
<register name="q29"/>
<register name="q30"/>
</prefersplit>
<default_proto>
<prototype name="__cdecl" extrapop="0" stackshift="0">
<input>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d0"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d1"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d2"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d3"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d4"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d5"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d6"/>
</pentry>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d7"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x0"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x1"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x2"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x3"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x4"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x5"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x6"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x7"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="0" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d0"/>
</pentry>
<pentry minsize="1" maxsize="8" extension="zero">
<register name="x0"/>
</pentry>
</output>
<unaffected>
<register name="x19"/>
<register name="x20"/>
<register name="x21"/>
<register name="x22"/>
<register name="x23"/>
<register name="x24"/>
<register name="x25"/>
<register name="x26"/>
<register name="x27"/>
<register name="x28"/>
<register name="x29"/>
<register name="x30"/>
<register name="sp"/>
<!-- vectors -->
<register name="d8"/>
<register name="d9"/>
<register name="d10"/>
<register name="d11"/>
<register name="d12"/>
<register name="d13"/>
<register name="d14"/>
<register name="d15"/>
</unaffected>
<killedbycall>
<!-- x8: indirect result location register, which is not
reflected in the pentry list -->
<register name="x8"/>
<register name="x9"/>
<register name="x10"/>
<register name="x11"/>
<register name="x12"/>
<register name="x13"/>
<register name="x14"/>
<register name="x15"/>
<register name="x16"/>
<register name="x17"/>
<register name="x18"/>
<!-- vectors -->
<register name="d16"/>
<register name="d17"/>
<register name="d18"/>
<register name="d19"/>
<register name="d20"/>
<register name="d21"/>
<register name="d22"/>
<register name="d23"/>
<register name="d24"/>
<register name="d25"/>
<register name="d26"/>
<register name="d27"/>
<register name="d28"/>
<register name="d29"/>
<register name="d30"/>
<register name="d31"/>
</killedbycall>
</prototype>
</default_proto>
<modelalias name="__stdcall" parent="__cdecl"/>
<callfixup name="security_push_cookie">
<target name="__security_push_cookie"/>
<pcode>
<body><![CDATA[
sp = sp - 16;
]]></body>
</pcode>
</callfixup>
<callfixup name="security_pop_cookie">
<target name="__security_pop_cookie"/>
<pcode>
<body><![CDATA[
sp = sp + 16;
]]></body>
</pcode>
</callfixup>
</compiler_spec>
python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc
+8392 -8392
View File
File diff suppressed because it is too large Load Diff
python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64instructions.sinc
+4006 -4006
View File
File diff suppressed because it is too large Load Diff
python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64ldst.sinc
+10258 -10258
View File
File diff suppressed because it is too large Load Diff
python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64neon.sinc
+29904 -29911
View File
File diff suppressed because it is too large Load Diff
python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64sve.sinc
+7405 -7405
View File
File diff suppressed because it is too large Load Diff
python/icicle/Ghidra/Processors/AARCH64/data/languages/AppleSilicon.ldefs
+18 -18
View File
@@ -1,18 +1,18 @@
<?xml version="1.1" encoding="UTF-8"?>
<language_definitions>
<language processor="AARCH64"
endian="little"
size="64"
variant="AppleSilicon"
version="1.5"
slafile="AARCH64_AppleSilicon.sla"
processorspec="AARCH64.pspec"
manualindexfile="../manuals/AARCH64.idx"
id="AARCH64:LE:64:AppleSilicon">
<description>AppleSilicon ARM v8.5-A LE instructions, LE data, AMX extensions</description>
<compiler name="default" spec="AARCH64.cspec" id="default"/>
<external_name tool="gnu" name="aarch64"/>
<external_name tool="gnu" name="aarch64:ilp32"/>
<external_name tool="DWARF.register.mapping.file" name="AARCH64.dwarf"/>
</language>
</language_definitions>
<?xml version="1.1" encoding="UTF-8"?>
<language_definitions>
<language processor="AARCH64"
endian="little"
size="64"
variant="AppleSilicon"
version="1.5"
slafile="AARCH64_AppleSilicon.sla"
processorspec="AARCH64.pspec"
manualindexfile="../manuals/AARCH64.idx"
id="AARCH64:LE:64:AppleSilicon">
<description>AppleSilicon ARM v8.5-A LE instructions, LE data, AMX extensions</description>
<compiler name="default" spec="AARCH64.cspec" id="default"/>
<external_name tool="gnu" name="aarch64"/>
<external_name tool="gnu" name="aarch64:ilp32"/>
<external_name tool="DWARF.register.mapping.file" name="AARCH64.dwarf"/>
</language>
</language_definitions>
python/icicle/Ghidra/Processors/ARM/data/languages/ARM.cspec
+266 -266
View File
@@ -1,266 +1,266 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<!--
Assumes Procedure Call Standard for the ARM Architecture (AAPCS) Applies.
-->
<data_organization> <!-- These tags were generated with gcc 4.2.4 -->
<absolute_max_alignment value="0" />
<machine_alignment value="2" />
<default_alignment value="1" />
<default_pointer_alignment value="4" />
<pointer_size value="4" />
<wchar_size value="4" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="8" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="8" />
</size_alignment_map>
</data_organization>
<global>
<range space="ram"/>
</global>
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/> <!-- Function pointers are word aligned and leastsig bit may encode otherstuff -->
<default_proto>
<prototype name="__stdcall" extrapop="0" stackshift="0">
<input>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s0"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s1"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s2"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s3"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s4"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s5"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s6"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s7"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r0"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r1"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r2"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r3"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="0" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d0"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r0"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="r1" piece2="r0"/>
</pentry>
</output>
<unaffected>
<register name="r4"/>
<register name="r5"/>
<register name="r6"/>
<register name="r7"/>
<register name="r8"/>
<register name="r9"/>
<register name="r10"/>
<register name="r11"/>
<register name="d8"/>
<register name="d9"/>
<register name="d10"/>
<register name="d11"/>
<register name="d12"/>
<register name="d13"/>
<register name="d14"/>
<register name="d15"/>
<register name="sp"/>
</unaffected>
<killedbycall>
<register name="r1"/>
<register name="d0"/>
<register name="d1"/>
<register name="d2"/>
<register name="d3"/>
<register name="d4"/>
<register name="d5"/>
<register name="d6"/>
<register name="d7"/>
</killedbycall>
</prototype>
</default_proto>
<prototype name="processEntry" extrapop="0" stackshift="0">
<input pointermax="4">
<pentry minsize="1" maxsize="4">
<register name="r0"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="0" space="stack"/>
</pentry>
</input>
<output killedbycall="true">
<pentry minsize="1" maxsize="4">
<register name="r0"/>
</pentry>
</output>
<unaffected>
<register name="sp"/>
</unaffected>
</prototype>
<callfixup name="switch8_r3">
<target name="switch8_r3"/>
<target name="__ARM_common_switch8"/>
<pcode>
<body><![CDATA[
tmpptr = lr - 1;
tblsize = *:1 tmpptr;
r12 = zext(tblsize);
inbounds = r3 < r12;
if (!inbounds) goto <next1>;
offset = *:1 (lr + r3);
r3 = zext(offset);
<next1>
if (inbounds) goto <next2>;
offset = *:1 (lr + r12);
r3 = zext(offset);
<next2>
r3 = r3 * 2;
r12 = lr + r3;
ISAModeSwitch = (r12 & 1) != 1;
TB = ISAModeSwitch;
pc = r12 & 0xfffffffe;
goto [pc];
]]></body>
</pcode>
</callfixup>
<callfixup name="switch8_r0">
<target name="__gnu_thumb1_case_uqi"/>
<target name="switch8_r0"/>
<pcode>
<body><![CDATA[
tmpptr = lr & 0xfffffffe;
offset = *:1 (tmpptr + r0);
lr = lr + 2 * zext(offset);
ISAModeSwitch = (lr & 1) != 0;
TB = ISAModeSwitch;
pc = lr & 0xfffffffe;
goto [pc];
]]></body>
</pcode>
</callfixup>
<callfixup name="switchS8_r0">
<target name="__gnu_thumb1_case_sqi"/>
<target name="switchS8_r0"/>
<pcode>
<body><![CDATA[
tmpptr = lr & 0xfffffffe;
offset = *:1 (tmpptr + r0);
lr = lr + 2 * sext(offset);
ISAModeSwitch = (lr & 1) != 0;
TB = ISAModeSwitch;
pc = lr & 0xfffffffe;
goto [pc];
]]></body>
</pcode>
</callfixup>
<callfixup name="switch16_shi_r0">
<target name="__gnu_thumb1_case_shi"/>
<target name="switch16_shi_r0"/>
<pcode>
<body><![CDATA[
tmpptr = lr & 0xfffffffe;
index = r0 * 2;
offset = *:2 (tmpptr + index);
lr = lr + 2 * sext(offset);
ISAModeSwitch = (lr & 1) != 0;
TB = ISAModeSwitch;
pc = lr & 0xfffffffe;
goto [pc];
]]></body>
</pcode>
</callfixup>
<callfixup name="switch16_uhi_r0">
<target name="__gnu_thumb1_case_uhi"/>
<target name="switch16_shi_r0"/>
<pcode>
<body><![CDATA[
tmpptr = lr & 0xfffffffe;
index = r0 * 2;
offset = *:2 (tmpptr + index);
lr = lr + 2 * zext(offset);
ISAModeSwitch = (lr & 1) != 0;
TB = ISAModeSwitch;
pc = lr & 0xfffffffe;
goto [pc];
]]></body>
</pcode>
</callfixup>
<callfixup name="switch32_si_r0">
<target name="__gnu_thumb1_case_si"/>
<target name="switch32_si_r0"/>
<pcode>
<body><![CDATA[
tmpptr = (lr + 2) & 0xfffffffc;
index = r0 * 4;
offset = *:4 (tmpptr + index);
offset = offset * 4;
lr = lr + offset;
ISAModeSwitch = (lr & 1) != 0;
TB = ISAModeSwitch;
pc = lr & 0xfffffffe;
goto [pc];
]]></body>
</pcode>
</callfixup>
</compiler_spec>
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<!--
Assumes Procedure Call Standard for the ARM Architecture (AAPCS) Applies.
-->
<data_organization> <!-- These tags were generated with gcc 4.2.4 -->
<absolute_max_alignment value="0" />
<machine_alignment value="2" />
<default_alignment value="1" />
<default_pointer_alignment value="4" />
<pointer_size value="4" />
<wchar_size value="4" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="8" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="8" />
</size_alignment_map>
</data_organization>
<global>
<range space="ram"/>
</global>
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/> <!-- Function pointers are word aligned and leastsig bit may encode otherstuff -->
<default_proto>
<prototype name="__stdcall" extrapop="0" stackshift="0">
<input>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s0"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s1"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s2"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s3"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s4"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s5"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s6"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s7"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r0"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r1"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r2"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r3"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="0" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="8" metatype="float">
<register name="d0"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r0"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="r1" piece2="r0"/>
</pentry>
</output>
<unaffected>
<register name="r4"/>
<register name="r5"/>
<register name="r6"/>
<register name="r7"/>
<register name="r8"/>
<register name="r9"/>
<register name="r10"/>
<register name="r11"/>
<register name="d8"/>
<register name="d9"/>
<register name="d10"/>
<register name="d11"/>
<register name="d12"/>
<register name="d13"/>
<register name="d14"/>
<register name="d15"/>
<register name="sp"/>
</unaffected>
<killedbycall>
<register name="r1"/>
<register name="d0"/>
<register name="d1"/>
<register name="d2"/>
<register name="d3"/>
<register name="d4"/>
<register name="d5"/>
<register name="d6"/>
<register name="d7"/>
</killedbycall>
</prototype>
</default_proto>
<prototype name="processEntry" extrapop="0" stackshift="0">
<input pointermax="4">
<pentry minsize="1" maxsize="4">
<register name="r0"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="0" space="stack"/>
</pentry>
</input>
<output killedbycall="true">
<pentry minsize="1" maxsize="4">
<register name="r0"/>
</pentry>
</output>
<unaffected>
<register name="sp"/>
</unaffected>
</prototype>
<callfixup name="switch8_r3">
<target name="switch8_r3"/>
<target name="__ARM_common_switch8"/>
<pcode>
<body><![CDATA[
tmpptr = lr - 1;
tblsize = *:1 tmpptr;
r12 = zext(tblsize);
inbounds = r3 < r12;
if (!inbounds) goto <next1>;
offset = *:1 (lr + r3);
r3 = zext(offset);
<next1>
if (inbounds) goto <next2>;
offset = *:1 (lr + r12);
r3 = zext(offset);
<next2>
r3 = r3 * 2;
r12 = lr + r3;
ISAModeSwitch = (r12 & 1) != 1;
TB = ISAModeSwitch;
pc = r12 & 0xfffffffe;
goto [pc];
]]></body>
</pcode>
</callfixup>
<callfixup name="switch8_r0">
<target name="__gnu_thumb1_case_uqi"/>
<target name="switch8_r0"/>
<pcode>
<body><![CDATA[
tmpptr = lr & 0xfffffffe;
offset = *:1 (tmpptr + r0);
lr = lr + 2 * zext(offset);
ISAModeSwitch = (lr & 1) != 0;
TB = ISAModeSwitch;
pc = lr & 0xfffffffe;
goto [pc];
]]></body>
</pcode>
</callfixup>
<callfixup name="switchS8_r0">
<target name="__gnu_thumb1_case_sqi"/>
<target name="switchS8_r0"/>
<pcode>
<body><![CDATA[
tmpptr = lr & 0xfffffffe;
offset = *:1 (tmpptr + r0);
lr = lr + 2 * sext(offset);
ISAModeSwitch = (lr & 1) != 0;
TB = ISAModeSwitch;
pc = lr & 0xfffffffe;
goto [pc];
]]></body>
</pcode>
</callfixup>
<callfixup name="switch16_shi_r0">
<target name="__gnu_thumb1_case_shi"/>
<target name="switch16_shi_r0"/>
<pcode>
<body><![CDATA[
tmpptr = lr & 0xfffffffe;
index = r0 * 2;
offset = *:2 (tmpptr + index);
lr = lr + 2 * sext(offset);
ISAModeSwitch = (lr & 1) != 0;
TB = ISAModeSwitch;
pc = lr & 0xfffffffe;
goto [pc];
]]></body>
</pcode>
</callfixup>
<callfixup name="switch16_uhi_r0">
<target name="__gnu_thumb1_case_uhi"/>
<target name="switch16_shi_r0"/>
<pcode>
<body><![CDATA[
tmpptr = lr & 0xfffffffe;
index = r0 * 2;
offset = *:2 (tmpptr + index);
lr = lr + 2 * zext(offset);
ISAModeSwitch = (lr & 1) != 0;
TB = ISAModeSwitch;
pc = lr & 0xfffffffe;
goto [pc];
]]></body>
</pcode>
</callfixup>
<callfixup name="switch32_si_r0">
<target name="__gnu_thumb1_case_si"/>
<target name="switch32_si_r0"/>
<pcode>
<body><![CDATA[
tmpptr = (lr + 2) & 0xfffffffc;
index = r0 * 4;
offset = *:4 (tmpptr + index);
offset = offset * 4;
lr = lr + offset;
ISAModeSwitch = (lr & 1) != 0;
TB = ISAModeSwitch;
pc = lr & 0xfffffffe;
goto [pc];
]]></body>
</pcode>
</callfixup>
</compiler_spec>
python/icicle/Ghidra/Processors/ARM/data/languages/ARM.dwarf
+12 -12
View File
@@ -1,12 +1,12 @@
<dwarf>
<register_mappings>
<register_mapping dwarf="0" ghidra="r0" auto_count="13"/> <!-- r0..r12 -->
<register_mapping dwarf="13" ghidra="sp" stackpointer="true"/>
<register_mapping dwarf="14" ghidra="lr"/>
<register_mapping dwarf="15" ghidra="pc"/>
<register_mapping dwarf="16" ghidra="fpsr"/>
<register_mapping dwarf="17" ghidra="cpsr"/>
</register_mappings>
<call_frame_cfa value="0"/>
<use_formal_parameter_storage/>
</dwarf>
<dwarf>
<register_mappings>
<register_mapping dwarf="0" ghidra="r0" auto_count="13"/> <!-- r0..r12 -->
<register_mapping dwarf="13" ghidra="sp" stackpointer="true"/>
<register_mapping dwarf="14" ghidra="lr"/>
<register_mapping dwarf="15" ghidra="pc"/>
<register_mapping dwarf="16" ghidra="fpsr"/>
<register_mapping dwarf="17" ghidra="cpsr"/>
</register_mappings>
<call_frame_cfa value="0"/>
<use_formal_parameter_storage/>
</dwarf>
python/icicle/Ghidra/Processors/ARM/data/languages/ARM.gdis
+41 -41
View File
@@ -1,41 +1,41 @@
<!--
This file determines the disassembler options sent to the GNU external disassembler.
You can see which options are available for all architectures in the objdump man page.
Given a version of objdump compiled for a specific architecture, you can see what options
are available with "objdump -i -m"
The options for ARM are:
"reg-names-std" (the default)
"reg-names-apcs"
"reg-names-raw"
"reg-names-apcs"
"reg-names-special-apcs"
"force-thumb" (force thumb disassembly)
"no-force-thumb" (force arm disassembly)
(see the objdump manpage for the precise details about the different register
naming options)
"optstring" is the string of options, and "display_prefix" is an optional prefix prepended to the
external disassembly field. In this file, "A: " is prepended to ARM disassembly, and
"T: " is prepended to Thumb disassembly.
To send multiple options, concatenate them into a CSV list. For example, "no-force-thumb,reg-names-raw"
is a valid optstring. You can also have a "global" element whose "optstring" attribute is
always sent to the GNU disassembler.
If there is not a context register defined, the global optstring is sent by itself (see x86-16.gdis for
an example). If there is a context register defined, the global optstring is prepended to the
optstring determined by a context register value.
This file must be listed in the .ldefs file for the processor, e.g.
<external_name tool="gdis.disassembler.options.file" name="ARM.gdis"/>
-->
<gdis>
<context_register>TMode</context_register>
<options>
<option value="0x0" optstring="no-force-thumb" display_prefix = "A: "/>
<option value="0x1" optstring="force-thumb" display_prefix = "T: "/>
</options>
</gdis>
<!--
This file determines the disassembler options sent to the GNU external disassembler.
You can see which options are available for all architectures in the objdump man page.
Given a version of objdump compiled for a specific architecture, you can see what options
are available with "objdump -i -m"
The options for ARM are:
"reg-names-std" (the default)
"reg-names-apcs"
"reg-names-raw"
"reg-names-apcs"
"reg-names-special-apcs"
"force-thumb" (force thumb disassembly)
"no-force-thumb" (force arm disassembly)
(see the objdump manpage for the precise details about the different register
naming options)
"optstring" is the string of options, and "display_prefix" is an optional prefix prepended to the
external disassembly field. In this file, "A: " is prepended to ARM disassembly, and
"T: " is prepended to Thumb disassembly.
To send multiple options, concatenate them into a CSV list. For example, "no-force-thumb,reg-names-raw"
is a valid optstring. You can also have a "global" element whose "optstring" attribute is
always sent to the GNU disassembler.
If there is not a context register defined, the global optstring is sent by itself (see x86-16.gdis for
an example). If there is a context register defined, the global optstring is prepended to the
optstring determined by a context register value.
This file must be listed in the .ldefs file for the processor, e.g.
<external_name tool="gdis.disassembler.options.file" name="ARM.gdis"/>
-->
<gdis>
<context_register>TMode</context_register>
<options>
<option value="0x0" optstring="no-force-thumb" display_prefix = "A: "/>
<option value="0x1" optstring="force-thumb" display_prefix = "T: "/>
</options>
</gdis>
python/icicle/Ghidra/Processors/ARM/data/languages/ARM.ldefs
+377 -377
View File
@@ -1,377 +1,377 @@
<?xml version="1.1" encoding="UTF-8"?>
<language_definitions>
<language processor="ARM"
endian="little"
size="32"
variant="v8"
version="1.107"
slafile="ARM8_le.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:LE:32:v8">
<description>Generic ARM/Thumb v8 little endian</description>
<compiler name="default" spec="ARM.cspec" id="default"/>
<compiler name="Visual Studio" spec="ARM_win.cspec" id="windows"/>
<external_name tool="gnu" name="iwmmxt"/>
<external_name tool="gnu" name="armv8-a"/>
<external_name tool="gnu" name="armv8-r"/>
<external_name tool="gnu" name="armv8-m.base"/>
<external_name tool="gnu" name="armv8-m.main"/>
<external_name tool="gnu" name="armv8.1-m.main"/>
<external_name tool="gnu" name="arm_any"/>
<external_name tool="gdis.disassembler.options.file" name="ARM.gdis"/>
<external_name tool="IDA-PRO" name="arm"/>
<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
</language>
<language processor="ARM"
endian="little"
size="32"
variant="v8T"
version="1.107"
slafile="ARM8_le.sla"
processorspec="ARMtTHUMB.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:LE:32:v8T">
<description>Generic ARM/Thumb v8 little endian (Thumb is default)</description>
<compiler name="default" spec="ARM.cspec" id="default"/>
<compiler name="Visual Studio" spec="ARM_win.cspec" id="windows"/>
<external_name tool="gnu" name="iwmmxt"/>
<external_name tool="gnu" name="arm_any"/>
<external_name tool="gdis.disassembler.options.file" name="ARM.gdis"/>
<external_name tool="IDA-PRO" name="arm"/>
<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
</language>
<language processor="ARM"
endian="big"
instructionEndian="little"
size="32"
variant="v8LEInstruction"
version="1.107"
slafile="ARM8_le.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:LEBE:32:v8LEInstruction">
<description>Generic ARM/Thumb v8 little endian instructions and big endian data</description>
<compiler name="default" spec="ARM.cspec" id="default"/>
<compiler name="Visual Studio" spec="ARM.cspec" id="windows"/>
<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
</language>
<language processor="ARM"
endian="big"
size="32"
variant="v8"
version="1.107"
slafile="ARM8_be.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:BE:32:v8">
<description>Generic ARM/Thumb v8 big endian</description>
<compiler name="default" spec="ARM.cspec" id="default"/>
<external_name tool="gnu" name="iwmmxt"/>
<external_name tool="gnu" name="armv8-a"/>
<external_name tool="gnu" name="armv8-r"/>
<external_name tool="gnu" name="armv8-m.base"/>
<external_name tool="gnu" name="armv8-m.main"/>
<external_name tool="gnu" name="armv8.1-m.main"/>
<external_name tool="gnu" name="arm_any"/>
<external_name tool="gdis.disassembler.options.file" name="ARM.gdis"/>
<external_name tool="IDA-PRO" name="armb"/>
<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
</language>
<language processor="ARM"
endian="big"
size="32"
variant="v8T"
version="1.107"
slafile="ARM8_be.sla"
processorspec="ARMtTHUMB.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:BE:32:v8T">
<description>Generic ARM/Thumb v8 big endian (Thumb is default)</description>
<compiler name="default" spec="ARM.cspec" id="default"/>
<external_name tool="gnu" name="iwmmxt"/>
<external_name tool="gnu" name="arm_any"/>
<external_name tool="IDA-PRO" name="armb"/>
<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
</language>
<language processor="ARM"
endian="little"
size="32"
variant="v7"
version="1.107"
slafile="ARM7_le.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:LE:32:v7">
<description>Generic ARM/Thumb v7 little endian</description>
<compiler name="default" spec="ARM.cspec" id="default"/>
<compiler name="Visual Studio" spec="ARM_win.cspec" id="windows"/>
<external_name tool="gnu" name="iwmmxt"/>
<external_name tool="gnu" name="armv7"/>
<external_name tool="gdis.disassembler.options.file" name="ARM.gdis"/>
<external_name tool="IDA-PRO" name="arm"/>
<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
</language>
<language processor="ARM"
endian="big"
instructionEndian="little"
size="32"
variant="v7LEInstruction"
version="1.107"
slafile="ARM7_le.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:LEBE:32:v7LEInstruction">
<description>Generic ARM/Thumb v7 little endian instructions and big endian data</description>
<compiler name="default" spec="ARM.cspec" id="default"/>
<compiler name="Visual Studio" spec="ARM.cspec" id="windows"/>
<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
</language>
<language processor="ARM"
endian="big"
size="32"
variant="v7"
version="1.107"
slafile="ARM7_be.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:BE:32:v7">
<description>Generic ARM/Thumb v7 big endian</description>
<compiler name="default" spec="ARM.cspec" id="default"/>
<external_name tool="gnu" name="iwmmxt"/>
<external_name tool="gnu" name="armv7"/>
<external_name tool="gdis.disassembler.options.file" name="ARM.gdis"/>
<external_name tool="IDA-PRO" name="armb"/>
<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
</language>
<language processor="ARM"
endian="little"
size="32"
variant="Cortex"
version="1.107"
slafile="ARM7_le.sla"
processorspec="ARMCortex.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:LE:32:Cortex">
<description>ARM Cortex / Thumb little endian</description>
<compiler name="default" spec="ARM.cspec" id="default"/>
<external_name tool="gnu" name="armv7e-m"/>
<external_name tool="gnu" name="armv6k"/>
<external_name tool="gnu" name="armv6kz"/>
<external_name tool="gnu" name="armv6-m"/>
<external_name tool="gnu" name="armv6s-m"/>
<external_name tool="IDA-PRO" name="arm"/>
<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
</language>
<language processor="ARM"
endian="big"
size="32"
variant="Cortex"
version="1.107"
slafile="ARM7_be.sla"
processorspec="ARMCortex.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:BE:32:Cortex">
<description>ARM Cortex / Thumb big endian</description>
<compiler name="default" spec="ARM.cspec" id="default"/>
<external_name tool="gnu" name="armv6k"/>
<external_name tool="gnu" name="armv6kz"/>
<external_name tool="gnu" name="armv6-m"/>
<external_name tool="gnu" name="armv6s-m"/>
<external_name tool="IDA-PRO" name="armb"/>
<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
</language>
<language processor="ARM"
endian="little"
size="32"
variant="v6"
version="1.107"
slafile="ARM6_le.sla"
processorspec="ARMt_v6.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:LE:32:v6">
<description>Generic ARM/Thumb v6 little endian</description>
<compiler name="default" spec="ARM_v45.cspec" id="default"/>
<external_name tool="gnu" name="xscale"/>
<external_name tool="gnu" name="armv6"/>
<external_name tool="gdis.disassembler.options.file" name="ARM.gdis"/>
<external_name tool="IDA-PRO" name="arm"/>
<external_name tool="DWARF.register.mapping.file" name="ARM.dwarf"/>
<!-- change DWARF register mapping to ARMneon.dwarf if VFPv2 is enabled -->
<!-- <external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/> -->
</language>
<language processor="ARM"
endian="big"
size="32"
variant="v6"
version="1.107"
slafile="ARM6_be.sla"
processorspec="ARMt_v6.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:BE:32:v6">
<description>Generic ARM/Thumb v6 big endian</description>
<compiler name="default" spec="ARM_v45.cspec" id="default"/>
<external_name tool="gnu" name="xscale"/>
<external_name tool="gnu" name="armv6"/>
<external_name tool="gdis.disassembler.options.file" name="ARM.gdis"/>
<external_name tool="IDA-PRO" name="armb"/>
<external_name tool="DWARF.register.mapping.file" name="ARM.dwarf"/>
<!-- change DWARF register mapping to ARMneon.dwarf if VFPv2 is enabled -->
<!-- <external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/> -->
</language>
<language processor="ARM"
endian="little"
size="32"
variant="v5t"
version="1.107"
slafile="ARM5t_le.sla"
processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:LE:32:v5t">
<description>Generic ARM/Thumb v5 little endian (T-variant)</description>
<compiler name="default" spec="ARM_v45.cspec" id="default"/>
<external_name tool="gnu" name="armv5t"/>
<external_name tool="gnu" name="armv5tej"/>
<external_name tool="gdis.disassembler.options.file" name="ARM.gdis"/>
<external_name tool="IDA-PRO" name="arm"/>
<external_name tool="DWARF.register.mapping.file" name="ARM.dwarf"/>
</language>
<language processor="ARM"
endian="big"
size="32"
variant="v5t"
version="1.107"
slafile="ARM5t_be.sla"
processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:BE:32:v5t">
<description>Generic ARM/Thumb v5 big endian (T-variant)</description>
<compiler name="default" spec="ARM_v45.cspec" id="default"/>
<external_name tool="gnu" name="armv5t"/>
<external_name tool="gnu" name="armv5tej"/>
<external_name tool="gdis.disassembler.options.file" name="ARM.gdis"/>
<external_name tool="IDA-PRO" name="armb"/>
<external_name tool="DWARF.register.mapping.file" name="ARM.dwarf"/>
</language>
<language processor="ARM"
endian="little"
size="32"
variant="v5"
version="1.107"
slafile="ARM5_le.sla"
processorspec="ARM_v45.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:LE:32:v5">
<description>Generic ARM v5 little endian</description>
<compiler name="default" spec="ARM_v45.cspec" id="default"/>
<external_name tool="gnu" name="armv5"/>
<external_name tool="IDA-PRO" name="arm"/>
<external_name tool="DWARF.register.mapping.file" name="ARM.dwarf"/>
</language>
<language processor="ARM"
endian="big"
size="32"
variant="v5"
version="1.101"
slafile="ARM5_be.sla"
processorspec="ARM_v45.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:BE:32:v5">
<description>Generic ARM v5 big endian</description>
<compiler name="default" spec="ARM_v45.cspec" id="default"/>
<external_name tool="gnu" name="armv5"/>
<external_name tool="IDA-PRO" name="armb"/>
<external_name tool="DWARF.register.mapping.file" name="ARM.dwarf"/>
</language>
<language processor="ARM"
endian="little"
size="32"
variant="v4t"
version="1.107"
slafile="ARM4t_le.sla"
processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:LE:32:v4t">
<description>Generic ARM/Thumb v4 little endian (T-variant)</description>
<compiler name="default" spec="ARM_v45.cspec" id="default"/>
<external_name tool="gnu" name="armv4t"/>
<external_name tool="gdis.disassembler.options.file" name="ARM.gdis"/>
<external_name tool="IDA-PRO" name="arm"/>
<external_name tool="DWARF.register.mapping.file" name="ARM.dwarf"/>
</language>
<language processor="ARM"
endian="big"
size="32"
variant="v4t"
version="1.107"
slafile="ARM4t_be.sla"
processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:BE:32:v4t">
<description>Generic ARM/Thumb v4 big endian (T-variant)</description>
<compiler name="default" spec="ARM_v45.cspec" id="default"/>
<external_name tool="gnu" name="armv4t"/>
<external_name tool="gdis.disassembler.options.file" name="ARM.gdis"/>
<external_name tool="IDA-PRO" name="armb"/>
<external_name tool="DWARF.register.mapping.file" name="ARM.dwarf"/>
</language>
<language processor="ARM"
endian="little"
size="32"
variant="v4"
version="1.107"
slafile="ARM4_le.sla"
processorspec="ARM_v45.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:LE:32:v4">
<description>Generic ARM v4 little endian</description>
<compiler name="default" spec="ARM_v45.cspec" id="default"/>
<external_name tool="gnu" name="armv4"/>
<external_name tool="gnu" name="armv2"/>
<external_name tool="gnu" name="armv2a"/>
<external_name tool="gnu" name="armv3"/>
<external_name tool="gnu" name="armv3m"/>
<external_name tool="IDA-PRO" name="arm"/>
<external_name tool="DWARF.register.mapping.file" name="ARM.dwarf"/>
</language>
<language processor="ARM"
endian="big"
size="32"
variant="v4"
version="1.107"
slafile="ARM4_be.sla"
processorspec="ARM_v45.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:BE:32:v4">
<description>Generic ARM v4 big endian</description>
<compiler name="default" spec="ARM_v45.cspec" id="default"/>
<external_name tool="gnu" name="armv4"/>
<external_name tool="gnu" name="armv2"/>
<external_name tool="gnu" name="armv2a"/>
<external_name tool="gnu" name="armv3"/>
<external_name tool="gnu" name="armv3m"/>
<external_name tool="IDA-PRO" name="armb"/>
<external_name tool="DWARF.register.mapping.file" name="ARM.dwarf"/>
</language>
</language_definitions>
<?xml version="1.1" encoding="UTF-8"?>
<language_definitions>
<language processor="ARM"
endian="little"
size="32"
variant="v8"
version="1.107"
slafile="ARM8_le.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:LE:32:v8">
<description>Generic ARM/Thumb v8 little endian</description>
<compiler name="default" spec="ARM.cspec" id="default"/>
<compiler name="Visual Studio" spec="ARM_win.cspec" id="windows"/>
<external_name tool="gnu" name="iwmmxt"/>
<external_name tool="gnu" name="armv8-a"/>
<external_name tool="gnu" name="armv8-r"/>
<external_name tool="gnu" name="armv8-m.base"/>
<external_name tool="gnu" name="armv8-m.main"/>
<external_name tool="gnu" name="armv8.1-m.main"/>
<external_name tool="gnu" name="arm_any"/>
<external_name tool="gdis.disassembler.options.file" name="ARM.gdis"/>
<external_name tool="IDA-PRO" name="arm"/>
<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
</language>
<language processor="ARM"
endian="little"
size="32"
variant="v8T"
version="1.107"
slafile="ARM8_le.sla"
processorspec="ARMtTHUMB.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:LE:32:v8T">
<description>Generic ARM/Thumb v8 little endian (Thumb is default)</description>
<compiler name="default" spec="ARM.cspec" id="default"/>
<compiler name="Visual Studio" spec="ARM_win.cspec" id="windows"/>
<external_name tool="gnu" name="iwmmxt"/>
<external_name tool="gnu" name="arm_any"/>
<external_name tool="gdis.disassembler.options.file" name="ARM.gdis"/>
<external_name tool="IDA-PRO" name="arm"/>
<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
</language>
<language processor="ARM"
endian="big"
instructionEndian="little"
size="32"
variant="v8LEInstruction"
version="1.107"
slafile="ARM8_le.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:LEBE:32:v8LEInstruction">
<description>Generic ARM/Thumb v8 little endian instructions and big endian data</description>
<compiler name="default" spec="ARM.cspec" id="default"/>
<compiler name="Visual Studio" spec="ARM.cspec" id="windows"/>
<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
</language>
<language processor="ARM"
endian="big"
size="32"
variant="v8"
version="1.107"
slafile="ARM8_be.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:BE:32:v8">
<description>Generic ARM/Thumb v8 big endian</description>
<compiler name="default" spec="ARM.cspec" id="default"/>
<external_name tool="gnu" name="iwmmxt"/>
<external_name tool="gnu" name="armv8-a"/>
<external_name tool="gnu" name="armv8-r"/>
<external_name tool="gnu" name="armv8-m.base"/>
<external_name tool="gnu" name="armv8-m.main"/>
<external_name tool="gnu" name="armv8.1-m.main"/>
<external_name tool="gnu" name="arm_any"/>
<external_name tool="gdis.disassembler.options.file" name="ARM.gdis"/>
<external_name tool="IDA-PRO" name="armb"/>
<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
</language>
<language processor="ARM"
endian="big"
size="32"
variant="v8T"
version="1.107"
slafile="ARM8_be.sla"
processorspec="ARMtTHUMB.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:BE:32:v8T">
<description>Generic ARM/Thumb v8 big endian (Thumb is default)</description>
<compiler name="default" spec="ARM.cspec" id="default"/>
<external_name tool="gnu" name="iwmmxt"/>
<external_name tool="gnu" name="arm_any"/>
<external_name tool="IDA-PRO" name="armb"/>
<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
</language>
<language processor="ARM"
endian="little"
size="32"
variant="v7"
version="1.107"
slafile="ARM7_le.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:LE:32:v7">
<description>Generic ARM/Thumb v7 little endian</description>
<compiler name="default" spec="ARM.cspec" id="default"/>
<compiler name="Visual Studio" spec="ARM_win.cspec" id="windows"/>
<external_name tool="gnu" name="iwmmxt"/>
<external_name tool="gnu" name="armv7"/>
<external_name tool="gdis.disassembler.options.file" name="ARM.gdis"/>
<external_name tool="IDA-PRO" name="arm"/>
<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
</language>
<language processor="ARM"
endian="big"
instructionEndian="little"
size="32"
variant="v7LEInstruction"
version="1.107"
slafile="ARM7_le.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:LEBE:32:v7LEInstruction">
<description>Generic ARM/Thumb v7 little endian instructions and big endian data</description>
<compiler name="default" spec="ARM.cspec" id="default"/>
<compiler name="Visual Studio" spec="ARM.cspec" id="windows"/>
<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
</language>
<language processor="ARM"
endian="big"
size="32"
variant="v7"
version="1.107"
slafile="ARM7_be.sla"
processorspec="ARMt.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:BE:32:v7">
<description>Generic ARM/Thumb v7 big endian</description>
<compiler name="default" spec="ARM.cspec" id="default"/>
<external_name tool="gnu" name="iwmmxt"/>
<external_name tool="gnu" name="armv7"/>
<external_name tool="gdis.disassembler.options.file" name="ARM.gdis"/>
<external_name tool="IDA-PRO" name="armb"/>
<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
</language>
<language processor="ARM"
endian="little"
size="32"
variant="Cortex"
version="1.107"
slafile="ARM7_le.sla"
processorspec="ARMCortex.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:LE:32:Cortex">
<description>ARM Cortex / Thumb little endian</description>
<compiler name="default" spec="ARM.cspec" id="default"/>
<external_name tool="gnu" name="armv7e-m"/>
<external_name tool="gnu" name="armv6k"/>
<external_name tool="gnu" name="armv6kz"/>
<external_name tool="gnu" name="armv6-m"/>
<external_name tool="gnu" name="armv6s-m"/>
<external_name tool="IDA-PRO" name="arm"/>
<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
</language>
<language processor="ARM"
endian="big"
size="32"
variant="Cortex"
version="1.107"
slafile="ARM7_be.sla"
processorspec="ARMCortex.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:BE:32:Cortex">
<description>ARM Cortex / Thumb big endian</description>
<compiler name="default" spec="ARM.cspec" id="default"/>
<external_name tool="gnu" name="armv6k"/>
<external_name tool="gnu" name="armv6kz"/>
<external_name tool="gnu" name="armv6-m"/>
<external_name tool="gnu" name="armv6s-m"/>
<external_name tool="IDA-PRO" name="armb"/>
<external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/>
</language>
<language processor="ARM"
endian="little"
size="32"
variant="v6"
version="1.107"
slafile="ARM6_le.sla"
processorspec="ARMt_v6.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:LE:32:v6">
<description>Generic ARM/Thumb v6 little endian</description>
<compiler name="default" spec="ARM_v45.cspec" id="default"/>
<external_name tool="gnu" name="xscale"/>
<external_name tool="gnu" name="armv6"/>
<external_name tool="gdis.disassembler.options.file" name="ARM.gdis"/>
<external_name tool="IDA-PRO" name="arm"/>
<external_name tool="DWARF.register.mapping.file" name="ARM.dwarf"/>
<!-- change DWARF register mapping to ARMneon.dwarf if VFPv2 is enabled -->
<!-- <external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/> -->
</language>
<language processor="ARM"
endian="big"
size="32"
variant="v6"
version="1.107"
slafile="ARM6_be.sla"
processorspec="ARMt_v6.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:BE:32:v6">
<description>Generic ARM/Thumb v6 big endian</description>
<compiler name="default" spec="ARM_v45.cspec" id="default"/>
<external_name tool="gnu" name="xscale"/>
<external_name tool="gnu" name="armv6"/>
<external_name tool="gdis.disassembler.options.file" name="ARM.gdis"/>
<external_name tool="IDA-PRO" name="armb"/>
<external_name tool="DWARF.register.mapping.file" name="ARM.dwarf"/>
<!-- change DWARF register mapping to ARMneon.dwarf if VFPv2 is enabled -->
<!-- <external_name tool="DWARF.register.mapping.file" name="ARMneon.dwarf"/> -->
</language>
<language processor="ARM"
endian="little"
size="32"
variant="v5t"
version="1.107"
slafile="ARM5t_le.sla"
processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:LE:32:v5t">
<description>Generic ARM/Thumb v5 little endian (T-variant)</description>
<compiler name="default" spec="ARM_v45.cspec" id="default"/>
<external_name tool="gnu" name="armv5t"/>
<external_name tool="gnu" name="armv5tej"/>
<external_name tool="gdis.disassembler.options.file" name="ARM.gdis"/>
<external_name tool="IDA-PRO" name="arm"/>
<external_name tool="DWARF.register.mapping.file" name="ARM.dwarf"/>
</language>
<language processor="ARM"
endian="big"
size="32"
variant="v5t"
version="1.107"
slafile="ARM5t_be.sla"
processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:BE:32:v5t">
<description>Generic ARM/Thumb v5 big endian (T-variant)</description>
<compiler name="default" spec="ARM_v45.cspec" id="default"/>
<external_name tool="gnu" name="armv5t"/>
<external_name tool="gnu" name="armv5tej"/>
<external_name tool="gdis.disassembler.options.file" name="ARM.gdis"/>
<external_name tool="IDA-PRO" name="armb"/>
<external_name tool="DWARF.register.mapping.file" name="ARM.dwarf"/>
</language>
<language processor="ARM"
endian="little"
size="32"
variant="v5"
version="1.107"
slafile="ARM5_le.sla"
processorspec="ARM_v45.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:LE:32:v5">
<description>Generic ARM v5 little endian</description>
<compiler name="default" spec="ARM_v45.cspec" id="default"/>
<external_name tool="gnu" name="armv5"/>
<external_name tool="IDA-PRO" name="arm"/>
<external_name tool="DWARF.register.mapping.file" name="ARM.dwarf"/>
</language>
<language processor="ARM"
endian="big"
size="32"
variant="v5"
version="1.101"
slafile="ARM5_be.sla"
processorspec="ARM_v45.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:BE:32:v5">
<description>Generic ARM v5 big endian</description>
<compiler name="default" spec="ARM_v45.cspec" id="default"/>
<external_name tool="gnu" name="armv5"/>
<external_name tool="IDA-PRO" name="armb"/>
<external_name tool="DWARF.register.mapping.file" name="ARM.dwarf"/>
</language>
<language processor="ARM"
endian="little"
size="32"
variant="v4t"
version="1.107"
slafile="ARM4t_le.sla"
processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:LE:32:v4t">
<description>Generic ARM/Thumb v4 little endian (T-variant)</description>
<compiler name="default" spec="ARM_v45.cspec" id="default"/>
<external_name tool="gnu" name="armv4t"/>
<external_name tool="gdis.disassembler.options.file" name="ARM.gdis"/>
<external_name tool="IDA-PRO" name="arm"/>
<external_name tool="DWARF.register.mapping.file" name="ARM.dwarf"/>
</language>
<language processor="ARM"
endian="big"
size="32"
variant="v4t"
version="1.107"
slafile="ARM4t_be.sla"
processorspec="ARMt_v45.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:BE:32:v4t">
<description>Generic ARM/Thumb v4 big endian (T-variant)</description>
<compiler name="default" spec="ARM_v45.cspec" id="default"/>
<external_name tool="gnu" name="armv4t"/>
<external_name tool="gdis.disassembler.options.file" name="ARM.gdis"/>
<external_name tool="IDA-PRO" name="armb"/>
<external_name tool="DWARF.register.mapping.file" name="ARM.dwarf"/>
</language>
<language processor="ARM"
endian="little"
size="32"
variant="v4"
version="1.107"
slafile="ARM4_le.sla"
processorspec="ARM_v45.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:LE:32:v4">
<description>Generic ARM v4 little endian</description>
<compiler name="default" spec="ARM_v45.cspec" id="default"/>
<external_name tool="gnu" name="armv4"/>
<external_name tool="gnu" name="armv2"/>
<external_name tool="gnu" name="armv2a"/>
<external_name tool="gnu" name="armv3"/>
<external_name tool="gnu" name="armv3m"/>
<external_name tool="IDA-PRO" name="arm"/>
<external_name tool="DWARF.register.mapping.file" name="ARM.dwarf"/>
</language>
<language processor="ARM"
endian="big"
size="32"
variant="v4"
version="1.107"
slafile="ARM4_be.sla"
processorspec="ARM_v45.pspec"
manualindexfile="../manuals/ARM.idx"
id="ARM:BE:32:v4">
<description>Generic ARM v4 big endian</description>
<compiler name="default" spec="ARM_v45.cspec" id="default"/>
<external_name tool="gnu" name="armv4"/>
<external_name tool="gnu" name="armv2"/>
<external_name tool="gnu" name="armv2a"/>
<external_name tool="gnu" name="armv3"/>
<external_name tool="gnu" name="armv3m"/>
<external_name tool="IDA-PRO" name="armb"/>
<external_name tool="DWARF.register.mapping.file" name="ARM.dwarf"/>
</language>
</language_definitions>
python/icicle/Ghidra/Processors/ARM/data/languages/ARM.opinion
+68 -68
View File
@@ -1,68 +1,68 @@
<opinions>
<!--
NOTE: secondary key constraints can be matched at the bit level or as a hex value (if the
key is an integer value).
When matching at the bit level, prefix the secondary key constraint value with "0b", followed
by a sequence of 0's and 1's to specify the key value. Dots (".") can be used as a wild card
for individual bits. Space and underscores ("_") are ignored and can be used for formatting.
When matching a hex value, prefix the secondary key constraint value with "0x", followed
by the hex value. No wildcarding is supported.
-->
<constraint loader="Portable Executable (PE)">
<constraint compilerSpecID="windows">
<constraint primary="448" processor="ARM" endian="little" size="32" variant="v8" />
<constraint primary="450" processor="ARM" endian="little" size="32" variant="v8" /> <!-- ARM and Thumb, spec says only Thumb -->
<constraint primary="452" processor="ARM" endian="little" size="32" variant="v8" />
</constraint>
<constraint compilerSpecID="default">
<constraint primary="2560" processor="ARM" endian="big" size="32" variant="v8" />
</constraint>
</constraint>
<constraint loader="Debug Symbols (DBG)" compilerSpecID="windows">
<constraint primary="448" processor="ARM" endian="little" size="32" variant="v8" />
<constraint primary="450" processor="ARM" endian="little" size="32" variant="v8" /> <!-- ARM and Thumb, spec says only Thumb -->
<constraint primary="452" processor="ARM" endian="little" size="32" variant="v8" />
</constraint>
<constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default">
<!--
Elf e_flags are used for the secondary attribute, the following are pulled from binutils include/elf/arm.h
/* Constants defined in AAELF. */
EF_ARM_BE8 0x00800000
EF_ARM_LE8 0x00400000
EF_ARM_EABIMASK 0xFF000000
EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK)
EF_ARM_EABI_UNKNOWN 0x00000000
EF_ARM_EABI_VER1 0x01000000
EF_ARM_EABI_VER2 0x02000000
EF_ARM_EABI_VER3 0x03000000
EF_ARM_EABI_VER4 0x04000000
EF_ARM_EABI_VER5 0x05000000
-->
<constraint primary="40" processor="ARM" size="32" variant="v8"
secondary= "0b .... .... 0... .... .... .... .... ...."/>
<constraint primary="40" processor="ARM" size="32" variant="v8LEInstruction"
secondary= "0b .... .... 1... .... .... .... .... ...."/> <!-- EF_ARM_BE8 -->
</constraint>
<constraint loader="Mac OS X Mach-O" compilerSpecID="default">
<constraint primary="12.0" processor="ARM" endian="little" size="32" variant="v8" /><!-- ARM all -->
<constraint primary="12.5" processor="ARM" endian="little" size="32" variant="v4t" /><!-- ARM v4T -->
<constraint primary="12.6" processor="ARM" endian="little" size="32" variant="v6" /><!-- ARM v6 -->
<constraint primary="12.9" processor="ARM" endian="little" size="32" variant="v8" /><!-- ARM v8 -->
<constraint primary="12.10" processor="ARM" endian="little" size="32" variant="v8" /><!-- ARM v8f -->
<constraint primary="12.11" processor="ARM" endian="little" size="32" variant="v8" /><!-- ARM v8s -->
<constraint primary="12.12" processor="ARM" endian="little" size="32" variant="v8" /><!-- ARM v8k -->
</constraint>
<constraint loader="DYLD Cache" compilerSpecID="default">
<constraint primary="armv6" processor="ARM" endian="little" size="32" variant="v6" />
<constraint primary="arm7" processor="ARM" endian="little" size="32" variant="v7" />
</constraint>
<constraint loader="MS Common Object File Format (COFF)" compilerSpecID="windows">
<constraint primary="448" processor="ARM" endian="little" size="32" variant="v8" />
<constraint primary="450" processor="ARM" endian="little" size="32" variant="v8T" /> <!-- THUMB -->
<constraint primary="452" processor="ARM" endian="little" size="32" variant="v8T" /> <!-- THUMB -->
</constraint>
</opinions>
<opinions>
<!--
NOTE: secondary key constraints can be matched at the bit level or as a hex value (if the
key is an integer value).
When matching at the bit level, prefix the secondary key constraint value with "0b", followed
by a sequence of 0's and 1's to specify the key value. Dots (".") can be used as a wild card
for individual bits. Space and underscores ("_") are ignored and can be used for formatting.
When matching a hex value, prefix the secondary key constraint value with "0x", followed
by the hex value. No wildcarding is supported.
-->
<constraint loader="Portable Executable (PE)">
<constraint compilerSpecID="windows">
<constraint primary="448" processor="ARM" endian="little" size="32" variant="v8" />
<constraint primary="450" processor="ARM" endian="little" size="32" variant="v8" /> <!-- ARM and Thumb, spec says only Thumb -->
<constraint primary="452" processor="ARM" endian="little" size="32" variant="v8" />
</constraint>
<constraint compilerSpecID="default">
<constraint primary="2560" processor="ARM" endian="big" size="32" variant="v8" />
</constraint>
</constraint>
<constraint loader="Debug Symbols (DBG)" compilerSpecID="windows">
<constraint primary="448" processor="ARM" endian="little" size="32" variant="v8" />
<constraint primary="450" processor="ARM" endian="little" size="32" variant="v8" /> <!-- ARM and Thumb, spec says only Thumb -->
<constraint primary="452" processor="ARM" endian="little" size="32" variant="v8" />
</constraint>
<constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default">
<!--
Elf e_flags are used for the secondary attribute, the following are pulled from binutils include/elf/arm.h
/* Constants defined in AAELF. */
EF_ARM_BE8 0x00800000
EF_ARM_LE8 0x00400000
EF_ARM_EABIMASK 0xFF000000
EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK)
EF_ARM_EABI_UNKNOWN 0x00000000
EF_ARM_EABI_VER1 0x01000000
EF_ARM_EABI_VER2 0x02000000
EF_ARM_EABI_VER3 0x03000000
EF_ARM_EABI_VER4 0x04000000
EF_ARM_EABI_VER5 0x05000000
-->
<constraint primary="40" processor="ARM" size="32" variant="v8"
secondary= "0b .... .... 0... .... .... .... .... ...."/>
<constraint primary="40" processor="ARM" size="32" variant="v8LEInstruction"
secondary= "0b .... .... 1... .... .... .... .... ...."/> <!-- EF_ARM_BE8 -->
</constraint>
<constraint loader="Mac OS X Mach-O" compilerSpecID="default">
<constraint primary="12.0" processor="ARM" endian="little" size="32" variant="v8" /><!-- ARM all -->
<constraint primary="12.5" processor="ARM" endian="little" size="32" variant="v4t" /><!-- ARM v4T -->
<constraint primary="12.6" processor="ARM" endian="little" size="32" variant="v6" /><!-- ARM v6 -->
<constraint primary="12.9" processor="ARM" endian="little" size="32" variant="v8" /><!-- ARM v8 -->
<constraint primary="12.10" processor="ARM" endian="little" size="32" variant="v8" /><!-- ARM v8f -->
<constraint primary="12.11" processor="ARM" endian="little" size="32" variant="v8" /><!-- ARM v8s -->
<constraint primary="12.12" processor="ARM" endian="little" size="32" variant="v8" /><!-- ARM v8k -->
</constraint>
<constraint loader="DYLD Cache" compilerSpecID="default">
<constraint primary="armv6" processor="ARM" endian="little" size="32" variant="v6" />
<constraint primary="arm7" processor="ARM" endian="little" size="32" variant="v7" />
</constraint>
<constraint loader="MS Common Object File Format (COFF)" compilerSpecID="windows">
<constraint primary="448" processor="ARM" endian="little" size="32" variant="v8" />
<constraint primary="450" processor="ARM" endian="little" size="32" variant="v8T" /> <!-- THUMB -->
<constraint primary="452" processor="ARM" endian="little" size="32" variant="v8T" /> <!-- THUMB -->
</constraint>
</opinions>
python/icicle/Ghidra/Processors/ARM/data/languages/ARM.sinc
+302 -302
View File
@@ -1,302 +1,302 @@
# Specification for the ARM Version 4, 4T, 5, 5T, 5E
# The following boolean defines control specific support: T_VARIANT, VERSION_5, VERSION_5E
define endian=$(ENDIAN);
define alignment=2;
define space ram type=ram_space size=4 default;
define space register type=register_space size=4;
define register offset=0x0020 size=4 [ r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 sp lr pc ];
define register offset=0x0060 size=1 [ NG ZR CY OV tmpNG tmpZR tmpCY tmpOV shift_carry TB Q GE1 GE2 GE3 GE4 ];
define register offset=0x0070 size=4 [ cpsr spsr ];
define register offset=0x0080 size=4 [ mult_addr ]; # Special internal register for dealing with multiple stores/loads
define register offset=0x0084 size=4 [ r14_svc r13_svc spsr_svc ];
define register offset=0x0090 size=8 [ mult_dat8 ]; # Special internal register for dealing with multiple stores/loads
define register offset=0x0090 size=16 [ mult_dat16 ]; # Special internal register for dealing with multiple stores/loads
define register offset=0x00A0 size=4 [ fpsr ]; # floating point state register (for FPA10 floating-point accelerator)
define register offset=0x00B0 size=1 [ ISAModeSwitch ]; # generic name for TB ThumbBit - set same as TB
@define FPSCR_N "fpscr[31,1]"
@define FPSCR_Z "fpscr[30,1]"
@define FPSCR_C "fpscr[29,1]"
@define FPSCR_V "fpscr[28,1]"
@if defined(VFPv2) || defined(VFPv3) || defined(SIMD)
define register offset=0x00B0 size=4 [ fpsid fpscr fpexc mvfr0 mvfr1 ];
@endif
define register offset=0x0100 size=10 [ fp0 fp1 fp2 fp3 fp4 fp5 fp6 fp7 ]; # eight 80-bit floating registers
# pseudo-registers for coprocessor calculations
define register offset=0x0200 size=4 [ cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 cr8 cr9 cr10 cr11 cr12 cr13 cr14 cr15 ];
# Advanced SIMD and VFP extension registers
@if defined(VFPv2) || defined(VFPv3)
@if ENDIAN == "little"
define register offset=0x0300 size=4 [ s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15
s16 s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31 ];
@else # ENDIAN == "big"
define register offset=0x0300 size=4 [ s31 s30 s29 s28 s27 s26 s25 s24 s23 s22 s21 s20 s19 s18 s17 s16
s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 ];
@endif # ENDIAN = "big"
@endif # VFPv2 || VFPv3
@if defined(VFPv2)
@if ENDIAN == "little"
define register offset=0x0300 size=8 [ d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ];
@else # ENDIAN == "big"
define register offset=0x0300 size=8 [ d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ];
@endif # ENDIAN = "big"
@endif # VFPv2
@if defined(SIMD) || defined(VFPv3)
@if ENDIAN == "little"
define register offset=0x0300 size=8 [ d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15
d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 ];
@else # ENDIAN == "big"
define register offset=0x0300 size=8 [ d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16
d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ];
@endif # ENDIAN = "big"
@endif # SIMD || VFPv3
@if defined(SIMD)
@if ENDIAN == "little"
define register offset=0x0300 size=16 [ q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 ];
@else # ENDIAN == "big"
define register offset=0x0300 size=16 [ q15 q14 q13 q12 q11 q10 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 ];
@endif # ENDIAN = "big"
@endif # SIMD
# Define context bits
# WARNING: when adjusting context keep compiler packing in mind
# and make sure fields do not span a 32-bit boundary before or
# after context packing
define register offset=0x00 size=8 contextreg;
define context contextreg
@ifdef T_VARIANT
TMode = (0,0) # 1 if in Thumb instruction decode mode
T = (0,0) # exact copy (alias!) of TMode
LowBitCodeMode = (0,0) # 1 if low bit of instruction address is set on a branch
ISA_MODE = (0,0) # 1 for Thumb instruction decode mode
@endif
LRset = (1,1) noflow # 1 if the instruction right before was a mov lr,pc
REToverride = (2,2) noflow # 1 if the instruction should be a branch not a return
CALLoverride = (3,3) noflow # 1 if the call should actually be a jump
@if defined(VERSION_6T2) || defined(VERSION_7)
TEEMode = (4,4) # 1 if in ThumbEE mode, changes some instruction behavior, and makes some instructions invalid
condit = (5,13) noflow # both base and shift
cond_mask = (10,13) # base condition
cond_full = (6,9) # full condition
cond_true = (9,9) # true if this condition should be tested for true
cond_base = (6,8) # shift mask for controlling shift
cond_shft = (9,13) # mask and lower bit of it condition field
itmode = (5,5) # true if in ITBlock mode
@endif
# Transient context bits
counter = (14,18) # 0 to 7 counter (for building variable length register lists)
# dreg = (17,21) # D register (attached, for building register lists)
# sreg = (17,21) # S register (attached, for building register lists)
regNum = (19,23) # D register number (see dreg)
counter2 = (24,26) # 0 to 7 counter (for building variable length register lists)
# dreg2 = (25,29) # 2nd D register (attached, for building register lists)
# sreg2 = (25,29) # 2nd S register (attached, for building register lists)
reg2Num = (27,31) # 2nd D register number (see dreg2)
# --- do not allow any field to span 32-bit boundary ---
regInc = (32,33) # Pair register increment
ARMcond = (34,34) # ARM conditional instruction
ARMcondCk = (35,35) # Finished ARM condition check phase
;
define pcodeop coprocessor_function;
define pcodeop coprocessor_function2;
define pcodeop coprocessor_load;
define pcodeop coprocessor_load2;
define pcodeop coprocessor_loadlong;
define pcodeop coprocessor_loadlong2;
define pcodeop coprocessor_moveto;
define pcodeop coprocessor_moveto2;
define pcodeop coprocessor_movefromRt;
define pcodeop coprocessor_movefromRt2;
define pcodeop coprocessor_movefrom2;
define pcodeop coprocessor_store;
define pcodeop coprocessor_store2;
define pcodeop coprocessor_storelong;
define pcodeop coprocessor_storelong2;
define pcodeop software_interrupt;
define pcodeop software_bkpt;
define pcodeop software_udf;
define pcodeop software_hlt;
define pcodeop software_hvc;
define pcodeop software_smc;
# CPS methods (Version 6)
define pcodeop setUserMode;
define pcodeop setFIQMode;
define pcodeop setIRQMode;
define pcodeop setSupervisorMode;
define pcodeop setMonitorMode;
define pcodeop setAbortMode;
define pcodeop setUndefinedMode;
define pcodeop setSystemMode;
define pcodeop enableIRQinterrupts;
define pcodeop enableFIQinterrupts;
define pcodeop enableDataAbortInterrupts;
define pcodeop disableIRQinterrupts;
define pcodeop disableFIQinterrupts;
define pcodeop isFIQinterruptsEnabled;
define pcodeop isIRQinterruptsEnabled;
define pcodeop disableDataAbortInterrupts;
define pcodeop hasExclusiveAccess;
define pcodeop isCurrentModePrivileged;
define pcodeop setThreadModePrivileged;
define pcodeop isThreadMode;
define pcodeop jazelle_branch;
define pcodeop ClearExclusiveLocal;
define pcodeop HintDebug;
define pcodeop DataMemoryBarrier;
define pcodeop DataSynchronizationBarrier;
define pcodeop secureMonitorCall;
define pcodeop WaitForEvent;
define pcodeop WaitForInterrupt;
define pcodeop HintYield;
define pcodeop InstructionSynchronizationBarrier;
define pcodeop HintPreloadData;
define pcodeop HintPreloadDataForWrite;
define pcodeop HintPreloadInstruction;
define pcodeop SignedSaturate;
define pcodeop SignedDoesSaturate;
define pcodeop UnsignedSaturate;
define pcodeop UnsignedDoesSaturate;
define pcodeop Absolute;
define pcodeop ReverseBitOrder;
define pcodeop SendEvent;
define pcodeop setEndianState;
macro affectflags() {
CY = tmpCY; ZR = tmpZR; NG = tmpNG; OV = tmpOV;
}
macro affect_resflags() {
ZR = tmpZR; NG = tmpNG;
}
macro SetThumbMode(value) {
ISAModeSwitch = value;
TB = ISAModeSwitch;
}
#
# simple branch, not inter-working
macro BranchWritePC(addr) {
pc = addr;
}
#
# Interworking branch, ARM<->Thumb
macro BXWritePC(addr) {
SetThumbMode((addr & 0x1) != 0);
local tmp = addr & 0xfffffffe;
pc = tmp;
}
#
# Branch depends on version
macro LoadWritePC(addr) {
@if defined(VERSION_5)
BXWritePC(addr);
@else
BranchWritePC(addr);
@endif
}
# Branch depends on version
macro ALUWritePC(addr) {
@if defined(VERSION_7)
BXWritePC(addr);
@else
BranchWritePC(addr);
@endif
}
@if defined(T_VARIANT)
ItCond: is TMode=1 { }
CheckInIT_CZNO: is TMode=1 { CY = tmpCY; ZR = tmpZR; NG = tmpNG; OV = tmpOV; } # in older, arms always affect flags
CheckInIT_CZN: is TMode=1 { CY = tmpCY; ZR = tmpZR; NG = tmpNG; } # in older, arms always affect flags
CheckInIT_ZN: is TMode=1 { ZR = tmpZR; NG = tmpNG; } # in older, arms always affect flags
@endif
@if defined(VERSION_6T2) || defined(VERSION_7)
# conditionals for instruction following IT Block
thfcc: "eq" is cond_full=0 { local tmp:1 = (ZR!=0); export tmp; }
thfcc: "ne" is cond_full=1 { local tmp:1 = (ZR==0); export tmp; }
thfcc: "cs" is cond_full=2 { local tmp:1 = (CY!=0); export tmp; }
thfcc: "cc" is cond_full=3 { local tmp:1 = (CY==0); export tmp; }
thfcc: "mi" is cond_full=4 { local tmp:1 = (NG!=0); export tmp; }
thfcc: "pl" is cond_full=5 { local tmp:1 = (NG==0); export tmp; }
thfcc: "vs" is cond_full=6 { local tmp:1 = (OV!=0); export tmp; }
thfcc: "vc" is cond_full=7 { local tmp:1 = (OV==0); export tmp; }
thfcc: "hi" is cond_full=8 { local tmp:1 = CY && !ZR; export tmp; }
thfcc: "ls" is cond_full=9 { local tmp:1 = !CY || ZR; export tmp; }
thfcc: "ge" is cond_full=10 { local tmp:1 = (NG == OV); export tmp; }
thfcc: "lt" is cond_full=11 { local tmp:1 = (NG != OV); export tmp; }
thfcc: "gt" is cond_full=12 { local tmp:1 = !ZR && (NG == OV); export tmp; }
thfcc: "le" is cond_full=13 { local tmp:1 = ZR || (NG != OV); export tmp; }
thfcc: "al" is cond_full=14 { local tmp:1 = 1; export tmp; } #can happen
#thfcc: "nv" is cond_full=15 { local tmp:1 = 0; export tmp; } #unpredictable, shouldn't happen
# no ITcondition
ItCond: is TMode=1 & itmode=0 & cond_mask=0 {}
# ITBlock then/else case - the condition being tested is modified by the shift below
ItCond: "."thfcc is TMode=1 & itmode=0 & cond_mask & thfcc [ itmode=1; globalset(inst_next,condit);]
{ if (!thfcc) goto inst_next; }
# last ITBlock then/else case - the condition being tested is modified by the shift below
ItCond: "."thfcc is TMode=1 & itmode=0 & cond_mask=8 & thfcc
{ if (!thfcc) goto inst_next; }
# certain Thumb instructions don't affect all flags in the IT block
CheckInIT_CZNO: is TMode=1 & itmode=1 & cond_mask { } # Do nothing to the flag bits
CheckInIT_CZNO: is TMode=1 & itmode=0 & cond_mask { } # Do nothing to the flag bits
CheckInIT_CZNO: "s" is TMode=1 & itmode=0 & cond_mask=0 { CY = tmpCY; ZR = tmpZR; NG = tmpNG; OV = tmpOV; }
CheckInIT_CZN: is TMode=1 & itmode=1 & cond_mask { } # Do nothing to the flag bits
CheckInIT_CZN: is TMode=1 & itmode=0 & cond_mask { } # Do nothing to the flag bits
CheckInIT_CZN: "s" is TMode=1 & itmode=0 & cond_mask=0 { CY = tmpCY; ZR = tmpZR; NG = tmpNG; }
CheckInIT_ZN: is TMode=1 & itmode=1 & cond_mask { } # Do nothing to the flag bits
CheckInIT_ZN: is TMode=1 & itmode=0 & cond_mask { } # Do nothing to the flag bits
CheckInIT_ZN: "s" is TMode=1 & itmode=0 & cond_mask=0 { ZR = tmpZR; NG = tmpNG; }
:^instruction is itmode=1 & cond_mask=8 & instruction [ condit=0; ] {}
:^instruction is itmode=1 & cond_mask & instruction [ cond_shft=cond_shft << 1; itmode=0; ]{}
@endif # defined(VERSION_6T2) || defined(VERSION_7)
@include "ARMinstructions.sinc"
# THUMB instructions
@ifdef T_VARIANT
@include "ARMTHUMBinstructions.sinc"
@endif
# Specification for the ARM Version 4, 4T, 5, 5T, 5E
# The following boolean defines control specific support: T_VARIANT, VERSION_5, VERSION_5E
define endian=$(ENDIAN);
define alignment=2;
define space ram type=ram_space size=4 default;
define space register type=register_space size=4;
define register offset=0x0020 size=4 [ r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 sp lr pc ];
define register offset=0x0060 size=1 [ NG ZR CY OV tmpNG tmpZR tmpCY tmpOV shift_carry TB Q GE1 GE2 GE3 GE4 ];
define register offset=0x0070 size=4 [ cpsr spsr ];
define register offset=0x0080 size=4 [ mult_addr ]; # Special internal register for dealing with multiple stores/loads
define register offset=0x0084 size=4 [ r14_svc r13_svc spsr_svc ];
define register offset=0x0090 size=8 [ mult_dat8 ]; # Special internal register for dealing with multiple stores/loads
define register offset=0x0090 size=16 [ mult_dat16 ]; # Special internal register for dealing with multiple stores/loads
define register offset=0x00A0 size=4 [ fpsr ]; # floating point state register (for FPA10 floating-point accelerator)
define register offset=0x00B0 size=1 [ ISAModeSwitch ]; # generic name for TB ThumbBit - set same as TB
@define FPSCR_N "fpscr[31,1]"
@define FPSCR_Z "fpscr[30,1]"
@define FPSCR_C "fpscr[29,1]"
@define FPSCR_V "fpscr[28,1]"
@if defined(VFPv2) || defined(VFPv3) || defined(SIMD)
define register offset=0x00B0 size=4 [ fpsid fpscr fpexc mvfr0 mvfr1 ];
@endif
define register offset=0x0100 size=10 [ fp0 fp1 fp2 fp3 fp4 fp5 fp6 fp7 ]; # eight 80-bit floating registers
# pseudo-registers for coprocessor calculations
define register offset=0x0200 size=4 [ cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 cr8 cr9 cr10 cr11 cr12 cr13 cr14 cr15 ];
# Advanced SIMD and VFP extension registers
@if defined(VFPv2) || defined(VFPv3)
@if ENDIAN == "little"
define register offset=0x0300 size=4 [ s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15
s16 s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31 ];
@else # ENDIAN == "big"
define register offset=0x0300 size=4 [ s31 s30 s29 s28 s27 s26 s25 s24 s23 s22 s21 s20 s19 s18 s17 s16
s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 ];
@endif # ENDIAN = "big"
@endif # VFPv2 || VFPv3
@if defined(VFPv2)
@if ENDIAN == "little"
define register offset=0x0300 size=8 [ d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ];
@else # ENDIAN == "big"
define register offset=0x0300 size=8 [ d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ];
@endif # ENDIAN = "big"
@endif # VFPv2
@if defined(SIMD) || defined(VFPv3)
@if ENDIAN == "little"
define register offset=0x0300 size=8 [ d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15
d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 ];
@else # ENDIAN == "big"
define register offset=0x0300 size=8 [ d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16
d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ];
@endif # ENDIAN = "big"
@endif # SIMD || VFPv3
@if defined(SIMD)
@if ENDIAN == "little"
define register offset=0x0300 size=16 [ q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 ];
@else # ENDIAN == "big"
define register offset=0x0300 size=16 [ q15 q14 q13 q12 q11 q10 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 ];
@endif # ENDIAN = "big"
@endif # SIMD
# Define context bits
# WARNING: when adjusting context keep compiler packing in mind
# and make sure fields do not span a 32-bit boundary before or
# after context packing
define register offset=0x00 size=8 contextreg;
define context contextreg
@ifdef T_VARIANT
TMode = (0,0) # 1 if in Thumb instruction decode mode
T = (0,0) # exact copy (alias!) of TMode
LowBitCodeMode = (0,0) # 1 if low bit of instruction address is set on a branch
ISA_MODE = (0,0) # 1 for Thumb instruction decode mode
@endif
LRset = (1,1) noflow # 1 if the instruction right before was a mov lr,pc
REToverride = (2,2) noflow # 1 if the instruction should be a branch not a return
CALLoverride = (3,3) noflow # 1 if the call should actually be a jump
@if defined(VERSION_6T2) || defined(VERSION_7)
TEEMode = (4,4) # 1 if in ThumbEE mode, changes some instruction behavior, and makes some instructions invalid
condit = (5,13) noflow # both base and shift
cond_mask = (10,13) # base condition
cond_full = (6,9) # full condition
cond_true = (9,9) # true if this condition should be tested for true
cond_base = (6,8) # shift mask for controlling shift
cond_shft = (9,13) # mask and lower bit of it condition field
itmode = (5,5) # true if in ITBlock mode
@endif
# Transient context bits
counter = (14,18) # 0 to 7 counter (for building variable length register lists)
# dreg = (17,21) # D register (attached, for building register lists)
# sreg = (17,21) # S register (attached, for building register lists)
regNum = (19,23) # D register number (see dreg)
counter2 = (24,26) # 0 to 7 counter (for building variable length register lists)
# dreg2 = (25,29) # 2nd D register (attached, for building register lists)
# sreg2 = (25,29) # 2nd S register (attached, for building register lists)
reg2Num = (27,31) # 2nd D register number (see dreg2)
# --- do not allow any field to span 32-bit boundary ---
regInc = (32,33) # Pair register increment
ARMcond = (34,34) # ARM conditional instruction
ARMcondCk = (35,35) # Finished ARM condition check phase
;
define pcodeop coprocessor_function;
define pcodeop coprocessor_function2;
define pcodeop coprocessor_load;
define pcodeop coprocessor_load2;
define pcodeop coprocessor_loadlong;
define pcodeop coprocessor_loadlong2;
define pcodeop coprocessor_moveto;
define pcodeop coprocessor_moveto2;
define pcodeop coprocessor_movefromRt;
define pcodeop coprocessor_movefromRt2;
define pcodeop coprocessor_movefrom2;
define pcodeop coprocessor_store;
define pcodeop coprocessor_store2;
define pcodeop coprocessor_storelong;
define pcodeop coprocessor_storelong2;
define pcodeop software_interrupt;
define pcodeop software_bkpt;
define pcodeop software_udf;
define pcodeop software_hlt;
define pcodeop software_hvc;
define pcodeop software_smc;
# CPS methods (Version 6)
define pcodeop setUserMode;
define pcodeop setFIQMode;
define pcodeop setIRQMode;
define pcodeop setSupervisorMode;
define pcodeop setMonitorMode;
define pcodeop setAbortMode;
define pcodeop setUndefinedMode;
define pcodeop setSystemMode;
define pcodeop enableIRQinterrupts;
define pcodeop enableFIQinterrupts;
define pcodeop enableDataAbortInterrupts;
define pcodeop disableIRQinterrupts;
define pcodeop disableFIQinterrupts;
define pcodeop isFIQinterruptsEnabled;
define pcodeop isIRQinterruptsEnabled;
define pcodeop disableDataAbortInterrupts;
define pcodeop hasExclusiveAccess;
define pcodeop isCurrentModePrivileged;
define pcodeop setThreadModePrivileged;
define pcodeop isThreadMode;
define pcodeop jazelle_branch;
define pcodeop ClearExclusiveLocal;
define pcodeop HintDebug;
define pcodeop DataMemoryBarrier;
define pcodeop DataSynchronizationBarrier;
define pcodeop secureMonitorCall;
define pcodeop WaitForEvent;
define pcodeop WaitForInterrupt;
define pcodeop HintYield;
define pcodeop InstructionSynchronizationBarrier;
define pcodeop HintPreloadData;
define pcodeop HintPreloadDataForWrite;
define pcodeop HintPreloadInstruction;
define pcodeop SignedSaturate;
define pcodeop SignedDoesSaturate;
define pcodeop UnsignedSaturate;
define pcodeop UnsignedDoesSaturate;
define pcodeop Absolute;
define pcodeop ReverseBitOrder;
define pcodeop SendEvent;
define pcodeop setEndianState;
macro affectflags() {
CY = tmpCY; ZR = tmpZR; NG = tmpNG; OV = tmpOV;
}
macro affect_resflags() {
ZR = tmpZR; NG = tmpNG;
}
macro SetThumbMode(value) {
ISAModeSwitch = value;
TB = ISAModeSwitch;
}
#
# simple branch, not inter-working
macro BranchWritePC(addr) {
pc = addr;
}
#
# Interworking branch, ARM<->Thumb
macro BXWritePC(addr) {
SetThumbMode((addr & 0x1) != 0);
local tmp = addr & 0xfffffffe;
pc = tmp;
}
#
# Branch depends on version
macro LoadWritePC(addr) {
@if defined(VERSION_5)
BXWritePC(addr);
@else
BranchWritePC(addr);
@endif
}
# Branch depends on version
macro ALUWritePC(addr) {
@if defined(VERSION_7)
BXWritePC(addr);
@else
BranchWritePC(addr);
@endif
}
@if defined(T_VARIANT)
ItCond: is TMode=1 { }
CheckInIT_CZNO: is TMode=1 { CY = tmpCY; ZR = tmpZR; NG = tmpNG; OV = tmpOV; } # in older, arms always affect flags
CheckInIT_CZN: is TMode=1 { CY = tmpCY; ZR = tmpZR; NG = tmpNG; } # in older, arms always affect flags
CheckInIT_ZN: is TMode=1 { ZR = tmpZR; NG = tmpNG; } # in older, arms always affect flags
@endif
@if defined(VERSION_6T2) || defined(VERSION_7)
# conditionals for instruction following IT Block
thfcc: "eq" is cond_full=0 { local tmp:1 = (ZR!=0); export tmp; }
thfcc: "ne" is cond_full=1 { local tmp:1 = (ZR==0); export tmp; }
thfcc: "cs" is cond_full=2 { local tmp:1 = (CY!=0); export tmp; }
thfcc: "cc" is cond_full=3 { local tmp:1 = (CY==0); export tmp; }
thfcc: "mi" is cond_full=4 { local tmp:1 = (NG!=0); export tmp; }
thfcc: "pl" is cond_full=5 { local tmp:1 = (NG==0); export tmp; }
thfcc: "vs" is cond_full=6 { local tmp:1 = (OV!=0); export tmp; }
thfcc: "vc" is cond_full=7 { local tmp:1 = (OV==0); export tmp; }
thfcc: "hi" is cond_full=8 { local tmp:1 = CY && !ZR; export tmp; }
thfcc: "ls" is cond_full=9 { local tmp:1 = !CY || ZR; export tmp; }
thfcc: "ge" is cond_full=10 { local tmp:1 = (NG == OV); export tmp; }
thfcc: "lt" is cond_full=11 { local tmp:1 = (NG != OV); export tmp; }
thfcc: "gt" is cond_full=12 { local tmp:1 = !ZR && (NG == OV); export tmp; }
thfcc: "le" is cond_full=13 { local tmp:1 = ZR || (NG != OV); export tmp; }
thfcc: "al" is cond_full=14 { local tmp:1 = 1; export tmp; } #can happen
#thfcc: "nv" is cond_full=15 { local tmp:1 = 0; export tmp; } #unpredictable, shouldn't happen
# no ITcondition
ItCond: is TMode=1 & itmode=0 & cond_mask=0 {}
# ITBlock then/else case - the condition being tested is modified by the shift below
ItCond: "."thfcc is TMode=1 & itmode=0 & cond_mask & thfcc [ itmode=1; globalset(inst_next,condit);]
{ if (!thfcc) goto inst_next; }
# last ITBlock then/else case - the condition being tested is modified by the shift below
ItCond: "."thfcc is TMode=1 & itmode=0 & cond_mask=8 & thfcc
{ if (!thfcc) goto inst_next; }
# certain Thumb instructions don't affect all flags in the IT block
CheckInIT_CZNO: is TMode=1 & itmode=1 & cond_mask { } # Do nothing to the flag bits
CheckInIT_CZNO: is TMode=1 & itmode=0 & cond_mask { } # Do nothing to the flag bits
CheckInIT_CZNO: "s" is TMode=1 & itmode=0 & cond_mask=0 { CY = tmpCY; ZR = tmpZR; NG = tmpNG; OV = tmpOV; }
CheckInIT_CZN: is TMode=1 & itmode=1 & cond_mask { } # Do nothing to the flag bits
CheckInIT_CZN: is TMode=1 & itmode=0 & cond_mask { } # Do nothing to the flag bits
CheckInIT_CZN: "s" is TMode=1 & itmode=0 & cond_mask=0 { CY = tmpCY; ZR = tmpZR; NG = tmpNG; }
CheckInIT_ZN: is TMode=1 & itmode=1 & cond_mask { } # Do nothing to the flag bits
CheckInIT_ZN: is TMode=1 & itmode=0 & cond_mask { } # Do nothing to the flag bits
CheckInIT_ZN: "s" is TMode=1 & itmode=0 & cond_mask=0 { ZR = tmpZR; NG = tmpNG; }
:^instruction is itmode=1 & cond_mask=8 & instruction [ condit=0; ] {}
:^instruction is itmode=1 & cond_mask & instruction [ cond_shft=cond_shft << 1; itmode=0; ]{}
@endif # defined(VERSION_6T2) || defined(VERSION_7)
@include "ARMinstructions.sinc"
# THUMB instructions
@ifdef T_VARIANT
@include "ARMTHUMBinstructions.sinc"
@endif
python/icicle/Ghidra/Processors/ARM/data/languages/ARM4_be.slaspec
+5 -5
View File
@@ -1,5 +1,5 @@
@define ENDIAN "big"
@include "ARM.sinc"
@define ENDIAN "big"
@include "ARM.sinc"
python/icicle/Ghidra/Processors/ARM/data/languages/ARM4_le.slaspec
+5 -5
View File
@@ -1,5 +1,5 @@
@define ENDIAN "little"
@include "ARM.sinc"
@define ENDIAN "little"
@include "ARM.sinc"
python/icicle/Ghidra/Processors/ARM/data/languages/ARM4t_be.slaspec
+6 -6
View File
@@ -1,6 +1,6 @@
@define ENDIAN "big"
@define T_VARIANT ""
@include "ARM.sinc"
@define ENDIAN "big"
@define T_VARIANT ""
@include "ARM.sinc"
python/icicle/Ghidra/Processors/ARM/data/languages/ARM4t_le.slaspec
+6 -6
View File
@@ -1,6 +1,6 @@
@define ENDIAN "little"
@define T_VARIANT ""
@include "ARM.sinc"
@define ENDIAN "little"
@define T_VARIANT ""
@include "ARM.sinc"
python/icicle/Ghidra/Processors/ARM/data/languages/ARM5_be.slaspec
+7 -7
View File
@@ -1,7 +1,7 @@
@define ENDIAN "big"
@define VERSION_5 ""
@define VERSION_5E ""
@include "ARM.sinc"
@define ENDIAN "big"
@define VERSION_5 ""
@define VERSION_5E ""
@include "ARM.sinc"
python/icicle/Ghidra/Processors/ARM/data/languages/ARM5_le.slaspec
+7 -7
View File
@@ -1,7 +1,7 @@
@define ENDIAN "little"
@define VERSION_5 ""
@define VERSION_5E ""
@include "ARM.sinc"
@define ENDIAN "little"
@define VERSION_5 ""
@define VERSION_5E ""
@include "ARM.sinc"
python/icicle/Ghidra/Processors/ARM/data/languages/ARM5t_be.slaspec
+9 -9
View File
@@ -1,9 +1,9 @@
@define ENDIAN "big"
@define T_VARIANT ""
@define VERSION_5 ""
@define VERSION_5E ""
@include "ARM.sinc"
@define ENDIAN "big"
@define T_VARIANT ""
@define VERSION_5 ""
@define VERSION_5E ""
@include "ARM.sinc"
python/icicle/Ghidra/Processors/ARM/data/languages/ARM5t_le.slaspec
+8 -8
View File
@@ -1,8 +1,8 @@
@define ENDIAN "little"
@define T_VARIANT ""
@define VERSION_5 ""
@define VERSION_5E ""
@include "ARM.sinc"
@define ENDIAN "little"
@define T_VARIANT ""
@define VERSION_5 ""
@define VERSION_5E ""
@include "ARM.sinc"
python/icicle/Ghidra/Processors/ARM/data/languages/ARM6_be.slaspec
+12 -12
View File
@@ -1,12 +1,12 @@
@define ENDIAN "big"
@define T_VARIANT ""
@define VERSION_5 ""
@define VERSION_5E ""
@define VERSION_6 ""
@define VERSION_6K ""
@define VERSION_6T2 ""
@define VFPv2 ""
@include "ARM.sinc"
@define ENDIAN "big"
@define T_VARIANT ""
@define VERSION_5 ""
@define VERSION_5E ""
@define VERSION_6 ""
@define VERSION_6K ""
@define VERSION_6T2 ""
@define VFPv2 ""
@include "ARM.sinc"
python/icicle/Ghidra/Processors/ARM/data/languages/ARM6_le.slaspec
+12 -12
View File
@@ -1,12 +1,12 @@
@define ENDIAN "little"
@define T_VARIANT ""
@define VERSION_5 ""
@define VERSION_5E ""
@define VERSION_6 ""
@define VERSION_6K ""
@define VERSION_6T2 ""
@define VFPv2 ""
@include "ARM.sinc"
@define ENDIAN "little"
@define T_VARIANT ""
@define VERSION_5 ""
@define VERSION_5E ""
@define VERSION_6 ""
@define VERSION_6K ""
@define VERSION_6T2 ""
@define VFPv2 ""
@include "ARM.sinc"
python/icicle/Ghidra/Processors/ARM/data/languages/ARM7_be.slaspec
+16 -16
View File
@@ -1,16 +1,16 @@
@define ENDIAN "big"
@define T_VARIANT ""
@define VERSION_5 ""
@define VERSION_5E ""
@define VERSION_6 ""
@define VERSION_6K ""
@define VERSION_6T2 ""
@define VERSION_7 ""
@define VERSION_7M ""
@define SIMD ""
@define VFPv3 ""
@define VFPv4 ""
@include "ARM.sinc"
@define ENDIAN "big"
@define T_VARIANT ""
@define VERSION_5 ""
@define VERSION_5E ""
@define VERSION_6 ""
@define VERSION_6K ""
@define VERSION_6T2 ""
@define VERSION_7 ""
@define VERSION_7M ""
@define SIMD ""
@define VFPv3 ""
@define VFPv4 ""
@include "ARM.sinc"
python/icicle/Ghidra/Processors/ARM/data/languages/ARM7_le.slaspec
+16 -16
View File
@@ -1,16 +1,16 @@
@define ENDIAN "little"
@define T_VARIANT ""
@define VERSION_5 ""
@define VERSION_5E ""
@define VERSION_6 ""
@define VERSION_6K ""
@define VERSION_6T2 ""
@define VERSION_7 ""
@define VERSION_7M ""
@define SIMD ""
@define VFPv3 ""
@define VFPv4 ""
@include "ARM.sinc"
@define ENDIAN "little"
@define T_VARIANT ""
@define VERSION_5 ""
@define VERSION_5E ""
@define VERSION_6 ""
@define VERSION_6K ""
@define VERSION_6T2 ""
@define VERSION_7 ""
@define VERSION_7M ""
@define SIMD ""
@define VFPv3 ""
@define VFPv4 ""
@include "ARM.sinc"
python/icicle/Ghidra/Processors/ARM/data/languages/ARM8_be.slaspec
+17 -17
View File
@@ -1,17 +1,17 @@
@define ENDIAN "big"
@define T_VARIANT ""
@define VERSION_5 ""
@define VERSION_5E ""
@define VERSION_6 ""
@define VERSION_6K ""
@define VERSION_6T2 ""
@define VERSION_7 ""
@define VERSION_7M ""
@define VERSION_8 ""
@define SIMD ""
@define VFPv3 ""
@define VFPv4 ""
@include "ARM.sinc"
@define ENDIAN "big"
@define T_VARIANT ""
@define VERSION_5 ""
@define VERSION_5E ""
@define VERSION_6 ""
@define VERSION_6K ""
@define VERSION_6T2 ""
@define VERSION_7 ""
@define VERSION_7M ""
@define VERSION_8 ""
@define SIMD ""
@define VFPv3 ""
@define VFPv4 ""
@include "ARM.sinc"
python/icicle/Ghidra/Processors/ARM/data/languages/ARM8_le.slaspec
+17 -17
View File
@@ -1,17 +1,17 @@
@define ENDIAN "little"
@define T_VARIANT ""
@define VERSION_5 ""
@define VERSION_5E ""
@define VERSION_6 ""
@define VERSION_6K ""
@define VERSION_6T2 ""
@define VERSION_7 ""
@define VERSION_7M ""
@define VERSION_8 ""
@define SIMD ""
@define VFPv3 ""
@define VFPv4 ""
@include "ARM.sinc"
@define ENDIAN "little"
@define T_VARIANT ""
@define VERSION_5 ""
@define VERSION_5E ""
@define VERSION_6 ""
@define VERSION_6K ""
@define VERSION_6T2 ""
@define VERSION_7 ""
@define VERSION_7M ""
@define VERSION_8 ""
@define SIMD ""
@define VFPv3 ""
@define VFPv4 ""
@include "ARM.sinc"
python/icicle/Ghidra/Processors/ARM/data/languages/ARMCortex.pspec
+42 -42
View File
@@ -1,42 +1,42 @@
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<properties>
<property key="addressesDoNotAppearDirectlyInCode" value="true"/>
<property key="allowOffcutReferencesToFunctionStarts" value="true"/>
<property key="useNewFunctionStackAnalysis" value="true"/>
<property key="enableContiguousFunctionsOnly" value="false"/>
<property key="emulateInstructionStateModifierClass" value="ghidra.program.emulation.ARMEmulateInstructionStateModifier"/>
</properties>
<programcounter register="pc"/>
<context_data>
<context_set space="ram">
<set name="TMode" val="1" description="0 for ARM 32-bit, 1 for THUMB 16-bit"/>
<set name="LRset" val="0" description="0 lr reg not set, 1 for LR set, affects BX as a call"/>
</context_set>
<tracked_set space="ram">
<set name="spsr" val="0"/>
</tracked_set>
</context_data>
<default_symbols>
<symbol name="MasterStackPointer" address="ram:0x0" entry="false" type="code_ptr"/>
<symbol name="Reset" address="ram:0x4" entry="true" type="code_ptr"/>
<symbol name="NMI" address="ram:0x8" entry="true" type="code_ptr"/>
<symbol name="HardFault" address="ram:0xC" entry="true" type="code_ptr"/>
<symbol name="MemManage" address="ram:0x10" entry="true" type="code_ptr"/>
<symbol name="BusFault" address="ram:0x14" entry="true" type="code_ptr"/>
<symbol name="UsageFault" address="ram:0x18" entry="true" type="code_ptr"/>
<symbol name="Reserved1" address="ram:0x1c" entry="true" type="code_ptr"/>
<symbol name="Reserved2" address="ram:0x20" entry="true" type="code_ptr"/>
<symbol name="Reserved3" address="ram:0x24" entry="true" type="code_ptr"/>
<symbol name="Reserved4" address="ram:0x28" entry="true" type="code_ptr"/>
<symbol name="SVCall" address="ram:0x2c" entry="true" type="code_ptr"/>
<symbol name="Reserved5" address="ram:0x30" entry="true" type="code_ptr"/>
<symbol name="Reserved6" address="ram:0x34" entry="true" type="code_ptr"/>
<symbol name="PendSV" address="ram:0x38" entry="true" type="code_ptr"/>
<symbol name="SysTick" address="ram:0x3C" entry="true" type="code_ptr"/>
<symbol name="IRQ" address="ram:0x40" entry="true" type="code_ptr"/>
</default_symbols>
</processor_spec>
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<properties>
<property key="addressesDoNotAppearDirectlyInCode" value="true"/>
<property key="allowOffcutReferencesToFunctionStarts" value="true"/>
<property key="useNewFunctionStackAnalysis" value="true"/>
<property key="enableContiguousFunctionsOnly" value="false"/>
<property key="emulateInstructionStateModifierClass" value="ghidra.program.emulation.ARMEmulateInstructionStateModifier"/>
</properties>
<programcounter register="pc"/>
<context_data>
<context_set space="ram">
<set name="TMode" val="1" description="0 for ARM 32-bit, 1 for THUMB 16-bit"/>
<set name="LRset" val="0" description="0 lr reg not set, 1 for LR set, affects BX as a call"/>
</context_set>
<tracked_set space="ram">
<set name="spsr" val="0"/>
</tracked_set>
</context_data>
<default_symbols>
<symbol name="MasterStackPointer" address="ram:0x0" entry="false" type="code_ptr"/>
<symbol name="Reset" address="ram:0x4" entry="true" type="code_ptr"/>
<symbol name="NMI" address="ram:0x8" entry="true" type="code_ptr"/>
<symbol name="HardFault" address="ram:0xC" entry="true" type="code_ptr"/>
<symbol name="MemManage" address="ram:0x10" entry="true" type="code_ptr"/>
<symbol name="BusFault" address="ram:0x14" entry="true" type="code_ptr"/>
<symbol name="UsageFault" address="ram:0x18" entry="true" type="code_ptr"/>
<symbol name="Reserved1" address="ram:0x1c" entry="true" type="code_ptr"/>
<symbol name="Reserved2" address="ram:0x20" entry="true" type="code_ptr"/>
<symbol name="Reserved3" address="ram:0x24" entry="true" type="code_ptr"/>
<symbol name="Reserved4" address="ram:0x28" entry="true" type="code_ptr"/>
<symbol name="SVCall" address="ram:0x2c" entry="true" type="code_ptr"/>
<symbol name="Reserved5" address="ram:0x30" entry="true" type="code_ptr"/>
<symbol name="Reserved6" address="ram:0x34" entry="true" type="code_ptr"/>
<symbol name="PendSV" address="ram:0x38" entry="true" type="code_ptr"/>
<symbol name="SysTick" address="ram:0x3C" entry="true" type="code_ptr"/>
<symbol name="IRQ" address="ram:0x40" entry="true" type="code_ptr"/>
</default_symbols>
</processor_spec>
python/icicle/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc
+5330 -5330
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python/icicle/Ghidra/Processors/ARM/data/languages/ARM_v45.cspec
+209 -209
View File
@@ -1,209 +1,209 @@
<?xml version="1.0" encoding="UTF-8"?>
<!--
This arm cspec split from the main arm.cspec.
The difference is no floating point registers for
older arm variants (pre-v7)
-->
<compiler_spec>
<!--
Assumes Procedure Call Standard for the ARM Architecture (AAPCS) Applies.
-->
<data_organization> <!-- These tags were generated with gcc 4.2.4 -->
<absolute_max_alignment value="0" />
<machine_alignment value="2" />
<default_alignment value="1" />
<default_pointer_alignment value="4" />
<pointer_size value="4" />
<wchar_size value="4" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="8" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="8" />
</size_alignment_map>
</data_organization>
<global>
<range space="ram"/>
</global>
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/> <!-- Function pointers are word aligned and leastsig bit may encode otherstuff -->
<default_proto>
<prototype name="__stdcall" extrapop="0" stackshift="0">
<input>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r0"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r1"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r2"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r3"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="0" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r0"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="r1" piece2="r0"/>
</pentry>
</output>
<unaffected>
<register name="r4"/>
<register name="r5"/>
<register name="r6"/>
<register name="r7"/>
<register name="r8"/>
<register name="r9"/>
<register name="r10"/>
<register name="r11"/>
<register name="sp"/>
</unaffected>
<killedbycall>
<register name="r1"/>
</killedbycall>
</prototype>
</default_proto>
<callfixup name="switch8_r3">
<target name="switch8_r3"/>
<pcode>
<body><![CDATA[
tmpptr = lr - 1;
tblsize = *:1 tmpptr;
r12 = zext(tblsize);
inbounds = r3 < r12;
if (!inbounds) goto <next1>;
offset = *:1 (lr + r3);
r3 = zext(offset);
<next1>
if (inbounds) goto <next2>;
offset = *:1 (lr + r12);
r3 = zext(offset);
<next2>
r3 = r3 * 2;
r12 = lr + r3;
ISAModeSwitch = (r12 & 1) != 1;
TB = ISAModeSwitch;
pc = r12 & 0xfffffffe;
goto [pc];
]]></body>
</pcode>
</callfixup>
<callfixup name="switch8_r0">
<target name="__gnu_thumb1_case_uqi"/>
<target name="switch8_r0"/>
<pcode>
<body><![CDATA[
tmpptr = lr & 0xfffffffe;
offset = *:1 (tmpptr + r0);
lr = lr + 2 * zext(offset);
ISAModeSwitch = (lr & 1) != 0;
TB = ISAModeSwitch;
pc = lr & 0xfffffffe;
goto [pc];
]]></body>
</pcode>
</callfixup>
<callfixup name="switchS8_r0">
<target name="__gnu_thumb1_case_sqi"/>
<target name="switchS8_r0"/>
<pcode>
<body><![CDATA[
tmpptr = lr & 0xfffffffe;
offset = *:1 (tmpptr + r0);
lr = lr + 2 * sext(offset);
ISAModeSwitch = (lr & 1) != 0;
TB = ISAModeSwitch;
pc = lr & 0xfffffffe;
goto [pc];
]]></body>
</pcode>
</callfixup>
<callfixup name="switch16_shi_r0">
<target name="__gnu_thumb1_case_shi"/>
<target name="switch16_shi_r0"/>
<pcode>
<body><![CDATA[
tmpptr = lr & 0xfffffffe;
index = r0 * 2;
offset = *:2 (tmpptr + index);
lr = lr + 2 * sext(offset);
ISAModeSwitch = (lr & 1) != 0;
TB = ISAModeSwitch;
pc = lr & 0xfffffffe;
goto [pc];
]]></body>
</pcode>
</callfixup>
<callfixup name="switch16_uhi_r0">
<target name="__gnu_thumb1_case_uhi"/>
<target name="switch16_shi_r0"/>
<pcode>
<body><![CDATA[
tmpptr = lr & 0xfffffffe;
index = r0 * 2;
offset = *:2 (tmpptr + index);
lr = lr + 2 * zext(offset);
ISAModeSwitch = (lr & 1) != 0;
TB = ISAModeSwitch;
pc = lr & 0xfffffffe;
goto [pc];
]]></body>
</pcode>
</callfixup>
<callfixup name="switch32_si_r0">
<target name="__gnu_thumb1_case_si"/>
<target name="switch32_si_r0"/>
<pcode>
<body><![CDATA[
tmpptr = (lr + 2) & 0xfffffffc;
index = r0 * 4;
offset = *:4 (tmpptr + index);
offset = offset * 4;
lr = lr + offset;
ISAModeSwitch = (lr & 1) != 0;
TB = ISAModeSwitch;
pc = lr & 0xfffffffe;
goto [pc];
]]></body>
</pcode>
</callfixup>
</compiler_spec>
<?xml version="1.0" encoding="UTF-8"?>
<!--
This arm cspec split from the main arm.cspec.
The difference is no floating point registers for
older arm variants (pre-v7)
-->
<compiler_spec>
<!--
Assumes Procedure Call Standard for the ARM Architecture (AAPCS) Applies.
-->
<data_organization> <!-- These tags were generated with gcc 4.2.4 -->
<absolute_max_alignment value="0" />
<machine_alignment value="2" />
<default_alignment value="1" />
<default_pointer_alignment value="4" />
<pointer_size value="4" />
<wchar_size value="4" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="8" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="8" />
</size_alignment_map>
</data_organization>
<global>
<range space="ram"/>
</global>
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/> <!-- Function pointers are word aligned and leastsig bit may encode otherstuff -->
<default_proto>
<prototype name="__stdcall" extrapop="0" stackshift="0">
<input>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r0"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r1"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r2"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r3"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="0" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r0"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="r1" piece2="r0"/>
</pentry>
</output>
<unaffected>
<register name="r4"/>
<register name="r5"/>
<register name="r6"/>
<register name="r7"/>
<register name="r8"/>
<register name="r9"/>
<register name="r10"/>
<register name="r11"/>
<register name="sp"/>
</unaffected>
<killedbycall>
<register name="r1"/>
</killedbycall>
</prototype>
</default_proto>
<callfixup name="switch8_r3">
<target name="switch8_r3"/>
<pcode>
<body><![CDATA[
tmpptr = lr - 1;
tblsize = *:1 tmpptr;
r12 = zext(tblsize);
inbounds = r3 < r12;
if (!inbounds) goto <next1>;
offset = *:1 (lr + r3);
r3 = zext(offset);
<next1>
if (inbounds) goto <next2>;
offset = *:1 (lr + r12);
r3 = zext(offset);
<next2>
r3 = r3 * 2;
r12 = lr + r3;
ISAModeSwitch = (r12 & 1) != 1;
TB = ISAModeSwitch;
pc = r12 & 0xfffffffe;
goto [pc];
]]></body>
</pcode>
</callfixup>
<callfixup name="switch8_r0">
<target name="__gnu_thumb1_case_uqi"/>
<target name="switch8_r0"/>
<pcode>
<body><![CDATA[
tmpptr = lr & 0xfffffffe;
offset = *:1 (tmpptr + r0);
lr = lr + 2 * zext(offset);
ISAModeSwitch = (lr & 1) != 0;
TB = ISAModeSwitch;
pc = lr & 0xfffffffe;
goto [pc];
]]></body>
</pcode>
</callfixup>
<callfixup name="switchS8_r0">
<target name="__gnu_thumb1_case_sqi"/>
<target name="switchS8_r0"/>
<pcode>
<body><![CDATA[
tmpptr = lr & 0xfffffffe;
offset = *:1 (tmpptr + r0);
lr = lr + 2 * sext(offset);
ISAModeSwitch = (lr & 1) != 0;
TB = ISAModeSwitch;
pc = lr & 0xfffffffe;
goto [pc];
]]></body>
</pcode>
</callfixup>
<callfixup name="switch16_shi_r0">
<target name="__gnu_thumb1_case_shi"/>
<target name="switch16_shi_r0"/>
<pcode>
<body><![CDATA[
tmpptr = lr & 0xfffffffe;
index = r0 * 2;
offset = *:2 (tmpptr + index);
lr = lr + 2 * sext(offset);
ISAModeSwitch = (lr & 1) != 0;
TB = ISAModeSwitch;
pc = lr & 0xfffffffe;
goto [pc];
]]></body>
</pcode>
</callfixup>
<callfixup name="switch16_uhi_r0">
<target name="__gnu_thumb1_case_uhi"/>
<target name="switch16_shi_r0"/>
<pcode>
<body><![CDATA[
tmpptr = lr & 0xfffffffe;
index = r0 * 2;
offset = *:2 (tmpptr + index);
lr = lr + 2 * zext(offset);
ISAModeSwitch = (lr & 1) != 0;
TB = ISAModeSwitch;
pc = lr & 0xfffffffe;
goto [pc];
]]></body>
</pcode>
</callfixup>
<callfixup name="switch32_si_r0">
<target name="__gnu_thumb1_case_si"/>
<target name="switch32_si_r0"/>
<pcode>
<body><![CDATA[
tmpptr = (lr + 2) & 0xfffffffc;
index = r0 * 4;
offset = *:4 (tmpptr + index);
offset = offset * 4;
lr = lr + offset;
ISAModeSwitch = (lr & 1) != 0;
TB = ISAModeSwitch;
pc = lr & 0xfffffffe;
goto [pc];
]]></body>
</pcode>
</callfixup>
</compiler_spec>
python/icicle/Ghidra/Processors/ARM/data/languages/ARM_v45.pspec
+40 -40
View File
@@ -1,40 +1,40 @@
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<properties>
<property key="addressesDoNotAppearDirectlyInCode" value="true"/>
<property key="allowOffcutReferencesToFunctionStarts" value="true"/>
<property key="useNewFunctionStackAnalysis" value="true"/>
<property key="enableSharedReturnAnalysis" value="false"/>
<property key="enableContiguousFunctionsOnly" value="false"/>
<property key="emulateInstructionStateModifierClass" value="ghidra.program.emulation.ARMEmulateInstructionStateModifier"/>
</properties>
<programcounter register="pc"/>
<context_data>
<context_set space="ram">
<set name="LRset" val="0" description="0 lr reg not set, 1 for LR set, affects BX as a call"/>
</context_set>
<tracked_set space="ram">
<set name="spsr" val="0"/>
</tracked_set>
</context_data>
<default_symbols>
<symbol name="Reset" address="ram:0x0" entry="true"/>
<symbol name="UndefinedInstruction" address="ram:0x4" entry="true"/>
<symbol name="SupervisorCall" address="ram:0x8" entry="true"/>
<symbol name="PrefetchAbort" address="ram:0xC" entry="true"/>
<symbol name="DataAbort" address="ram:0x10" entry="true"/>
<symbol name="IRQ" address="ram:0x18" entry="true"/>
<symbol name="FIQ" address="ram:0x1c" entry="true"/>
<symbol name="H_Reset" address="ram:0xFFFF0000" entry="true"/>
<symbol name="H_UndefinedInstruction" address="ram:0xFFFF0004" entry="true"/>
<symbol name="H_SupervisorCall" address="ram:0xFFFF0008" entry="true"/>
<symbol name="H_PrefetchAbort" address="ram:0xFFFF000C" entry="true"/>
<symbol name="H_DataAbort" address="ram:0xFFFF0010" entry="true"/>
<symbol name="H_IRQ" address="ram:0xFFFF0018" entry="true"/>
<symbol name="H_FIQ" address="ram:0xFFFF001c" entry="true"/>
</default_symbols>
</processor_spec>
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<properties>
<property key="addressesDoNotAppearDirectlyInCode" value="true"/>
<property key="allowOffcutReferencesToFunctionStarts" value="true"/>
<property key="useNewFunctionStackAnalysis" value="true"/>
<property key="enableSharedReturnAnalysis" value="false"/>
<property key="enableContiguousFunctionsOnly" value="false"/>
<property key="emulateInstructionStateModifierClass" value="ghidra.program.emulation.ARMEmulateInstructionStateModifier"/>
</properties>
<programcounter register="pc"/>
<context_data>
<context_set space="ram">
<set name="LRset" val="0" description="0 lr reg not set, 1 for LR set, affects BX as a call"/>
</context_set>
<tracked_set space="ram">
<set name="spsr" val="0"/>
</tracked_set>
</context_data>
<default_symbols>
<symbol name="Reset" address="ram:0x0" entry="true"/>
<symbol name="UndefinedInstruction" address="ram:0x4" entry="true"/>
<symbol name="SupervisorCall" address="ram:0x8" entry="true"/>
<symbol name="PrefetchAbort" address="ram:0xC" entry="true"/>
<symbol name="DataAbort" address="ram:0x10" entry="true"/>
<symbol name="IRQ" address="ram:0x18" entry="true"/>
<symbol name="FIQ" address="ram:0x1c" entry="true"/>
<symbol name="H_Reset" address="ram:0xFFFF0000" entry="true"/>
<symbol name="H_UndefinedInstruction" address="ram:0xFFFF0004" entry="true"/>
<symbol name="H_SupervisorCall" address="ram:0xFFFF0008" entry="true"/>
<symbol name="H_PrefetchAbort" address="ram:0xFFFF000C" entry="true"/>
<symbol name="H_DataAbort" address="ram:0xFFFF0010" entry="true"/>
<symbol name="H_IRQ" address="ram:0xFFFF0018" entry="true"/>
<symbol name="H_FIQ" address="ram:0xFFFF001c" entry="true"/>
</default_symbols>
</processor_spec>
python/icicle/Ghidra/Processors/ARM/data/languages/ARM_win.cspec
+131 -131
View File
@@ -1,131 +1,131 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<!-- Copied from ARM.cspec and modified... See: https://docs.microsoft.com/en-us/cpp/build/overview-of-arm-abi-conventions?view=vs-2019 -->
<data_organization>
<absolute_max_alignment value="0" />
<machine_alignment value="2" />
<default_alignment value="1" />
<default_pointer_alignment value="4" />
<pointer_size value="4" />
<wchar_size value="2" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="8" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="8" />
</size_alignment_map>
<bitfield_packing>
<use_MS_convention value="true"/>
</bitfield_packing>
</data_organization>
<global>
<range space="ram"/>
</global>
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/> <!-- Function pointers are word aligned and leastsig bit may encode otherstuff -->
<default_proto>
<prototype name="__stdcall" extrapop="0" stackshift="0">
<input>
<!-- we cannot accurately model the allocation scheme when parameters are larger than 4 bytes -->
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s0"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s1"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s2"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s3"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s4"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s5"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s6"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s7"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r0"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r1"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r2"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r3"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="0" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="16" metatype="float">
<register name="q0"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r0"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="r1" piece2="r0"/>
</pentry>
</output>
<unaffected>
<register name="r4"/>
<register name="r5"/>
<register name="r6"/>
<register name="r7"/>
<register name="r8"/>
<register name="r9"/>
<register name="r10"/>
<register name="r11"/>
<register name="q4"/>
<register name="q5"/>
<register name="q6"/>
<register name="q7"/>
<register name="sp"/>
<register name="lr"/>
<register name="pc"/>
</unaffected>
<killedbycall>
<register name="r0"/>
<register name="r1"/>
<register name="r2"/>
<register name="r3"/>
<register name="r12"/>
<register name="q0"/>
<register name="q1"/>
<register name="q2"/>
<register name="q3"/>
<register name="q8"/>
<register name="q9"/>
<register name="q10"/>
<register name="q11"/>
<register name="q12"/>
<register name="q13"/>
<register name="q14"/>
<register name="q15"/>
</killedbycall>
</prototype>
</default_proto>
</compiler_spec>
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<!-- Copied from ARM.cspec and modified... See: https://docs.microsoft.com/en-us/cpp/build/overview-of-arm-abi-conventions?view=vs-2019 -->
<data_organization>
<absolute_max_alignment value="0" />
<machine_alignment value="2" />
<default_alignment value="1" />
<default_pointer_alignment value="4" />
<pointer_size value="4" />
<wchar_size value="2" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="8" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="8" />
</size_alignment_map>
<bitfield_packing>
<use_MS_convention value="true"/>
</bitfield_packing>
</data_organization>
<global>
<range space="ram"/>
</global>
<stackpointer register="sp" space="ram"/>
<funcptr align="2"/> <!-- Function pointers are word aligned and leastsig bit may encode otherstuff -->
<default_proto>
<prototype name="__stdcall" extrapop="0" stackshift="0">
<input>
<!-- we cannot accurately model the allocation scheme when parameters are larger than 4 bytes -->
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s0"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s1"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s2"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s3"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s4"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s5"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s6"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="s7"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r0"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r1"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r2"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r3"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="0" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="16" metatype="float">
<register name="q0"/>
</pentry>
<pentry minsize="1" maxsize="4" extension="inttype">
<register name="r0"/>
</pentry>
<pentry minsize="5" maxsize="8">
<addr space="join" piece1="r1" piece2="r0"/>
</pentry>
</output>
<unaffected>
<register name="r4"/>
<register name="r5"/>
<register name="r6"/>
<register name="r7"/>
<register name="r8"/>
<register name="r9"/>
<register name="r10"/>
<register name="r11"/>
<register name="q4"/>
<register name="q5"/>
<register name="q6"/>
<register name="q7"/>
<register name="sp"/>
<register name="lr"/>
<register name="pc"/>
</unaffected>
<killedbycall>
<register name="r0"/>
<register name="r1"/>
<register name="r2"/>
<register name="r3"/>
<register name="r12"/>
<register name="q0"/>
<register name="q1"/>
<register name="q2"/>
<register name="q3"/>
<register name="q8"/>
<register name="q9"/>
<register name="q10"/>
<register name="q11"/>
<register name="q12"/>
<register name="q13"/>
<register name="q14"/>
<register name="q15"/>
</killedbycall>
</prototype>
</default_proto>
</compiler_spec>
python/icicle/Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc
+6488 -6488
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File diff suppressed because it is too large Load Diff
python/icicle/Ghidra/Processors/ARM/data/languages/ARMneon.dwarf
+14 -14
View File
@@ -1,14 +1,14 @@
<dwarf>
<register_mappings>
<register_mapping dwarf="0" ghidra="r0" auto_count="13"/> <!-- r0..r12 -->
<register_mapping dwarf="13" ghidra="sp" stackpointer="true"/>
<register_mapping dwarf="14" ghidra="lr"/>
<register_mapping dwarf="15" ghidra="pc"/>
<register_mapping dwarf="16" ghidra="fpsr"/>
<register_mapping dwarf="17" ghidra="cpsr"/>
<register_mapping dwarf="256" ghidra="d0" auto_count="32"/> <!-- d0..d31 -->
<register_mapping dwarf="64" ghidra="s0" auto_count="32"/> <!-- s0..s31 -->
</register_mappings>
<call_frame_cfa value="0"/>
<use_formal_parameter_storage/>
</dwarf>
<dwarf>
<register_mappings>
<register_mapping dwarf="0" ghidra="r0" auto_count="13"/> <!-- r0..r12 -->
<register_mapping dwarf="13" ghidra="sp" stackpointer="true"/>
<register_mapping dwarf="14" ghidra="lr"/>
<register_mapping dwarf="15" ghidra="pc"/>
<register_mapping dwarf="16" ghidra="fpsr"/>
<register_mapping dwarf="17" ghidra="cpsr"/>
<register_mapping dwarf="256" ghidra="d0" auto_count="32"/> <!-- d0..d31 -->
<register_mapping dwarf="64" ghidra="s0" auto_count="32"/> <!-- s0..s31 -->
</register_mappings>
<call_frame_cfa value="0"/>
<use_formal_parameter_storage/>
</dwarf>
python/icicle/Ghidra/Processors/ARM/data/languages/ARMneon.sinc
+6141 -6141
View File
File diff suppressed because it is too large Load Diff
python/icicle/Ghidra/Processors/ARM/data/languages/ARMt.pspec
+64 -64
View File
@@ -1,64 +1,64 @@
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<properties>
<property key="addressesDoNotAppearDirectlyInCode" value="true"/>
<property key="allowOffcutReferencesToFunctionStarts" value="true"/>
<property key="useNewFunctionStackAnalysis" value="true"/>
<property key="enableContiguousFunctionsOnly" value="false"/>
<property key="emulateInstructionStateModifierClass" value="ghidra.program.emulation.ARMEmulateInstructionStateModifier"/>
<property key="assemblyRating:ARM:BE:32:v7" value="PLATINUM"/>
<property key="assemblyRating:ARM:LE:32:v7" value="PLATINUM"/>
</properties>
<programcounter register="pc"/>
<context_data>
<context_set space="ram">
<set name="TMode" val="0" description="0 for ARM 32-bit, 1 for THUMB 16-bit"/>
<set name="LRset" val="0" description="0 lr reg not set, 1 for LR set, affects BX as a call"/>
</context_set>
<tracked_set space="ram">
<set name="spsr" val="0"/>
</tracked_set>
</context_data>
<default_symbols>
<symbol name="Reset" address="ram:0x0" entry="true"/>
<symbol name="UndefinedInstruction" address="ram:0x4" entry="true"/>
<symbol name="SupervisorCall" address="ram:0x8" entry="true"/>
<symbol name="PrefetchAbort" address="ram:0xC" entry="true"/>
<symbol name="DataAbort" address="ram:0x10" entry="true"/>
<symbol name="NotUsed" address="ram:0x14" entry="true"/>
<symbol name="IRQ" address="ram:0x18" entry="true"/>
<symbol name="FIQ" address="ram:0x1c" entry="true"/>
<symbol name="H_Reset" address="ram:0xFFFF0000" entry="true"/>
<symbol name="H_UndefinedInstruction" address="ram:0xFFFF0004" entry="true"/>
<symbol name="H_SupervisorCall" address="ram:0xFFFF0008" entry="true"/>
<symbol name="H_PrefetchAbort" address="ram:0xFFFF000C" entry="true"/>
<symbol name="H_DataAbort" address="ram:0xFFFF0010" entry="true"/>
<symbol name="H_NotUsed" address="ram:0xFFFF0014" entry="true"/>
<symbol name="H_IRQ" address="ram:0xFFFF0018" entry="true"/>
<symbol name="H_FIQ" address="ram:0xFFFF001c" entry="true"/>
</default_symbols>
<register_data>
<register name="q0" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q1" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q2" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q3" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q4" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q5" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q6" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q7" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q8" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q9" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q10" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q11" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q12" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q13" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q14" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q15" group="NEON" vector_lane_sizes="1,2,4"/>
</register_data>
</processor_spec>
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<properties>
<property key="addressesDoNotAppearDirectlyInCode" value="true"/>
<property key="allowOffcutReferencesToFunctionStarts" value="true"/>
<property key="useNewFunctionStackAnalysis" value="true"/>
<property key="enableContiguousFunctionsOnly" value="false"/>
<property key="emulateInstructionStateModifierClass" value="ghidra.program.emulation.ARMEmulateInstructionStateModifier"/>
<property key="assemblyRating:ARM:BE:32:v7" value="PLATINUM"/>
<property key="assemblyRating:ARM:LE:32:v7" value="PLATINUM"/>
</properties>
<programcounter register="pc"/>
<context_data>
<context_set space="ram">
<set name="TMode" val="0" description="0 for ARM 32-bit, 1 for THUMB 16-bit"/>
<set name="LRset" val="0" description="0 lr reg not set, 1 for LR set, affects BX as a call"/>
</context_set>
<tracked_set space="ram">
<set name="spsr" val="0"/>
</tracked_set>
</context_data>
<default_symbols>
<symbol name="Reset" address="ram:0x0" entry="true"/>
<symbol name="UndefinedInstruction" address="ram:0x4" entry="true"/>
<symbol name="SupervisorCall" address="ram:0x8" entry="true"/>
<symbol name="PrefetchAbort" address="ram:0xC" entry="true"/>
<symbol name="DataAbort" address="ram:0x10" entry="true"/>
<symbol name="NotUsed" address="ram:0x14" entry="true"/>
<symbol name="IRQ" address="ram:0x18" entry="true"/>
<symbol name="FIQ" address="ram:0x1c" entry="true"/>
<symbol name="H_Reset" address="ram:0xFFFF0000" entry="true"/>
<symbol name="H_UndefinedInstruction" address="ram:0xFFFF0004" entry="true"/>
<symbol name="H_SupervisorCall" address="ram:0xFFFF0008" entry="true"/>
<symbol name="H_PrefetchAbort" address="ram:0xFFFF000C" entry="true"/>
<symbol name="H_DataAbort" address="ram:0xFFFF0010" entry="true"/>
<symbol name="H_NotUsed" address="ram:0xFFFF0014" entry="true"/>
<symbol name="H_IRQ" address="ram:0xFFFF0018" entry="true"/>
<symbol name="H_FIQ" address="ram:0xFFFF001c" entry="true"/>
</default_symbols>
<register_data>
<register name="q0" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q1" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q2" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q3" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q4" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q5" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q6" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q7" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q8" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q9" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q10" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q11" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q12" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q13" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q14" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q15" group="NEON" vector_lane_sizes="1,2,4"/>
</register_data>
</processor_spec>
python/icicle/Ghidra/Processors/ARM/data/languages/ARMtTHUMB.pspec
+65 -65
View File
@@ -1,65 +1,65 @@
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<!-- THIS PSPEC IS A COPY OF ARMt.pspec AND ONLY DIFFERS WITH ENABLEMENT OF THUMB AS DEFAULT CONTEXT -->
<properties>
<property key="addressesDoNotAppearDirectlyInCode" value="true"/>
<property key="allowOffcutReferencesToFunctionStarts" value="true"/>
<property key="useNewFunctionStackAnalysis" value="true"/>
<property key="enableContiguousFunctionsOnly" value="false"/>
<property key="emulateInstructionStateModifierClass" value="ghidra.program.emulation.ARMEmulateInstructionStateModifier"/>
<property key="assemblyRating:ARM:BE:32:v7" value="PLATINUM"/>
<property key="assemblyRating:ARM:LE:32:v7" value="PLATINUM"/>
</properties>
<programcounter register="pc"/>
<context_data>
<context_set space="ram">
<set name="TMode" val="1" description="0 for ARM 32-bit, 1 for THUMB 16-bit"/>
<set name="LRset" val="0" description="0 lr reg not set, 1 for LR set, affects BX as a call"/>
</context_set>
<tracked_set space="ram">
<set name="spsr" val="0"/>
</tracked_set>
</context_data>
<default_symbols>
<symbol name="Reset" address="ram:0x0" entry="true"/>
<symbol name="UndefinedInstruction" address="ram:0x4" entry="true"/>
<symbol name="SupervisorCall" address="ram:0x8" entry="true"/>
<symbol name="PrefetchAbort" address="ram:0xC" entry="true"/>
<symbol name="DataAbort" address="ram:0x10" entry="true"/>
<symbol name="NotUsed" address="ram:0x14" entry="true"/>
<symbol name="IRQ" address="ram:0x18" entry="true"/>
<symbol name="FIQ" address="ram:0x1c" entry="true"/>
<symbol name="H_Reset" address="ram:0xFFFF0000" entry="true"/>
<symbol name="H_UndefinedInstruction" address="ram:0xFFFF0004" entry="true"/>
<symbol name="H_SupervisorCall" address="ram:0xFFFF0008" entry="true"/>
<symbol name="H_PrefetchAbort" address="ram:0xFFFF000C" entry="true"/>
<symbol name="H_DataAbort" address="ram:0xFFFF0010" entry="true"/>
<symbol name="H_NotUsed" address="ram:0xFFFF0014" entry="true"/>
<symbol name="H_IRQ" address="ram:0xFFFF0018" entry="true"/>
<symbol name="H_FIQ" address="ram:0xFFFF001c" entry="true"/>
</default_symbols>
<register_data>
<register name="q0" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q1" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q2" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q3" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q4" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q5" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q6" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q7" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q8" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q9" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q10" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q11" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q12" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q13" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q14" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q15" group="NEON" vector_lane_sizes="1,2,4"/>
</register_data>
</processor_spec>
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<!-- THIS PSPEC IS A COPY OF ARMt.pspec AND ONLY DIFFERS WITH ENABLEMENT OF THUMB AS DEFAULT CONTEXT -->
<properties>
<property key="addressesDoNotAppearDirectlyInCode" value="true"/>
<property key="allowOffcutReferencesToFunctionStarts" value="true"/>
<property key="useNewFunctionStackAnalysis" value="true"/>
<property key="enableContiguousFunctionsOnly" value="false"/>
<property key="emulateInstructionStateModifierClass" value="ghidra.program.emulation.ARMEmulateInstructionStateModifier"/>
<property key="assemblyRating:ARM:BE:32:v7" value="PLATINUM"/>
<property key="assemblyRating:ARM:LE:32:v7" value="PLATINUM"/>
</properties>
<programcounter register="pc"/>
<context_data>
<context_set space="ram">
<set name="TMode" val="1" description="0 for ARM 32-bit, 1 for THUMB 16-bit"/>
<set name="LRset" val="0" description="0 lr reg not set, 1 for LR set, affects BX as a call"/>
</context_set>
<tracked_set space="ram">
<set name="spsr" val="0"/>
</tracked_set>
</context_data>
<default_symbols>
<symbol name="Reset" address="ram:0x0" entry="true"/>
<symbol name="UndefinedInstruction" address="ram:0x4" entry="true"/>
<symbol name="SupervisorCall" address="ram:0x8" entry="true"/>
<symbol name="PrefetchAbort" address="ram:0xC" entry="true"/>
<symbol name="DataAbort" address="ram:0x10" entry="true"/>
<symbol name="NotUsed" address="ram:0x14" entry="true"/>
<symbol name="IRQ" address="ram:0x18" entry="true"/>
<symbol name="FIQ" address="ram:0x1c" entry="true"/>
<symbol name="H_Reset" address="ram:0xFFFF0000" entry="true"/>
<symbol name="H_UndefinedInstruction" address="ram:0xFFFF0004" entry="true"/>
<symbol name="H_SupervisorCall" address="ram:0xFFFF0008" entry="true"/>
<symbol name="H_PrefetchAbort" address="ram:0xFFFF000C" entry="true"/>
<symbol name="H_DataAbort" address="ram:0xFFFF0010" entry="true"/>
<symbol name="H_NotUsed" address="ram:0xFFFF0014" entry="true"/>
<symbol name="H_IRQ" address="ram:0xFFFF0018" entry="true"/>
<symbol name="H_FIQ" address="ram:0xFFFF001c" entry="true"/>
</default_symbols>
<register_data>
<register name="q0" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q1" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q2" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q3" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q4" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q5" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q6" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q7" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q8" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q9" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q10" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q11" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q12" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q13" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q14" group="NEON" vector_lane_sizes="1,2,4"/>
<register name="q15" group="NEON" vector_lane_sizes="1,2,4"/>
</register_data>
</processor_spec>
python/icicle/Ghidra/Processors/ARM/data/languages/ARMt_v45.pspec
+43 -43
View File
@@ -1,43 +1,43 @@
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<properties>
<property key="addressesDoNotAppearDirectlyInCode" value="true"/>
<property key="allowOffcutReferencesToFunctionStarts" value="true"/>
<property key="useNewFunctionStackAnalysis" value="true"/>
<property key="enableSharedReturnAnalysis" value="false"/>
<property key="enableContiguousFunctionsOnly" value="false"/>
<property key="emulateInstructionStateModifierClass" value="ghidra.program.emulation.ARMEmulateInstructionStateModifier"/>
</properties>
<programcounter register="pc"/>
<context_data>
<context_set space="ram">
<set name="TMode" val="0" description="0 for ARM 32-bit, 1 for THUMB 16-bit"/>
<set name="LRset" val="0" description="0 lr reg not set, 1 for LR set, affects BX as a call"/>
</context_set>
<tracked_set space="ram">
<set name="spsr" val="0"/>
</tracked_set>
</context_data>
<default_symbols>
<symbol name="Reset" address="ram:0x0" entry="true"/>
<symbol name="UndefinedInstruction" address="ram:0x4" entry="true"/>
<symbol name="SupervisorCall" address="ram:0x8" entry="true"/>
<symbol name="PrefetchAbort" address="ram:0xC" entry="true"/>
<symbol name="DataAbort" address="ram:0x10" entry="true"/>
<symbol name="NotUsed" address="ram:0x14" entry="true"/>
<symbol name="IRQ" address="ram:0x18" entry="true"/>
<symbol name="FIQ" address="ram:0x1c" entry="true"/>
<symbol name="H_Reset" address="ram:0xFFFF0000" entry="true"/>
<symbol name="H_UndefinedInstruction" address="ram:0xFFFF0004" entry="true"/>
<symbol name="H_SupervisorCall" address="ram:0xFFFF0008" entry="true"/>
<symbol name="H_PrefetchAbort" address="ram:0xFFFF000C" entry="true"/>
<symbol name="H_DataAbort" address="ram:0xFFFF0010" entry="true"/>
<symbol name="H_NotUsed" address="ram:0xFFFF0014" entry="true"/>
<symbol name="H_IRQ" address="ram:0xFFFF0018" entry="true"/>
<symbol name="H_FIQ" address="ram:0xFFFF001c" entry="true"/>
</default_symbols>
</processor_spec>
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<properties>
<property key="addressesDoNotAppearDirectlyInCode" value="true"/>
<property key="allowOffcutReferencesToFunctionStarts" value="true"/>
<property key="useNewFunctionStackAnalysis" value="true"/>
<property key="enableSharedReturnAnalysis" value="false"/>
<property key="enableContiguousFunctionsOnly" value="false"/>
<property key="emulateInstructionStateModifierClass" value="ghidra.program.emulation.ARMEmulateInstructionStateModifier"/>
</properties>
<programcounter register="pc"/>
<context_data>
<context_set space="ram">
<set name="TMode" val="0" description="0 for ARM 32-bit, 1 for THUMB 16-bit"/>
<set name="LRset" val="0" description="0 lr reg not set, 1 for LR set, affects BX as a call"/>
</context_set>
<tracked_set space="ram">
<set name="spsr" val="0"/>
</tracked_set>
</context_data>
<default_symbols>
<symbol name="Reset" address="ram:0x0" entry="true"/>
<symbol name="UndefinedInstruction" address="ram:0x4" entry="true"/>
<symbol name="SupervisorCall" address="ram:0x8" entry="true"/>
<symbol name="PrefetchAbort" address="ram:0xC" entry="true"/>
<symbol name="DataAbort" address="ram:0x10" entry="true"/>
<symbol name="NotUsed" address="ram:0x14" entry="true"/>
<symbol name="IRQ" address="ram:0x18" entry="true"/>
<symbol name="FIQ" address="ram:0x1c" entry="true"/>
<symbol name="H_Reset" address="ram:0xFFFF0000" entry="true"/>
<symbol name="H_UndefinedInstruction" address="ram:0xFFFF0004" entry="true"/>
<symbol name="H_SupervisorCall" address="ram:0xFFFF0008" entry="true"/>
<symbol name="H_PrefetchAbort" address="ram:0xFFFF000C" entry="true"/>
<symbol name="H_DataAbort" address="ram:0xFFFF0010" entry="true"/>
<symbol name="H_NotUsed" address="ram:0xFFFF0014" entry="true"/>
<symbol name="H_IRQ" address="ram:0xFFFF0018" entry="true"/>
<symbol name="H_FIQ" address="ram:0xFFFF001c" entry="true"/>
</default_symbols>
</processor_spec>
python/icicle/Ghidra/Processors/ARM/data/languages/ARMt_v6.pspec
+44 -44
View File
@@ -1,44 +1,44 @@
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<properties>
<property key="addressesDoNotAppearDirectlyInCode" value="true"/>
<property key="allowOffcutReferencesToFunctionStarts" value="true"/>
<property key="useNewFunctionStackAnalysis" value="true"/>
<property key="enableContiguousFunctionsOnly" value="false"/>
<property key="emulateInstructionStateModifierClass" value="ghidra.program.emulation.ARMEmulateInstructionStateModifier"/>
<property key="assemblyRating:ARM:BE:32:v7" value="PLATINUM"/>
<property key="assemblyRating:ARM:LE:32:v7" value="PLATINUM"/>
</properties>
<programcounter register="pc"/>
<context_data>
<context_set space="ram">
<set name="TMode" val="0" description="0 for ARM 32-bit, 1 for THUMB 16-bit"/>
<set name="LRset" val="0" description="0 lr reg not set, 1 for LR set, affects BX as a call"/>
</context_set>
<tracked_set space="ram">
<set name="spsr" val="0"/>
</tracked_set>
</context_data>
<default_symbols>
<symbol name="Reset" address="ram:0x0" entry="true"/>
<symbol name="UndefinedInstruction" address="ram:0x4" entry="true"/>
<symbol name="SupervisorCall" address="ram:0x8" entry="true"/>
<symbol name="PrefetchAbort" address="ram:0xC" entry="true"/>
<symbol name="DataAbort" address="ram:0x10" entry="true"/>
<symbol name="NotUsed" address="ram:0x14" entry="true"/>
<symbol name="IRQ" address="ram:0x18" entry="true"/>
<symbol name="FIQ" address="ram:0x1c" entry="true"/>
<symbol name="H_Reset" address="ram:0xFFFF0000" entry="true"/>
<symbol name="H_UndefinedInstruction" address="ram:0xFFFF0004" entry="true"/>
<symbol name="H_SupervisorCall" address="ram:0xFFFF0008" entry="true"/>
<symbol name="H_PrefetchAbort" address="ram:0xFFFF000C" entry="true"/>
<symbol name="H_DataAbort" address="ram:0xFFFF0010" entry="true"/>
<symbol name="H_NotUsed" address="ram:0xFFFF0014" entry="true"/>
<symbol name="H_IRQ" address="ram:0xFFFF0018" entry="true"/>
<symbol name="H_FIQ" address="ram:0xFFFF001c" entry="true"/>
</default_symbols>
</processor_spec>
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<properties>
<property key="addressesDoNotAppearDirectlyInCode" value="true"/>
<property key="allowOffcutReferencesToFunctionStarts" value="true"/>
<property key="useNewFunctionStackAnalysis" value="true"/>
<property key="enableContiguousFunctionsOnly" value="false"/>
<property key="emulateInstructionStateModifierClass" value="ghidra.program.emulation.ARMEmulateInstructionStateModifier"/>
<property key="assemblyRating:ARM:BE:32:v7" value="PLATINUM"/>
<property key="assemblyRating:ARM:LE:32:v7" value="PLATINUM"/>
</properties>
<programcounter register="pc"/>
<context_data>
<context_set space="ram">
<set name="TMode" val="0" description="0 for ARM 32-bit, 1 for THUMB 16-bit"/>
<set name="LRset" val="0" description="0 lr reg not set, 1 for LR set, affects BX as a call"/>
</context_set>
<tracked_set space="ram">
<set name="spsr" val="0"/>
</tracked_set>
</context_data>
<default_symbols>
<symbol name="Reset" address="ram:0x0" entry="true"/>
<symbol name="UndefinedInstruction" address="ram:0x4" entry="true"/>
<symbol name="SupervisorCall" address="ram:0x8" entry="true"/>
<symbol name="PrefetchAbort" address="ram:0xC" entry="true"/>
<symbol name="DataAbort" address="ram:0x10" entry="true"/>
<symbol name="NotUsed" address="ram:0x14" entry="true"/>
<symbol name="IRQ" address="ram:0x18" entry="true"/>
<symbol name="FIQ" address="ram:0x1c" entry="true"/>
<symbol name="H_Reset" address="ram:0xFFFF0000" entry="true"/>
<symbol name="H_UndefinedInstruction" address="ram:0xFFFF0004" entry="true"/>
<symbol name="H_SupervisorCall" address="ram:0xFFFF0008" entry="true"/>
<symbol name="H_PrefetchAbort" address="ram:0xFFFF000C" entry="true"/>
<symbol name="H_DataAbort" address="ram:0xFFFF0010" entry="true"/>
<symbol name="H_NotUsed" address="ram:0xFFFF0014" entry="true"/>
<symbol name="H_IRQ" address="ram:0xFFFF0018" entry="true"/>
<symbol name="H_FIQ" address="ram:0xFFFF001c" entry="true"/>
</default_symbols>
</processor_spec>
python/icicle/Ghidra/Processors/ARM/data/languages/ARMv8.sinc
+1348 -1348
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python/icicle/Ghidra/Processors/ARM/data/languages/old/ARMv5.lang
+62 -62
View File
@@ -1,62 +1,62 @@
<?xml version="1.0" encoding="UTF-8"?>
<language version="1" endian="little">
<description>
<id>ARM:LE:32:DEPRECATED ARM V5</id>
<processor>ARM</processor>
</description>
<spaces>
<space name="ram" type="ram" size="4" default="yes" />
<space name="register" type="register" size="4" />
</spaces>
<registers>
<register name="r0" offset="0x0" bitsize="32" />
<register name="r1" offset="0x4" bitsize="32" />
<register name="r2" offset="0x8" bitsize="32" />
<register name="r3" offset="0xc" bitsize="32" />
<register name="r4" offset="0x10" bitsize="32" />
<register name="r5" offset="0x14" bitsize="32" />
<register name="r6" offset="0x18" bitsize="32" />
<register name="r7" offset="0x1c" bitsize="32" />
<register name="r8" offset="0x20" bitsize="32" />
<register name="r9" offset="0x24" bitsize="32" />
<register name="sl" offset="0x28" bitsize="32" />
<register name="fp" offset="0x2c" bitsize="32" />
<register name="ip" offset="0x30" bitsize="32" />
<register name="sp" offset="0x34" bitsize="32" />
<register name="lr" offset="0x38" bitsize="32" />
<register name="pc" offset="0x3c" bitsize="32" />
<register name="NG" offset="0x40" bitsize="8" />
<register name="ZR" offset="0x41" bitsize="8" />
<register name="CY" offset="0x42" bitsize="8" />
<register name="OV" offset="0x43" bitsize="8" />
<register name="tmpNG" offset="0x44" bitsize="8" />
<register name="tmpZR" offset="0x45" bitsize="8" />
<register name="tmpCY" offset="0x46" bitsize="8" />
<register name="tmpOV" offset="0x47" bitsize="8" />
<register name="shift_carry" offset="0x48" bitsize="8" />
<register name="TB" offset="0x49" bitsize="8" />
<register name="cpsr" offset="0x50" bitsize="32" />
<register name="spsr" offset="0x54" bitsize="32" />
<register name="mult_addr" offset="0x60" bitsize="32" />
<register name="r14_svc" offset="0x64" bitsize="32" />
<register name="r13_svc" offset="0x68" bitsize="32" />
<register name="spsr_svc" offset="0x6c" bitsize="32" />
<register name="cr0" offset="0x100" bitsize="32" />
<register name="cr1" offset="0x104" bitsize="32" />
<register name="cr2" offset="0x108" bitsize="32" />
<register name="cr3" offset="0x10c" bitsize="32" />
<register name="cr4" offset="0x110" bitsize="32" />
<register name="cr5" offset="0x114" bitsize="32" />
<register name="cr6" offset="0x118" bitsize="32" />
<register name="cr7" offset="0x11c" bitsize="32" />
<register name="cr8" offset="0x120" bitsize="32" />
<register name="cr9" offset="0x124" bitsize="32" />
<register name="cr10" offset="0x128" bitsize="32" />
<register name="cr11" offset="0x12c" bitsize="32" />
<register name="cr12" offset="0x130" bitsize="32" />
<register name="cr13" offset="0x134" bitsize="32" />
<register name="cr14" offset="0x138" bitsize="32" />
<register name="cr15" offset="0x13c" bitsize="32" />
</registers>
</language>
<?xml version="1.0" encoding="UTF-8"?>
<language version="1" endian="little">
<description>
<id>ARM:LE:32:DEPRECATED ARM V5</id>
<processor>ARM</processor>
</description>
<spaces>
<space name="ram" type="ram" size="4" default="yes" />
<space name="register" type="register" size="4" />
</spaces>
<registers>
<register name="r0" offset="0x0" bitsize="32" />
<register name="r1" offset="0x4" bitsize="32" />
<register name="r2" offset="0x8" bitsize="32" />
<register name="r3" offset="0xc" bitsize="32" />
<register name="r4" offset="0x10" bitsize="32" />
<register name="r5" offset="0x14" bitsize="32" />
<register name="r6" offset="0x18" bitsize="32" />
<register name="r7" offset="0x1c" bitsize="32" />
<register name="r8" offset="0x20" bitsize="32" />
<register name="r9" offset="0x24" bitsize="32" />
<register name="sl" offset="0x28" bitsize="32" />
<register name="fp" offset="0x2c" bitsize="32" />
<register name="ip" offset="0x30" bitsize="32" />
<register name="sp" offset="0x34" bitsize="32" />
<register name="lr" offset="0x38" bitsize="32" />
<register name="pc" offset="0x3c" bitsize="32" />
<register name="NG" offset="0x40" bitsize="8" />
<register name="ZR" offset="0x41" bitsize="8" />
<register name="CY" offset="0x42" bitsize="8" />
<register name="OV" offset="0x43" bitsize="8" />
<register name="tmpNG" offset="0x44" bitsize="8" />
<register name="tmpZR" offset="0x45" bitsize="8" />
<register name="tmpCY" offset="0x46" bitsize="8" />
<register name="tmpOV" offset="0x47" bitsize="8" />
<register name="shift_carry" offset="0x48" bitsize="8" />
<register name="TB" offset="0x49" bitsize="8" />
<register name="cpsr" offset="0x50" bitsize="32" />
<register name="spsr" offset="0x54" bitsize="32" />
<register name="mult_addr" offset="0x60" bitsize="32" />
<register name="r14_svc" offset="0x64" bitsize="32" />
<register name="r13_svc" offset="0x68" bitsize="32" />
<register name="spsr_svc" offset="0x6c" bitsize="32" />
<register name="cr0" offset="0x100" bitsize="32" />
<register name="cr1" offset="0x104" bitsize="32" />
<register name="cr2" offset="0x108" bitsize="32" />
<register name="cr3" offset="0x10c" bitsize="32" />
<register name="cr4" offset="0x110" bitsize="32" />
<register name="cr5" offset="0x114" bitsize="32" />
<register name="cr6" offset="0x118" bitsize="32" />
<register name="cr7" offset="0x11c" bitsize="32" />
<register name="cr8" offset="0x120" bitsize="32" />
<register name="cr9" offset="0x124" bitsize="32" />
<register name="cr10" offset="0x128" bitsize="32" />
<register name="cr11" offset="0x12c" bitsize="32" />
<register name="cr12" offset="0x130" bitsize="32" />
<register name="cr13" offset="0x134" bitsize="32" />
<register name="cr14" offset="0x138" bitsize="32" />
<register name="cr15" offset="0x13c" bitsize="32" />
</registers>
</language>
python/icicle/Ghidra/Processors/ARM/data/languages/old/ARMv5.trans
+6 -6
View File
@@ -1,6 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<language_translation>
<from_language version="1">Sleigh-ARMv5</from_language>
<to_language version="1">ARM:LE:32:v5</to_language>
</language_translation>
<?xml version="1.0" encoding="UTF-8"?>
<language_translation>
<from_language version="1">Sleigh-ARMv5</from_language>
<to_language version="1">ARM:LE:32:v5</to_language>
</language_translation>
python/icicle/Ghidra/Processors/ARM/data/languages/old/THUMBv2.lang
+55 -55
View File
@@ -1,55 +1,55 @@
<?xml version="1.0" encoding="UTF-8"?>
<language version="1" endian="little">
<description>
<id>ARM:LE:32:DEPRECATED THUMB V2</id>
<processor>ARM</processor>
</description>
<spaces>
<space name="ram" type="ram" size="4" default="yes" />
<space name="register" type="register" size="4" />
</spaces>
<registers>
<register name="r0" offset="0x0" bitsize="32" />
<register name="r1" offset="0x4" bitsize="32" />
<register name="r2" offset="0x8" bitsize="32" />
<register name="r3" offset="0xc" bitsize="32" />
<register name="r4" offset="0x10" bitsize="32" />
<register name="r5" offset="0x14" bitsize="32" />
<register name="r6" offset="0x18" bitsize="32" />
<register name="r7" offset="0x1c" bitsize="32" />
<register name="r8" offset="0x20" bitsize="32" />
<register name="r9" offset="0x24" bitsize="32" />
<register name="sl" offset="0x28" bitsize="32" />
<register name="fp" offset="0x2c" bitsize="32" />
<register name="ip" offset="0x30" bitsize="32" />
<register name="sp" offset="0x34" bitsize="32" />
<register name="lr" offset="0x38" bitsize="32" />
<register name="pc" offset="0x3c" bitsize="32" />
<register name="NG" offset="0x40" bitsize="8" />
<register name="ZR" offset="0x41" bitsize="8" />
<register name="CY" offset="0x42" bitsize="8" />
<register name="OV" offset="0x43" bitsize="8" />
<register name="tmpNG" offset="0x44" bitsize="8" />
<register name="tmpZR" offset="0x45" bitsize="8" />
<register name="tmpCY" offset="0x46" bitsize="8" />
<register name="tmpOV" offset="0x47" bitsize="8" />
<register name="shift_carry" offset="0x48" bitsize="8" />
<register name="TB" offset="0x49" bitsize="8" />
<register name="cpsr" offset="0x50" bitsize="32" />
<register name="spsr" offset="0x54" bitsize="32" />
<register name="mult_addr" offset="0x60" bitsize="32" />
<register name="r14_svc" offset="0x64" bitsize="32" />
<register name="r13_svc" offset="0x68" bitsize="32" />
<register name="spsr_svc" offset="0x6c" bitsize="32" />
<register name="fpsr" offset="0x80" bitsize="32" />
<register name="fp0" offset="0x100" bitsize="80" />
<register name="fp1" offset="0x10a" bitsize="80" />
<register name="fp2" offset="0x114" bitsize="80" />
<register name="fp3" offset="0x11e" bitsize="80" />
<register name="fp4" offset="0x128" bitsize="80" />
<register name="fp5" offset="0x132" bitsize="80" />
<register name="fp6" offset="0x13c" bitsize="80" />
<register name="fp7" offset="0x146" bitsize="80" />
</registers>
</language>
<?xml version="1.0" encoding="UTF-8"?>
<language version="1" endian="little">
<description>
<id>ARM:LE:32:DEPRECATED THUMB V2</id>
<processor>ARM</processor>
</description>
<spaces>
<space name="ram" type="ram" size="4" default="yes" />
<space name="register" type="register" size="4" />
</spaces>
<registers>
<register name="r0" offset="0x0" bitsize="32" />
<register name="r1" offset="0x4" bitsize="32" />
<register name="r2" offset="0x8" bitsize="32" />
<register name="r3" offset="0xc" bitsize="32" />
<register name="r4" offset="0x10" bitsize="32" />
<register name="r5" offset="0x14" bitsize="32" />
<register name="r6" offset="0x18" bitsize="32" />
<register name="r7" offset="0x1c" bitsize="32" />
<register name="r8" offset="0x20" bitsize="32" />
<register name="r9" offset="0x24" bitsize="32" />
<register name="sl" offset="0x28" bitsize="32" />
<register name="fp" offset="0x2c" bitsize="32" />
<register name="ip" offset="0x30" bitsize="32" />
<register name="sp" offset="0x34" bitsize="32" />
<register name="lr" offset="0x38" bitsize="32" />
<register name="pc" offset="0x3c" bitsize="32" />
<register name="NG" offset="0x40" bitsize="8" />
<register name="ZR" offset="0x41" bitsize="8" />
<register name="CY" offset="0x42" bitsize="8" />
<register name="OV" offset="0x43" bitsize="8" />
<register name="tmpNG" offset="0x44" bitsize="8" />
<register name="tmpZR" offset="0x45" bitsize="8" />
<register name="tmpCY" offset="0x46" bitsize="8" />
<register name="tmpOV" offset="0x47" bitsize="8" />
<register name="shift_carry" offset="0x48" bitsize="8" />
<register name="TB" offset="0x49" bitsize="8" />
<register name="cpsr" offset="0x50" bitsize="32" />
<register name="spsr" offset="0x54" bitsize="32" />
<register name="mult_addr" offset="0x60" bitsize="32" />
<register name="r14_svc" offset="0x64" bitsize="32" />
<register name="r13_svc" offset="0x68" bitsize="32" />
<register name="spsr_svc" offset="0x6c" bitsize="32" />
<register name="fpsr" offset="0x80" bitsize="32" />
<register name="fp0" offset="0x100" bitsize="80" />
<register name="fp1" offset="0x10a" bitsize="80" />
<register name="fp2" offset="0x114" bitsize="80" />
<register name="fp3" offset="0x11e" bitsize="80" />
<register name="fp4" offset="0x128" bitsize="80" />
<register name="fp5" offset="0x132" bitsize="80" />
<register name="fp6" offset="0x13c" bitsize="80" />
<register name="fp7" offset="0x146" bitsize="80" />
</registers>
</language>
python/icicle/Ghidra/Processors/ARM/data/languages/old/THUMBv2.trans
+11 -11
View File
@@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<language_translation>
<from_language version="1">Sleigh-THUMBv2</from_language>
<to_language version="1">ARM:LE:32:v5t</to_language>
<!--
Set THUMB mode context everywhere
-->
<set_context name="TMode" value="1" />
</language_translation>
<?xml version="1.0" encoding="UTF-8"?>
<language_translation>
<from_language version="1">Sleigh-THUMBv2</from_language>
<to_language version="1">ARM:LE:32:v5t</to_language>
<!--
Set THUMB mode context everywhere
-->
<set_context name="TMode" value="1" />
</language_translation>
python/icicle/Ghidra/Processors/Atmel/data/languages/atmega256.pspec
+422 -422
View File
@@ -1,422 +1,422 @@
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="PC"/>
<data_space space="mem"/>
<!--
- NOTE: The settings within this file may be specific to a particular
- processor variant and will likely need to be changed to reflect
- the specific target processor.
The RAMPx, EIND, SREG registers are not marked volatile, even though they could be changed
indirectly with memory references. If they are made volatile, then the addressing
won't work in decompiler or reference recovery.
Some registers only appear in newer avr8's, or with large memory spaces
-->
<volatile outputop="write_volatile" inputop="read_volatile">
<range space="mem" first="0x20" last="0x57"/>
<range space="mem" first="0x60" last="0xff"/>
</volatile>
<context_data>
<tracked_set space="code">
<set name="R1" val="0"/>
</tracked_set>
</context_data>
<default_symbols>
<symbol name="RESET" address="code:0x0000" entry="true"/>
<symbol name="INT0" address="code:0x0002" entry="true"/>
<symbol name="INT1" address="code:0x0004" entry="true"/>
<symbol name="INT2" address="code:0x0006" entry="true"/>
<symbol name="INT3" address="code:0x0008" entry="true"/>
<symbol name="INT4" address="code:0x000A" entry="true"/>
<symbol name="INT5" address="code:0x000C" entry="true"/>
<symbol name="INT6" address="code:0x000E" entry="true"/>
<symbol name="INT7" address="code:0x0010" entry="true"/>
<symbol name="PCINT0" address="code:0x0012" entry="true"/>
<symbol name="PCINT1" address="code:0x0014" entry="true"/>
<symbol name="PCINT2" address="code:0x0016" entry="true"/>
<symbol name="WDT" address="code:0x0018" entry="true"/>
<symbol name="TIMER2_COMPA" address="code:0x001A" entry="true"/>
<symbol name="TIMER2_COMPB" address="code:0x001C" entry="true"/>
<symbol name="TIMER2_OVF" address="code:0x001E" entry="true"/>
<symbol name="TIMER1_CAPT" address="code:0x0020" entry="true"/>
<symbol name="TIMER1_COMPA" address="code:0x0022" entry="true"/>
<symbol name="TIMER1_COMPB" address="code:0x0024" entry="true"/>
<symbol name="TIMER1_COMPC" address="code:0x0026" entry="true"/>
<symbol name="TIMER1_OVF" address="code:0x0028" entry="true"/>
<symbol name="TIMER0_COMPA" address="code:0x002A" entry="true"/>
<symbol name="TIMER0_COMPB" address="code:0x002C" entry="true"/>
<symbol name="TIMER0_OVF" address="code:0x002E" entry="true"/>
<symbol name="SPI_STC" address="code:0x0030" entry="true"/>
<symbol name="USART0_RX" address="code:0x0032" entry="true"/>
<symbol name="USART0_UDRE" address="code:0x0034" entry="true"/>
<symbol name="USART0_TX" address="code:0x0036" entry="true"/>
<symbol name="ANALOG_COMP" address="code:0x0038" entry="true"/>
<symbol name="ADC_ADC" address="code:0x003A" entry="true"/>
<symbol name="EE_READY" address="code:0x003C" entry="true"/>
<symbol name="TIMER3_CAPT" address="code:0x003E" entry="true"/>
<symbol name="TIMER3_COMPA" address="code:0x0040" entry="true"/>
<symbol name="TIMER3_COMPB" address="code:0x0042" entry="true"/>
<symbol name="TIMER3_COMPC" address="code:0x0044" entry="true"/>
<symbol name="TIMER3_OVF" address="code:0x0046" entry="true"/>
<symbol name="USART1_RX" address="code:0x0048" entry="true"/>
<symbol name="USART1_UDRE" address="code:0x004A" entry="true"/>
<symbol name="USART1_TX" address="code:0x004C" entry="true"/>
<symbol name="TWI" address="code:0x004E" entry="true"/>
<symbol name="SPM_READY" address="code:0x0050" entry="true"/>
<symbol name="TIMER4_CAPT" address="code:0x0052" entry="true"/>
<symbol name="TIMER4_COMPA" address="code:0x0054" entry="true"/>
<symbol name="TIMER4_COMPB" address="code:0x0056" entry="true"/>
<symbol name="TIMER4_COMPC" address="code:0x0058" entry="true"/>
<symbol name="TIMER4_OVF" address="code:0x005A" entry="true"/>
<symbol name="TIMER5_CAPT" address="code:0x005C" entry="true"/>
<symbol name="TIMER5_COMPA" address="code:0x005E" entry="true"/>
<symbol name="TIMER5_COMPB" address="code:0x0060" entry="true"/>
<symbol name="TIMER5_COMPC" address="code:0x0062" entry="true"/>
<symbol name="TIMER5_OVF" address="code:0x0064" entry="true"/>
<symbol name="USART2_RX" address="code:0x0066" entry="true"/>
<symbol name="USART2_UDRE" address="code:0x0068" entry="true"/>
<symbol name="USART2_TX" address="code:0x006A" entry="true"/>
<symbol name="USART3_RX" address="code:0x006C" entry="true"/>
<symbol name="USART3_UDRE" address="code:0x006E" entry="true"/>
<symbol name="USART3_TX" address="code:0x0070" entry="true"/>
<symbol name="PINA" address="mem:0x20"/>
<symbol name="DDRA" address="mem:0x21"/>
<symbol name="PORTA" address="mem:0x22"/>
<symbol name="PINB" address="mem:0x23"/>
<symbol name="DDRB" address="mem:0x24"/>
<symbol name="PORTB" address="mem:0x25"/>
<symbol name="PINC" address="mem:0x26"/>
<symbol name="DDRC" address="mem:0x27"/>
<symbol name="PORTC" address="mem:0x28"/>
<symbol name="PIND" address="mem:0x29"/>
<symbol name="DDRD" address="mem:0x2a"/>
<symbol name="PORTD" address="mem:0x2b"/>
<symbol name="PINE" address="mem:0x2c"/>
<symbol name="DDRE" address="mem:0x2d"/>
<symbol name="PORTE" address="mem:0x2e"/>
<symbol name="PINF" address="mem:0x2f"/>
<symbol name="DDRF" address="mem:0x30"/>
<symbol name="PORTF" address="mem:0x31"/>
<symbol name="PING" address="mem:0x32"/>
<symbol name="DDRG" address="mem:0x33"/>
<symbol name="PORTG" address="mem:0x34"/>
<symbol name="TIFR0" address="mem:0x35"/>
<symbol name="TIFR1" address="mem:0x36"/>
<symbol name="TIFR2" address="mem:0x37"/>
<symbol name="TIFR3" address="mem:0x38"/>
<symbol name="TIFR4" address="mem:0x39"/>
<symbol name="TIFR5" address="mem:0x3a"/>
<symbol name="PCIFR" address="mem:0x3b"/>
<symbol name="EIFR" address="mem:0x3c"/>
<symbol name="EIMSK" address="mem:0x3d"/>
<symbol name="GPIOR0" address="mem:0x3e"/>
<symbol name="EECR" address="mem:0x3f"/>
<symbol name="EEDR" address="mem:0x40"/>
<symbol name="EEARL" address="mem:0x41"/>
<symbol name="EEARH" address="mem:0x42"/>
<symbol name="GTCCR" address="mem:0x43"/>
<symbol name="TCCR0A" address="mem:0x44"/>
<symbol name="TCCR0B" address="mem:0x45"/>
<symbol name="TCNT0" address="mem:0x46"/>
<symbol name="OCR0A" address="mem:0x47"/>
<symbol name="OCR0B" address="mem:0x48"/>
<symbol name="GPIOR1" address="mem:0x4a"/>
<symbol name="GPIOR2" address="mem:0x4b"/>
<symbol name="SPCR" address="mem:0x4c"/>
<symbol name="SPSR" address="mem:0x4d"/>
<symbol name="SPDR" address="mem:0x4e"/>
<symbol name="ACSR" address="mem:0x50"/>
<symbol name="OCDR" address="mem:0x51"/>
<symbol name="SMCR" address="mem:0x53"/>
<symbol name="MCUSR" address="mem:0x54"/>
<symbol name="MCUCR" address="mem:0x55"/>
<symbol name="SPMCSR" address="mem:0x57"/>
<symbol name="RAMPZ" address="mem:0x5b"/>
<symbol name="EIND" address="mem:0x5c"/>
<symbol name="_SPL" address="mem:0x5d"/>
<symbol name="_SPH" address="mem:0x5e"/>
<symbol name="WDTCSR" address="mem:0x60"/>
<symbol name="CLKPR" address="mem:0x61"/>
<symbol name="PRR2" address="mem:0x63"/>
<symbol name="PRR0" address="mem:0x64"/>
<symbol name="PRR1" address="mem:0x65"/>
<symbol name="OSCCAL" address="mem:0x66"/>
<symbol name="BGCR" address="mem:0x67"/>
<symbol name="PCICR" address="mem:0x68"/>
<symbol name="EICRA" address="mem:0x69"/>
<symbol name="EICRB" address="mem:0x6a"/>
<symbol name="PCMSK0" address="mem:0x6b"/>
<symbol name="PCMSK1" address="mem:0x6c"/>
<symbol name="PCMSK2" address="mem:0x6d"/>
<symbol name="TIMSK0" address="mem:0x6e"/>
<symbol name="TIMSK1" address="mem:0x6f"/>
<symbol name="TIMSK2" address="mem:0x70"/>
<symbol name="TIMSK3" address="mem:0x71"/>
<symbol name="TIMSK4" address="mem:0x72"/>
<symbol name="TIMSK5" address="mem:0x73"/>
<symbol name="NEMCR" address="mem:0x75"/>
<symbol name="ADCSRC" address="mem:0x77"/>
<symbol name="ADCL" address="mem:0x78"/>
<symbol name="ADCH" address="mem:0x79"/>
<symbol name="ADCSRA" address="mem:0x7a"/>
<symbol name="ADCSRB" address="mem:0x7b"/>
<symbol name="ADMUX" address="mem:0x7c"/>
<symbol name="DIDR2" address="mem:0x7d"/>
<symbol name="DIDR0" address="mem:0x7e"/>
<symbol name="DIDR1" address="mem:0x7f"/>
<symbol name="TCCR1A" address="mem:0x80"/>
<symbol name="TCCR1B" address="mem:0x81"/>
<symbol name="TCCR1C" address="mem:0x82"/>
<symbol name="TCNT1L" address="mem:0x84"/>
<symbol name="TCNT1H" address="mem:0x85"/>
<symbol name="ICR1L" address="mem:0x86"/>
<symbol name="ICR1H" address="mem:0x87"/>
<symbol name="OCR1AL" address="mem:0x88"/>
<symbol name="OCR1AH" address="mem:0x89"/>
<symbol name="OCR1BL" address="mem:0x8a"/>
<symbol name="OCR1BH" address="mem:0x8b"/>
<symbol name="OCR1CL" address="mem:0x8c"/>
<symbol name="OCR1CH" address="mem:0x8d"/>
<symbol name="TCCR3A" address="mem:0x90"/>
<symbol name="TCCR3B" address="mem:0x91"/>
<symbol name="TCCR3C" address="mem:0x92"/>
<symbol name="TCNT3L" address="mem:0x94"/>
<symbol name="TCNT3H" address="mem:0x95"/>
<symbol name="ICR3L" address="mem:0x96"/>
<symbol name="ICR3H" address="mem:0x97"/>
<symbol name="OCR3AL" address="mem:0x98"/>
<symbol name="OCR3AH" address="mem:0x99"/>
<symbol name="OCR3BL" address="mem:0x9a"/>
<symbol name="OCR3BH" address="mem:0x9b"/>
<symbol name="OCR3CL" address="mem:0x9c"/>
<symbol name="OCR3CH" address="mem:0x9d"/>
<symbol name="TCCR4A" address="mem:0xa0"/>
<symbol name="TCCR4B" address="mem:0xa1"/>
<symbol name="TCCR4C" address="mem:0xa2"/>
<symbol name="TCNT4L" address="mem:0xa4"/>
<symbol name="TCNT4H" address="mem:0xa5"/>
<symbol name="ICR4L" address="mem:0xa6"/>
<symbol name="ICR4H" address="mem:0xa7"/>
<symbol name="OCR4AL" address="mem:0xa8"/>
<symbol name="OCR4AH" address="mem:0xa9"/>
<symbol name="OCR4BL" address="mem:0xaa"/>
<symbol name="OCR4BH" address="mem:0xab"/>
<symbol name="OCR4CL" address="mem:0xac"/>
<symbol name="OCR4CH" address="mem:0xad"/>
<symbol name="TCCR2A" address="mem:0xb0"/>
<symbol name="TCCR2B" address="mem:0xb1"/>
<symbol name="TCNT2" address="mem:0xb2"/>
<symbol name="OCR2A" address="mem:0xb3"/>
<symbol name="OCR2B" address="mem:0xb4"/>
<symbol name="ASSR" address="mem:0xb6"/>
<symbol name="TWBR" address="mem:0xb8"/>
<symbol name="TWSR" address="mem:0xb9"/>
<symbol name="TWAR" address="mem:0xba"/>
<symbol name="TWDR" address="mem:0xbb"/>
<symbol name="TWCR" address="mem:0xbc"/>
<symbol name="TWAMR" address="mem:0xbd"/>
<symbol name="IRQ_MASK1" address="mem:0xbe"/>
<symbol name="IRQ_STATUS1" address="mem:0xbf"/>
<symbol name="UCSR0A" address="mem:0xc0"/>
<symbol name="UCSR0B" address="mem:0xc1"/>
<symbol name="UCSR0C" address="mem:0xc2"/>
<symbol name="UBRR0L" address="mem:0xc4"/>
<symbol name="UBRR0H" address="mem:0xc5"/>
<symbol name="UDR0" address="mem:0xc6"/>
<symbol name="UCSR1A" address="mem:0xc8"/>
<symbol name="UCSR1B" address="mem:0xc9"/>
<symbol name="UCSR1C" address="mem:0xca"/>
<symbol name="UBRR1L" address="mem:0xcc"/>
<symbol name="UBRR1H" address="mem:0xcd"/>
<symbol name="UDR1" address="mem:0xce"/>
<symbol name="UCSR2A" address="mem:0xd0"/>
<symbol name="UCSR2B" address="mem:0xd1"/>
<symbol name="UCSR2C" address="mem:0xd2"/>
<symbol name="SCRSTRLL" address="mem:0xd7"/>
<symbol name="SCRSTRLH " address="mem:0xd8"/>
<symbol name="SCRSTRHL" address="mem:0xd9"/>
<symbol name="SCRSTRHH" address="mem:0xda"/>
<symbol name="SCCSR" address="mem:0xdb"/>
<symbol name="SCCR0 " address="mem:0xdc"/>
<symbol name="SCCR1" address="mem:0xdd"/>
<symbol name="SCSR" address="mem:0xde"/>
<symbol name="SCIRQM" address="mem:0xdf"/>
<symbol name="SCIRQS" address="mem:0xe0"/>
<symbol name="SCCNTLL " address="mem:0xe1"/>
<symbol name="SCCNTLH" address="mem:0xe2"/>
<symbol name="SCCNTHL" address="mem:0xe3"/>
<symbol name="SCCNTHH" address="mem:0xe4"/>
<symbol name="SCBTSRLL " address="mem:0xe5"/>
<symbol name="SCBTSRLH" address="mem:0xe6"/>
<symbol name="SCBTSRHL" address="mem:0xe7"/>
<symbol name="SCBTSRHH" address="mem:0xe8"/>
<symbol name="SCTSRLL" address="mem:0xe9"/>
<symbol name="SCTSRLH" address="mem:0xea"/>
<symbol name="SCTSRHL" address="mem:0xeb"/>
<symbol name="SCTSRHH" address="mem:0xec"/>
<symbol name="SCOCR3LL" address="mem:0xed"/>
<symbol name="SCOCR3LH" address="mem:0xee"/>
<symbol name="SCOCR3HL" address="mem:0xef"/>
<symbol name="SCOCR3HH" address="mem:0xf0"/>
<symbol name="SCOCR2LL " address="mem:0xf1"/>
<symbol name="SCOCR2LH" address="mem:0xf2"/>
<symbol name="SCOCR2HL" address="mem:0xf3"/>
<symbol name="SCOCR2HH" address="mem:0xf4"/>
<symbol name="SCOCR1LL " address="mem:0xf5"/>
<symbol name="SCOCR1LH" address="mem:0xf6"/>
<symbol name="SCOCR1HL" address="mem:0xf7"/>
<symbol name="SCOCR1HH" address="mem:0xf8"/>
<symbol name="SCTSTRLL" address="mem:0xf9"/>
<symbol name="SCTSTRLH" address="mem:0xfa"/>
<symbol name="SCTSTRHL" address="mem:0xfb"/>
<symbol name="SCTSTRHH" address="mem:0xfc"/>
<symbol name="MAFCR0" address="mem:0x10c"/>
<symbol name="MAFCR1" address="mem:0x10d"/>
<symbol name="MAFSA0L" address="mem:0x10e"/>
<symbol name="MAFSA0H" address="mem:0x10f"/>
<symbol name="MAFPA0L" address="mem:0x110"/>
<symbol name="MAFPA0H" address="mem:0x111"/>
<symbol name="MAFSA1L" address="mem:0x112"/>
<symbol name="MAFSA1H" address="mem:0x113"/>
<symbol name="MAFPA1L" address="mem:0x114"/>
<symbol name="MAFPA1H" address="mem:0x115"/>
<symbol name="MAFSA2L" address="mem:0x116"/>
<symbol name="MAFSA2H" address="mem:0x117"/>
<symbol name="MAFPA2L" address="mem:0x118"/>
<symbol name="MAFPA2H" address="mem:0x119"/>
<symbol name="MAFSA3L" address="mem:0x11a"/>
<symbol name="MAFSA3H" address="mem:0x11b"/>
<symbol name="MAFPA3L" address="mem:0x11c"/>
<symbol name="MAFPA3H" address="mem:0x11d"/>
<symbol name="TCCR5A" address="mem:0x120"/>
<symbol name="TCCR5B" address="mem:0x121"/>
<symbol name="TCCR5C" address="mem:0x122"/>
<symbol name="TCNT5L" address="mem:0x124"/>
<symbol name="TCNT5H" address="mem:0x125"/>
<symbol name="ICR5L" address="mem:0x126"/>
<symbol name="ICR5H" address="mem:0x127"/>
<symbol name="OCR5AL" address="mem:0x128"/>
<symbol name="OCR5AH" address="mem:0x129"/>
<symbol name="OCR5BL" address="mem:0x12a"/>
<symbol name="OCR5BH" address="mem:0x12b"/>
<symbol name="OCR5CL" address="mem:0x12c"/>
<symbol name="OCR5CH" address="mem:0x12d"/>
<symbol name="LLCR" address="mem:0x12f"/>
<symbol name="LLDRL" address="mem:0x130"/>
<symbol name="LLDRH" address="mem:0x131"/>
<symbol name="DRTRAM3" address="mem:0x132"/>
<symbol name="DRTRAM2" address="mem:0x133"/>
<symbol name="DRTRAM1" address="mem:0x134"/>
<symbol name="DRTRAM0" address="mem:0x135"/>
<symbol name="DPDS0" address="mem:0x136"/>
<symbol name="DPDS1" address="mem:0x137"/>
<symbol name="PARCR" address="mem:0x138"/>
<symbol name="TRXPR" address="mem:0x139"/>
<symbol name="AES_CTRL" address="mem:0x13c"/>
<symbol name="AES_STATUS" address="mem:0x13d"/>
<symbol name="AES_STATE" address="mem:0x13e"/>
<symbol name="AES_KEY" address="mem:0x13f"/>
<symbol name="TRX_STATUS" address="mem:0x141"/>
<symbol name="TRX_STATE" address="mem:0x142"/>
<symbol name="TRX_CTRL_0" address="mem:0x143"/>
<symbol name="TRX_CTRL_1" address="mem:0x144"/>
<symbol name="PHY_TX_PWR" address="mem:0x145"/>
<symbol name="PHY_RSSI" address="mem:0x146"/>
<symbol name="PHY_ED_LEVEL" address="mem:0x147"/>
<symbol name="PHY_CC_CCA" address="mem:0x148"/>
<symbol name="CCA_THRES" address="mem:0x149"/>
<symbol name="RX_CTRL" address="mem:0x14a"/>
<symbol name="SFD_VALUE" address="mem:0x14b"/>
<symbol name="TRX_CTRL_2" address="mem:0x14c"/>
<symbol name="ANT_DIV" address="mem:0x14d"/>
<symbol name="IRQ_MASK" address="mem:0x14e"/>
<symbol name="IRQ_STATUS" address="mem:0x14f"/>
<symbol name="VREG_CTRL" address="mem:0x150"/>
<symbol name="BATMON" address="mem:0x151"/>
<symbol name="XOSC_CTRL" address="mem:0x152"/>
<symbol name="CC_CTRL_0" address="mem:0x153"/>
<symbol name="CC_CTRL_1" address="mem:0x154"/>
<symbol name="RX_SYN" address="mem:0x155"/>
<symbol name="TRX_RPC" address="mem:0x156"/>
<symbol name="XAH_CTRL_1" address="mem:0x157"/>
<symbol name="FTN_CTRL" address="mem:0x158"/>
<symbol name="PLL_CF" address="mem:0x15a"/>
<symbol name="PLL_DCU" address="mem:0x15b"/>
<symbol name="PART_NUM" address="mem:0x15c"/>
<symbol name="VERSION_NUM " address="mem:0x15d"/>
<symbol name="MAN_ID_0" address="mem:0x15e"/>
<symbol name="MAN_ID_1" address="mem:0x15f"/>
<symbol name="SHORT_ADDR_0" address="mem:0x160"/>
<symbol name="SHORT_ADDR_1" address="mem:0x161"/>
<symbol name="PAN_ID_0" address="mem:0x162"/>
<symbol name="PAN_ID_1" address="mem:0x163"/>
<symbol name="IEEE_ADDR_0" address="mem:0x164"/>
<symbol name="IEEE_ADDR_1" address="mem:0x165"/>
<symbol name="IEEE_ADDR_2" address="mem:0x166"/>
<symbol name="IEEE_ADDR_3" address="mem:0x167"/>
<symbol name="IEEE_ADDR_4" address="mem:0x168"/>
<symbol name="IEEE_ADDR_5" address="mem:0x169"/>
<symbol name="IEEE_ADDR_6" address="mem:0x16a"/>
<symbol name="IEEE_ADDR_7" address="mem:0x16b"/>
<symbol name="XAH_CTRL_0" address="mem:0x16c"/>
<symbol name="CSMA_SEED_0" address="mem:0x16d"/>
<symbol name="CSMA_SEED_1" address="mem:0x16e"/>
<symbol name="CSMA_BE" address="mem:0x16f"/>
<symbol name="TST_CTRL_DIGI" address="mem:0x176"/>
<symbol name="TST_RX_LENGTH" address="mem:0x17b"/>
<symbol name="TST_AGC" address="mem:0x17c"/>
<symbol name="TST_SDM" address="mem:0x17d"/>
<symbol name="TRXFBST" address="mem:0x180"/>
<symbol name="TRXFBEND" address="mem:0x1ff"/>
</default_symbols>
<default_memory_blocks>
<memory_block name="regalias" start_address="mem:0x00" length="0x20" initialized="false"/>
<memory_block name="iospace" start_address="mem:0x20" length="0x1e0" initialized="false"/>
<memory_block name="sram" start_address="mem:0x200" length="0x4000" initialized="false"/>
<memory_block name="codebyte" start_address="codebyte:0x0" length="0x40000" byte_mapped_address="code:0x0"/>
</default_memory_blocks>
</processor_spec>
<?xml version="1.0" encoding="UTF-8"?>
<processor_spec>
<programcounter register="PC"/>
<data_space space="mem"/>
<!--
- NOTE: The settings within this file may be specific to a particular
- processor variant and will likely need to be changed to reflect
- the specific target processor.
The RAMPx, EIND, SREG registers are not marked volatile, even though they could be changed
indirectly with memory references. If they are made volatile, then the addressing
won't work in decompiler or reference recovery.
Some registers only appear in newer avr8's, or with large memory spaces
-->
<volatile outputop="write_volatile" inputop="read_volatile">
<range space="mem" first="0x20" last="0x57"/>
<range space="mem" first="0x60" last="0xff"/>
</volatile>
<context_data>
<tracked_set space="code">
<set name="R1" val="0"/>
</tracked_set>
</context_data>
<default_symbols>
<symbol name="RESET" address="code:0x0000" entry="true"/>
<symbol name="INT0" address="code:0x0002" entry="true"/>
<symbol name="INT1" address="code:0x0004" entry="true"/>
<symbol name="INT2" address="code:0x0006" entry="true"/>
<symbol name="INT3" address="code:0x0008" entry="true"/>
<symbol name="INT4" address="code:0x000A" entry="true"/>
<symbol name="INT5" address="code:0x000C" entry="true"/>
<symbol name="INT6" address="code:0x000E" entry="true"/>
<symbol name="INT7" address="code:0x0010" entry="true"/>
<symbol name="PCINT0" address="code:0x0012" entry="true"/>
<symbol name="PCINT1" address="code:0x0014" entry="true"/>
<symbol name="PCINT2" address="code:0x0016" entry="true"/>
<symbol name="WDT" address="code:0x0018" entry="true"/>
<symbol name="TIMER2_COMPA" address="code:0x001A" entry="true"/>
<symbol name="TIMER2_COMPB" address="code:0x001C" entry="true"/>
<symbol name="TIMER2_OVF" address="code:0x001E" entry="true"/>
<symbol name="TIMER1_CAPT" address="code:0x0020" entry="true"/>
<symbol name="TIMER1_COMPA" address="code:0x0022" entry="true"/>
<symbol name="TIMER1_COMPB" address="code:0x0024" entry="true"/>
<symbol name="TIMER1_COMPC" address="code:0x0026" entry="true"/>
<symbol name="TIMER1_OVF" address="code:0x0028" entry="true"/>
<symbol name="TIMER0_COMPA" address="code:0x002A" entry="true"/>
<symbol name="TIMER0_COMPB" address="code:0x002C" entry="true"/>
<symbol name="TIMER0_OVF" address="code:0x002E" entry="true"/>
<symbol name="SPI_STC" address="code:0x0030" entry="true"/>
<symbol name="USART0_RX" address="code:0x0032" entry="true"/>
<symbol name="USART0_UDRE" address="code:0x0034" entry="true"/>
<symbol name="USART0_TX" address="code:0x0036" entry="true"/>
<symbol name="ANALOG_COMP" address="code:0x0038" entry="true"/>
<symbol name="ADC_ADC" address="code:0x003A" entry="true"/>
<symbol name="EE_READY" address="code:0x003C" entry="true"/>
<symbol name="TIMER3_CAPT" address="code:0x003E" entry="true"/>
<symbol name="TIMER3_COMPA" address="code:0x0040" entry="true"/>
<symbol name="TIMER3_COMPB" address="code:0x0042" entry="true"/>
<symbol name="TIMER3_COMPC" address="code:0x0044" entry="true"/>
<symbol name="TIMER3_OVF" address="code:0x0046" entry="true"/>
<symbol name="USART1_RX" address="code:0x0048" entry="true"/>
<symbol name="USART1_UDRE" address="code:0x004A" entry="true"/>
<symbol name="USART1_TX" address="code:0x004C" entry="true"/>
<symbol name="TWI" address="code:0x004E" entry="true"/>
<symbol name="SPM_READY" address="code:0x0050" entry="true"/>
<symbol name="TIMER4_CAPT" address="code:0x0052" entry="true"/>
<symbol name="TIMER4_COMPA" address="code:0x0054" entry="true"/>
<symbol name="TIMER4_COMPB" address="code:0x0056" entry="true"/>
<symbol name="TIMER4_COMPC" address="code:0x0058" entry="true"/>
<symbol name="TIMER4_OVF" address="code:0x005A" entry="true"/>
<symbol name="TIMER5_CAPT" address="code:0x005C" entry="true"/>
<symbol name="TIMER5_COMPA" address="code:0x005E" entry="true"/>
<symbol name="TIMER5_COMPB" address="code:0x0060" entry="true"/>
<symbol name="TIMER5_COMPC" address="code:0x0062" entry="true"/>
<symbol name="TIMER5_OVF" address="code:0x0064" entry="true"/>
<symbol name="USART2_RX" address="code:0x0066" entry="true"/>
<symbol name="USART2_UDRE" address="code:0x0068" entry="true"/>
<symbol name="USART2_TX" address="code:0x006A" entry="true"/>
<symbol name="USART3_RX" address="code:0x006C" entry="true"/>
<symbol name="USART3_UDRE" address="code:0x006E" entry="true"/>
<symbol name="USART3_TX" address="code:0x0070" entry="true"/>
<symbol name="PINA" address="mem:0x20"/>
<symbol name="DDRA" address="mem:0x21"/>
<symbol name="PORTA" address="mem:0x22"/>
<symbol name="PINB" address="mem:0x23"/>
<symbol name="DDRB" address="mem:0x24"/>
<symbol name="PORTB" address="mem:0x25"/>
<symbol name="PINC" address="mem:0x26"/>
<symbol name="DDRC" address="mem:0x27"/>
<symbol name="PORTC" address="mem:0x28"/>
<symbol name="PIND" address="mem:0x29"/>
<symbol name="DDRD" address="mem:0x2a"/>
<symbol name="PORTD" address="mem:0x2b"/>
<symbol name="PINE" address="mem:0x2c"/>
<symbol name="DDRE" address="mem:0x2d"/>
<symbol name="PORTE" address="mem:0x2e"/>
<symbol name="PINF" address="mem:0x2f"/>
<symbol name="DDRF" address="mem:0x30"/>
<symbol name="PORTF" address="mem:0x31"/>
<symbol name="PING" address="mem:0x32"/>
<symbol name="DDRG" address="mem:0x33"/>
<symbol name="PORTG" address="mem:0x34"/>
<symbol name="TIFR0" address="mem:0x35"/>
<symbol name="TIFR1" address="mem:0x36"/>
<symbol name="TIFR2" address="mem:0x37"/>
<symbol name="TIFR3" address="mem:0x38"/>
<symbol name="TIFR4" address="mem:0x39"/>
<symbol name="TIFR5" address="mem:0x3a"/>
<symbol name="PCIFR" address="mem:0x3b"/>
<symbol name="EIFR" address="mem:0x3c"/>
<symbol name="EIMSK" address="mem:0x3d"/>
<symbol name="GPIOR0" address="mem:0x3e"/>
<symbol name="EECR" address="mem:0x3f"/>
<symbol name="EEDR" address="mem:0x40"/>
<symbol name="EEARL" address="mem:0x41"/>
<symbol name="EEARH" address="mem:0x42"/>
<symbol name="GTCCR" address="mem:0x43"/>
<symbol name="TCCR0A" address="mem:0x44"/>
<symbol name="TCCR0B" address="mem:0x45"/>
<symbol name="TCNT0" address="mem:0x46"/>
<symbol name="OCR0A" address="mem:0x47"/>
<symbol name="OCR0B" address="mem:0x48"/>
<symbol name="GPIOR1" address="mem:0x4a"/>
<symbol name="GPIOR2" address="mem:0x4b"/>
<symbol name="SPCR" address="mem:0x4c"/>
<symbol name="SPSR" address="mem:0x4d"/>
<symbol name="SPDR" address="mem:0x4e"/>
<symbol name="ACSR" address="mem:0x50"/>
<symbol name="OCDR" address="mem:0x51"/>
<symbol name="SMCR" address="mem:0x53"/>
<symbol name="MCUSR" address="mem:0x54"/>
<symbol name="MCUCR" address="mem:0x55"/>
<symbol name="SPMCSR" address="mem:0x57"/>
<symbol name="RAMPZ" address="mem:0x5b"/>
<symbol name="EIND" address="mem:0x5c"/>
<symbol name="_SPL" address="mem:0x5d"/>
<symbol name="_SPH" address="mem:0x5e"/>
<symbol name="WDTCSR" address="mem:0x60"/>
<symbol name="CLKPR" address="mem:0x61"/>
<symbol name="PRR2" address="mem:0x63"/>
<symbol name="PRR0" address="mem:0x64"/>
<symbol name="PRR1" address="mem:0x65"/>
<symbol name="OSCCAL" address="mem:0x66"/>
<symbol name="BGCR" address="mem:0x67"/>
<symbol name="PCICR" address="mem:0x68"/>
<symbol name="EICRA" address="mem:0x69"/>
<symbol name="EICRB" address="mem:0x6a"/>
<symbol name="PCMSK0" address="mem:0x6b"/>
<symbol name="PCMSK1" address="mem:0x6c"/>
<symbol name="PCMSK2" address="mem:0x6d"/>
<symbol name="TIMSK0" address="mem:0x6e"/>
<symbol name="TIMSK1" address="mem:0x6f"/>
<symbol name="TIMSK2" address="mem:0x70"/>
<symbol name="TIMSK3" address="mem:0x71"/>
<symbol name="TIMSK4" address="mem:0x72"/>
<symbol name="TIMSK5" address="mem:0x73"/>
<symbol name="NEMCR" address="mem:0x75"/>
<symbol name="ADCSRC" address="mem:0x77"/>
<symbol name="ADCL" address="mem:0x78"/>
<symbol name="ADCH" address="mem:0x79"/>
<symbol name="ADCSRA" address="mem:0x7a"/>
<symbol name="ADCSRB" address="mem:0x7b"/>
<symbol name="ADMUX" address="mem:0x7c"/>
<symbol name="DIDR2" address="mem:0x7d"/>
<symbol name="DIDR0" address="mem:0x7e"/>
<symbol name="DIDR1" address="mem:0x7f"/>
<symbol name="TCCR1A" address="mem:0x80"/>
<symbol name="TCCR1B" address="mem:0x81"/>
<symbol name="TCCR1C" address="mem:0x82"/>
<symbol name="TCNT1L" address="mem:0x84"/>
<symbol name="TCNT1H" address="mem:0x85"/>
<symbol name="ICR1L" address="mem:0x86"/>
<symbol name="ICR1H" address="mem:0x87"/>
<symbol name="OCR1AL" address="mem:0x88"/>
<symbol name="OCR1AH" address="mem:0x89"/>
<symbol name="OCR1BL" address="mem:0x8a"/>
<symbol name="OCR1BH" address="mem:0x8b"/>
<symbol name="OCR1CL" address="mem:0x8c"/>
<symbol name="OCR1CH" address="mem:0x8d"/>
<symbol name="TCCR3A" address="mem:0x90"/>
<symbol name="TCCR3B" address="mem:0x91"/>
<symbol name="TCCR3C" address="mem:0x92"/>
<symbol name="TCNT3L" address="mem:0x94"/>
<symbol name="TCNT3H" address="mem:0x95"/>
<symbol name="ICR3L" address="mem:0x96"/>
<symbol name="ICR3H" address="mem:0x97"/>
<symbol name="OCR3AL" address="mem:0x98"/>
<symbol name="OCR3AH" address="mem:0x99"/>
<symbol name="OCR3BL" address="mem:0x9a"/>
<symbol name="OCR3BH" address="mem:0x9b"/>
<symbol name="OCR3CL" address="mem:0x9c"/>
<symbol name="OCR3CH" address="mem:0x9d"/>
<symbol name="TCCR4A" address="mem:0xa0"/>
<symbol name="TCCR4B" address="mem:0xa1"/>
<symbol name="TCCR4C" address="mem:0xa2"/>
<symbol name="TCNT4L" address="mem:0xa4"/>
<symbol name="TCNT4H" address="mem:0xa5"/>
<symbol name="ICR4L" address="mem:0xa6"/>
<symbol name="ICR4H" address="mem:0xa7"/>
<symbol name="OCR4AL" address="mem:0xa8"/>
<symbol name="OCR4AH" address="mem:0xa9"/>
<symbol name="OCR4BL" address="mem:0xaa"/>
<symbol name="OCR4BH" address="mem:0xab"/>
<symbol name="OCR4CL" address="mem:0xac"/>
<symbol name="OCR4CH" address="mem:0xad"/>
<symbol name="TCCR2A" address="mem:0xb0"/>
<symbol name="TCCR2B" address="mem:0xb1"/>
<symbol name="TCNT2" address="mem:0xb2"/>
<symbol name="OCR2A" address="mem:0xb3"/>
<symbol name="OCR2B" address="mem:0xb4"/>
<symbol name="ASSR" address="mem:0xb6"/>
<symbol name="TWBR" address="mem:0xb8"/>
<symbol name="TWSR" address="mem:0xb9"/>
<symbol name="TWAR" address="mem:0xba"/>
<symbol name="TWDR" address="mem:0xbb"/>
<symbol name="TWCR" address="mem:0xbc"/>
<symbol name="TWAMR" address="mem:0xbd"/>
<symbol name="IRQ_MASK1" address="mem:0xbe"/>
<symbol name="IRQ_STATUS1" address="mem:0xbf"/>
<symbol name="UCSR0A" address="mem:0xc0"/>
<symbol name="UCSR0B" address="mem:0xc1"/>
<symbol name="UCSR0C" address="mem:0xc2"/>
<symbol name="UBRR0L" address="mem:0xc4"/>
<symbol name="UBRR0H" address="mem:0xc5"/>
<symbol name="UDR0" address="mem:0xc6"/>
<symbol name="UCSR1A" address="mem:0xc8"/>
<symbol name="UCSR1B" address="mem:0xc9"/>
<symbol name="UCSR1C" address="mem:0xca"/>
<symbol name="UBRR1L" address="mem:0xcc"/>
<symbol name="UBRR1H" address="mem:0xcd"/>
<symbol name="UDR1" address="mem:0xce"/>
<symbol name="UCSR2A" address="mem:0xd0"/>
<symbol name="UCSR2B" address="mem:0xd1"/>
<symbol name="UCSR2C" address="mem:0xd2"/>
<symbol name="SCRSTRLL" address="mem:0xd7"/>
<symbol name="SCRSTRLH " address="mem:0xd8"/>
<symbol name="SCRSTRHL" address="mem:0xd9"/>
<symbol name="SCRSTRHH" address="mem:0xda"/>
<symbol name="SCCSR" address="mem:0xdb"/>
<symbol name="SCCR0 " address="mem:0xdc"/>
<symbol name="SCCR1" address="mem:0xdd"/>
<symbol name="SCSR" address="mem:0xde"/>
<symbol name="SCIRQM" address="mem:0xdf"/>
<symbol name="SCIRQS" address="mem:0xe0"/>
<symbol name="SCCNTLL " address="mem:0xe1"/>
<symbol name="SCCNTLH" address="mem:0xe2"/>
<symbol name="SCCNTHL" address="mem:0xe3"/>
<symbol name="SCCNTHH" address="mem:0xe4"/>
<symbol name="SCBTSRLL " address="mem:0xe5"/>
<symbol name="SCBTSRLH" address="mem:0xe6"/>
<symbol name="SCBTSRHL" address="mem:0xe7"/>
<symbol name="SCBTSRHH" address="mem:0xe8"/>
<symbol name="SCTSRLL" address="mem:0xe9"/>
<symbol name="SCTSRLH" address="mem:0xea"/>
<symbol name="SCTSRHL" address="mem:0xeb"/>
<symbol name="SCTSRHH" address="mem:0xec"/>
<symbol name="SCOCR3LL" address="mem:0xed"/>
<symbol name="SCOCR3LH" address="mem:0xee"/>
<symbol name="SCOCR3HL" address="mem:0xef"/>
<symbol name="SCOCR3HH" address="mem:0xf0"/>
<symbol name="SCOCR2LL " address="mem:0xf1"/>
<symbol name="SCOCR2LH" address="mem:0xf2"/>
<symbol name="SCOCR2HL" address="mem:0xf3"/>
<symbol name="SCOCR2HH" address="mem:0xf4"/>
<symbol name="SCOCR1LL " address="mem:0xf5"/>
<symbol name="SCOCR1LH" address="mem:0xf6"/>
<symbol name="SCOCR1HL" address="mem:0xf7"/>
<symbol name="SCOCR1HH" address="mem:0xf8"/>
<symbol name="SCTSTRLL" address="mem:0xf9"/>
<symbol name="SCTSTRLH" address="mem:0xfa"/>
<symbol name="SCTSTRHL" address="mem:0xfb"/>
<symbol name="SCTSTRHH" address="mem:0xfc"/>
<symbol name="MAFCR0" address="mem:0x10c"/>
<symbol name="MAFCR1" address="mem:0x10d"/>
<symbol name="MAFSA0L" address="mem:0x10e"/>
<symbol name="MAFSA0H" address="mem:0x10f"/>
<symbol name="MAFPA0L" address="mem:0x110"/>
<symbol name="MAFPA0H" address="mem:0x111"/>
<symbol name="MAFSA1L" address="mem:0x112"/>
<symbol name="MAFSA1H" address="mem:0x113"/>
<symbol name="MAFPA1L" address="mem:0x114"/>
<symbol name="MAFPA1H" address="mem:0x115"/>
<symbol name="MAFSA2L" address="mem:0x116"/>
<symbol name="MAFSA2H" address="mem:0x117"/>
<symbol name="MAFPA2L" address="mem:0x118"/>
<symbol name="MAFPA2H" address="mem:0x119"/>
<symbol name="MAFSA3L" address="mem:0x11a"/>
<symbol name="MAFSA3H" address="mem:0x11b"/>
<symbol name="MAFPA3L" address="mem:0x11c"/>
<symbol name="MAFPA3H" address="mem:0x11d"/>
<symbol name="TCCR5A" address="mem:0x120"/>
<symbol name="TCCR5B" address="mem:0x121"/>
<symbol name="TCCR5C" address="mem:0x122"/>
<symbol name="TCNT5L" address="mem:0x124"/>
<symbol name="TCNT5H" address="mem:0x125"/>
<symbol name="ICR5L" address="mem:0x126"/>
<symbol name="ICR5H" address="mem:0x127"/>
<symbol name="OCR5AL" address="mem:0x128"/>
<symbol name="OCR5AH" address="mem:0x129"/>
<symbol name="OCR5BL" address="mem:0x12a"/>
<symbol name="OCR5BH" address="mem:0x12b"/>
<symbol name="OCR5CL" address="mem:0x12c"/>
<symbol name="OCR5CH" address="mem:0x12d"/>
<symbol name="LLCR" address="mem:0x12f"/>
<symbol name="LLDRL" address="mem:0x130"/>
<symbol name="LLDRH" address="mem:0x131"/>
<symbol name="DRTRAM3" address="mem:0x132"/>
<symbol name="DRTRAM2" address="mem:0x133"/>
<symbol name="DRTRAM1" address="mem:0x134"/>
<symbol name="DRTRAM0" address="mem:0x135"/>
<symbol name="DPDS0" address="mem:0x136"/>
<symbol name="DPDS1" address="mem:0x137"/>
<symbol name="PARCR" address="mem:0x138"/>
<symbol name="TRXPR" address="mem:0x139"/>
<symbol name="AES_CTRL" address="mem:0x13c"/>
<symbol name="AES_STATUS" address="mem:0x13d"/>
<symbol name="AES_STATE" address="mem:0x13e"/>
<symbol name="AES_KEY" address="mem:0x13f"/>
<symbol name="TRX_STATUS" address="mem:0x141"/>
<symbol name="TRX_STATE" address="mem:0x142"/>
<symbol name="TRX_CTRL_0" address="mem:0x143"/>
<symbol name="TRX_CTRL_1" address="mem:0x144"/>
<symbol name="PHY_TX_PWR" address="mem:0x145"/>
<symbol name="PHY_RSSI" address="mem:0x146"/>
<symbol name="PHY_ED_LEVEL" address="mem:0x147"/>
<symbol name="PHY_CC_CCA" address="mem:0x148"/>
<symbol name="CCA_THRES" address="mem:0x149"/>
<symbol name="RX_CTRL" address="mem:0x14a"/>
<symbol name="SFD_VALUE" address="mem:0x14b"/>
<symbol name="TRX_CTRL_2" address="mem:0x14c"/>
<symbol name="ANT_DIV" address="mem:0x14d"/>
<symbol name="IRQ_MASK" address="mem:0x14e"/>
<symbol name="IRQ_STATUS" address="mem:0x14f"/>
<symbol name="VREG_CTRL" address="mem:0x150"/>
<symbol name="BATMON" address="mem:0x151"/>
<symbol name="XOSC_CTRL" address="mem:0x152"/>
<symbol name="CC_CTRL_0" address="mem:0x153"/>
<symbol name="CC_CTRL_1" address="mem:0x154"/>
<symbol name="RX_SYN" address="mem:0x155"/>
<symbol name="TRX_RPC" address="mem:0x156"/>
<symbol name="XAH_CTRL_1" address="mem:0x157"/>
<symbol name="FTN_CTRL" address="mem:0x158"/>
<symbol name="PLL_CF" address="mem:0x15a"/>
<symbol name="PLL_DCU" address="mem:0x15b"/>
<symbol name="PART_NUM" address="mem:0x15c"/>
<symbol name="VERSION_NUM " address="mem:0x15d"/>
<symbol name="MAN_ID_0" address="mem:0x15e"/>
<symbol name="MAN_ID_1" address="mem:0x15f"/>
<symbol name="SHORT_ADDR_0" address="mem:0x160"/>
<symbol name="SHORT_ADDR_1" address="mem:0x161"/>
<symbol name="PAN_ID_0" address="mem:0x162"/>
<symbol name="PAN_ID_1" address="mem:0x163"/>
<symbol name="IEEE_ADDR_0" address="mem:0x164"/>
<symbol name="IEEE_ADDR_1" address="mem:0x165"/>
<symbol name="IEEE_ADDR_2" address="mem:0x166"/>
<symbol name="IEEE_ADDR_3" address="mem:0x167"/>
<symbol name="IEEE_ADDR_4" address="mem:0x168"/>
<symbol name="IEEE_ADDR_5" address="mem:0x169"/>
<symbol name="IEEE_ADDR_6" address="mem:0x16a"/>
<symbol name="IEEE_ADDR_7" address="mem:0x16b"/>
<symbol name="XAH_CTRL_0" address="mem:0x16c"/>
<symbol name="CSMA_SEED_0" address="mem:0x16d"/>
<symbol name="CSMA_SEED_1" address="mem:0x16e"/>
<symbol name="CSMA_BE" address="mem:0x16f"/>
<symbol name="TST_CTRL_DIGI" address="mem:0x176"/>
<symbol name="TST_RX_LENGTH" address="mem:0x17b"/>
<symbol name="TST_AGC" address="mem:0x17c"/>
<symbol name="TST_SDM" address="mem:0x17d"/>
<symbol name="TRXFBST" address="mem:0x180"/>
<symbol name="TRXFBEND" address="mem:0x1ff"/>
</default_symbols>
<default_memory_blocks>
<memory_block name="regalias" start_address="mem:0x00" length="0x20" initialized="false"/>
<memory_block name="iospace" start_address="mem:0x20" length="0x1e0" initialized="false"/>
<memory_block name="sram" start_address="mem:0x200" length="0x4000" initialized="false"/>
<memory_block name="codebyte" start_address="codebyte:0x0" length="0x40000" byte_mapped_address="code:0x0"/>
</default_memory_blocks>
</processor_spec>
python/icicle/Ghidra/Processors/Atmel/data/languages/avr32.opinion
+6 -6
View File
@@ -1,6 +1,6 @@
<opinions>
<constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default">
<constraint primary="6317" processor="AVR32" endian="big" size="32" />
<constraint primary="185" processor="AVR32" endian="big" size="32" />
</constraint>
</opinions>
<opinions>
<constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default">
<constraint primary="6317" processor="AVR32" endian="big" size="32" />
<constraint primary="185" processor="AVR32" endian="big" size="32" />
</constraint>
</opinions>
python/icicle/Ghidra/Processors/Atmel/data/languages/avr32a.cspec
+53 -53
View File
@@ -1,53 +1,53 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<global>
<range space="RAM"/>
</global>
<stackpointer register="SP" space="RAM"/>
<default_proto>
<prototype name="__stdcall" extrapop="unknown" stackshift="4">
<input>
<pentry minsize="1" maxsize="4">
<register name="R12"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="R11"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="R10"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="R9"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="R8"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="0" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4">
<register name="R12"/>
</pentry>
</output>
<unaffected>
<varnode space="RAM" offset="0" size="4"/>
<register name="SP"/>
<register name="LR"/>
<register name="R0"/>
<register name="R1"/>
<register name="R2"/>
<register name="R3"/>
<register name="R4"/>
<register name="R5"/>
<register name="R6"/>
<register name="R7"/>
</unaffected>
<killedbycall>
<register name="Z"/>
</killedbycall>
</prototype>
</default_proto>
</compiler_spec>
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<global>
<range space="RAM"/>
</global>
<stackpointer register="SP" space="RAM"/>
<default_proto>
<prototype name="__stdcall" extrapop="unknown" stackshift="4">
<input>
<pentry minsize="1" maxsize="4">
<register name="R12"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="R11"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="R10"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="R9"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="R8"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="0" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4">
<register name="R12"/>
</pentry>
</output>
<unaffected>
<varnode space="RAM" offset="0" size="4"/>
<register name="SP"/>
<register name="LR"/>
<register name="R0"/>
<register name="R1"/>
<register name="R2"/>
<register name="R3"/>
<register name="R4"/>
<register name="R5"/>
<register name="R6"/>
<register name="R7"/>
</unaffected>
<killedbycall>
<register name="Z"/>
</killedbycall>
</prototype>
</default_proto>
</compiler_spec>

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