diff --git a/.gitattributes b/.gitattributes
new file mode 100644
index 0000000..36ab773
--- /dev/null
+++ b/.gitattributes
@@ -0,0 +1 @@
+python/Ghidra/** linguist-generated
\ No newline at end of file
diff --git a/.github/workflows/CI.yml b/.github/workflows/CI.yml
index 8ca982d..dff158a 100644
--- a/.github/workflows/CI.yml
+++ b/.github/workflows/CI.yml
@@ -1,111 +1,124 @@
-# This file is autogenerated by maturin v1.0.1
-# To update, run
-#
-# maturin generate-ci github
-#
name: CI
-on:
- push:
- branches:
- - main
- - master
- tags:
- - '*'
- pull_request:
- workflow_dispatch:
-
-permissions:
- contents: read
+on: [push, pull_request]
jobs:
- linux:
- runs-on: ubuntu-latest
- strategy:
- matrix:
- target: [x86_64, aarch64]
- steps:
- - uses: actions/checkout@v3
- with:
- submodules: 'true'
- - uses: actions/setup-python@v4
- with:
- python-version: '3.10'
- - name: Build wheels
- uses: PyO3/maturin-action@v1
- with:
- target: ${{ matrix.target }}
- args: --release --out dist --find-interpreter
- sccache: 'true'
- manylinux: auto
- - name: Upload wheels
- uses: actions/upload-artifact@v3
- with:
- name: wheels
- path: dist
+ # linux:
+ # runs-on: ubuntu-latest
+ # strategy:
+ # matrix:
+ # target: [x86_64, aarch64]
+ # steps:
+ # - uses: actions/checkout@v3
+ # with:
+ # submodules: 'true'
+
+ # - uses: actions/setup-python@v4
+ # with:
+ # python-version: '3.10'
+
+ # - name: Install Rust toolchain
+ # uses: dtolnay/rust-toolchain@stable
+ # with:
+ # targets: aarch64-linux-gnu, x86-64-linux-gnu
- windows:
- runs-on: windows-latest
- strategy:
- matrix:
- target: [x64]
- steps:
- - uses: actions/checkout@v3
- with:
- submodules: 'true'
- - uses: actions/setup-python@v4
- with:
- python-version: '3.10'
- architecture: ${{ matrix.target }}
- - name: Build wheels
- uses: PyO3/maturin-action@v1
- with:
- target: ${{ matrix.target }}
- args: --release --out dist --find-interpreter
- sccache: 'true'
- - name: Upload wheels
- uses: actions/upload-artifact@v3
- with:
- name: wheels
- path: dist
+ # - name: Install Rust aarch64-apple-darwin target
+ # if: matrix.platform.os == 'macos-latest'
+ # run: rustup target add aarch64-apple-darwin
+
+ # - name: Upload wheels
+ # uses: actions/upload-artifact@v3
+ # with:
+ # name: wheels
+ # path: dist
+
+ # windows:
+ # runs-on: windows-latest
+ # strategy:
+ # matrix:
+ # target: [x64]
+ # steps:
+ # - uses: actions/checkout@v3
+ # with:
+ # submodules: 'true'
+
+ # - uses: actions/setup-python@v4
+ # with:
+ # python-version: '3.10'
+ # architecture: ${{ matrix.target }}
+
+ # - name: Build wheels
+ # uses: PyO3/maturin-action@v1
+ # with:
+ # target: ${{ matrix.target }}
+ # args: --release --out dist --find-interpreter
+ # sccache: 'true'
+
+ # - name: Upload wheels
+ # uses: actions/upload-artifact@v3
+ # with:
+ # name: wheels
+ # path: dist
macos:
+ # Skip building pull requests from the same repository
+ if: ${{ github.event_name == 'push' || (github.event_name == 'pull_request' && github.event.pull_request.head.repo.full_name != github.repository) }}
runs-on: macos-latest
- strategy:
- matrix:
- target: [x86_64, aarch64]
steps:
- - uses: actions/checkout@v3
+ - name: Checkout
+ uses: actions/checkout@v3
with:
submodules: 'true'
- - uses: actions/setup-python@v4
+
+ - name: Python environment
+ uses: actions/setup-python@v4
with:
python-version: '3.10'
- - name: Build wheels
- uses: PyO3/maturin-action@v1
+
+ - name: Install Rust toolchain
+ uses: dtolnay/rust-toolchain@stable
with:
- target: ${{ matrix.target }}
- args: --release --out dist --find-interpreter
- sccache: 'true'
+ targets: aarch64-apple-darwin, x86_64-apple-darwin
+
+ - name: Build
+ shell: bash
+ env:
+ DEVELOPER_DIR: /Applications/Xcode.app/Contents/Developer
+ MACOSX_DEPLOYMENT_TARGET: '10.9'
+ ARCHFLAGS: -arch x86_64 -arch arm64
+ PYO3_CROSS_LIB_DIR: /Applications/Xcode.app/Contents/Developer/Library/Frameworks/Python3.framework/Versions/3.8/lib
+ run: |
+ pip install -r requirements.txt
+ python setup.py bdist_wheel --py-limited-api=cp37
+ pip install --force-reinstall dist/*_universal2.whl
+ python -c "import icicle"
+
+ - name: Test
+ run: |
+ pip install -r tests/requirements.txt
+ python tests/example.py
+ python tests/invalid.py
+
- name: Upload wheels
uses: actions/upload-artifact@v3
with:
name: wheels
path: dist
- release:
- name: Release
- runs-on: ubuntu-latest
- if: "startsWith(github.ref, 'refs/tags/')"
- needs: [linux, windows, macos]
- steps:
- - uses: actions/download-artifact@v3
- with:
- name: wheels
- - name: Publish to PyPI
- uses: PyO3/maturin-action@v1
- env:
- MATURIN_PYPI_TOKEN: ${{ secrets.PYPI_API_TOKEN }}
- with:
- command: upload
- args: --skip-existing *
+
+ # release:
+ # name: Release
+ # runs-on: ubuntu-latest
+ # if: "startsWith(github.ref, 'refs/tags/')"
+ # needs: [linux, windows, macos]
+ # steps:
+ # - uses: actions/download-artifact@v3
+ # with:
+ # name: wheels
+ # - name: Publish to PyPI
+ # uses: PyO3/maturin-action@v1
+ # env:
+ # MATURIN_PYPI_TOKEN: ${{ secrets.PYPI_API_TOKEN }}
+ # with:
+ # command: upload
+ # args: --skip-existing *
diff --git a/.gitignore b/.gitignore
index cc16070..00aa120 100644
--- a/.gitignore
+++ b/.gitignore
@@ -5,4 +5,10 @@ debug/
venv*/
.env/
dist/
-.DS_Store
\ No newline at end of file
+build/
+.DS_Store
+__pycache__/
+*.egg-info/
+*.so
+*.dll
+*.dylib
\ No newline at end of file
diff --git a/Cargo.lock b/Cargo.lock
index 2cf8cfc..387e20d 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -321,7 +321,7 @@ dependencies = [
"cranelift-module",
"cranelift-native",
"icicle-cpu",
- "memoffset",
+ "memoffset 0.8.0",
"pcode",
"target-lexicon",
"tracing",
@@ -463,6 +463,15 @@ dependencies = [
"autocfg",
]
+[[package]]
+name = "memoffset"
+version = "0.9.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5a634b1c61a95585bd15607c6ab0c4e5b226e695ff2800ba0cdccddf208c406c"
+dependencies = [
+ "autocfg",
+]
+
[[package]]
name = "miniz_oxide"
version = "0.7.1"
@@ -552,15 +561,15 @@ dependencies = [
[[package]]
name = "pyo3"
-version = "0.18.3"
+version = "0.19.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e3b1ac5b3731ba34fdaa9785f8d74d17448cd18f30cf19e0c7e7b1fdb5272109"
+checksum = "e681a6cfdc4adcc93b4d3cf993749a4552018ee0a9b65fc0ccfad74352c72a38"
dependencies = [
"cfg-if",
"indexmap",
"indoc",
"libc",
- "memoffset",
+ "memoffset 0.9.0",
"parking_lot",
"pyo3-build-config",
"pyo3-ffi",
@@ -570,9 +579,9 @@ dependencies = [
[[package]]
name = "pyo3-build-config"
-version = "0.18.3"
+version = "0.19.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9cb946f5ac61bb61a5014924910d936ebd2b23b705f7a4a3c40b05c720b079a3"
+checksum = "076c73d0bc438f7a4ef6fdd0c3bb4732149136abd952b110ac93e4edb13a6ba5"
dependencies = [
"once_cell",
"target-lexicon",
@@ -580,9 +589,9 @@ dependencies = [
[[package]]
name = "pyo3-ffi"
-version = "0.18.3"
+version = "0.19.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "fd4d7c5337821916ea2a1d21d1092e8443cf34879e53a0ac653fbb98f44ff65c"
+checksum = "e53cee42e77ebe256066ba8aa77eff722b3bb91f3419177cf4cd0f304d3284d9"
dependencies = [
"libc",
"pyo3-build-config",
@@ -590,9 +599,9 @@ dependencies = [
[[package]]
name = "pyo3-macros"
-version = "0.18.3"
+version = "0.19.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a9d39c55dab3fc5a4b25bbd1ac10a2da452c4aca13bb450f22818a002e29648d"
+checksum = "dfeb4c99597e136528c6dd7d5e3de5434d1ceaf487436a3f03b2d56b6fc9efd1"
dependencies = [
"proc-macro2",
"pyo3-macros-backend",
@@ -602,9 +611,9 @@ dependencies = [
[[package]]
name = "pyo3-macros-backend"
-version = "0.18.3"
+version = "0.19.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "97daff08a4c48320587b5224cc98d609e3c27b6d437315bd40b605c98eeb5918"
+checksum = "947dc12175c254889edc0c02e399476c2f652b4b9ebd123aa655c224de259536"
dependencies = [
"proc-macro2",
"quote",
diff --git a/Cargo.toml b/Cargo.toml
index 554d28b..1308565 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -15,10 +15,10 @@ icicle-vm = { path = "icicle-emu/icicle-vm" }
pcode = { path = "icicle-emu/sleigh/pcode" }
sleigh-runtime = { path = "icicle-emu/sleigh/sleigh-runtime" }
indexmap = "1.9.3"
-pyo3 = { version = "0.18.3", features = ["extension-module", "indexmap"] }
+pyo3 = { version = "0.19.2", features = ["extension-module", "indexmap", "abi3-py37"] }
target-lexicon = "0.12.7"
tracing = "*"
tracing-subscriber = "0.3.17"
[build-dependencies]
-pyo3-build-config = "0.18.3"
+pyo3-build-config = "0.19.2"
diff --git a/LICENSE b/LICENSE
new file mode 100644
index 0000000..127a5bc
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,23 @@
+Boost Software License - Version 1.0 - August 17th, 2003
+
+Permission is hereby granted, free of charge, to any person or organization
+obtaining a copy of the software and accompanying documentation covered by
+this license (the "Software") to use, reproduce, display, distribute,
+execute, and transmit the Software, and to prepare derivative works of the
+Software, and to permit third-parties to whom the Software is furnished to
+do so, all subject to the following:
+
+The copyright notices in the Software and this entire statement, including
+the above license grant, this restriction and the following disclaimer,
+must be included in all copies of the Software, in whole or in part, and
+all derivative works of the Software, unless such copies or derivative
+works are solely in the form of machine-executable object code generated by
+a source language processor.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.
\ No newline at end of file
diff --git a/MANIFEST.in b/MANIFEST.in
new file mode 100644
index 0000000..2bbea80
--- /dev/null
+++ b/MANIFEST.in
@@ -0,0 +1,12 @@
+include Cargo.lock
+include Cargo.toml
+include README.md
+include build.rs
+include requirements.txt
+include copy-ghidra.py
+recursive-include src *
+recursive-include icicle-emu *
+recursive-include python *.py
+recursive-include python *.pyi
+recursive-include python py.typed
+recursive-include python/icicle/Ghidra *
\ No newline at end of file
diff --git a/copy-ghidra.py b/copy-ghidra.py
new file mode 100644
index 0000000..15f5099
--- /dev/null
+++ b/copy-ghidra.py
@@ -0,0 +1,39 @@
+from os import makedirs
+from pathlib import Path
+from shutil import copytree, rmtree
+from argparse import ArgumentParser
+
+def main():
+ parser = ArgumentParser()
+ parser.add_argument("ghidra_src", help="Path to the Ghidra source code")
+ args = parser.parse_args()
+ ghidra_src = Path(args.ghidra_src)
+ if not ghidra_src.is_dir():
+ raise FileNotFoundError(f"Not a directory: {ghidra_src}")
+ processors = ghidra_src.joinpath("Ghidra", "Processors")
+ if not ghidra_src.is_dir():
+ raise FileNotFoundError(f"Not found: {processors}")
+ target_root = Path.cwd().joinpath("python", "icicle", "Ghidra", "Processors")
+ if target_root.exists():
+ rmtree(target_root)
+ for processor in processors.glob("*"):
+ if not processor.is_dir():
+ continue
+ name = processor.name
+ languages = processor.joinpath("data", "languages")
+ if not languages.is_dir():
+ print(f"Processor skipped: {name}")
+ continue
+ print(f"Processor: {name}")
+ processor_root = target_root.joinpath(name, "data", "languages")
+ copytree(languages, processor_root, dirs_exist_ok=True)
+ continue
+ for file in languages.glob("*"):
+ if not file.is_file():
+ print(f"Skip: {file}")
+ continue
+ destination = processor_root.joinpath(file.name)
+ print(f"Copy {file} -> {destination}")
+
+if __name__ == "__main__":
+ main()
\ No newline at end of file
diff --git a/pyproject.toml b/pyproject.toml
index a8ecb6a..c620797 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -1,15 +1,7 @@
[build-system]
-requires = ["maturin>=1.0,<2.0"]
-build-backend = "maturin"
-
-[project]
-name = "icicle-emu"
-requires-python = ">=3.7"
-classifiers = [
- "Programming Language :: Rust",
- "Programming Language :: Python :: Implementation :: CPython",
- "Programming Language :: Python :: Implementation :: PyPy",
+requires = [
+ "setuptools",
+ "wheel",
+ "setuptools-rust",
]
-
-[tool.maturin]
-features = ["pyo3/extension-module"]
+build-backend = "setuptools.build_meta"
\ No newline at end of file
diff --git a/python/icicle/Ghidra/Processors/6502/data/languages/6502.cspec b/python/icicle/Ghidra/Processors/6502/data/languages/6502.cspec
new file mode 100644
index 0000000..315970d
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/6502/data/languages/6502.cspec
@@ -0,0 +1,34 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/python/icicle/Ghidra/Processors/6502/data/languages/6502.ldefs b/python/icicle/Ghidra/Processors/6502/data/languages/6502.ldefs
new file mode 100644
index 0000000..bd51b55
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/6502/data/languages/6502.ldefs
@@ -0,0 +1,33 @@
+
+
+
+
+
+ 6502 Microcontroller Family
+
+
+
+
+
+ 65C02 Microcontroller Family
+
+
+
+
+
diff --git a/python/icicle/Ghidra/Processors/6502/data/languages/6502.pspec b/python/icicle/Ghidra/Processors/6502/data/languages/6502.pspec
new file mode 100644
index 0000000..b44a7e4
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/6502/data/languages/6502.pspec
@@ -0,0 +1,16 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/python/icicle/Ghidra/Processors/6502/data/languages/6502.slaspec b/python/icicle/Ghidra/Processors/6502/data/languages/6502.slaspec
new file mode 100644
index 0000000..4b3b4cd
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/6502/data/languages/6502.slaspec
@@ -0,0 +1,499 @@
+# sleigh specification file for MOS 6502
+
+define endian=little;
+define alignment=1;
+
+define space RAM type=ram_space size=2 default;
+define space register type=register_space size=1;
+
+define register offset=0x00 size=1 [ A X Y P ];
+define register offset=0x20 size=2 [ PC SP ];
+define register offset=0x20 size=1 [ PCL PCH S SH ];
+define register offset=0x30 size=1 [ N V B D I Z C ]; # status bits
+
+#TOKENS
+
+define token opbyte (8)
+ op = (0,7)
+
+ aaa = (5,7)
+ bbb = (2,4)
+ cc = (0,1)
+;
+
+define token data8 (8)
+ imm8 = (0,7)
+ rel = (0,7) signed
+;
+
+define token data (16)
+ imm16 = (0,15)
+;
+
+macro popSR() {
+ SP = SP + 1;
+ local ccr = *:1 SP;
+ N = ccr[7,1];
+ V = ccr[6,1];
+ B = ccr[4,1];
+ D = ccr[3,1];
+ I = ccr[2,1];
+ Z = ccr[1,1];
+ C = ccr[0,1];
+}
+
+macro pushSR() {
+ local ccr:1 = 0xff;
+ ccr[7,1] = N;
+ ccr[6,1] = V;
+ ccr[4,1] = B;
+ ccr[3,1] = D;
+ ccr[2,1] = I;
+ ccr[1,1] = Z;
+ ccr[0,1] = C;
+ *:1 (SP) = ccr;
+ SP = SP -1;
+}
+
+macro resultFlags(value) {
+ Z = (value == 0);
+ N = (value s< 0);
+}
+
+macro subtraction_flags1(register, operand, result) {
+ local complement_register = ~register;
+
+ V = ( ((register & ~operand & ~result) | (complement_register & operand & result)) & 0b10000000 ) != 0;
+ N = (result s< 0);
+ Z = (result == 0);
+ C = ( ((complement_register & operand) | (operand & result) | (result & complement_register)) & 0b10000000 ) != 0;
+}
+
+
+################################################################
+# Pseudo Instructions
+################################################################
+
+define pcodeop readIRQ;
+
+################################################################
+REL: reloc is rel [ reloc = inst_next + rel; ] { export *:2 reloc; }
+
+# Immediate
+OP1: "#"imm8 is bbb=2; imm8 { tmp:1 = imm8; export tmp; }
+# Zero Page
+OP1: imm8 is bbb=1; imm8 { export *:1 imm8; }
+# Zero Page Indexed X
+OP1: imm8,X is bbb=5 & X; imm8 { tmp:2 = zext(imm8 + X); export *:1 tmp; }
+# Absolute
+OP1: imm16 is bbb=3; imm16 { export *:1 imm16; }
+# Absolute Indexed X
+OP1: imm16,X is bbb=7 & X; imm16 { tmp:2 = imm16 + zext(X); export *:1 tmp; }
+# Absolute Indexed Y
+OP1: imm16,Y is bbb=6 & Y; imm16 { tmp:2 = imm16 + zext(Y); export *:1 tmp; }
+# Indirect X
+OP1: (imm8,X) is bbb=0 & X; imm8 { addr:2 = zext(imm8 + X); tmp:2 = *:2 addr; export *:1 tmp; }
+# Indirect Y
+OP1: (imm8),Y is bbb=4 & Y; imm8 { addr:2 = imm8; tmp:2 = *:2 addr; tmp = tmp + zext(Y); export *:1 tmp; }
+
+# Immediate
+OP2: "#"imm8 is bbb=0; imm8 { tmp:1 = imm8; export tmp; }
+# Zero Page
+OP2: imm8 is bbb=1; imm8 { export *:1 imm8; }
+OP2: A is bbb=2 & A { export A; }
+# Absolute
+OP2: imm16 is bbb=3; imm16 { export *:1 imm16; }
+# Zero Page Indexed X
+OP2: imm8,X is bbb=5 & X; imm8 { tmp:2 = zext(imm8 + X); export *:1 tmp; }
+# Absolute Indexed X
+OP2: imm16,X is bbb=7 & X; imm16 { tmp:2 = imm16 + zext(X); export *:1 tmp; }
+
+OP2ST: OP2 is OP2 { export OP2; }
+OP2ST: imm8,Y is bbb=5 & Y; imm8 { tmp:2 = zext(imm8 + Y); export *:1 tmp; }
+
+OP2LD: OP2 is OP2 { export OP2; }
+OP2LD: imm8,Y is bbb=5 & Y; imm8 { tmp:2 = zext(imm8 + Y); export *:1 tmp; }
+OP2LD: imm16,Y is bbb=7 & Y; imm16 { tmp:2 = imm16 + zext(Y); export *:1 tmp; }
+
+
+ADDR8: imm8 is imm8 { export *:1 imm8; }
+ADDR16: imm16 is imm16 { export *:1 imm16; }
+ADDRI: (imm16) is imm16 { tmp:2 = imm16; export *:2 tmp; }
+
+
+# Instructions
+
+
+:ADC OP1 is (cc=1 & aaa=3) ... & OP1
+{
+ local op1 = OP1;
+ local tmpC = C;
+
+ C = carry(A, op1);
+
+ A = A + op1 + tmpC;
+
+ resultFlags(A);
+ V = C;
+}
+
+:AND OP1 is (cc=1 & aaa=1) ... & OP1
+{
+ A = A & OP1;
+ resultFlags(A);
+}
+
+:ASL OP2 is (op=0x06 | op=0x0A | op=0x0E | op=0x16 | op=0x1E) ... & OP2
+{
+ local tmp = OP2;
+ C = tmp >> 7;
+ tmp = tmp << 1;
+ OP2 = tmp;
+ resultFlags(tmp);
+}
+
+:BCC REL is op=0x90; REL
+{
+ if (C == 0) goto REL;
+}
+
+:BCS REL is op=0xB0; REL
+{
+ if (C) goto REL;
+}
+
+:BEQ REL is op=0xF0; REL
+{
+ if (Z) goto REL;
+}
+
+:BIT OP2 is (op=0x24 | op=0x2C) ... & OP2
+{
+ N = (OP2 & 0x80) == 0x80;
+ V = (OP2 & 0x40) == 0x40;
+ local value = A & OP2;
+ Z = (value == 0);
+}
+
+:BMI REL is op=0x30; REL
+{
+ if (N) goto REL;
+}
+
+:BNE REL is op=0xD0; REL
+{
+ if (Z == 0) goto REL;
+}
+
+:BPL REL is op=0x10; REL
+{
+ if (N == 0) goto REL;
+}
+
+:BRK is op=0x00
+{
+ *:2 (SP - 1) = inst_next;
+ SP = SP - 2;
+ B = 1;
+ pushSR();
+ I = 1;
+ local target:2 = 0xFFFE;
+ goto [*:2 target];
+}
+
+:BVC REL is op=0x50; REL
+{
+ if (V == 0) goto REL;
+}
+
+:BVS REL is op=0x70; REL
+{
+ if (V) goto REL;
+}
+
+:CLC is op=0x18
+{
+ C = 0;
+}
+
+:CLD is op=0xD8
+{
+ D = 0;
+}
+
+:CLI is op=0x58
+{
+ I = 0;
+}
+
+:CLV is op=0xB8
+{
+ V = 0;
+}
+
+:CMP OP1 is (cc=1 & aaa=6) ... & OP1
+{
+ local op1 = OP1;
+ local tmp = A - op1;
+ resultFlags(tmp);
+ C = (A >= op1);
+}
+
+:CPX OP2 is (op=0xE0 | op=0xE4 | op=0xEC) ... & OP2
+{
+ local op1 = OP2;
+ local tmp = X - op1;
+ resultFlags(tmp);
+ C = (X >= op1);
+}
+
+:CPY OP2 is (op=0xC0 | op=0xC4 | op=0xCC) ... & OP2
+{
+ local op1 = OP2;
+ local tmp = Y - op1;
+ resultFlags(tmp);
+ C = (Y >= op1);
+}
+
+:DEC OP2 is (op=0xC6 | op=0xCE | op=0xD6 | op=0xDE) ... & OP2
+{
+ local tmp = OP2 - 1;
+ OP2 = tmp;
+ resultFlags(tmp);
+}
+
+:DEX is op=0xCA
+{
+ X = X - 1;
+ resultFlags(X);
+}
+
+
+:DEY is op=0x88
+{
+ Y = Y -1;
+ resultFlags(Y);
+}
+
+:EOR OP1 is (cc=1 & aaa=2) ... & OP1
+{
+ local op1 = OP1;
+ A = A ^ op1;
+ resultFlags(A);
+}
+
+:INC OP2 is (op=0xE6 | op=0xEE | op=0xF6 | op=0xFE) ... & OP2
+{
+ local tmp = OP2 + 1;
+ OP2 = tmp;
+ resultFlags(tmp);
+}
+
+:INY is op=0xC8
+{
+ Y = Y + 1;
+ resultFlags(Y);
+}
+
+:INX is op=0xE8
+{
+ X = X + 1;
+ resultFlags(X);
+}
+
+:JMP ADDR16 is (op=0x4C); ADDR16
+{
+ goto ADDR16;
+}
+
+:JMP ADDRI is (op=0x6c); ADDRI
+{
+ goto [ADDRI];
+}
+
+:JSR ADDR16 is op=0x20; ADDR16
+{
+ *:2 (SP-1) = inst_next;
+ SP=SP-2;
+ call ADDR16;
+}
+
+:LDA OP1 is (cc=1 & aaa=5) ... & OP1
+{
+ A = OP1;
+ resultFlags(A);
+}
+
+:LDY OP2 is (op=0xA0 | op=0xA4 | op=0xAC | op=0xB4 | op=0xBC) ... & OP2
+{
+ Y = OP2;
+ resultFlags(Y);
+}
+
+:LDX OP2LD is (op=0xA2 | op=0xA6 | op=0xAE | op=0xB6 | op=0xBE) ... & OP2LD
+{
+ X = OP2LD;
+ resultFlags(X);
+}
+
+:LSR OP2 is (op=0x46 | op=0x4A | op=0x4E | op=0x56 | op=0x5E) ... & OP2
+{
+ local tmp = OP2;
+ C = tmp & 1;
+ tmp = tmp >> 1;
+ OP2 = tmp;
+ Z = (tmp == 0);
+ N = 0;
+}
+
+:NOP is op=0xEA
+{
+}
+
+:ORA OP1 is (cc=1 & aaa=0) ... & OP1
+{
+ A = A | OP1;
+ resultFlags(A);
+}
+
+:PHP is op=0x8
+{
+ pushSR();
+}
+
+:PLP is op=0x28
+{
+ popSR();
+}
+
+:PHA is op=0x48
+{
+ *:1 (SP) = A;
+ SP = SP - 1;
+}
+
+:PLA is op=0x68
+{
+ SP = SP + 1;
+ A = *:1 (SP);
+ resultFlags(A);
+}
+
+:ROL OP2 is (op=0x26 | op=0x2A | op=0x2E | op=0x36 | op=0x3E) ... & OP2
+{
+ local tmpC = C;
+ local op2 = OP2;
+ C = op2 >> 7;
+ local result = op2 << 1;
+ result = result | tmpC;
+ OP2 = result;
+ resultFlags(result);
+}
+
+:ROR OP2 is (op=0x66 | op=0x6A | op=0x6E | op=0x76 | op=0x7E) ... & OP2
+{
+ local tmpC = C << 7;
+ local tmp = OP2;
+ C = tmp & 1;
+ tmp = tmp >> 1;
+ tmp = tmp | tmpC;
+ OP2 = tmp;
+ resultFlags(tmp);
+}
+
+:RTI is op=0x40
+{
+ popSR();
+
+ SP = SP+1;
+ tmp:2 = *:2 SP;
+ SP = SP+1;
+
+ return [tmp];
+}
+
+:RTS is op=0x60
+{
+ SP = SP+1;
+ tmp:2 = *:2 SP;
+ SP = SP+1;
+
+ return [tmp];
+}
+
+:SBC OP1 is (cc=1 & aaa=7) ... & OP1
+{
+ local op1 = OP1;
+ local result = A - op1 - !C;
+
+ subtraction_flags1(A, op1, result);
+ A = result;
+
+ # resultFlags(tmp);
+ # C = ((A <= op1) * C) | (A < op1);
+ # A = tmp;
+}
+
+:SEC is op=0x38
+{
+ C = 1;
+}
+
+:SED is op=0xF8
+{
+ D = 1;
+}
+
+:SEI is op=0x78
+{
+ I = 1;
+}
+
+:STA OP1 is (cc=1 & aaa=4) ... & OP1
+{
+ OP1 = A;
+}
+
+:STX OP2ST is (op=0x86 | op=0x8E | op=0x96) ... & OP2ST
+{
+ OP2ST = X;
+}
+
+:STY OP2 is (op=0x84 | op=0x8C | op=0x94) ... & OP2
+{
+ OP2 = Y;
+}
+
+:TAX is op=0xAA
+{
+ X = A;
+ resultFlags(X);
+}
+
+:TAY is op=0xA8
+{
+ Y = A;
+ resultFlags(Y);
+}
+
+:TSX is op=0xBA
+{
+ X = S;
+}
+
+:TXA is op=0x8A
+{
+ A = X;
+ resultFlags(A);
+}
+
+:TXS is op=0x9A
+{
+ S = X;
+}
+
+:TYA is op=0x98
+{
+ A = Y;
+ resultFlags(A);
+}
diff --git a/python/icicle/Ghidra/Processors/6502/data/languages/65c02.slaspec b/python/icicle/Ghidra/Processors/6502/data/languages/65c02.slaspec
new file mode 100644
index 0000000..adb21ee
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/6502/data/languages/65c02.slaspec
@@ -0,0 +1,222 @@
+@include "6502.slaspec"
+
+define token bitopbyte (8)
+ bitop = (0,7)
+
+ action = (7,7)
+ bitindex = (4,6) dec
+ optype = (0,3)
+;
+
+define token testopbyte (8)
+ top = (0, 7)
+ taaa = (5, 7)
+ td = (4, 4)
+ tbb = (2, 3)
+ tcc = (0, 1)
+;
+
+################################################################
+
+# Zero Page Indirect
+ZIOP: (imm8) is bbb=4; imm8 { addr:2 = imm8; tmp:2 = *:2 addr; export *:1 tmp; }
+
+OPTB: imm8 is tbb=1; imm8 { export *:1 imm8; }
+OPTB: imm16 is tbb=3; imm16 { export *:1 imm16; }
+
+# Absolute Indexed Indirect
+ADDRIX: (imm16,X) is X; imm16 { addr:2 = imm16 + zext(X); tmp:2 = *:2 addr; export tmp; }
+
+# Instructions
+
+:ADC ZIOP is (cc=2 & aaa=3) ... & ZIOP
+{
+ local op1 = ZIOP;
+ local tmpC = C;
+
+ C = carry(A, op1);
+ A = A + op1 + tmpC;
+ resultFlags(A);
+ V = C;
+}
+
+:AND ZIOP is (cc=2 & aaa=1) ... & ZIOP
+{
+ A = A & ZIOP;
+ resultFlags(A);
+}
+
+:BBR "#"bitindex, imm8, REL is (action=0 & optype=0xF) & bitindex ; imm8 ; REL {
+ local ptr:2 = imm8;
+ local value:1 = *:1 ptr;
+ local jump = (value & (1 << bitindex)) == 0;
+ if (jump) goto REL;
+}
+
+:BBS "#"bitindex, imm8, REL is (action=1 & optype=0xF) & bitindex ; imm8 ; REL {
+ local ptr:2 = imm8;
+ local value:1 = *:1 ptr;
+ local jump = (value & (1 << bitindex)) != 0;
+ if (jump) goto REL;
+}
+
+:BIT "#"imm8 is op=0x89; imm8
+{
+ local value:1 = imm8;
+ N = (value & 0x80) == 0x80;
+ V = (value & 0x40) == 0x40;
+ value = A & value;
+ Z = (value == 0);
+}
+
+:BIT OP2 is (op=0x34 | op=0x3C) ... & OP2
+{
+ N = (OP2 & 0x80) == 0x80;
+ V = (OP2 & 0x40) == 0x40;
+ local value = A & OP2;
+ Z = (value == 0);
+}
+
+:BRA REL is op=0x80; REL
+{
+ goto REL;
+}
+
+:CMP ZIOP is (cc=2 & aaa=6) ... & ZIOP
+{
+ local op1 = ZIOP;
+ local tmp = A - op1;
+ resultFlags(tmp);
+ C = (A >= op1);
+}
+
+:DEC A is op=0x3A & A
+{
+ local tmp = A - 1;
+ A = tmp;
+ resultFlags(tmp);
+}
+
+:EOR ZIOP is (cc=2 & aaa=2) ... & ZIOP
+{
+ local op1 = ZIOP;
+ A = A ^ op1;
+ resultFlags(A);
+}
+
+:INC A is op=0x1A & A
+{
+ A = A + 1;
+ resultFlags(A);
+}
+
+:JMP ADDRIX is (op=0x7C); ADDRIX
+{
+ goto [ADDRIX];
+}
+
+:LDA ZIOP is (cc=2 & aaa=5) ... & ZIOP
+{
+ A = ZIOP;
+ resultFlags(A);
+}
+
+:ORA ZIOP is (cc=2 & aaa=0) ... & ZIOP
+{
+ A = A | ZIOP;
+ resultFlags(A);
+}
+
+:PHX is op=0xDA
+{
+ *:1 (SP) = X;
+ SP = SP - 1;
+}
+
+:PLX is op=0xFA
+{
+ SP = SP + 1;
+ X = *:1 (SP);
+ resultFlags(X);
+}
+
+:PHY is op=0x5A
+{
+ *:1 (SP) = Y;
+ SP = SP - 1;
+}
+
+:PLY is op=0x7A
+{
+ SP = SP + 1;
+ Y = *:1 (SP);
+ resultFlags(Y);
+}
+
+:RMB "#"bitindex, imm8 is (action=0 & optype=7) & bitindex ; imm8 {
+ local ptr:2 = imm8;
+ local value:1 = *:1 ptr;
+ value = value & ~(1 << bitindex);
+ *:1 ptr = value;
+}
+
+:SBC ZIOP is (cc=2 & aaa=7) ... & ZIOP
+{
+ local op1 = ZIOP;
+ local result = A - op1 - !C;
+
+ subtraction_flags1(A, op1, result);
+ A = result;
+}
+
+:SMB "#"bitindex, imm8 is (action=1 & optype=7) & bitindex ; imm8 {
+ local ptr:2 = imm8;
+ local value:1 = *:1 ptr;
+ value = value | (1 << bitindex);
+ *:1 ptr = value;
+}
+
+:STA ZIOP is (cc=2 & aaa=4) ... & ZIOP
+{
+ ZIOP = A;
+}
+
+:STZ imm8 is op=0x64 ; imm8
+{
+ local tmp:2 = imm8;
+ *:1 tmp = 0;
+}
+
+:STZ imm8,X is op=0x74 & X ; imm8
+{
+ local tmp:2 = zext(imm8 + X);
+ *:1 tmp = 0;
+}
+
+:STZ imm16 is op=0x9C ; imm16
+{
+ local tmp:2 = imm16;
+ *:1 tmp = 0;
+}
+
+:STZ imm16,X is op=0x9E & X ; imm16
+{
+ local tmp:2 = imm16 + zext(X);
+ *:1 tmp = 0;
+}
+
+:TRB OPTB is (tcc=0 & taaa=0 & td=1) ... & OPTB
+{
+ local op1 = OPTB;
+ local result = (~A) & op1;
+ OPTB = result;
+ Z = result == 0;
+}
+
+:TSB OPTB is (tcc=0 & taaa=0 & td=0) ... & OPTB
+{
+ local op1 = OPTB;
+ local result = A | op1;
+ OPTB = result;
+ Z = result == 0;
+}
diff --git a/python/icicle/Ghidra/Processors/68000/data/languages/68000.cspec b/python/icicle/Ghidra/Processors/68000/data/languages/68000.cspec
new file mode 100644
index 0000000..fe7c760
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/68000/data/languages/68000.cspec
@@ -0,0 +1,69 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/python/icicle/Ghidra/Processors/68000/data/languages/68000.dwarf b/python/icicle/Ghidra/Processors/68000/data/languages/68000.dwarf
new file mode 100644
index 0000000..9fcce0b
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/68000/data/languages/68000.dwarf
@@ -0,0 +1,10 @@
+
+
+
+
+
+
+
+
+
+
diff --git a/python/icicle/Ghidra/Processors/68000/data/languages/68000.ldefs b/python/icicle/Ghidra/Processors/68000/data/languages/68000.ldefs
new file mode 100644
index 0000000..e065db0
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/68000/data/languages/68000.ldefs
@@ -0,0 +1,67 @@
+
+
+
+
+ Motorola 32-bit 68040
+
+
+
+
+
+
+
+
+ Motorola 32-bit 68030
+
+
+
+
+
+
+ Motorola 32-bit 68020
+
+
+
+
+
+
+
+
+ Motorola 32-bit Coldfire
+
+
+
+
+
diff --git a/python/icicle/Ghidra/Processors/68000/data/languages/68000.opinion b/python/icicle/Ghidra/Processors/68000/data/languages/68000.opinion
new file mode 100644
index 0000000..5ead96f
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/68000/data/languages/68000.opinion
@@ -0,0 +1,17 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/python/icicle/Ghidra/Processors/68000/data/languages/68000.pspec b/python/icicle/Ghidra/Processors/68000/data/languages/68000.pspec
new file mode 100644
index 0000000..14df2cb
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/68000/data/languages/68000.pspec
@@ -0,0 +1,9 @@
+
+
+
+
+
+
+
+
+
diff --git a/python/icicle/Ghidra/Processors/68000/data/languages/68000.sinc b/python/icicle/Ghidra/Processors/68000/data/languages/68000.sinc
new file mode 100644
index 0000000..ff97468
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/68000/data/languages/68000.sinc
@@ -0,0 +1,2954 @@
+# SLA specification for Motorola 68000 series
+
+define endian=big;
+define alignment=2;
+
+define space ram type=ram_space size=4 default;
+define space register type=register_space size=4;
+
+define register offset=0 size=4 [ D0 D1 D2 D3 D4 D5 D6 D7 ]; # Data registers
+define register offset=0 size=2 [ D0u D0w D1u D1w D2u D2w D3u D3w D4u D4w D5u D5w D6u D6w D7u D7w];
+define register offset=0 size=1 [ _ _ _ D0b _ _ _ D1b _ _ _ D2b _ _ _ D3b _ _ _ D4b _ _ _ D5b _ _ _ D6b _ _ _ D7b ];
+define register offset=0x20 size=4 [ A0 A1 A2 A3 A4 A5 A6 SP ]; # Address registers
+define register offset=0x20 size=2 [ A0u A0w A1u A1w A2u A2w A3u A3w A4u A4w A5u A5w A6u A6w A7u A7w];
+define register offset=0x20 size=1 [ _ _ _ A0b _ _ _ A1b _ _ _ A2b _ _ _ A3b _ _ _ A4b _ _ _ A5b _ _ _ A6b _ _ _ A7b ];
+define register offset=0x40 size=1 [ TF SVF IPL XF NF ZF VF CF ]; # Condition flags
+define register offset=0x50 size=4 PC; # Program counter register
+
+# Floating point registers are 80 bits internally, but are 96 bits to/from memory.
+# Note that 12-byte float needed to be added to FloatFormat.java
+# Also note that the 96 bit format is not really IEEE, because it gets mapped to 80 bits.
+define register offset=0x700 size=12 [ FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 ];
+
+define register offset=0xb0 size=4 [ FPCR FPSR FPIAR ];
+define register offset=0xe0 size=8 [ CRP ];
+define register offset=0x100 size=4 [ ISP MSP VBR CACR CAAR AC0 AC1 USP TT0 TT1 ];
+define register offset=0x140 size=4 [ SFC DFC TC ITT0 ITT1 DTT0 DTT1 MMUSR URP SRP PCR CAC ];
+define register offset=0x180 size=4 [ BUSCR MBB RAMBAR0 RAMBAR1 ];
+define register offset=0x200 size=2 [ SR ACUSR ];
+# NOTE that SR overlaps XF, ZF, VF, CF
+# NOTE that A7 refers to USP, ISP, or MSP depending on privilege level
+
+
+define register offset=0x300 size=4 [ glbdenom movemptr ];
+define register offset=0x400 size=4 [ contextreg ];
+
+@ifdef COLDFIRE
+# TODO: add a pure MAC variant, for now, just do EMAC
+define register offset=0x500 size=4 [ MACSR MASK ];
+define register offset=0x600 size=4 [ EMACSR ACC0 ACC1 ACC2 ACC3 ACCext01 ACCext23 EMASK ];
+@endif
+
+#TODO: These mode constraints do not constrain the various mode=7 sub-modes identified by regan bits
+@define MEM_ALTER_ADDR_MODES "(op4=1 | op5=1)" # Memory alterable addressing modes (All modes except mode=1 and mode=0)
+@define DAT_ALTER_ADDR_MODES "(mode=0 | op4=1 | op5=1)" # Data alterable addressing modes (All modes except mode=1)
+@define DAT_DIR_CTL_ADDR_MODES "(mode=0 | mode=2 | mode=5 | mode=6 | mode=7)" # Data direct and control addressing modes
+@define CTL_ADDR_MODES "(mode=2 | mode=5 | mode=6 | mode=7)" # Control addressing modes
+@define POSTINC_CTL_ADDR_MODES "(mode=2 | mode=3 | mode=5 | mode=6 | mode=7)" # Control addressing modes
+@define PREDEC_CTL_ADDR_MODES "(mode=2 | mode=4 | mode=5 | mode=6 | mode=7)" # Control addressing modes
+
+#TODO: These mode constraints do not constrain the various mode=7 sub-modes identified by regan bits
+@define MEM_ALTER_ADDR_MODES2 "(op7=1 | op8=1)" # Memory alterable addressing modes (All modes except mode=1 and mode=0)
+@define DAT_ALTER_ADDR_MODES2 "(mode2=0 | op7=1 | op8=1)" # Data alterable addressing modes (All modes except mode=1)
+@define DAT_DIR_CTL_ADDR_MODES2 "(mode2=0 | mode2=2 | mode2=5 | mode2=6 | mode=7)" # Data direct and control addressing modes
+@define CTL_ADDR_MODES2 "(mode2=2 | mode2=5 | mode2=6 | mode2=7)" # Control addressing modes
+
+# Floating-point condition code bits within FPSR
+@define N_FP "FPSR[27,1]"
+@define Z_FP "FPSR[26,1]"
+@define I_FP "FPSR[25,1]"
+@define NAN_FP "FPSR[24,1]"
+
+define token instr (16)
+ mode = (3,5)
+ mode2 = (6,8)
+ regdn = (0,2)
+ regdnw = (0,2)
+ regdnb = (0,2)
+ regan = (0,2)
+ reganw = (0,2)
+ reganb = (0,2)
+ rmbit = (3,3)
+ reg9dn = (9,11)
+ reg9dnw = (9,11)
+ reg9dnb = (9,11)
+ reg9an = (9,11)
+ copid = (9,11)
+ op = (12,15)
+ opbig = (8,15)
+ op01 = (0,1)
+ op02 = (0,2)
+ op03 = (0,3)
+ op08 = (0,8)
+ op015 = (0,15)
+ op34 = (3,4)
+ op35 = (3,5)
+ op37 = (3,7)
+ op38 = (3,8)
+ op45 = (4,5)
+ op48 = (4,8)
+ op69 = (6,9)
+ op68 = (6,8)
+ op67 = (6,7)
+ op1315 = (13,15)
+ op4 = (4,4)
+ op5 = (5,5)
+ op7 = (7,7)
+ op8 = (8,8)
+ op11 = (11,11)
+ quick = (9,11)
+ op811 = (8,11)
+ copcc1 = (0,5)
+ d8base = (0,7) signed
+@ifdef COLDFIRE
+ reg03y = (0,3)
+ reg03ywu = (0,3)
+ reg03ywl = (0,3)
+ op47 = (4,7)
+ op611 = (6,11)
+ op6 = (6,6)
+ op0910 = (9,10)
+ acclsb = (7,7)
+ d911 = (9,11)
+ reg315 = (3, 15)
+ reg9dnu = (9,11)
+ reg9dnl = (9,11)
+ reg9anu = (9,11)
+ reg9anl = (9,11)
+@endif
+;
+
+define token extword (16)
+ opx015 = (0,15)
+ opx1315= (13,15)
+ opx515 = (5,15)
+ da = (15,15)
+ regda = (12,15)
+ regxdn = (12,14)
+ regxdnw = (12,14)
+ regxan = (12,14)
+ regxanw = (12,14)
+ wl = (11,11)
+ mregn = (10,12)
+ rwx = (9,9)
+ scale = (9,10)
+ ext_911 = (9,11)
+ bigopx = (8,15)
+ fbit = (8,8)
+ regdu = (6,8)
+ regduw = (6,8)
+ regdub = (6,8)
+ fcmask = (5,7)
+ aregx = (5,7)
+ ext_35 = (3,5)
+ regdc = (0,2)
+ regdcw = (0,2)
+ regdcb = (0,2)
+ d8 = (0,7) signed
+ bs = (7,7)
+ IS = (6,6)
+ bdsize = (4,5)
+ iis = (0,2)
+ odsize = (0,1)
+ copcc2 = (0,5)
+ fc4 = (4,4)
+ fc3 = (3,3)
+ fc03 = (0,3)
+ fc02 = (0,2)
+ ctl = (0,11)
+@ifdef COLDFIRE
+ sfact = (9,10)
+ accmsb = (4,4)
+ reg03yu = (0,3)
+ reg03yl = (0,3)
+ ereg03y = (0,3)
+ accw = (2,3)
+ reg12x = (12,15)
+ reg12xwu = (12,15)
+ reg12xwl = (12,15)
+@endif
+;
+
+define token extword2 (16)
+ regda2 = (12,15)
+ ext2_911 = (9,11)
+ ext2_35 = (3,5)
+ regdu2 = (6,8)
+ regdu2w = (6,8)
+ regdc2 = (0,2)
+ regdc2w = (0,2)
+;
+
+define token fpword (16)
+ fop = (12,15)
+ fcopid = (9,11)
+ fword = (0,15)
+ fcnt = (0,2)
+ f1515 = (15,15)
+ f1415 = (14,15)
+ f1315 = (13,15)
+ f1015 = (10,15)
+ f0009 = (0,9)
+ f0008 = (0,8)
+ f0808 = (8,8)
+ f0810 = (8,10)
+ f0707 = (7,7)
+ f0609 = (6,9)
+ f0608 = (6,8)
+ f0615 = (6,15)
+ f0308 = (3,8)
+ f0306 = (3,6)
+ fmode = (0,2)
+ frm = (14,14)
+ f1313 = (13,13)
+ fsrc = (10,12) # attached to FP registers
+ f1012 = (10,12)
+ f10 = (10,10)
+ f11 = (11,11)
+ f12 = (12,12)
+ fdcos = (0,2) # attached to FP registers
+ fdsin = (7,9) # attached to FP registers
+ ffmt = (10,12)
+ fdst = (7,9) # attached to FP registers
+ fdr = (13,13)
+ fsize = (6,6)
+ fcode = (0,5)
+ fopmode = (0,6)
+ fkfactor = (0,6)
+ fkfacreg = (4,6)
+ fromoffset = (0,6)
+ flmode_t = (11,11)
+ flmode_m = (12,12)
+ fldynreg = (4,6)
+ freglist = (0,7)
+ frlist0 = (0,0)
+ frlist1 = (1,1)
+ frlist2 = (2,2)
+ frlist3 = (3,3)
+ frlist4 = (4,4)
+ frlist5 = (5,5)
+ frlist6 = (6,6)
+ frlist7 = (7,7)
+;
+
+define token disp16 (16) d16 = (0,15) signed;
+define token disp32 (32) d32 = (0,31) signed;
+define token disp64 (64)
+ signD = (63,63)
+ exponentD = (52,62)
+ mantissaD = (0,51)
+ d64 = (0,63) signed
+;
+define token disp96X_1 (32)
+ signX = (31,31)
+ exponentX = (16,30)
+;
+define token disp96X_2 (64)
+ expintbitX = (63,63)
+ mantissaX = (0,62)
+;
+define token bdisp16 (16) bd16 = (0,15) signed;
+define token bdisp32 (32) bd32 = (0,31) signed;
+define token odisp16 (16) od16 = (0,15) signed;
+define token odisp32 (32) od32 = (0,31) signed;
+define token fldparm (16)
+ flddo=(11,11)
+ fldoffdat=(6,10)
+ fldoffreg=(6,8)
+ flddw=(5,5)
+ fldwddat=(0,4)
+ fldwdreg=(0,2)
+ f_reg=(12,14)
+ regdr=(0,2)
+ regdq=(12,14)
+ divsgn=(11,11)
+ divsz=(10,10)
+ mvm0 = (0,0) # Bits in the register list mask for movem
+ mvm1 = (1,1)
+ mvm2 = (2,2)
+ mvm3 = (3,3)
+ mvm4 = (4,4)
+ mvm5 = (5,5)
+ mvm6 = (6,6)
+ mvm7 = (7,7)
+ mvm8 = (8,8)
+ mvm9 = (9,9)
+ mvm10 = (10,10)
+ mvm11 = (11,11)
+ mvm12 = (12,12)
+ mvm13 = (13,13)
+ mvm14 = (14,14)
+ mvm15 = (15,15)
+;
+
+# Context bits for getting base register bits into the addressing mode
+define context contextreg
+ eanum = (0,0) # Which effective address is this (the regf's or the regs's)
+ pcmode = (1,1) # is this a PC relative mode
+ regfan = (2,4) # saved base register for first effective address
+ regtfan = (2,4)
+ savmod1 = (5,7)
+ savmod2 = (8,10) # Mode for the second effective address
+ regsdn = (11,13)
+ regsdnw = (11,13)
+ regsdnb = (11,13)
+ regsan = (11,13)
+ regtsan = (11,13)
+ regsanw = (11,13)
+ regsanb = (11,13)
+ extGUARD = (14,14) # guard for saving off modes before starting instructions
+;
+
+attach variables [ regdn regxdn reg9dn regdr regdq regsdn regdu regdc regdu2 regdc2 ] [ D0 D1 D2 D3 D4 D5 D6 D7 ];
+attach variables [ fldoffreg fldwdreg f_reg fcnt fkfacreg fldynreg ] [ D0 D1 D2 D3 D4 D5 D6 D7 ];
+attach variables [ regdnw regxdnw reg9dnw regsdnw regduw regdcw regdu2w regdc2w ] [ D0w D1w D2w D3w D4w D5w D6w D7w ];
+attach variables [ regdnb reg9dnb regsdnb regdub regdcb ] [ D0b D1b D2b D3b D4b D5b D6b D7b ];
+attach variables [ regda regda2 ] [ D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 SP ];
+attach variables [ regan regxan reg9an regfan regsan aregx ] [ A0 A1 A2 A3 A4 A5 A6 SP ];
+attach variables [ reganw regxanw regsanw ] [ A0w A1w A2w A3w A4w A5w A6w A7w ];
+attach variables [ reganb regsanb ] [ A0b A1b A2b A3b A4b A5b A6b A7b ];
+
+attach variables [ fsrc fdst fdcos fdsin ] [ FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 ];
+
+@ifdef COLDFIRE
+attach variables [ reg03y ereg03y reg12x ] [ D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 SP ];
+attach variables [reg03ywu reg12xwu reg03yu ] [ D0u D1u D2u D3u D4u D5u D6u D7u A0u A1u A2u A3u A4u A5u A6u A7u ];
+attach variables [reg03ywl reg12xwl reg03yl ] [ D0w D1w D2w D3w D4w D5w D6w D7w A0w A1w A2w A3w A4w A5w A6w A7w ];
+attach variables [reg9dnu] [ D0u D1u D2u D3u D4u D5u D6u D7u ];
+attach variables [reg9dnl] [ D0w D1w D2w D3w D4w D5w D6w D7w ];
+attach variables [reg9anu] [ A0u A1u A2u A3u A4u A5u A6u A7u ];
+attach variables [reg9anl] [ A0w A1w A2w A3w A4w A5w A6w A7w ];
+attach variables [accw] [ACC0 ACC1 ACC2 ACC3];
+
+attach values d911 [ -1 1 2 3 4 5 6 7 ];
+@endif
+
+attach values scale [ 1 2 4 8 ];
+attach values quick [ 8 1 2 3 4 5 6 7 ];
+
+define pcodeop kfactor;
+define pcodeop ftrap;
+define pcodeop __m68k_trap;
+define pcodeop __m68k_trapv;
+define pcodeop reset;
+define pcodeop saveFPUStateFrame;
+define pcodeop restoreFPUStateFrame;
+define pcodeop pushInvalidateCaches;
+
+define pcodeop bcdAdjust;
+
+define pcodeop sin;
+define pcodeop cos;
+define pcodeop tan;
+define pcodeop asin;
+define pcodeop acos;
+define pcodeop atan;
+define pcodeop sinh;
+define pcodeop cosh;
+define pcodeop tanh;
+
+ea_index: regxan*scale is da=1 & wl=1 & regxan & scale { tmp:4 = regxan*scale; export tmp; }
+ea_index: regxanw*scale is da=1 & wl=0 & regxanw & scale { tmp:4 = sext(regxanw)*scale; export tmp; }
+ea_index: regxdn*scale is da=0 & wl=1 & regxdn & scale { tmp:4 = regxdn*scale; export tmp; }
+ea_index: regxdnw*scale is da=0 & wl=0 & regxdnw & scale { tmp:4 = sext(regxdnw)*scale; export tmp; }
+
+
+breg: regfan is eanum=0 & regfan { export regfan; }
+breg: regsan is eanum=1 & regsan { export regsan; }
+#breg: PC is pcmode=1 & eanum & PC { tmp:4 = inst_start; }
+
+fl_breg: "-" is bs=1 { export 0:4; }
+fl_breg: "ZPC" is bs=1 & pcmode=1 { export 0:4; }
+fl_breg: breg is bs=0 & pcmode=0 & breg { export breg; }
+fl_breg: PC is PC & bs=0 & pcmode=1 { tmp:4 = inst_start + 2; export tmp; }
+
+# shift amount parameter
+cntreg: reg9dn is reg9dn & op5=1 { local tmp = reg9dn & 63; export tmp; }
+cntreg: "#"^quick is quick & op5=0 { export *[const]:4 quick; }
+
+# Extension word forms of the effective address
+ # 8-bit displacement (brief extension)
+extw: d8,breg,ea_index is breg; ea_index & d8 & fbit=0 { local tmp = breg+d8+ea_index; export tmp; }
+extw: rela,PC,ea_index is pcmode=1 & PC; ea_index & d8 & fbit=0
+ [ rela = inst_start+d8+2; ]
+ { tmp:4 = rela; tmp = tmp+ea_index; export tmp; }
+ # Base displacement (indexed)
+extw: fl_breg,ea_index is ea_index & fl_breg & fbit=1 & bdsize=1 & IS=0 & iis=0 { local tmp = fl_breg+ea_index; export tmp; }
+extw: bd16,fl_breg,ea_index is ea_index & fl_breg & fbit=1 & bdsize=2 & IS=0 & iis=0; bd16 { local tmp = fl_breg+ea_index+bd16; export tmp; }
+extw: bd32,fl_breg,ea_index is ea_index & fl_breg & fbit=1 & bdsize=3 & IS=0 & iis=0; bd32 { local tmp = fl_breg+ea_index+bd32; export tmp; }
+ # Memory Indirect Postindexed Mode
+extw: [fl_breg],ea_index is ea_index & fl_breg & fbit=1 & bdsize=1 & IS=0 & iis=1 { local tmp = *:4 fl_breg + ea_index; export tmp; }
+extw: [bd16,fl_breg],ea_index is ea_index & fl_breg & fbit=1 & bdsize=2 & IS=0 & iis=1; bd16 { local tmp = *:4 (fl_breg+bd16) + ea_index; export tmp; }
+extw: [bd32,fl_breg],ea_index is ea_index & fl_breg & fbit=1 & bdsize=3 & IS=0 & iis=1; bd32 { local tmp = *:4 (fl_breg+bd32) + ea_index; export tmp; }
+extw: [fl_breg],ea_index,od16 is ea_index & fl_breg & fbit=1 & bdsize=1 & IS=0 & iis=2; od16 { local tmp = *:4 fl_breg + ea_index + od16; export tmp; }
+extw: [bd16,fl_breg],ea_index,od16 is ea_index & fl_breg & fbit=1 & bdsize=2 & IS=0 & iis=2; bd16; od16 { local tmp = *:4 (fl_breg+bd16) + ea_index + od16; export tmp; }
+extw: [bd32,fl_breg],ea_index,od16 is ea_index & fl_breg & fbit=1 & bdsize=3 & IS=0 & iis=2; bd32; od16 { local tmp = *:4 (fl_breg+bd32) + ea_index + od16; export tmp; }
+extw: [fl_breg],ea_index,od32 is ea_index & fl_breg & fbit=1 & bdsize=1 & IS=0 & iis=3; od32 { local tmp = *:4 fl_breg + ea_index + od32; export tmp; }
+extw: [bd16,fl_breg],ea_index,od32 is ea_index & fl_breg & fbit=1 & bdsize=2 & IS=0 & iis=3; bd16; od32 { local tmp = *:4 (fl_breg+bd16) + ea_index + od32; export tmp; }
+extw: [bd32,fl_breg],ea_index,od32 is ea_index & fl_breg & fbit=1 & bdsize=3 & IS=0 & iis=3; bd32; od32 { local tmp = *:4 (fl_breg+bd32) + ea_index + od32; export tmp; }
+ # Memory Indirect Preindexed Mode
+extw: [fl_breg,ea_index] is ea_index & fl_breg & fbit=1 & bdsize=1 & IS=0 & iis=5 { local tmp = *:4 (fl_breg+ea_index); export tmp; }
+extw: [bd16,fl_breg,ea_index] is ea_index & fl_breg & fbit=1 & bdsize=2 & IS=0 & iis=5; bd16 { local tmp = *:4 (fl_breg+ea_index+bd16); export tmp; }
+extw: [bd32,fl_breg,ea_index] is ea_index & fl_breg & fbit=1 & bdsize=3 & IS=0 & iis=5; bd32 { local tmp = *:4 (fl_breg+ea_index+bd32); export tmp; }
+extw: [fl_breg,ea_index],od16 is ea_index & fl_breg & fbit=1 & bdsize=1 & IS=0 & iis=6; od16 { local tmp = *:4 (fl_breg+ea_index) + od16; export tmp; }
+extw: [bd16,fl_breg,ea_index],od16 is ea_index & fl_breg & fbit=1 & bdsize=2 & IS=0 & iis=6; bd16; od16 { local tmp = *:4 (fl_breg+ea_index+bd16) + od16; export tmp; }
+extw: [bd32,fl_breg,ea_index],od16 is ea_index & fl_breg & fbit=1 & bdsize=3 & IS=0 & iis=6; bd32; od16 { local tmp = *:4 (fl_breg+ea_index+bd32) + od16; export tmp; }
+extw: [fl_breg,ea_index],od32 is ea_index & fl_breg & fbit=1 & bdsize=1 & IS=0 & iis=7; od32 { local tmp = *:4 (fl_breg+ea_index) + od32; export tmp; }
+extw: [bd16,fl_breg,ea_index],od32 is ea_index & fl_breg & fbit=1 & bdsize=2 & IS=0 & iis=7; bd16; od32 { local tmp = *:4 (fl_breg+ea_index+bd16) + od32; export tmp; }
+extw: [bd32,fl_breg,ea_index],od32 is ea_index & fl_breg & fbit=1 & bdsize=3 & IS=0 & iis=7; bd32; od32 { local tmp = *:4 (fl_breg+ea_index+bd32) + od32; export tmp; }
+ # Base displacement
+extw: fl_breg is fl_breg & fbit=1 & bdsize=1 & IS=1 & iis=0 { export fl_breg; }
+extw: bd16,fl_breg is fl_breg & fbit=1 & bdsize=2 & IS=1 & iis=0; bd16 { local tmp = fl_breg+bd16; export tmp; }
+extw: bd32,fl_breg is fl_breg & fbit=1 & bdsize=3 & IS=1 & iis=0; bd32 { local tmp = fl_breg+bd32; export tmp; }
+ # Memory Indirect
+extw: [fl_breg] is fl_breg & fbit=1 & bdsize=1 & IS=1 & iis=1 { local tmp = *:4 fl_breg; export tmp; }
+extw: [bd16,fl_breg] is fl_breg & fbit=1 & bdsize=2 & IS=1 & iis=1; bd16 { local tmp = *:4 (fl_breg+bd16); export tmp; }
+extw: [bd32,fl_breg] is fl_breg & fbit=1 & bdsize=3 & IS=1 & iis=1; bd32 { local tmp = *:4 (fl_breg+bd32); export tmp; }
+extw: [fl_breg],od16 is fl_breg & fbit=1 & bdsize=1 & IS=1 & iis=2; od16 { local tmp = *:4 fl_breg + od16; export tmp; }
+extw: [bd16,fl_breg],od16 is fl_breg & fbit=1 & bdsize=2 & IS=1 & iis=2; bd16; od16 { local tmp = *:4 (fl_breg+bd16) + od16; export tmp; }
+extw: [bd32,fl_breg],od16 is fl_breg & fbit=1 & bdsize=3 & IS=1 & iis=2; bd32; od16 { local tmp = *:4 (fl_breg+bd32) + od16; export tmp; }
+extw: [fl_breg],od32 is fl_breg & fbit=1 & bdsize=1 & IS=1 & iis=3; od32 { local tmp = *:4 fl_breg + od32; export tmp; }
+extw: [bd16,fl_breg],od32 is fl_breg & fbit=1 & bdsize=2 & IS=1 & iis=3; bd16; od32 { local tmp = *:4 (fl_breg+bd16) + od32; export tmp; }
+extw: [bd32,fl_breg],od32 is fl_breg & fbit=1 & bdsize=3 & IS=1 & iis=3; bd32; od32 { local tmp = *:4 (fl_breg+bd32) + od32; export tmp; }
+
+
+# The main effective address table
+ # size=long
+eal: regdn is mode=0 & regdn { export regdn; }
+eal: regan is mode=1 & regan { export regan; }
+eal: (regan) is mode=2 & regan { export *:4 regan; }
+eal: (regan)+ is mode=3 & regan { local tmp = regan; regan = regan + 4; export *:4 tmp; }
+eal: -(regan) is mode=4 & regan { regan = regan - 4; export *:4 regan; }
+eal: (d16,regan) is mode=5 & regan; d16 { local tmp = regan + d16; export *:4 tmp; }
+eal: (extw) is mode=6 & regan; extw [ regtfan = regan; pcmode = 0; ] { build extw; export *:4 extw; }
+eal: (d16,PC) is PC & mode=7 & regan=2; d16 { tmp:4 = inst_start + 2 + d16; export *:4 tmp; }
+eal: (extw) is mode=7 & regan=3; extw [ pcmode=1; ] { build extw; export *:4 extw; }
+eal: (d16)".w" is mode=7 & regan=0; d16 { export *:4 d16; }
+eal: (d32)".l" is mode=7 & regan=1; d32 { export *:4 d32; }
+eal: "#"^d32 is mode=7 & regan=4; d32 { export *[const]:4 d32; }
+ # size=word
+eaw: regdnw is mode=0 & regdnw { export regdnw; }
+eaw: reganw is mode=1 & reganw { export reganw; }
+eaw: (regan) is mode=2 & regan { export *:2 regan; }
+eaw: (regan)+ is mode=3 & regan { local tmp = regan; regan = regan + 2; export *:2 tmp; }
+eaw: -(regan) is mode=4 & regan { regan = regan - 2; export *:2 regan; }
+eaw: (d16,regan) is mode=5 & regan; d16 { local tmp = regan + d16; export *:2 tmp; }
+eaw: (extw) is mode=6 & regan; extw [ pcmode=0; regtfan=regan; ] { build extw; export *:2 extw; }
+eaw: (d16,PC) is PC & mode=7 & regan=2; d16 { tmp:4 = inst_start + 2 + d16; export *:2 tmp; }
+eaw: (extw) is mode=7 & regan=3; extw [ pcmode=1; ] { build extw; export *:2 extw; }
+eaw: (d16)".w" is mode=7 & regan=0; d16 { export *:2 d16; }
+eaw: (d32)".l" is mode=7 & regan=1; d32 { export *:2 d32; }
+eaw: "#"^d16 is mode=7 & regan=4; d16 { export *[const]:2 d16; }
+ # size=byte
+eab: regdnb is mode=0 & regdnb { export regdnb; }
+eab: reganb is mode=1 & reganb { export reganb; }
+eab: (regan) is mode=2 & regan { export *:1 regan; }
+eab: (regan)+ is mode=3 & regan & regan=7 { local tmp = regan; regan = regan + 2; export *:1 tmp; }
+eab: (regan)+ is mode=3 & regan { local tmp = regan; regan = regan + 1; export *:1 tmp; }
+eab: -(regan) is mode=4 & regan & regan=7 { regan = regan - 2; export *:1 regan; }
+eab: -(regan) is mode=4 & regan { regan = regan - 1; export *:1 regan; }
+eab: (d16,regan) is mode=5 & regan; d16 { local tmp = regan + d16; export *:1 tmp; }
+eab: (extw) is mode=6 & regan; extw [ pcmode=0; regtfan=regan; ] { build extw; export *:1 extw; }
+eab: (d16,PC) is PC & mode=7 & regan=2; d16 { tmp:4 = inst_start + 2 + d16; export *:1 tmp; }
+eab: (extw) is mode=7 & regan=3; extw [ pcmode=1; ] { build extw; export *:1 extw; }
+eab: (d16)".w" is mode=7 & regan=0; d16 { export *:1 d16; }
+eab: (d32)".l" is mode=7 & regan=1; d32 { export *:1 d32; }
+eab: "#"^d8 is mode=7 & regan=4; d8 { export *[const]:1 d8; }
+
+# Second effective address calculation for mov
+
+# NB- Extended-precsion are 12 bytes, so we need to increment or decrement the reg by 12 not 4
+#
+ # size=extend | packed (96-bit)
+ # The fmovem.x insn needs the movemptr to be set here
+e2x: (regsan) is savmod2=2 & regsan { movemptr = regsan; export *:12 regsan; }
+e2x: (regsan)+ is savmod2=3 & regsan { movemptr = regsan; local tmp = regsan; regsan = regsan + 12; export *:12 tmp; }
+e2x: -(regsan) is savmod2=4 & regsan { movemptr = regsan; regsan = regsan - 12; export *:12 regsan; }
+e2x: (d16,regsan) is savmod2=5 & regsan; d16 { local tmp = regsan + d16; movemptr = tmp; export *:12 tmp; }
+e2x: (extw) is savmod2=6; extw [ pcmode=0; eanum=1; ] { build extw; movemptr = extw; export *:12 extw; }
+e2x: (d16,PC) is PC & savmod2=7 & regsan=2; d16 { tmp:4 = inst_start + 2 + d16; movemptr = tmp; export *:12 tmp; }
+e2x: (extw) is savmod2=7 & regsan=3; extw [ pcmode=1; ] { build extw; movemptr = extw; export *:12 extw; }
+e2x: (d16)".w" is savmod2=7 & regsan=0; d16 { movemptr = d16; export *:12 d16; }
+e2x: (d32)".l" is savmod2=7 & regsan=1; d32 { movemptr = d32; export *:12 d32; }
+e2x: "#( -1E"^signX^" * 2E"^exp^"*1."^mantissaX) is savmod1=7 & regtfan=4; signX & exponentX; expintbitX & mantissaX
+ [exp=exponentX-0x3FFF;]
+ { movemptr = mantissaX; export *[const]:12 mantissaX; } # bug: doesn't construct a real, only exports the 64-bit mantissa
+ # size=quad (limited mode)
+
+# NB- Doubles are 8 bytes, so we need to increment or decrement the reg by 8 not 4
+#
+e2d: (regsan) is savmod2=2 & regsan { export *:8 regsan; }
+e2d: (regsan)+ is savmod2=3 & regsan { local tmp = regsan; regsan = regsan + 8; export *:8 tmp; }
+e2d: -(regsan) is savmod2=4 & regsan { regsan = regsan - 8; export *:8 regsan; }
+e2d: (d16,regsan) is savmod2=5 & regsan; d16 { local tmp = regsan + d16; export *:8 tmp; }
+e2d: (extw) is savmod2=6; extw [ pcmode=0; eanum=1; ] { build extw; export *:8 extw; }
+e2d: (d16,PC) is PC & savmod2=7 & regsan=2; d16 { tmp:4 = inst_start + 2 + d16; export *:8 tmp; }
+e2d: (extw) is savmod2=7 & regsan=3; extw [ pcmode=1; ] { build extw; export *:8 extw; }
+e2d: (d16)".w" is savmod2=7 & regsan=0; d16 { export *:8 d16; }
+e2d: (d32)".l" is savmod2=7 & regsan=1; d32 { export *:8 d32; }
+e2d: "#"^d64 is savmod2=7 & regsan=4; d64 { export *[const]:8 d64; }
+
+ # size=long
+e2l: regsdn is savmod2=0 & regsdn { export regsdn; }
+e2l: regsan is savmod2=1 & regsan { export regsan; }
+e2l: (regsan) is savmod2=2 & regsan { export *:4 regsan; }
+e2l: (regsan)+ is savmod2=3 & regsan { local tmp = regsan; regsan = regsan + 4; export *:4 tmp; }
+e2l: -(regsan) is savmod2=4 & regsan { regsan = regsan - 4; export *:4 regsan; }
+e2l: (d16,regsan) is savmod2=5 & regsan; d16 { local tmp = regsan + d16; export *:4 tmp; }
+e2l: (extw) is savmod2=6; extw [ pcmode=0; eanum=1; ] { build extw; export *:4 extw; }
+e2l: (d16,PC) is PC & savmod2=7 & regsan=2; d16 { tmp:4 = inst_start + 2 + d16; export *:4 tmp; }
+e2l: (extw) is savmod2=7 & regsan=3; extw [ pcmode=1; ] { build extw; export *:4 extw; }
+e2l: (d16)".w" is savmod2=7 & regsan=0; d16 { export *:4 d16; }
+e2l: (d32)".l" is savmod2=7 & regsan=1; d32 { export *:4 d32; }
+e2l: "#"^d32 is savmod2=7 & regsan=4; d32 { export *[const]:4 d32; }
+ # size=word
+e2w: regsdnw is savmod2=0 & regsdnw { export regsdnw; }
+e2w: regsanw is savmod2=1 & regsanw { export regsanw; }
+e2w: (regsan) is savmod2=2 & regsan { export *:2 regsan; }
+e2w: (regsan)+ is savmod2=3 & regsan { local tmp = regsan; regsan = regsan + 2; export *:2 tmp; }
+e2w: -(regsan) is savmod2=4 & regsan { regsan = regsan - 2; export *:2 regsan; }
+e2w: (d16,regsan) is savmod2=5 & regsan; d16 { local tmp = regsan + d16; export *:2 tmp; }
+e2w: (extw) is savmod2=6; extw [ pcmode=0; eanum=1; ] { build extw; export *:2 extw; }
+e2w: (d16,PC) is PC & savmod2=7 & regsan=2; d16 { tmp:4 = inst_start + 2 + d16; export *:2 tmp; }
+e2w: (extw) is savmod2=7 & regsan=3; extw [ pcmode=1; ] { build extw; export *:2 extw; }
+e2w: (d16)".w" is savmod2=7 & regsan=0; d16 { export *:2 d16; }
+e2w: (d32)".l" is savmod2=7 & regsan=1; d32 { export *:2 d32; }
+e2w: "#"^d16 is savmod2=7 & regsan=4; d16 { export *[const]:2 d16; }
+
+ # size=byte
+ # NB- Manual says that if in predecrement or postincrement mode and the res is the SP, then must inc/dec by 2, not by 1
+e2b: regsdnb is savmod2=0 & regsdnb { export regsdnb; }
+e2b: regsanb is savmod2=1 & regsanb { export regsanb; }
+e2b: (regsan) is savmod2=2 & regsan { export *:1 regsan; }
+e2b: (regsan)+ is savmod2=3 & regsan & regsan=7 { local tmp = regsan; regsan = regsan + 2; export *:1 tmp; }
+e2b: (regsan)+ is savmod2=3 & regsan { local tmp = regsan; regsan = regsan + 1; export *:1 tmp; }
+e2b: -(regsan) is savmod2=4 & regsan & regsan=7 { regsan = regsan - 2; export *:1 regsan; }
+e2b: -(regsan) is savmod2=4 & regsan { regsan = regsan - 1; export *:1 regsan; }
+e2b: (d16,regsan) is savmod2=5 & regsan; d16 { local tmp = regsan + d16; export *:1 tmp; }
+e2b: (extw) is savmod2=6; extw [ pcmode=0; eanum=1; ] { build extw; export *:1 extw; }
+e2b: (d16,PC) is PC & savmod2=7 & regsan=2; d16 { tmp:4 = inst_start + 2 + d16; export *:1 tmp; }
+e2b: (extw) is savmod2=7 & regsan=3; extw [ pcmode=1; ] { build extw; export *:1 extw; }
+e2b: (d16)".w" is savmod2=7 & regsan=0; d16 { export *:1 d16; }
+e2b: (d32)".l" is savmod2=7 & regsan=1; d32 { export *:1 d32; }
+e2b: "#"^d8 is savmod2=7 & regsan=4; d8 { export *[const]:1 d8; }
+
+# For instructions like lea and pea that manipulative the effective address
+# itself rather than the data the address is pointing at
+eaptr: (regan) is mode=2 & regan { export regan; }
+eaptr: (d16,regan) is mode=5 & regan; d16 { local tmp = regan+d16; export tmp; }
+eaptr: (extw) is mode=6 & regan; extw [ pcmode=0; regtfan=regan; ] { export extw; }
+eaptr: (d16,PC) is mode=7 & regan=2; d16 & PC { tmp:4 = inst_start+2+d16; export tmp; }
+eaptr: (extw) is mode=7 & regan=3; extw [ pcmode=1; ] { export extw; }
+eaptr: (d16)".w" is mode=7 & regan=0; d16 { export *[const]:4 d16; }
+eaptr: (d32)".l" is mode=7 & regan=1; d32 { export *[const]:4 d32; }
+
+# Data register or predecrement addressing
+Ty: -(regan) is rmbit=1 & regan { regan = regan-4; export *:4 regan; }
+Ty: regdn is rmbit=0 & regdn { export regdn; }
+Tx: -(reg9an) is rmbit=1 & reg9an { reg9an = reg9an-4; export *:4 reg9an; }
+Tx: reg9dn is rmbit=0 & reg9dn { export reg9dn; }
+Tyw: -(regan) is rmbit=1 & regan { regan = regan-2; export *:2 regan; }
+Tyw: regdnw is rmbit=0 & regdnw { export regdnw; }
+Txw: -(reg9an) is rmbit=1 & reg9an { reg9an = reg9an-2; export *:2 reg9an; }
+Txw: reg9dnw is rmbit=0 & reg9dnw { export reg9dnw; }
+Tyb: -(regan) is rmbit=1 & regan { regan = regan-1; export *:1 regan; }
+Tyb: regdnb is rmbit=0 & regdnb { export regdnb; }
+Txb: -(reg9an) is rmbit=1 & reg9an { reg9an = reg9an-1; export *:1 reg9an; }
+Txb: reg9dnb is rmbit=0 & reg9dnb { export reg9dnb; }
+
+# Bit field parameters
+f_off: fldoffdat is flddo=0 & fldoffdat { export *[const]:4 fldoffdat; }
+f_off: fldoffreg is flddo=1 & fldoffreg { export fldoffreg; }
+f_wd: fldwddat is flddw=0 & fldwddat { export *[const]:4 fldwddat; }
+f_wd: fldwdreg is flddw=1 & fldwdreg { export fldwdreg; }
+
+rreg: regxdn is da=0 & regxdn { export regxdn; }
+rreg: regxan is da=1 & regxan { export regxan; }
+
+# Condition codes
+
+cc: "t" is op811=0 { export 1:1; }
+cc: "f" is op811=1 { export 0:1; }
+cc: "hi" is op811=2 { tmp:1 = !(CF || ZF); export tmp; }
+cc: "ls" is op811=3 { tmp:1 = CF || ZF; export tmp; }
+cc: "cc" is op811=4 { tmp:1 = !CF; export tmp; }
+cc: "cs" is op811=5 { export CF; }
+cc: "ne" is op811=6 { tmp:1 = !ZF; export tmp; }
+cc: "eq" is op811=7 { export ZF; }
+cc: "vc" is op811=8 { tmp:1 = !VF; export tmp; }
+cc: "vs" is op811=9 { export VF; }
+cc: "pl" is op811=10 { tmp:1 = !NF; export tmp; }
+cc: "mi" is op811=11 { export NF; }
+cc: "ge" is op811=12 { tmp:1 = (VF==NF); export tmp; }
+cc: "lt" is op811=13 { tmp:1 = (VF!=NF); export tmp; }
+cc: "gt" is op811=14 { tmp:1 = !ZF && (VF==NF); export tmp; }
+cc: "le" is op811=15 { tmp:1 = ZF || (VF!=NF); export tmp; }
+
+const8: "#"^d8 is d8 { export *[const]:1 d8; }
+const16: "#"^d16 is d16 { export *[const]:2 d16; }
+const32: "#"^d32 is d32 { export *[const]:4 d32; }
+
+ctlreg: SFC is SFC & ctl=0x000 { export SFC; }
+ctlreg: DFC is DFC & ctl=0x001 { export DFC; }
+ctlreg: USP is USP & ctl=0x800 { export USP; }
+ctlreg: VBR is VBR & ctl=0x801 { export VBR; }
+ctlreg: CACR is CACR & ctl=0x002 { export CACR; }
+ctlreg: CAAR is CAAR & ctl=0x802 { export CAAR; }
+ctlreg: MSP is MSP & ctl=0x803 { export MSP; }
+ctlreg: ISP is ISP & ctl=0x804 { export ISP; }
+ctlreg: TC is TC & ctl=0x003 { export TC; }
+ctlreg: ITT0 is ITT0 & ctl=0x004 { export ITT0; }
+ctlreg: ITT1 is ITT1 & ctl=0x005 { export ITT1; }
+ctlreg: DTT0 is DTT0 & ctl=0x006 { export DTT0; }
+ctlreg: DTT1 is DTT1 & ctl=0x007 { export DTT1; }
+ctlreg: SRP is SRP & ctl=0x008 { export BUSCR; }
+ctlreg: MMUSR is MMUSR & ctl=0x805 { export MMUSR; }
+ctlreg: URP is URP & ctl=0x806 { export URP; }
+ctlreg: SRP is SRP & ctl=0x807 { export SRP; }
+ctlreg: PCR is PCR & ctl=0x808 { export PCR; }
+ctlreg: RAMBAR0 is RAMBAR0 & ctl=0xc04 { export RAMBAR0; }
+ctlreg: RAMBAR1 is RAMBAR1 & ctl=0xc05 { export RAMBAR1; }
+# ctlreg: PCR is PCR & ctl=0x808 { export PCR; }
+ctlreg: CAC is CAC & ctl=0xffe { export CAC; }
+ctlreg: MBB is MBB & ctl=0xfff { export MBB; }
+ctlreg: "UNK_CTL_"^ctl is ctl { tmp:4 = 0xffffffff; export tmp; }
+
+
+# Relative jump destinations
+addr8: reloc is d8base [ reloc=inst_start+2+d8base; ] { export *[ram]:4 reloc; }
+addr16: reloc is d16 [ reloc=inst_start+2+d16; ] { export *[ram]:4 reloc; }
+addr32: reloc is d32 [ reloc=inst_start+2+d32; ] { export *[ram]:4 reloc; }
+# Jump locations for coprocessor instructions
+#caddr16: reloc is d16 [ reloc=inst_next-2+d16; ] { export *[ram]:4 reloc; }
+#caddr32: reloc is d32 [ reloc=inst_next-4+d32; ] { export *[ram]:4 reloc; }
+
+# Macros for flags etc
+
+macro addflags(op1,op2) {
+ CF = carry(op1,op2);
+ VF = scarry(op1,op2);
+ XF = CF;
+}
+
+macro addxflags(op1, op2) {
+ local opSum = op1 + op2;
+ CF = carry(op1, op2) || carry(opSum, zext(XF));
+ VF = scarry(op1, op2) ^^ scarry(opSum, zext(XF));
+}
+
+macro subflags(op1,op2) {
+ CF = op1 < op2;
+ VF = sborrow(op1,op2);
+ XF = CF;
+}
+
+# This macro needs to consider the XF flag when finding the CF carry flag value: op1=op1-op2-XF
+# original was: CF = op1 < op2;
+macro subxflags(op1,op2) {
+ CF = (op1 < op2) || ( (XF == 1) && (op1 == op2) );
+ VF = sborrow(op1,op2);
+ XF = CF;
+}
+
+macro negxsubflags(op1) {
+ CF = 0 s< op1;
+ VF = sborrow(0,op1);
+ XF = CF;
+}
+
+macro logflags() {
+ VF=0;
+ CF=0;
+}
+
+macro resflags(result) {
+ NF = result s< 0;
+ ZF = result == 0;
+}
+
+macro resflags_fp(result) {
+ $(I_FP) = 0;
+ $(NAN_FP) = 0;
+ $(N_FP) = result f< 0;
+ $(Z_FP) = result == 0;
+}
+
+macro clearflags_fp() {
+ $(N_FP) = 0;
+ $(Z_FP) = 0;
+ $(NAN_FP) = 0;
+}
+
+macro bcdflags(result) {
+ XF = CF;
+ ZF = (result == 0) * ZF + (result != 0);
+}
+
+macro getbit(res,in,bitnum) {
+ res = ((in >> bitnum) & 1) != 0;
+}
+
+macro bitmask(res, width) {
+ res = (1 << width) - 1;
+}
+
+macro bfmask (res, off, width) {
+ res = ((1 << width) - 1) << (32 - off - width);
+}
+
+macro getbitfield(res, off, width) {
+ res = (res << off) >> (32 - width);
+}
+
+macro resbitflags(result, bitnum) {
+ NF = ((result >> bitnum) & 1) != 0;
+ ZF = result == 0;
+}
+
+macro packflags(res) {
+ res = zext((TF<<15)|(SVF<<13)|(IPL<<8)|(XF<<4)|(NF<<3)|(ZF<<2)|(VF<<1)|CF);
+}
+
+macro unpackflags(in) {
+ TF = (in & 0x8000)!=0;
+ SVF = (in & 0x2000)!=0;
+ IPL = in[8,3];
+ XF = (in & 0x10)!=0;
+ NF = (in & 8)!=0;
+ ZF = (in & 4)!=0;
+ VF = (in & 2)!=0;
+ CF = (in & 1)!=0;
+}
+
+# This macro sets the NF and ZF flags for extended arithmetic insns- addx, negx, and subx
+macro extendedResultFlags(result) {
+ NF = result s< 0;
+ ZF = (result == 0) && (ZF == 1);
+}
+
+macro arithmeticShiftLeft(count, register, width) {
+ local modcount = count & 63;
+ local lbit:1 = ((register >> (width - modcount) & 1) != 0);
+ local msbBefore:4 = zext(register s< 0);
+ register = register << modcount;
+ resflags(register);
+ local msbAfter:4 = zext(register s< 0);
+ VF = (msbBefore ^ msbAfter) != 0;
+ CF = (modcount != 0) * lbit;
+ XF = ((modcount == 0) * XF) + ((modcount != 0) * CF);
+}
+
+macro arithmeticShiftRight(count, register, width) {
+ local modcount = count & 63;
+ local lbit:1 = ((register >> (modcount-1) & 1) != 0);
+ local msbBefore:4 = zext(register s< 0);
+ register = register s>> modcount;
+ resflags(register);
+ local msbAfter:4 = zext(register s< 0);
+ VF = (msbBefore ^ msbAfter) != 0;
+ CF = (modcount != 0) * lbit;
+ XF = ((modcount == 0) * XF) + ((modcount != 0) * CF);
+}
+
+macro logicalShiftLeft(count, register, width) {
+ local modcount = count & 63;
+ local lbit:1 = ((register >> (width - modcount) & 1) != 0);
+ local msbBefore:4 = zext(register s< 0);
+ register = register << modcount;
+ resflags(register);
+ local msbAfter:4 = zext(register s< 0);
+ VF = (msbBefore ^ msbAfter) != 0;
+ CF = (modcount != 0) * lbit;
+ XF = ((modcount == 0) * XF) + ((modcount != 0) * CF);
+}
+
+macro logicalShiftRight(count, register, width) {
+ local modcount = count & 63;
+ local lbit:1 = ((register >> (modcount-1) & 1) != 0);
+ local msbBefore:4 = zext(register s< 0);
+ register = register >> modcount;
+ resflags(register);
+ local msbAfter:4 = zext(register s< 0);
+ VF = (msbBefore ^ msbAfter) != 0;
+ CF = (modcount != 0) * lbit;
+ XF = ((modcount == 0) * XF) + ((modcount != 0) * CF);
+}
+
+macro rotateLeft(count, register, width) {
+ local modcount = count & 63;
+ register = (register << modcount) | (register >> (width - modcount));
+ resflags(register);
+ CF = (register & 1) != 0;
+ VF = 0;
+}
+
+macro rotateRight(count, register, width) {
+ local modcount = count & 63;
+ register = (register << (width - modcount)) | (register >> modcount);
+ resflags(register);
+ CF = zext(register s< 0);
+ VF = 0;
+}
+
+macro rotateLeftExtended(count, register, width) {
+ local modcount = count & 63;
+ local xflag = (register & (1 << (width - modcount))) != 0;
+ local result = (register << modcount) | (zext(XF) << (modcount - 1)) | (register >> (width - modcount + 1));
+ register = (zext(modcount != 0) * result) + (zext(modcount == 0) * register);
+ resflags(register);
+ XF = (zext(modcount != 0) * xflag) + (zext(modcount == 0) * XF);
+ CF = XF;
+ VF = 0;
+}
+
+macro rotateRightExtended(count, register, width) {
+ local modcount = count & 63;
+ local xflag = (register & (1 << (modcount - 1))) != 0;
+ local result = (zext(XF) << (width - modcount)) | (register >> modcount) | (register << (width - modcount + 1));
+ register = (zext(modcount != 0) * result) + (zext(modcount == 0) * register);
+ resflags(register);
+ XF = (zext(modcount != 0) * xflag) + (zext(modcount == 0) * XF);
+ CF = XF;
+ VF = 0;
+}
+
+:^instruction is extGUARD=0 & mode2 & reg9an & mode & regan & instruction
+ [ extGUARD=1; regtfan=regan; savmod1=mode; regtsan=reg9an; savmod2=mode2; ] {}
+
+# Here are the instructions
+
+with : extGUARD=1 {
+
+:abcd Tyb,Txb is op=12 & op48=16 & Tyb & Txb {
+ CF = carry(Txb,carry(Tyb,XF));
+ Txb = Txb + Tyb + XF;
+ XF = bcdAdjust(Txb);
+ bcdflags(Txb);
+}
+
+:add.b eab,reg9dnb is (op=13 & reg9dnb & op68=0)... & eab { addflags(eab,reg9dnb); reg9dnb = reg9dnb + eab; resflags(reg9dnb); }
+:add.w eaw,reg9dnw is (op=13 & reg9dnw & op68=1)... & eaw { addflags(eaw,reg9dnw); reg9dnw = reg9dnw + eaw; resflags(reg9dnw); }
+:add.l eal,reg9dn is (op=13 & reg9dn & op68=2)... & eal { addflags(eal,reg9dn); reg9dn = reg9dn + eal; resflags(reg9dn); }
+:add.b reg9dnb,eab is (op=13 & reg9dnb & op68=4 & $(MEM_ALTER_ADDR_MODES))... & eab { addflags(reg9dnb,eab); eab = reg9dnb + eab; resflags(eab); }
+:add.w reg9dnw,eaw is (op=13 & reg9dnw & op68=5 & $(MEM_ALTER_ADDR_MODES))... & eaw { addflags(reg9dnw,eaw); eaw = reg9dnw + eaw; resflags(eaw); }
+:add.l reg9dn,eal is (op=13 & reg9dn & op68=6 & $(MEM_ALTER_ADDR_MODES))... & eal { addflags(reg9dn,eal); eal = reg9dn + eal; resflags(eal); }
+
+:adda.w eaw,reg9an is (op=13 & reg9an & op68=3)... & eaw { reg9an = sext(eaw) + reg9an; }
+:adda.l eal,reg9an is (op=13 & reg9an & op68=7)... & eal { reg9an = eal + reg9an; }
+
+:addi.b "#"^d8,e2b is opbig=6 & op67=0 & savmod1 & regtfan & $(DAT_ALTER_ADDR_MODES); d8; e2b [ savmod2=savmod1; regtsan=regtfan; ] { addflags(d8,e2b); e2b = d8 + e2b; resflags(e2b); }
+:addi.w "#"^d16,e2w is opbig=6 & op67=1 & savmod1 & regtfan & $(DAT_ALTER_ADDR_MODES); d16; e2w [ savmod2=savmod1; regtsan=regtfan; ] { addflags(d16,e2w); e2w = d16 + e2w; resflags(e2w); }
+:addi.l "#"^d32,e2l is opbig=6 & op67=2 & savmod1 & regtfan & $(DAT_ALTER_ADDR_MODES); d32; e2l [ savmod2=savmod1; regtsan=regtfan; ] { addflags(d32,e2l); e2l = d32+e2l; resflags(e2l); }
+
+:addq.b "#"^quick,eab is (op=5 & quick & op68=0)... & eab { addflags(quick,eab); eab = eab+quick; resflags(eab); }
+:addq.w "#"^quick,eaw is (op=5 & quick & op68=1)... & eaw { addflags(quick,eaw); eaw = eaw+quick; resflags(eaw); }
+:addq.l "#"^quick,eal is (op=5 & quick & op68=2)... & eal { addflags(quick,eal); eal = eal+quick; resflags(eal); }
+# special case for address register destination
+:addq.w "#"^quick,regan is op=5 & quick & op68=1 & mode=1 & regan { regan = regan + quick; }
+:addq.l "#"^quick,regan is op=5 & quick & op68=2 & mode=1 & regan { regan = regan + quick; }
+
+
+:addx.b Tyb,Txb is op=13 & op8=1 & op67=0 & op45=0 & Tyb & Txb
+ { addxflags(Tyb,Txb); Txb=Tyb+Txb+zext(XF); extendedResultFlags(Txb); }
+:addx.w Tyw,Txw is op=13 & op8=1 & op67=1 & op45=0 & Tyw & Txw
+ { addxflags(Tyw,Txw); Txw=Tyw+Txw+zext(XF); extendedResultFlags(Txw); }
+:addx.l Ty,Tx is op=13 & op8=1 & op67=2 & op45=0 & Ty & Tx
+ { addxflags(Ty,Tx); Tx=Ty+Tx+zext(XF); extendedResultFlags(Tx); }
+
+:and.b eab,reg9dnb is (op=12 & reg9dnb & op68=0 & $(DAT_ALTER_ADDR_MODES))... & eab { logflags(); reg9dnb = reg9dnb & eab; resflags(reg9dnb); }
+:and.w eaw,reg9dnw is (op=12 & reg9dnw & op68=1 & $(DAT_ALTER_ADDR_MODES))... & eaw { logflags(); reg9dnw = reg9dnw & eaw; resflags(reg9dnw); }
+:and.l eal,reg9dn is (op=12 & reg9dn & op68=2 & $(DAT_ALTER_ADDR_MODES))... & eal { logflags(); reg9dn = reg9dn & eal; resflags(reg9dn); }
+:and.b reg9dnb,eab is (op=12 & reg9dnb & op68=4 & $(MEM_ALTER_ADDR_MODES))... & eab { logflags(); eab = reg9dnb & eab; resflags(eab); }
+:and.w reg9dnw,eaw is (op=12 & reg9dnw & op68=5 & $(MEM_ALTER_ADDR_MODES))... & eaw { logflags(); eaw = reg9dnw & eaw; resflags(eaw); }
+:and.l reg9dn,eal is (op=12 & reg9dn & op68=6 & $(MEM_ALTER_ADDR_MODES))... & eal { logflags(); eal = reg9dn & eal; resflags(eal); }
+
+:andi.b const8,e2b is opbig=2 & op67=0 & $(DAT_ALTER_ADDR_MODES); const8; e2b [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); e2b = e2b & const8; resflags(e2b); }
+:andi.w const16,e2w is opbig=2 & op67=1 & $(DAT_ALTER_ADDR_MODES); const16; e2w [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); e2w = e2w & const16; resflags(e2w); }
+:andi.l const32,e2l is opbig=2 & op67=2 & $(DAT_ALTER_ADDR_MODES); const32; e2l [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); e2l=e2l & const32; resflags(e2l); }
+:andi const8,"CCR" is d16=0x23c; const8 { packflags(SR); SR = SR & zext(const8); unpackflags(SR); }
+:andi const16,SR is opbig=0x2 & d8base=0x7c; const16 & SR { packflags(SR); SR = SR & const16; unpackflags(SR); }
+
+:asl.b cntreg,regdnb is op=14 & cntreg & op8=1 & op67=0 & op34=0 & regdnb { arithmeticShiftLeft(cntreg, regdnb, 8); }
+:asl.w cntreg,regdnw is op=14 & cntreg & op8=1 & op67=1 & op34=0 & regdnw { arithmeticShiftLeft(cntreg, regdnw, 16); }
+:asl.l cntreg,regdn is op=14 & cntreg & op8=1 & op67=2 & op34=0 & regdn { arithmeticShiftLeft(cntreg, regdn, 32); }
+:asl eaw is (opbig=0xe1 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw {
+ local value:2 = eaw;
+ local msbBefore = value & 0x8000;
+ getbit(CF, value, 15);
+ value = value << 1;
+ resflags(value);
+ local msbAfter = value & 0x8000;
+ VF = (msbBefore ^ msbAfter) != 0;
+ eaw = value;
+ XF = CF;
+}
+
+:asr.b cntreg,regdnb is op=14 & cntreg & op8=0 & op67=0 & op34=0 & regdnb { arithmeticShiftRight(cntreg, regdnb, 8); }
+:asr.w cntreg,regdnw is op=14 & cntreg & op8=0 & op67=1 & op34=0 & regdnw { arithmeticShiftRight(cntreg, regdnw, 16); }
+:asr.l cntreg,regdn is op=14 & cntreg & op8=0 & op67=2 & op34=0 & regdn { arithmeticShiftRight(cntreg, regdn, 32); }
+:asr eaw is (opbig=0xe0 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw {
+ local value:2 = eaw;
+ local msbBefore = value & 0x8000;
+ getbit(CF, value, 0);
+ value = value s>> 1;
+ resflags(value);
+ local msbAfter = value & 0x8000;
+ VF = (msbBefore ^ msbAfter) != 0;
+ eaw = value;
+ XF = CF;
+}
+
+:b^cc^".b" addr8 is op=6 & cc & addr8 { if (cc) goto addr8; }
+:b^cc^".w" addr16 is op=6 & cc & d8base=0; addr16 { if (cc) goto addr16; }
+:b^cc^".l": addr32 is op=6 & cc & d8base=255; addr32 { if (cc) goto addr32; }
+
+:bchg.b reg9dn,eab is (op=0 & reg9dn & op68=5 & $(MEM_ALTER_ADDR_MODES))... & eab {
+ mask:1 = 1<<(reg9dn&7); ZF=(eab&mask)==0; eab=eab^mask; }
+
+:bchg.b d8,e2b is opbig=8 & op67=1 & $(MEM_ALTER_ADDR_MODES); d8; e2b
+ [ savmod2=savmod1; regtsan=regtfan; ] {
+ mask:1 = 1<<(d8 & 7); # target is a byte in memory, so the bit number in the byte is modulo 8
+ ZF=(e2b&mask)==0;
+ e2b=e2b^mask;}
+
+:bchg.l reg9dn,regdn is op=0 & reg9dn & op68=5 & mode=0 & regdn { mask:4 = 1<<(reg9dn&31); ZF=(regdn&mask)==0; regdn=regdn^mask; }
+:bchg.l d8,regdn is opbig=8 & op67=1 & mode=0 & regdn; d8 { mask:4 = 1<> (32 - f_wd); f_reg = tmp; tmp2:4 = e2l; getbitfield(tmp2, f_off, f_wd); resbitflags(tmp2, f_wd-1);
+
+}
+
+:bfextu e2l{f_off:f_wd},f_reg is opbig=0xe9 & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd & f_reg; e2l [ savmod2=savmod1; regtsan=regtfan; ] {
+ logflags(); tmp:4 = e2l; getbitfield(tmp, f_off, f_wd); f_reg = tmp; resbitflags(f_reg, f_wd-1);
+}
+
+:bfffo e2l{f_off:f_wd},f_reg is opbig=0xed & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd & f_reg & flddo=0 & fldoffdat=0 & flddw=0 & fldwddat=0; e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] {
+ # "Find First One in Bit Field" pronounced "boo-foe"
+ # Set the destination f_reg with the position of the first 1 bit in the source e2l.
+ # f_off and f_wd specify the offset and width of the field of the source to consider.
+ # If f_off=0 and f_wd=0 then this means the full 32-bit source is examined (implemented here).
+ #
+ tmp:4 = e2l;
+ NF = (tmp & 0x80000000) != 0;
+ ZF = (tmp == 0);
+ VF = 0;
+ CF = 0;
+ tmp2:4 = lzcount(tmp);
+ # NB- it seems the MSB left most bit is really at offset 0,
+ # and the right LSB is at offset 31
+ tmp3:4 = tmp2 % 32:4; # need mod for when there are all zeros, when tmp2 would = 32
+ f_reg = tmp3;
+}
+
+# TODO: complete bfffo for when f_off or f_wd !=0, and for when f_off and f_wd are in registers
+:bfffo e2l{f_off:f_wd},f_reg is opbig=0xed & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd & f_reg ; e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+
+
+:bfins f_reg,e2l{f_off:f_wd} is opbig=0xef & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd & f_reg; e2l [ savmod2=savmod1; regtsan=regtfan; ] {
+ logflags(); mask:4 = 0; bitmask(mask, f_wd); tmp:4 = f_reg & mask; resbitflags(tmp, f_wd-1); bfmask(mask,f_off,f_wd); e2l = (e2l & ~mask) | (tmp << (32 - f_off - f_wd));
+}
+
+:bfset e2l{f_off:f_wd} is opbig=0xee & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd; e2l [ savmod2=savmod1; regtsan=regtfan; ] {
+ logflags(); tmp:4 = e2l; getbitfield(tmp, f_off, f_wd); resbitflags(tmp, f_wd-1); mask:4 = 0; bfmask(mask,f_off,f_wd); e2l = e2l & ~mask;
+}
+
+:bftst e2l{f_off:f_wd} is opbig=0xe8 & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd; e2l [ savmod2=savmod1; regtsan=regtfan; ] {
+ logflags(); tmp:4 = e2l; getbitfield(tmp, f_off, f_wd); resbitflags(tmp, f_wd-1);
+}
+
+:bkpt "#"op02 is opbig=0x48 & op67=1 & op5=0 & op34=1 & op02 unimpl
+
+:bra.b addr8 is opbig=0x60 & addr8 { goto addr8; }
+:bra.w addr16 is opbig=0x60 & d8base=0; addr16 { goto addr16; }
+:bra.l addr32 is opbig=0x60 & d8base=255; addr32 { goto addr32; }
+
+:bset.b reg9dn,eab is (op=0 & reg9dn & op68=7 & $(MEM_ALTER_ADDR_MODES))... & eab { mask:1 = 1<<(reg9dn&7); ZF=(eab&mask)==0; eab=eab|mask; }
+:bset.b d8,e2b is opbig=8 & op67=3 & $(MEM_ALTER_ADDR_MODES); d8; e2b [ savmod2=savmod1; regtsan=regtfan; ] { mask:1=1<> 8) | ((regdn & 0xFF000000) >> 24);
+}
+
+@endif # COLDFIRE
+
+:callm "#"^d8,e2l is opbig=6 & op67=3 & $(CTL_ADDR_MODES); d8; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+
+#TODO: should constrain CAS to ignore mode=7 & regan=4 (place CAS2 before CAS to avoid problem)
+:cas2.w regdcw:regdc2w,regduw:regdu2w,(regda):(regda2) is op015=0x0cfc; regda & ext_911=0 & regduw & ext_35=0 & regdcw; regda2 & ext2_911=0 & regdu2w & ext2_35=0 & regdc2w {
+ dc1:4 = zext(regdcw);
+ dc2:4 = zext(regdc2w);
+ if(dc1!=regda) goto ;
+ if(dc2!=regda2) goto ;
+ regda = zext(regduw);
+ regda2 = zext(regdu2w);
+ ZF = 1;
+ NF = 0;
+ goto inst_next;
+
+ regdcw = regda(2);
+ regdc2w = regda2(2);
+ ZF = 0;
+ NF = 1;
+}
+:cas2.l regdc:regdc2,regdu:regdu2,(regda):(regda2) is op015=0x0efc; regda & ext_911=0 & regdu & ext_35=0 & regdc; regda2 & ext2_911=0 & regdu2 & ext2_35=0 & regdc2 {
+ if(regdc!=regda) goto ;
+ if(regdc2!=regda2) goto ;
+ regda = regdu;
+ regda2 = regdu2;
+ ZF = 1;
+ NF = 0;
+ goto inst_next;
+
+ regdc = regda;
+ regdc2 = regda2;
+ ZF = 0;
+ NF = 1;
+}
+
+:cas.b regdcb,regdub,e2b is opbig=0x0a & op67=3 & $(MEM_ALTER_ADDR_MODES); regda=0 & ext_911=0 & regdub & ext_35=0 & regdcb; e2b [ savmod2=savmod1; regtsan=regtfan; ] {
+ if(e2b==regdcb) goto ;
+ regdcb = e2b;
+ ZF = 0;
+ NF = 1;
+ goto inst_next;
+
+ e2b = regdub;
+ ZF = 1;
+ NF = 0;
+}
+:cas.w regdcw,regduw,e2w is opbig=0x0c & op67=3 & $(MEM_ALTER_ADDR_MODES); regda=0 & ext_911=0 & regduw & ext_35=0 & regdcw; e2w [ savmod2=savmod1; regtsan=regtfan; ] {
+ if(e2w==regdcw) goto ;
+ regdcw = e2w;
+ ZF = 0;
+ NF = 1;
+ goto inst_next;
+
+ e2w = regduw;
+ ZF = 1;
+ NF = 0;
+}
+:cas.l regdc,regdu,e2l is opbig=0x0e & op67=3 & $(MEM_ALTER_ADDR_MODES); regda=0 & ext_911=0 & regdu & ext_35=0 & regdc; e2l [ savmod2=savmod1; regtsan=regtfan; ] {
+ if(e2l==regdc) goto ;
+ regdc = e2l;
+ ZF = 0;
+ NF = 1;
+ goto inst_next;
+
+ e2l = regdu;
+ ZF = 1;
+ NF = 0;
+}
+
+:chk.w eaw,reg9dnw is (op=4 & reg9dnw & op68=6 & $(DAT_ALTER_ADDR_MODES))... & eaw {
+ build eaw;
+ local address:4 = zext(eaw);
+ local bound:2 = *:2 address;
+ local signed_bound:4 = sext(bound);
+ local signed_register:4 = sext(reg9dnw);
+
+ if ((signed_register s>= 0) && (signed_register s<= signed_bound)) goto inst_next;
+ NF = signed_register s< 0;
+ __m68k_trap(6:1);
+}
+
+:chk.l eal,reg9dn is (op=4 & reg9dn & op68=4 & $(DAT_ALTER_ADDR_MODES))... & eal {
+ build eal;
+ local address:4 = zext(eal);
+ local bound:4 = *:4 address;
+ local signed_bound:4 = sext(bound);
+ local signed_register:4 = sext(reg9dn);
+
+ if ((signed_register s>= 0) && (signed_register s<= signed_bound)) goto inst_next;
+ NF = signed_register s< 0;
+ __m68k_trap(6:1);
+}
+
+:chk2.b e2b,rreg is opbig=0 & op67=3 & $(CTL_ADDR_MODES); rreg & wl=1; e2b [ savmod2=savmod1; regtsan=regtfan; ] {
+ build e2b;
+ local address:4 = zext(e2b);
+ local lower:1 = *:1 address;
+ local upper:1 = *:1 (address + 1);
+ local signed_lower:4 = sext(lower);
+ local signed_upper:4 = sext(upper);
+ local signed_register:4 = sext(rreg);
+
+ ZF = ((signed_register == signed_lower) || (signed_register == signed_upper));
+ CF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper));
+ if (!CF) goto inst_next;
+ __m68k_trap(6:1);
+}
+
+:chk2.w e2w,rreg is opbig=2 & op67=3 & $(CTL_ADDR_MODES); rreg & wl=1; e2w [ savmod2=savmod1; regtsan=regtfan; ] {
+ build e2w;
+ local address:4 = zext(e2w);
+ local lower:2 = *:2 address;
+ local upper:2 = *:2 (address + 2);
+ local signed_lower:4 = sext(lower);
+ local signed_upper:4 = sext(upper);
+ local signed_register:4 = sext(rreg);
+
+ ZF = ((signed_register == signed_lower) || (signed_register == signed_upper));
+ CF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper));
+ if (!CF) goto inst_next;
+ __m68k_trap(6:1);
+}
+
+:chk2.l e2l,rreg is opbig=4 & op67=3 & $(CTL_ADDR_MODES); rreg & wl=1; e2l [ savmod2=savmod1; regtsan=regtfan; ] {
+ build e2l;
+ local address:4 = zext(e2l);
+ local lower:4 = *:4 address;
+ local upper:4 = *:4 (address + 4);
+ local signed_lower:4 = sext(lower);
+ local signed_upper:4 = sext(upper);
+ local signed_register:4 = sext(rreg);
+
+ ZF = ((signed_register == signed_lower) || (signed_register == signed_upper));
+ CF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper));
+ if (!CF) goto inst_next;
+ __m68k_trap(6:1);
+}
+
+:cmp2.b e2b,rreg is opbig=0 & op67=3 & $(CTL_ADDR_MODES); rreg & wl=0; e2b [ savmod2=savmod1; regtsan=regtfan; ] {
+ build e2b;
+ local address:4 = zext(e2b);
+ local lower:1 = *:1 address;
+ local upper:1 = *:1 (address + 1);
+ local signed_lower:4 = sext(lower);
+ local signed_upper:4 = sext(upper);
+ local signed_register:4 = sext(rreg);
+
+ ZF = ((signed_register == signed_lower) || (signed_register == signed_upper));
+ CF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper));
+}
+
+:cmp2.w e2w,rreg is opbig=2 & op67=3 & $(CTL_ADDR_MODES); rreg & wl=0; e2w [ savmod2=savmod1; regtsan=regtfan; ] {
+ build e2w;
+ local address:4 = zext(e2w);
+ local lower:2 = *:2 address;
+ local upper:2 = *:2 (address + 2);
+ local signed_lower:4 = sext(lower);
+ local signed_upper:4 = sext(upper);
+ local signed_register:4 = sext(rreg);
+
+ ZF = ((signed_register == signed_lower) || (signed_register == signed_upper));
+ CF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper));
+}
+
+:cmp2.l e2l,rreg is opbig=4 & op67=3 & $(CTL_ADDR_MODES); rreg & wl=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] {
+ build e2l;
+ local address:4 = zext(e2l);
+ local lower:4 = *:4 address;
+ local upper:4 = *:4 (address + 4);
+ local signed_lower:4 = sext(lower);
+ local signed_upper:4 = sext(upper);
+ local signed_register:4 = sext(rreg);
+
+ ZF = ((signed_register == signed_lower) || (signed_register == signed_upper));
+ CF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper));
+}
+
+@ifdef MC68040
+
+cachetype: "none" is op67=0 { export 0:4; }
+cachetype: "data" is op67=1 { export 1:4; }
+cachetype: "instr" is op67=2 { export 2:4; }
+cachetype: "both" is op67=3 { export 3:4; }
+:cinvl cachetype,(regan) is opbig=0xf4 & cachetype & op5=0 & op34=1 & regan unimpl
+:cinvp cachetype,(regan) is opbig=0xf4 & cachetype & op5=0 & op34=2 & regan unimpl
+:cinva cachetype is opbig=0xf4 & cachetype & op5=0 & op34=3 unimpl
+
+@endif # MC68040
+
+
+@ifdef MC68040
+
+:cpushl cachetype,(regan) is opbig=0xf4 & cachetype & op5=1 & op34=1 & regan {pushInvalidateCaches(regan);}
+:cpushp cachetype,(regan) is opbig=0xf4 & cachetype & op5=1 & op34=2 & regan {pushInvalidateCaches(regan);}
+:cpusha cachetype is opbig=0xf4 & cachetype & op5=1 & op34=3 {pushInvalidateCaches();}
+
+@endif # MC68040
+
+:clr.b eab is (opbig=0x42 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab { eab = 0; NF=0; ZF=1; VF=0; CF=0; }
+:clr.w eaw is (opbig=0x42 & op67=1 & $(DAT_ALTER_ADDR_MODES))... & eaw { eaw = 0; NF=0; ZF=1; VF=0; CF=0; }
+:clr.l eal is (opbig=0x42 & op67=2 & $(DAT_ALTER_ADDR_MODES))... & eal { eal=0; NF=0; ZF=1; VF=0; CF=0; }
+
+:cmp.b eab,reg9dnb is (op=11 & reg9dnb & op68=0)... & eab { o2:1=eab; subflags(reg9dnb,o2); local tmp =reg9dnb-o2; resflags(tmp); }
+:cmp.w eaw,reg9dnw is (op=11 & reg9dnw & op68=1)... & eaw { o2:2=eaw; subflags(reg9dnw,o2); local tmp =reg9dnw-o2; resflags(tmp); }
+:cmp.l eal,reg9dn is (op=11 & reg9dn & op68=2)... & eal { o2:4=eal; subflags(reg9dn,o2); local tmp =reg9dn-o2; resflags(tmp); }
+
+:cmpa.w eaw,reg9an is (op=11 & reg9an & op68=3)... & eaw { tmp1:4 = sext(eaw); subflags(reg9an,tmp1); local tmp =reg9an-tmp1; resflags(tmp); }
+:cmpa.l eal,reg9an is (op=11 & reg9an & op68=7)... & eal { o2:4=eal; subflags(reg9an,o2); local tmp =reg9an-o2; resflags(tmp); }
+
+
+:cmpi.b "#"^d8,e2b is opbig=12 & op67=0 & savmod1 & regtfan & $(DAT_ALTER_ADDR_MODES); d8; e2b [ savmod2=savmod1; regtsan=regtfan; ] { o2:1=e2b; subflags(o2,d8); local tmp =o2-d8; resflags(tmp); }
+:cmpi.w "#"^d16,e2w is opbig=12 & op67=1 & savmod1 & regtfan & $(DAT_ALTER_ADDR_MODES); d16; e2w [ savmod2=savmod1; regtsan=regtfan; ] { o2:2=e2w; subflags(o2,d16); local tmp =o2-d16; resflags(tmp);}
+:cmpi.l "#"^d32,e2l is opbig=12 & op67=2 & savmod1 & regtfan & $(DAT_ALTER_ADDR_MODES); d32; e2l [ savmod2=savmod1; regtsan=regtfan; ] { o2:4=e2l; subflags(o2,d32); local tmp =o2-d32; resflags(tmp);}
+
+:cmpm.b (regan)+,(reg9an)+ is op=11 & reg9an & op8=1 & op67=0 & op5=0 & op34=1 & regan { local tmp1=*:1 regan; regan=regan+1; local tmp2=*:1 reg9an; reg9an=reg9an+1;
+ subflags(tmp2,tmp1); local tmp =tmp2-tmp1; resflags(tmp); }
+:cmpm.w (regan)+,(reg9an)+ is op=11 & reg9an & op8=1 & op67=1 & op5=0 & op34=1 & regan { local tmp1=*:2 regan; regan=regan+2; local tmp2=*:2 reg9an; reg9an=reg9an+2;
+ subflags(tmp2,tmp1); local tmp =tmp2-tmp1; resflags(tmp); }
+:cmpm.l (regan)+,(reg9an)+ is op=11 & reg9an & op8=1 & op67=2 & op5=0 & op34=1 & regan { local tmp1=*:4 regan; regan=regan+4; local tmp2=*:4 reg9an; reg9an=reg9an+4;
+ subflags(tmp2,tmp1); local tmp =tmp2-tmp1; resflags(tmp); }
+# cpBcc # need to know specific copressors use copcc1
+# cpDBcc # use copcc2
+# cpGEN
+# cpScc # use copcc2
+# cpTRAPcc # use copcc2
+
+:db^cc regdnw,addr16 is op=5 & cc & op67=3 & op5=0 & op34=1 & regdnw; addr16 { if (cc) goto inst_next; regdnw=regdnw-1; if (regdnw!=-1) goto addr16; }
+
+:divs.w eaw,reg9dn is (op=8 & reg9dn & op68=7)... & eaw { local denom=sext(eaw); local div=reg9dn s/ denom; local rem=reg9dn s% denom; CF=0; resflags(div);
+ reg9dn = (rem<<16) | (div & 0xffff); }
+
+:divu.w eaw,reg9dn is (op=8 & reg9dn & op68=3)... & eaw { local denom=zext(eaw); local div=reg9dn / denom; local rem=reg9dn %denom; CF=0; resflags(div);
+ reg9dn = (rem<<16) | (div & 0xffff); }
+
+#remyes: "s" is regdq & (regdr=regdq) & divsgn=1 { }
+remyes: "sl" is divsgn=1 { }
+#remyes: "u" is regdq & (regdr=regdq) & divsgn=0 { }
+remyes: "ul" is divsgn=0 { }
+
+#subdiv: regdq is regdq & regdr=regdq & divsz=0 & divsgn=0 { regdq = regdq/glbdenom; export regdq; }
+
+# NB- Need to be very careful with div to not clobber when regdr and regdq refer to the same reg.
+# When this happens it seems the destination reg should get the quotient, not the remainder.
+#
+subdiv: regdr:regdq is regdq & regdr & divsz=0 & divsgn=0 {
+ local rem = regdq % glbdenom; local quot = regdq / glbdenom; regdr = rem; regdq = quot; export regdq; }
+
+subdiv: regdr:regdq is regdq & regdr & divsz=1 & divsgn=0 { divi:8 = (zext(regdr)<<32)|zext(regdq); denom:8=zext(glbdenom);
+ local quot=divi/denom; local rem=divi%denom; regdr=rem:4; regdq = quot:4; export regdq; }
+
+#subdiv: regdq is regdq & regdr=regdq & divsz=0 & divsgn=1 { regdq = regdq s/ glbdenom; export regdq; }
+
+subdiv: regdr:regdq is regdq & regdr & divsz=0 & divsgn=1 {
+ local rem = regdq s% glbdenom; local quot = regdq s/ glbdenom; regdr = rem; regdq = quot; export regdq; }
+
+subdiv: regdr:regdq is regdq & regdr & divsz=1 & divsgn=1 { divi:8 = (sext(regdr)<<32)|sext(regdq); denom:8=sext(glbdenom);
+ local quot=divi s/denom; local rem=divi s%denom; regdr=rem:4; regdq=quot:4; export regdq; }
+
+# when divsgn=0
+# divu.l is regdq / e2l -> regdq
+# divu.l (when divsz = 1) is regdr concat regdq / el2 - > regdr and regdq
+# divul.l (when divsz = 0) is regdq / el2 -> regdr and regdq
+#
+:div^remyes^".l" e2l,subdiv is opbig=0x4c & op67=1 & $(DAT_ALTER_ADDR_MODES); subdiv & remyes; e2l [ savmod2=savmod1; regtsan=regtfan;] { glbdenom=e2l; build subdiv; CF=0; resflags(subdiv);}
+
+:eor.b reg9dnb,eab is (op=11 & reg9dnb & op68=4 & $(DAT_ALTER_ADDR_MODES))... & eab { logflags(); eab = reg9dnb ^ eab; resflags(eab); }
+:eor.w reg9dnw,eaw is (op=11 & reg9dnw & op68=5 & $(DAT_ALTER_ADDR_MODES))... & eaw { logflags(); eaw = reg9dnw ^ eaw; resflags(eaw); }
+:eor.l reg9dn,eal is (op=11 & reg9dn & op68=6 & $(DAT_ALTER_ADDR_MODES))... & eal { logflags(); eal = reg9dn ^ eal; resflags(eal); }
+
+:eori.b "#"^d8,e2b is opbig=10 & op67=0 & $(DAT_ALTER_ADDR_MODES); d8; e2b [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); e2b = e2b^d8; resflags(e2b); }
+:eori.w "#"^d16,e2w is opbig=10 & op67=1 & $(DAT_ALTER_ADDR_MODES); d16; e2w [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); e2w = e2w^d16; resflags(e2w); }
+:eori.l "#"^d32,e2l is opbig=10 & op67=2 & $(DAT_ALTER_ADDR_MODES); d32; e2l [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); e2l=e2l^d32; resflags(e2l); }
+:eori "#"^d8,"CCR" is d16=0xa3c; d8 { packflags(SR); SR = SR ^ d8; unpackflags(SR); }
+:eori "#"^d16,SR is opbig=0x0a & d8base=0x7c; d16 & SR { packflags(SR); SR = SR ^ d16; unpackflags(SR); }
+
+
+:exg reg9dn,regdn is op=12 & reg9dn & op8=1 & op37=8 & regdn { local tmp = reg9dn; reg9dn=regdn; regdn=tmp; }
+:exg reg9an,regan is op=12 & reg9an & op8=1 & op37=9 & regan { local tmp = reg9an; reg9an=regan; regan=tmp; }
+:exg reg9dn,regan is op=12 & reg9dn & op8=1 & op37=17 & regan { local tmp = reg9dn; reg9dn=regan; regan=tmp; }
+
+:ext.w regdnw is op=4 & reg9dn=4 & op68=2 & op35=0 & regdnw { local tmp =regdnw:1; regdnw = sext(tmp); }
+:ext.l regdn is op=4 & reg9dn=4 & op68=3 & op35=0 & regdn { local tmp =regdn:2; regdn = sext(tmp); }
+:extb.l regdn is op=4 & reg9dn=4 & op68=7 & op35=0 & regdn { local tmp =regdn:1; regdn = sext(tmp); }
+
+:illegal is d16=0x4afc unimpl
+
+# jump addresses derived from effective address calculation
+addrpc16: reloc is d16 [ reloc = inst_start+2+d16; ] { export *[ram]:4 reloc; }
+addrd16: d16 is d16 { export *[ram]:4 d16; }
+addrd32: d32 is d32 { export *[ram]:4 d32; }
+
+:jmp (regan) is opbig=0x4e & op67=3 & mode=2 & regan { goto [regan]; }
+:jmp (d16,regan) is opbig=0x4e & op67=3 & mode=5 & regan; d16 { local tmp = regan + d16; goto [tmp]; }
+:jmp (extw) is opbig=0x4e & op67=3 & mode=6 & regan; extw [ pcmode=0; regtfan=regan; ] { build extw; goto [extw]; }
+:jmp addrpc16 is opbig=0x4e & op67=3 & mode=7 & regan=2; addrpc16 { goto addrpc16; }
+:jmp (extw) is opbig=0x4e & op67=3 & mode=7 & regan=3; extw [ pcmode=1; ] { build extw; goto [extw]; }
+:jmp addrd16".w" is opbig=0x4e & op67=3 & mode=7 & regan=0; addrd16 { goto addrd16; }
+:jmp addrd32".l" is opbig=0x4e & op67=3 & mode=7 & regan=1; addrd32 { goto addrd32; }
+
+:jsr (regan) is opbig=0x4e & op67=2 & mode=2 & regan { SP=SP-4; *:4 SP = inst_next; call [regan]; }
+:jsr (d16,regan) is opbig=0x4e & op67=2 & mode=5 & regan; d16 { SP=SP-4; *:4 SP = inst_next; local tmp = regan + d16; call [tmp]; }
+:jsr (extw) is opbig=0x4e & op67=2 & mode=6 & regan; extw [ pcmode=0; regtfan=regan;] { build extw; SP=SP-4; *:4 SP=inst_next; call [extw];}
+:jsr addrpc16 is opbig=0x4e & op67=2 & mode=7 & regan=2; addrpc16 { SP=SP-4; *:4 SP = inst_next; call addrpc16; }
+:jsr (extw) is opbig=0x4e & op67=2 & mode=7 & regan=3; extw [ pcmode=1; ] { build extw; SP=SP-4; *:4 SP = inst_next; call [extw]; }
+:jsr addrd16".w" is opbig=0x4e & op67=2 & mode=7 & regan=0; addrd16 { SP=SP-4; *:4 SP = inst_next; call addrd16; }
+:jsr addrd32".l" is opbig=0x4e & op67=2 & mode=7 & regan=1; addrd32 { SP=SP-4; *:4 SP = inst_next; call addrd32; }
+
+:lea eaptr,reg9an is (op=4 & reg9an & op68=7)... & eaptr { reg9an = eaptr; }
+
+:link.w regan,d16 is opbig=0x4e & op37=10 & regan; d16 { SP=SP-4; *:4 SP = regan; regan=SP; SP = SP + d16; }
+:link.l regan,d32 is opbig=0x48 & op37=1 & regan; d32 { SP=SP-4; *:4 SP = regan; regan=SP; SP = SP + d32; }
+
+macro shiftCXFlags(cntreg) {
+ CF = CF * (cntreg != 0);
+ XF = CF * (cntreg != 0) + XF * (cntreg == 0);
+}
+
+:lsl.b cntreg,regdnb is op=14 & cntreg & op8=1 & op67=0 & op34=1 & regdnb { logicalShiftLeft(cntreg, regdnb, 8); }
+:lsl.w cntreg,regdnw is op=14 & cntreg & op8=1 & op67=1 & op34=1 & regdnw { logicalShiftLeft(cntreg, regdnw, 16); }
+:lsl.l cntreg,regdn is op=14 & cntreg & op8=1 & op67=2 & op34=1 & regdn { logicalShiftLeft(cntreg, regdn, 32); }
+:lsl eaw is (opbig=0xe3 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw {
+ local value:2 = eaw;
+ getbit(CF, value, 15);
+ value = value << 1;
+ resflags(value);
+ eaw = value;
+ VF = 0;
+ XF = CF;
+}
+
+:lsr.b cntreg,regdnb is op=14 & cntreg & op8=0 & op67=0 & op34=1 & regdnb { logicalShiftRight(cntreg, regdnb, 8); }
+:lsr.w cntreg,regdnw is op=14 & cntreg & op8=0 & op67=1 & op34=1 & regdnw { logicalShiftRight(cntreg, regdnw, 16); }
+:lsr.l cntreg,regdn is op=14 & cntreg & op8=0 & op67=2 & op34=1 & regdn { logicalShiftRight(cntreg, regdn, 32); }
+:lsr eaw is (opbig=0xe2 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw {
+ local value:2 = eaw;
+ getbit(CF, value, 0);
+ value = value >> 1;
+ resflags(value);
+ eaw = value;
+ VF = 0;
+ XF = CF;
+}
+
+:move.b eab,e2b is (op=1 & $(DAT_ALTER_ADDR_MODES2))... & eab ; e2b { build eab; local tmp = eab; build e2b; e2b = tmp; resflags(tmp); logflags(); }
+:move.w eaw,e2w is (op=3 & $(DAT_ALTER_ADDR_MODES2))... & eaw ; e2w { build eaw; local tmp = eaw; build e2w; e2w = tmp; resflags(tmp); logflags(); }
+:move.l eal,e2l is (op=2 & $(DAT_ALTER_ADDR_MODES2))... & eal ; e2l { build eal; local tmp = eal; build e2l; e2l = tmp; resflags(tmp); logflags(); }
+
+:move "CCR",eaw is (opbig=0x42 & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eaw { packflags(SR); eaw = SR; }
+:move eaw,"CCR" is (opbig=0x44 & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eaw { unpackflags(eaw); }
+:move SR,eaw is SR; (opbig=0x40 & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eaw { packflags(SR); eaw = SR; }
+:move eaw,SR is SR; (opbig=0x46 & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eaw { SR = eaw; unpackflags(SR); }
+:move USP,regan is opbig=0x4e & op37=13 & regan & USP { regan = USP; }
+:move regan,USP is opbig=0x4e & op37=12 & regan & USP { USP = regan; }
+
+:movea.w eaw,reg9an is (op=3 & reg9an & mode2=1)... & eaw { reg9an = sext(eaw); }
+:movea.l eal,reg9an is (op=2 & reg9an & mode2=1)... & eal { reg9an = eal; }
+
+:movec ctlreg,rreg is d16=0x4e7a; rreg & ctlreg { rreg = ctlreg; }
+:movec rreg,ctlreg is d16=0x4e7b; rreg & ctlreg { ctlreg = rreg; }
+
+@ifdef MC68040
+
+:move16 (regan)+,(regxan)+ is opbig=0xf6 & op37=4 & regan; regxan & da=1 { local src=regan&0xfffffff0; local dst=regxan&0xfffffff0; regan=regan+16; regxan=regxan+16;
+ *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4;
+ *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; }
+:move16 (regan)+,(d32)".l" is opbig=0xf6 & op37=0 & regan; d32 { local src=regan&0xfffffff0; dst:4=d32&0xfffffff0; regan=regan+16;
+ *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4;
+ *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; }
+:move16 (d32)".l",(regan)+ is opbig=0xf6 & op37=1 & regan; d32 { local dst=regan&0xfffffff0; src:4=d32&0xfffffff0; regan=regan+16;
+ *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4;
+ *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; }
+:move16 (regan),(d32)".l" is opbig=0xf6 & op37=2 & regan; d32 { local src=regan&0xfffffff0; dst:4=d32&0xfffffff0;
+ *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4;
+ *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; }
+:move16 (d32)".l",(regan) is opbig=0xf6 & op37=3 & regan; d32 { local dst=regan&0xfffffff0; src:4=d32&0xfffffff0;
+ *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4;
+ *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; }
+@endif # MC68040
+
+@ifdef COLDFIRE
+
+:mvs.b: eab, reg9dn is (op=0x7 & op68=4 & reg9dn )... &eab { reg9dn = sext(eab); }
+:mvs.w: eaw, reg9dn is (op=0x7 & op68=5 & reg9dn )... &eaw { reg9dn = sext(eaw); }
+:mvz.b: eab, reg9dn is (op=0x7 & op68=6 & reg9dn )... &eab { reg9dn = zext(eab); }
+:mvz.w: eaw, reg9dn is (op=0x7 & op68=7 & reg9dn )... &eaw { reg9dn = zext(eaw); }
+:mov3q "#"^d911, eal is (op=0xa & op68=5 & d911 ) ... &eal { eal = d911; }
+
+:sats.l regdn is opbig=0x4c & op37=0x10 & regdn { if (VF == 0) goto inst_next; regdn = (zext(regdn == 0 ) * 0x80000000) + (zext(regdn != 0) * 0x7fffffff); VF=0; CF=0; }
+
+skip_addr: skipAddr is op02=2 [skipAddr = inst_next + 2;] { export *[ram]:4 skipAddr; }
+skip_addr: skipAddr is op02=3 [skipAddr = inst_next + 4;] { export *[ram]:4 skipAddr; }
+
+# TPF.w/l is occassionally used as a branch over a valid instruction.
+:tpf is opbig=0x51 & op37=0x1f & op02=4 { } # nop
+:tpf.w is opbig=0x51 & op37=0x1f & op02=2 & skip_addr { goto skip_addr; } # nop + 1 word
+:tpf.l is opbig=0x51 & op37=0x1f & op02=3 & skip_addr { goto skip_addr; } # nop + 2 word
+@endif # COLDFIRE
+
+# Tables for register lists, for the movem instruction
+ # Register to mememory, forward direction, via word
+r2mfwf: D0w is D0w & mvm0=1 { *movemptr = D0w; movemptr = movemptr + 2; }
+r2mfwf: is mvm0=0 { }
+r2mfwe: r2mfwf" "D1w is D1w & mvm1=1 & r2mfwf { *movemptr = D1w; movemptr = movemptr + 2; }
+r2mfwe: r2mfwf is mvm1=0 & r2mfwf { }
+r2mfwd: r2mfwe" "D2w is D2w & mvm2=1 & r2mfwe { *movemptr = D2w; movemptr = movemptr + 2; }
+r2mfwd: r2mfwe is mvm2=0 & r2mfwe { }
+r2mfwc: r2mfwd" "D3w is D3w & mvm3=1 & r2mfwd { *movemptr = D3w; movemptr = movemptr + 2; }
+r2mfwc: r2mfwd is mvm3=0 & r2mfwd { }
+r2mfwb: r2mfwc" "D4w is D4w & mvm4=1 & r2mfwc { *movemptr = D4w; movemptr = movemptr + 2; }
+r2mfwb: r2mfwc is mvm4=0 & r2mfwc { }
+r2mfwa: r2mfwb" "D5w is D5w & mvm5=1 & r2mfwb { *movemptr = D5w; movemptr = movemptr + 2; }
+r2mfwa: r2mfwb is mvm5=0 & r2mfwb { }
+r2mfw9: r2mfwa" "D6w is D6w & mvm6=1 & r2mfwa { *movemptr = D6w; movemptr = movemptr + 2; }
+r2mfw9: r2mfwa is mvm6=0 & r2mfwa { }
+r2mfw8: r2mfw9" "D7w is D7w & mvm7=1 & r2mfw9 { *movemptr = D7w; movemptr = movemptr + 2; }
+r2mfw8: r2mfw9 is mvm7=0 & r2mfw9 { }
+r2mfw7: r2mfw8" "A0w is A0w & mvm8=1 & r2mfw8 { *movemptr = A0w; movemptr = movemptr + 2; }
+r2mfw7: r2mfw8 is mvm8=0 & r2mfw8 { }
+r2mfw6: r2mfw7" "A1w is A1w & mvm9=1 & r2mfw7 { *movemptr = A1w; movemptr = movemptr + 2; }
+r2mfw6: r2mfw7 is mvm9=0 & r2mfw7 { }
+r2mfw5: r2mfw6" "A2w is A2w & mvm10=1 & r2mfw6 { *movemptr = A2w; movemptr = movemptr + 2; }
+r2mfw5: r2mfw6 is mvm10=0 & r2mfw6 { }
+r2mfw4: r2mfw5" "A3w is A3w & mvm11=1 & r2mfw5 { *movemptr = A3w; movemptr = movemptr + 2; }
+r2mfw4: r2mfw5 is mvm11=0 & r2mfw5 { }
+r2mfw3: r2mfw4" "A4w is A4w & mvm12=1 & r2mfw4 { *movemptr = A4w; movemptr = movemptr + 2; }
+r2mfw3: r2mfw4 is mvm12=0 & r2mfw4 { }
+r2mfw2: r2mfw3" "A5w is A5w & mvm13=1 & r2mfw3 { *movemptr = A5w; movemptr = movemptr + 2; }
+r2mfw2: r2mfw3 is mvm13=0 & r2mfw3 { }
+r2mfw1: r2mfw2" "A6w is A6w & mvm14=1 & r2mfw2 { *movemptr = A6w; movemptr = movemptr + 2; }
+r2mfw1: r2mfw2 is mvm14=0 & r2mfw2 { }
+r2mfw0: { r2mfw1" "A7w} is A7w & mvm15=1 & r2mfw1 { *movemptr = A7w; movemptr = movemptr + 2; }
+r2mfw0: { r2mfw1} is mvm15=0 & r2mfw1 { }
+
+
+ # Register to memory, forward direction, via long
+r2mflf: D0 is D0 & mvm0=1 { *movemptr = D0; movemptr = movemptr + 4; }
+r2mflf: is mvm0=0 { }
+r2mfle: r2mflf" "D1 is D1 & mvm1=1 & r2mflf { *movemptr = D1; movemptr = movemptr + 4; }
+r2mfle: r2mflf is mvm1=0 & r2mflf { }
+r2mfld: r2mfle" "D2 is D2 & mvm2=1 & r2mfle { *movemptr = D2; movemptr = movemptr + 4; }
+r2mfld: r2mfle is mvm2=0 & r2mfle { }
+r2mflc: r2mfld" "D3 is D3 & mvm3=1 & r2mfld { *movemptr = D3; movemptr = movemptr + 4; }
+r2mflc: r2mfld is mvm3=0 & r2mfld { }
+r2mflb: r2mflc" "D4 is D4 & mvm4=1 & r2mflc { *movemptr = D4; movemptr = movemptr + 4; }
+r2mflb: r2mflc is mvm4=0 & r2mflc { }
+r2mfla: r2mflb" "D5 is D5 & mvm5=1 & r2mflb { *movemptr = D5; movemptr = movemptr + 4; }
+r2mfla: r2mflb is mvm5=0 & r2mflb { }
+r2mfl9: r2mfla" "D6 is D6 & mvm6=1 & r2mfla { *movemptr = D6; movemptr = movemptr + 4; }
+r2mfl9: r2mfla is mvm6=0 & r2mfla { }
+r2mfl8: r2mfl9" "D7 is D7 & mvm7=1 & r2mfl9 { *movemptr = D7; movemptr = movemptr + 4; }
+r2mfl8: r2mfl9 is mvm7=0 & r2mfl9 { }
+r2mfl7: r2mfl8" "A0 is A0 & mvm8=1 & r2mfl8 { *movemptr = A0; movemptr = movemptr + 4; }
+r2mfl7: r2mfl8 is mvm8=0 & r2mfl8 { }
+r2mfl6: r2mfl7" "A1 is A1 & mvm9=1 & r2mfl7 { *movemptr = A1; movemptr = movemptr + 4; }
+r2mfl6: r2mfl7 is mvm9=0 & r2mfl7 { }
+r2mfl5: r2mfl6" "A2 is A2 & mvm10=1 & r2mfl6 { *movemptr = A2; movemptr = movemptr + 4; }
+r2mfl5: r2mfl6 is mvm10=0 & r2mfl6 { }
+r2mfl4: r2mfl5" "A3 is A3 & mvm11=1 & r2mfl5 { *movemptr = A3; movemptr = movemptr + 4; }
+r2mfl4: r2mfl5 is mvm11=0 & r2mfl5 { }
+r2mfl3: r2mfl4" "A4 is A4 & mvm12=1 & r2mfl4 { *movemptr = A4; movemptr = movemptr + 4; }
+r2mfl3: r2mfl4 is mvm12=0 & r2mfl4 { }
+r2mfl2: r2mfl3" "A5 is A5 & mvm13=1 & r2mfl3 { *movemptr = A5; movemptr = movemptr + 4; }
+r2mfl2: r2mfl3 is mvm13=0 & r2mfl3 { }
+r2mfl1: r2mfl2" "A6 is A6 & mvm14=1 & r2mfl2 { *movemptr = A6; movemptr = movemptr + 4; }
+r2mfl1: r2mfl2 is mvm14=0 & r2mfl2 { }
+r2mfl0: { r2mfl1" "SP} is SP & mvm15=1 & r2mfl1 { *movemptr = SP; movemptr = movemptr + 4; }
+r2mfl0: { r2mfl1} is mvm15=0 & r2mfl1 { }
+
+
+ # Register to memory, backward direction, via word
+r2mbwf: A7w is A7w & mvm0=1 { movemptr = movemptr - 4; *movemptr = A7w; }
+r2mbwf: is mvm0=0 { }
+r2mbwe: r2mbwf" "A6w is A6w & mvm1=1 & r2mbwf { movemptr = movemptr - 4; *movemptr = A6w; }
+r2mbwe: r2mbwf is mvm1=0 & r2mbwf { }
+r2mbwd: r2mbwe" "A5w is A5w & mvm2=1 & r2mbwe { movemptr = movemptr - 4; *movemptr = A5w; }
+r2mbwd: r2mbwe is mvm2=0 & r2mbwe { }
+r2mbwc: r2mbwd" "A4w is A4w & mvm3=1 & r2mbwd { movemptr = movemptr - 4; *movemptr = A4w; }
+r2mbwc: r2mbwd is mvm3=0 & r2mbwd { }
+r2mbwb: r2mbwc" "A3w is A3w & mvm4=1 & r2mbwc { movemptr = movemptr - 4; *movemptr = A3w; }
+r2mbwb: r2mbwc is mvm4=0 & r2mbwc { }
+r2mbwa: r2mbwb" "A2w is A2w & mvm5=1 & r2mbwb { movemptr = movemptr - 4; *movemptr = A2w; }
+r2mbwa: r2mbwb is mvm5=0 & r2mbwb { }
+r2mbw9: r2mbwa" "A1w is A1w & mvm6=1 & r2mbwa { movemptr = movemptr - 4; *movemptr = A1w; }
+r2mbw9: r2mbwa is mvm6=0 & r2mbwa { }
+r2mbw8: r2mbw9" "A0w is A0w & mvm7=1 & r2mbw9 { movemptr = movemptr - 4; *movemptr = A0w; }
+r2mbw8: r2mbw9 is mvm7=0 & r2mbw9 { }
+r2mbw7: r2mbw8" "D7w is D7w & mvm8=1 & r2mbw8 { movemptr = movemptr - 4; *movemptr = D7w; }
+r2mbw7: r2mbw8 is mvm8=0 & r2mbw8 { }
+r2mbw6: r2mbw7" "D6w is D6w & mvm9=1 & r2mbw7 { movemptr = movemptr - 4; *movemptr = D6w; }
+r2mbw6: r2mbw7 is mvm9=0 & r2mbw7 { }
+r2mbw5: r2mbw6" "D5w is D5w & mvm10=1 & r2mbw6 { movemptr = movemptr - 4; *movemptr = D5w; }
+r2mbw5: r2mbw6 is mvm10=0 & r2mbw6 { }
+r2mbw4: r2mbw5" "D4w is D4w & mvm11=1 & r2mbw5 { movemptr = movemptr - 4; *movemptr = D4w; }
+r2mbw4: r2mbw5 is mvm11=0 & r2mbw5 { }
+r2mbw3: r2mbw4" "D3w is D3w & mvm12=1 & r2mbw4 { movemptr = movemptr - 4; *movemptr = D3w; }
+r2mbw3: r2mbw4 is mvm12=0 & r2mbw4 { }
+r2mbw2: r2mbw3" "D2w is D2w & mvm13=1 & r2mbw3 { movemptr = movemptr - 4; *movemptr = D2w; }
+r2mbw2: r2mbw3 is mvm13=0 & r2mbw3 { }
+r2mbw1: r2mbw2" "D1w is D1w & mvm14=1 & r2mbw2 { movemptr = movemptr - 4; *movemptr = D1w; }
+r2mbw1: r2mbw2 is mvm14=0 & r2mbw2 { }
+r2mbw0: { r2mbw1" "D0w} is D0w & mvm15=1 & r2mbw1 { movemptr = movemptr - 4; *movemptr = D0w; }
+r2mbw0: { r2mbw1} is mvm15=0 & r2mbw1 { }
+
+
+ # Register to memory, backward direction, via long
+r2mblf: SP is SP & mvm0=1 { movemptr = movemptr - 4; *movemptr = SP; }
+r2mblf: is mvm0=0 { }
+r2mble: r2mblf" "A6 is A6 & mvm1=1 & r2mblf { movemptr = movemptr - 4; *movemptr = A6; }
+r2mble: r2mblf is mvm1=0 & r2mblf { }
+r2mbld: r2mble" "A5 is A5 & mvm2=1 & r2mble { movemptr = movemptr - 4; *movemptr = A5; }
+r2mbld: r2mble is mvm2=0 & r2mble { }
+r2mblc: r2mbld" "A4 is A4 & mvm3=1 & r2mbld { movemptr = movemptr - 4; *movemptr = A4; }
+r2mblc: r2mbld is mvm3=0 & r2mbld { }
+r2mblb: r2mblc" "A3 is A3 & mvm4=1 & r2mblc { movemptr = movemptr - 4; *movemptr = A3; }
+r2mblb: r2mblc is mvm4=0 & r2mblc { }
+r2mbla: r2mblb" "A2 is A2 & mvm5=1 & r2mblb { movemptr = movemptr - 4; *movemptr = A2; }
+r2mbla: r2mblb is mvm5=0 & r2mblb { }
+r2mbl9: r2mbla" "A1 is A1 & mvm6=1 & r2mbla { movemptr = movemptr - 4; *movemptr = A1; }
+r2mbl9: r2mbla is mvm6=0 & r2mbla { }
+r2mbl8: r2mbl9" "A0 is A0 & mvm7=1 & r2mbl9 { movemptr = movemptr - 4; *movemptr = A0; }
+r2mbl8: r2mbl9 is mvm7=0 & r2mbl9 { }
+r2mbl7: r2mbl8" "D7 is D7 & mvm8=1 & r2mbl8 { movemptr = movemptr - 4; *movemptr = D7; }
+r2mbl7: r2mbl8 is mvm8=0 & r2mbl8 { }
+r2mbl6: r2mbl7" "D6 is D6 & mvm9=1 & r2mbl7 { movemptr = movemptr - 4; *movemptr = D6; }
+r2mbl6: r2mbl7 is mvm9=0 & r2mbl7 { }
+r2mbl5: r2mbl6" "D5 is D5 & mvm10=1 & r2mbl6 { movemptr = movemptr - 4; *movemptr = D5; }
+r2mbl5: r2mbl6 is mvm10=0 & r2mbl6 { }
+r2mbl4: r2mbl5" "D4 is D4 & mvm11=1 & r2mbl5 { movemptr = movemptr - 4; *movemptr = D4; }
+r2mbl4: r2mbl5 is mvm11=0 & r2mbl5 { }
+r2mbl3: r2mbl4" "D3 is D3 & mvm12=1 & r2mbl4 { movemptr = movemptr - 4; *movemptr = D3; }
+r2mbl3: r2mbl4 is mvm12=0 & r2mbl4 { }
+r2mbl2: r2mbl3" "D2 is D2 & mvm13=1 & r2mbl3 { movemptr = movemptr - 4; *movemptr = D2; }
+r2mbl2: r2mbl3 is mvm13=0 & r2mbl3 { }
+r2mbl1: r2mbl2" "D1 is D1 & mvm14=1 & r2mbl2 { movemptr = movemptr - 4; *movemptr = D1; }
+r2mbl1: r2mbl2 is mvm14=0 & r2mbl2 { }
+r2mbl0: { r2mbl1" "D0} is D0 & mvm15=1 & r2mbl1 { movemptr = movemptr - 4; *movemptr = D0; }
+r2mbl0: { r2mbl1} is mvm15=0 & r2mbl1 { }
+
+
+ # Memory to register, forward direction, via word
+m2rfwf: D0 is D0 & mvm0=1 { D0 = sext(*:2 movemptr); movemptr = movemptr + 2; }
+m2rfwf: is mvm0=0 { }
+m2rfwe: m2rfwf" "D1 is D1 & mvm1=1 & m2rfwf { D1 = sext(*:2 movemptr); movemptr = movemptr + 2; }
+m2rfwe: m2rfwf is mvm1=0 & m2rfwf { }
+m2rfwd: m2rfwe" "D2 is D2 & mvm2=1 & m2rfwe { D2 = sext(*:2 movemptr); movemptr = movemptr + 2; }
+m2rfwd: m2rfwe is mvm2=0 & m2rfwe { }
+m2rfwc: m2rfwd" "D3 is D3 & mvm3=1 & m2rfwd { D3 = sext(*:2 movemptr); movemptr = movemptr + 2; }
+m2rfwc: m2rfwd is mvm3=0 & m2rfwd { }
+m2rfwb: m2rfwc" "D4 is D4 & mvm4=1 & m2rfwc { D4 = sext(*:2 movemptr); movemptr = movemptr + 2; }
+m2rfwb: m2rfwc is mvm4=0 & m2rfwc { }
+m2rfwa: m2rfwb" "D5 is D5 & mvm5=1 & m2rfwb { D5 = sext(*:2 movemptr); movemptr = movemptr + 2; }
+m2rfwa: m2rfwb is mvm5=0 & m2rfwb { }
+m2rfw9: m2rfwa" "D6 is D6 & mvm6=1 & m2rfwa { D6 = sext(*:2 movemptr); movemptr = movemptr + 2; }
+m2rfw9: m2rfwa is mvm6=0 & m2rfwa { }
+m2rfw8: m2rfw9" "D7 is D7 & mvm7=1 & m2rfw9 { D7 = sext(*:2 movemptr); movemptr = movemptr + 2; }
+m2rfw8: m2rfw9 is mvm7=0 & m2rfw9 { }
+m2rfw7: m2rfw8" "A0 is A0 & mvm8=1 & m2rfw8 { A0 = sext(*:2 movemptr); movemptr = movemptr + 2; }
+m2rfw7: m2rfw8 is mvm8=0 & m2rfw8 { }
+m2rfw6: m2rfw7" "A1 is A1 & mvm9=1 & m2rfw7 { A1 = sext(*:2 movemptr); movemptr = movemptr + 2; }
+m2rfw6: m2rfw7 is mvm9=0 & m2rfw7 { }
+m2rfw5: m2rfw6" "A2 is A2 & mvm10=1 & m2rfw6 { A2 = sext(*:2 movemptr); movemptr = movemptr + 2; }
+m2rfw5: m2rfw6 is mvm10=0 & m2rfw6 { }
+m2rfw4: m2rfw5" "A3 is A3 & mvm11=1 & m2rfw5 { A3 = sext(*:2 movemptr); movemptr = movemptr + 2; }
+m2rfw4: m2rfw5 is mvm11=0 & m2rfw5 { }
+m2rfw3: m2rfw4" "A4 is A4 & mvm12=1 & m2rfw4 { A4 = sext(*:2 movemptr); movemptr = movemptr + 2; }
+m2rfw3: m2rfw4 is mvm12=0 & m2rfw4 { }
+m2rfw2: m2rfw3" "A5 is A5 & mvm13=1 & m2rfw3 { A5 = sext(*:2 movemptr); movemptr = movemptr + 2; }
+m2rfw2: m2rfw3 is mvm13=0 & m2rfw3 { }
+m2rfw1: m2rfw2" "A6 is A6 & mvm14=1 & m2rfw2 { A6 = sext(*:2 movemptr); movemptr = movemptr + 2; }
+m2rfw1: m2rfw2 is mvm14=0 & m2rfw2 { }
+m2rfw0: { m2rfw1" "SP} is SP & mvm15=1 & m2rfw1 { SP = sext(*:2 movemptr); movemptr = movemptr + 2; }
+m2rfw0: { m2rfw1} is mvm15=0 & m2rfw1 { }
+
+
+
+ # Memory to register, forward direction, via long
+m2rflf: D0 is D0 & mvm0=1 { D0 = *movemptr; movemptr = movemptr + 4; }
+m2rflf: is mvm0=0 { }
+m2rfle: m2rflf" "D1 is D1 & mvm1=1 & m2rflf { D1 = *movemptr; movemptr = movemptr + 4; }
+m2rfle: m2rflf is mvm1=0 & m2rflf { }
+m2rfld: m2rfle" "D2 is D2 & mvm2=1 & m2rfle { D2 = *movemptr; movemptr = movemptr + 4; }
+m2rfld: m2rfle is mvm2=0 & m2rfle { }
+m2rflc: m2rfld" "D3 is D3 & mvm3=1 & m2rfld { D3 = *movemptr; movemptr = movemptr + 4; }
+m2rflc: m2rfld is mvm3=0 & m2rfld { }
+m2rflb: m2rflc" "D4 is D4 & mvm4=1 & m2rflc { D4 = *movemptr; movemptr = movemptr + 4; }
+m2rflb: m2rflc is mvm4=0 & m2rflc { }
+m2rfla: m2rflb" "D5 is D5 & mvm5=1 & m2rflb { D5 = *movemptr; movemptr = movemptr + 4; }
+m2rfla: m2rflb is mvm5=0 & m2rflb { }
+m2rfl9: m2rfla" "D6 is D6 & mvm6=1 & m2rfla { D6 = *movemptr; movemptr = movemptr + 4; }
+m2rfl9: m2rfla is mvm6=0 & m2rfla { }
+m2rfl8: m2rfl9" "D7 is D7 & mvm7=1 & m2rfl9 { D7 = *movemptr; movemptr = movemptr + 4; }
+m2rfl8: m2rfl9 is mvm7=0 & m2rfl9 { }
+m2rfl7: m2rfl8" "A0 is A0 & mvm8=1 & m2rfl8 { A0 = *movemptr; movemptr = movemptr + 4; }
+m2rfl7: m2rfl8 is mvm8=0 & m2rfl8 { }
+m2rfl6: m2rfl7" "A1 is A1 & mvm9=1 & m2rfl7 { A1 = *movemptr; movemptr = movemptr + 4; }
+m2rfl6: m2rfl7 is mvm9=0 & m2rfl7 { }
+m2rfl5: m2rfl6" "A2 is A2 & mvm10=1 & m2rfl6 { A2 = *movemptr; movemptr = movemptr + 4; }
+m2rfl5: m2rfl6 is mvm10=0 & m2rfl6 { }
+m2rfl4: m2rfl5" "A3 is A3 & mvm11=1 & m2rfl5 { A3 = *movemptr; movemptr = movemptr + 4; }
+m2rfl4: m2rfl5 is mvm11=0 & m2rfl5 { }
+m2rfl3: m2rfl4" "A4 is A4 & mvm12=1 & m2rfl4 { A4 = *movemptr; movemptr = movemptr + 4; }
+m2rfl3: m2rfl4 is mvm12=0 & m2rfl4 { }
+m2rfl2: m2rfl3" "A5 is A5 & mvm13=1 & m2rfl3 { A5 = *movemptr; movemptr = movemptr + 4; }
+m2rfl2: m2rfl3 is mvm13=0 & m2rfl3 { }
+m2rfl1: m2rfl2" "A6 is A6 & mvm14=1 & m2rfl2 { A6 = *movemptr; movemptr = movemptr + 4; }
+m2rfl1: m2rfl2 is mvm14=0 & m2rfl2 { }
+m2rfl0: { m2rfl1" "SP} is SP & mvm15=1 & m2rfl1 { SP = *movemptr; movemptr = movemptr + 4; }
+m2rfl0: { m2rfl1} is mvm15=0 & m2rfl1 { }
+
+
+
+:movem.w r2mfw0,(regan) is opbig=0x48 & op67=2 & mode=2 & regan; r2mfw0 { movemptr = regan; build r2mfw0; }
+:movem.w r2mbw0,-(regan) is opbig=0x48 & op67=2 & mode=4 & regan; r2mbw0 { movemptr = regan; build r2mbw0; regan = movemptr; }
+:movem.w r2mfw0,(d16,regan) is opbig=0x48 & op67=2 & mode=5 & regan; r2mfw0; d16 { movemptr = regan+d16; build r2mfw0; }
+:movem.w r2mfw0,(extw) is opbig=0x48 & op67=2 & mode=6 & regan; r2mfw0; extw [ pcmode=0; regtfan=regan; ] { build extw; movemptr = extw; build r2mfw0; }
+:movem.w r2mfw0,(d16)".w" is opbig=0x48 & op67=2 & mode=7 & regan=0; r2mfw0; d16 { movemptr = d16; build r2mfw0; }
+:movem.w r2mfw0,(d32)".l" is opbig=0x48 & op67=2 & mode=7 & regan=1; r2mfw0; d32 { movemptr = d32; build r2mfw0; }
+:movem.l r2mfl0,(regan) is opbig=0x48 & op67=3 & mode=2 & regan; r2mfl0 { movemptr = regan; build r2mfl0; }
+:movem.l r2mbl0,-(regan) is opbig=0x48 & op67=3 & mode=4 & regan; r2mbl0 { movemptr = regan; build r2mbl0; regan = movemptr; }
+:movem.l r2mfl0,(d16,regan) is opbig=0x48 & op67=3 & mode=5 & regan; r2mfl0; d16 { movemptr = regan+d16; build r2mfl0; }
+:movem.l r2mfl0,(extw) is opbig=0x48 & op67=3 & mode=6 & regan; r2mfl0; extw [ pcmode=0; regtfan=regan; ] { build extw; movemptr = extw; build r2mfl0; }
+:movem.l r2mfl0,(d16)".w" is opbig=0x48 & op67=3 & mode=7 & regan=0; r2mfl0; d16 { movemptr = d16; build r2mfl0; }
+:movem.l r2mfl0,(d32)".l" is opbig=0x48 & op67=3 & mode=7 & regan=1; r2mfl0; d32 { movemptr = d32; build r2mfl0; }
+
+:movem.w (regan),m2rfw0 is opbig=0x4c & op67=2 & mode=2 & regan; m2rfw0 { movemptr = regan; build m2rfw0; }
+:movem.w (regan)+,m2rfw0 is opbig=0x4c & op67=2 & mode=3 & regan; m2rfw0 { movemptr = regan; build m2rfw0; regan = movemptr; }
+:movem.w (d16,regan),m2rfw0 is opbig=0x4c & op67=2 & mode=5 & regan; m2rfw0; d16 { movemptr = regan+d16; build m2rfw0; }
+:movem.w (extw),m2rfw0 is opbig=0x4c & op67=2 & mode=6 & regan; m2rfw0; extw [ pcmode=0; regtfan=regan; ] { build extw; movemptr = extw; build m2rfw0; }
+:movem.w (d16,PC),m2rfw0 is opbig=0x4c & op67=2 & mode=7 & regan=2; m2rfw0; d16 & PC { movemptr = inst_start+2+d16; build m2rfw0; }
+:movem.w (extw),m2rfw0 is opbig=0x4c & op67=2 & mode=7 & regan=3; m2rfw0; extw [ pcmode=1; ] { build extw; movemptr = extw; build m2rfw0; }
+:movem.w (d16)".w",m2rfw0 is opbig=0x4c & op67=2 & mode=7 & regan=0; m2rfw0; d16 { movemptr = d16; build m2rfw0; }
+:movem.w (d32)".l",m2rfw0 is opbig=0x4c & op67=2 & mode=7 & regan=1; m2rfw0; d32 { movemptr = d32; build m2rfw0; }
+:movem.l (regan),m2rfl0 is opbig=0x4c & op67=3 & mode=2 & regan; m2rfl0 { movemptr = regan; build m2rfl0; }
+:movem.l (regan)+,m2rfl0 is opbig=0x4c & op67=3 & mode=3 & regan; m2rfl0 { movemptr = regan; build m2rfl0; regan = movemptr; }
+:movem.l (d16,regan),m2rfl0 is opbig=0x4c & op67=3 & mode=5 & regan; m2rfl0; d16 { movemptr = regan+d16; build m2rfl0; }
+:movem.l (extw),m2rfl0 is opbig=0x4c & op67=3 & mode=6 & regan; m2rfl0; extw [ pcmode=0; regtfan=regan; ] { build extw; movemptr = extw; build m2rfl0; }
+:movem.l (d16,PC),m2rfl0 is opbig=0x4c & op67=3 & mode=7 & regan=2; m2rfl0; d16 & PC { movemptr = inst_start+2+d16; build m2rfl0; }
+:movem.l (extw),m2rfl0 is opbig=0x4c & op67=3 & mode=7 & regan=3; m2rfl0; extw [ pcmode=1; ] { build extw; movemptr = extw; build m2rfl0; }
+:movem.l (d16)".w",m2rfl0 is opbig=0x4c & op67=3 & mode=7 & regan=0; m2rfl0; d16 { movemptr = d16; build m2rfl0; }
+:movem.l (d32)".l",m2rfl0 is opbig=0x4c & op67=3 & mode=7 & regan=1; m2rfl0; d32 { movemptr = d32; build m2rfl0; }
+
+:movep.w (d16,regan),reg9dnw is op=0 & reg9dnw & op68=4 & op35=1 & regan; d16 { src:4 = (regan + d16); ho:1 = *:1 src; lo:1 = *:1(src+2); reg9dnw = (zext(ho) << 8) | zext(lo); }
+:movep.l (d16,regan),reg9dn is op=0 & reg9dn & op68=5 & op35=1 & regan; d16 { src:4 = (regan + d16); ho:1 = *:1 src; mu:1 = *:1(src+2); ml:1 = *(src+4); lo:1 = *:1(src+6); reg9dn = (zext(ho) << 24) | (zext(mu) << 16) | (zext(ml) << 8) | zext(lo); }
+:movep.w reg9dnw,(d16,regan) is op=0 & reg9dnw & op68=6 & op35=1 & regan; d16 { src:4 = (regan + d16); local tmp = (reg9dnw >> 8); *:1 src = tmp:1; src = src+2; *:1 src = reg9dnw:1; }
+:movep.l reg9dn,(d16,regan) is op=0 & reg9dn & op68=7 & op35=1 & regan; d16 { src:4 = (regan + d16); local tmp = (reg9dn >> 24); *:1 src = tmp:1; src = src+2; tmp = (reg9dn >> 16); *:1 src = tmp:1; src = src+2; tmp = (reg9dn >> 8); *:1 src = tmp:1; src = src+2; *:1 src = reg9dn:1; }
+
+
+:moveq "#"^d8base,reg9dn is op=7 & reg9dn & op8=0 & d8base { reg9dn = d8base; resflags(reg9dn); logflags(); }
+
+:moves.b rreg,e2b is opbig=0x0e & op67=0 & mode & regan; rreg & wl=1; e2b [ regtsan=regan; savmod2=mode; ] { e2b = rreg:1; }
+:moves.w rreg,e2w is opbig=0x0e & op67=1 & mode & regan; rreg & wl=1; e2w [ regtsan=regan; savmod2=mode; ] { e2w = rreg:2; }
+:moves.l rreg,e2l is opbig=0x0e & op67=2 & mode & regan; rreg & wl=1; e2l [ regtsan=regan; savmod2=mode; ] { e2l = rreg; }
+:moves.b e2b,rreg is opbig=0x0e & op67=0 & mode & regan; da=0 & rreg & wl=0; e2b [ regtsan=regan; savmod2=mode; ] { rreg = (rreg & 0xffffff00) | zext(e2b); }
+:moves.w e2w,rreg is opbig=0x0e & op67=1 & mode & regan; da=0 & rreg & wl=0; e2w [ regtsan=regan; savmod2=mode; ] { rreg = (rreg & 0xffff0000) | zext(e2w); }
+:moves.b e2b,rreg is opbig=0x0e & op67=0 & mode & regan; da=1 & rreg & wl=0; e2b [ regtsan=regan; savmod2=mode; ] { rreg = sext(e2b); }
+:moves.w e2w,rreg is opbig=0x0e & op67=1 & mode & regan; da=1 & rreg & wl=0; e2w [ regtsan=regan; savmod2=mode; ] { rreg = sext(e2w); }
+:moves.l e2l,rreg is opbig=0x0e & op67=2 & mode & regan; rreg & wl=0; e2l [ regtsan=regan; savmod2=mode; ] { rreg = e2l; }
+
+:muls.w eaw,reg9dn is (op=12 & reg9dn & op68=7)... & eaw { tmp1:4 = sext( reg9dn:2 ); tmp2:4 = sext(eaw);
+ reg9dn = tmp1 * tmp2; resflags(reg9dn); CF=0; VF=0; }
+
+:mulu.w eaw,reg9dn is (op=12 & reg9dn & op68=3)... & eaw { tmp1:4 = zext( reg9dn:2 ); tmp2:4 = zext(eaw);
+ reg9dn = tmp1 * tmp2; resflags(reg9dn); CF=0; VF=0; }
+
+mulsize: "s.l" is divsgn=1 { }
+mulsize: "u.l" is divsgn=0 { }
+
+submul: regdq is regdq & divsgn=1 & divsz=0 { regdq = glbdenom * regdq; resflags(regdq); CF=0; }
+submul: regdr-regdq is regdq & divsgn=1 & divsz=1 & regdr { tmp1:8 = sext(glbdenom); tmp2:8 = sext(regdq); local res=tmp1*tmp2; regdq=res:4;
+ regdr=res(4); resflags(res); CF=0; VF=0; }
+submul: regdq is regdq & divsgn=0 & divsz=0 { regdq = glbdenom * regdq; resflags(regdq); CF=0; }
+submul: regdr-regdq is regdq & divsgn=0 & divsz=1 & regdr { tmp1:8 = zext(glbdenom); tmp2:8 = zext(regdq); local res=tmp1*tmp2; regdq=res:4;
+ regdr=res(4); resflags(res); CF=0; VF=0; }
+:mul^mulsize e2l,submul is opbig=0x4c & op67=0 & $(DAT_ALTER_ADDR_MODES); submul & mulsize; e2l [ savmod2=savmod1; regtsan=regtfan; ] { glbdenom=e2l; build submul; }
+
+:nbcd eab is (opbig=0x48 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab
+{ tmp:1 = eab; CF = (tmp != 0) || (XF == 1); tmp = 0 - tmp - XF; eab = bcdAdjust(tmp); bcdflags(tmp); }
+
+
+# NB: For the neg insn the CF carry flag is not set like other insns, from the manual:
+# XF - Set the same as the carry bit.
+# NF - Set if the result is negative; cleared otherwise.
+# ZF - Set if the result is zero; cleared otherwise.
+# VF - Set if an overflow occurs; cleared otherwise.
+# CF - Cleared if the result is zero; set otherwise.
+
+macro negFlags(op1) {
+ VF = sborrow(0, op1);
+}
+
+macro negResFlags(result) {
+ NF = result s< 0;
+ CF = result != 0;
+ XF = CF;
+ ZF = result == 0;
+}
+
+:neg.b eab is (opbig=0x44 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab
+ { o2:1=eab; negFlags(o2); o2 = -o2; eab=o2; negResFlags(o2); }
+:neg.w eaw is (opbig=0x44 & op67=1 & $(DAT_ALTER_ADDR_MODES))... & eaw
+ { o2:2=eaw; negFlags(o2); o2 = -o2; eaw=o2; negResFlags(o2); }
+:neg.l eal is (opbig=0x44 & op67=2 & $(DAT_ALTER_ADDR_MODES))... & eal
+ { o2:4=eal; negFlags(o2); o2 = -o2; eal=o2; negResFlags(o2); }
+
+# NB: For the negx insn the CF and ZF flags are not set like other insns, from the manual:
+# XF - Set the same as the carry bit.
+# NF - Set if the result is negative; cleared otherwise.
+# ZF - Cleared if the result is nonzero; unchanged otherwise.
+# VF - Set if an overflow occurs; cleared otherwise.
+# CF - Set if borrow occurs; otherwise.
+
+:negx.b eab is (opbig=0x40 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab
+ { local tmp = eab + XF; negxsubflags(tmp); tmp = -tmp; eab=tmp; extendedResultFlags(tmp); }
+:negx.w eaw is (opbig=0x40 & op67=1 & $(DAT_ALTER_ADDR_MODES))... & eaw
+ { local tmp = eaw + zext(XF); negxsubflags(tmp); tmp = -tmp; eaw=tmp; extendedResultFlags(tmp); }
+:negx.l eal is (opbig=0x40 & op67=2 & $(DAT_ALTER_ADDR_MODES))... & eal
+ { local tmp = eal + zext(XF); negxsubflags(tmp); tmp = -tmp; eal=tmp; extendedResultFlags(tmp); }
+
+:nop is opbig=0x4e & op37=14 & op02=1 { }
+
+:not.b eab is (opbig=0x46 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab { logflags(); eab = ~eab; resflags(eab); }
+:not.w eaw is (opbig=0x46 & op67=1 & $(DAT_ALTER_ADDR_MODES))... & eaw { logflags(); eaw = ~eaw; resflags(eaw); }
+:not.l eal is (opbig=0x46 & op67=2 & $(DAT_ALTER_ADDR_MODES))... & eal { logflags(); eal = ~eal; resflags(eal); }
+
+:or.b eab,reg9dnb is (op=8 & reg9dnb & op68=0 & $(DAT_ALTER_ADDR_MODES))... & eab { logflags(); reg9dnb = reg9dnb | eab; resflags(reg9dnb); }
+:or.w eaw,reg9dnw is (op=8 & reg9dnw & op68=1 & $(DAT_ALTER_ADDR_MODES))... & eaw { logflags(); reg9dnw = reg9dnw | eaw; resflags(reg9dnw); }
+:or.l eal,reg9dn is (op=8 & reg9dn & op68=2 & $(DAT_ALTER_ADDR_MODES))... & eal { logflags(); reg9dn = reg9dn | eal; resflags(reg9dn); }
+
+:or.b reg9dnb,eab is (op=8 & reg9dnb & op68=4 & $(MEM_ALTER_ADDR_MODES))... & eab { logflags(); eab = eab | reg9dnb; resflags(eab); }
+:or.w reg9dnw,eaw is (op=8 & reg9dnw & op68=5 & $(MEM_ALTER_ADDR_MODES))... & eaw { logflags(); eaw = eaw | reg9dnw; resflags(eaw); }
+:or.l reg9dn,eal is (op=8 & reg9dn & op68=6 & $(MEM_ALTER_ADDR_MODES))... & eal { logflags(); eal = eal | reg9dn; resflags(eal); }
+
+:ori.b "#"^d8,e2b is opbig=0 & op67=0 & $(DAT_ALTER_ADDR_MODES); d8; e2b [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); e2b = e2b | d8; resflags(e2b); }
+:ori.w "#"^d16,e2w is opbig=0 & op67=1 & $(DAT_ALTER_ADDR_MODES); d16; e2w [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); e2w = e2w | d16; resflags(e2w); }
+:ori.l "#"^d32,e2l is opbig=0 & op67=2 & $(DAT_ALTER_ADDR_MODES); d32; e2l [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); e2l = e2l | d32; resflags(e2l); }
+:ori "#"^d8,"CCR" is opbig=0 & op37=7 & op02=4; d8 { packflags(SR); SR=SR|d8; unpackflags(SR); }
+:ori "#"^d16,SR is SR; opbig=0x00 & d8base=0x7c; d16 { packflags(SR); SR=SR|d16; unpackflags(SR); }
+
+:pack Tyw,Txw,"#"d16 is op=8 & op48=20 & Txw & Tyw & rmbit=0; d16 {
+ local value = (Tyw & 0x0F0F) + d16;
+ Txw = (Txw & 0xFF00) | ((value & 0x0F00) >> 4) | (value & 0x000F);
+}
+
+:pack Tyw,Txb,"#"d16 is op=8 & op48=20 & Tyw & Txb & rmbit=1; d16 {
+ local value = (Tyw & 0x0F0F) + d16;
+ local result:2 = ((value & 0x0F00) >> 4) | (value & 0x000F);
+ Txb = result:1;
+}
+
+:pea eaptr is (opbig=0x48 & op67=1 & $(CTL_ADDR_MODES))... & eaptr { SP = SP-4; *SP = eaptr; }
+
+@ifdef MC68040
+
+:pflushn "("^regan^")" is opbig=0xf5 & op67=0 & op5=0 & op34=0 & regan unimpl
+:pflush "("^regan^")" is opbig=0xf5 & op67=0 & op5=0 & op34=1 & regan unimpl
+:pflushan is opbig=0xf5 & op67=0 & op5=0 & op34=2 & regan=0 unimpl
+:pflusha is opbig=0xf5 & op67=0 & op5=0 & op34=3 & regan=0 unimpl
+
+@endif # MC68040
+
+@ifdef MC68030
+
+:pflusha is opbig=0xf0 & op67=0 & mode=0 & regan=0; opx015=0x2400 unimpl
+
+FC: SFC is fc4=0 & fc3=0 & fc02=0 & SFC { export SFC; }
+FC: DFC is fc4=0 & fc3=0 & fc02=1 & DFC { export DFC; }
+FC: regdc is fc4=0 & fc3=1 & regdc { export regdc; }
+FC: "#"^fc03 is fc4=1 & fc3=0 & fc03 { export *[const]:4 fc03; }
+
+FCmask: "#"^fcmask is fcmask { export *[const]:1 fcmask; }
+
+:pflush FC,FCmask is opbig=0xf0 & op67=0 & mode=0 & regan=0; bigopx=0x30 & FCmask & FC unimpl
+
+:pflush FC,FCmask,e2l is opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); bigopx=0x38 & FCmask & FC; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+
+:ploadr FC,e2l is opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx515=0x110 & FC; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+
+:ploadw FC,e2l is opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx515=0x100 & FC; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+
+:pmove.l TC,e2l is TC & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=0 & rwx=1 & fbit=0 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:pmove.l e2l,TC is TC & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=0 & rwx=0 & fbit=0 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:pmovefd.l e2l,TC is TC & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=0 & rwx=0 & fbit=1 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+
+:pmove.d SRP,e2d is SRP & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=2 & rwx=1 & fbit=0 & d8=0; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:pmove.d e2d,SRP is SRP & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=2 & rwx=0 & fbit=0 & d8=0; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:pmovefd.d e2d,SRP is SRP & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=2 & rwx=0 & fbit=1 & d8=0; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+
+:pmove.d CRP,e2d is CRP & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=3 & rwx=1 & fbit=0 & d8=0; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:pmove.d e2d,CRP is CRP & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=3 & rwx=0 & fbit=0 & d8=0; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:pmovefd.d e2d,CRP is CRP & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=3 & rwx=0 & fbit=1 & d8=0; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+
+:pmove.w MMUSR,e2w is MMUSR & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=3 & mregn=0 & rwx=1 & fbit=0 & d8=0; e2w [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:pmove.w e2w,MMUSR is MMUSR & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=3 & mregn=0 & rwx=0 & fbit=0 & d8=0; e2w [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+
+:pmove.l TT0,e2l is TT0 & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=2 & rwx=1 & fbit=0 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:pmove.l e2l,TT0 is TT0 & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=2 & rwx=0 & fbit=0 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:pmovefd.l e2l,TT0 is TT0 & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=2 & rwx=0 & fbit=1 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+
+:pmove.l TT1,e2l is TT1 & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=3 & rwx=1 & fbit=0 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:pmove.l e2l,TT1 is TT1 & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=3 & rwx=0 & fbit=0 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:pmovefd.l e2l,TT1 is TT1 & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=3 & rwx=0 & fbit=1 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+
+#TODO: MC68EC030 only - conflicts with MMUSR form above
+#:pmove.w ACUSR,e2w is ACUSR & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=3 & mregn=0 & rwx=1 & fbit=0 & d8=0; e2w [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+#:pmove.w e2w,ACUSR is ACUSR & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=3 & mregn=0 & rwx=0 & fbit=0 & d8=0; e2w [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+
+#TODO: MC68EC030 only - - conflicts with TTx form above
+#:pmove.l ACx,e2l is ACx & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=? & rwx=1 & fbit=0 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+#:pmove.l e2l,ACx is ACx & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=? & rwx=0 & fbit=0 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+#:pmovefd.l e2l,ACx is ACx & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=0 & mregn=? & rwx=0 & fbit=1 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+
+@endif # MC68030
+
+#TODO: PMOVE PMMU Register - MC68851 only
+
+#TODO: PRESTORE PMMU Register - MC68851 only
+
+#TODO: PSAVE PMMU Register - MC68851 only
+
+#TODO: PScc PMMU Register - MC68851 only
+
+@ifdef MC68030
+
+ptestLevel: "#"^mregn is mregn { export *[const]:1 mregn; }
+
+:ptestr FC,e2l,ptestLevel is opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=4 & ptestLevel & rwx=1 & fbit=0 & aregx=0 & FC; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:ptestr FC,e2l,ptestLevel,aregx is opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=4 & ptestLevel & rwx=1 & fbit=1 & aregx & FC; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+
+:ptestw FC,e2l,ptestLevel is opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=4 & ptestLevel & rwx=0 & fbit=0 & aregx=0 & FC; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:ptestw FC,e2l,ptestLevel,aregx is opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=4 & ptestLevel & rwx=0 & fbit=1 & aregx & FC; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+
+@endif # MC68030
+
+#TODO: PTEST FC, - MC68EX030 only
+
+#TODO: PTEST FC,,#level,(An) - MC68851 only
+
+@ifdef MC68040
+
+:ptestr "("^regan^")" is opbig=0xf5 & op67=1 & op35=5 & regan unimpl
+:ptestw "("^regan^")" is opbig=0xf5 & op67=1 & op35=1 & regan unimpl
+
+@endif # MC68040
+
+#TODO: PTRAPcc - MC68851 only
+
+#TODO: PVALID - MC68851 only
+
+:reset is d16=0x4e70 { reset(); }
+
+:rol.b cntreg,regdnb is op=14 & cntreg & op8=1 & op67=0 & op34=3 & regdnb { rotateLeft(cntreg, regdnb, 8); }
+:rol.w cntreg,regdnw is op=14 & cntreg & op8=1 & op67=1 & op34=3 & regdnw { rotateLeft(cntreg, regdnw, 16); }
+:rol.l cntreg,regdn is op=14 & cntreg & op8=1 & op67=2 & op34=3 & regdn { rotateLeft(cntreg, regdn, 32); }
+:rol eaw is (opbig=0xe7 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw {
+ local value:2 = eaw;
+ value = (value << 1) | (value >> 15);
+ getbit(CF, value, 0);
+ resflags(value);
+ eaw = value;
+ VF = 0;
+}
+
+:ror.b cntreg,regdnb is op=14 & cntreg & op8=0 & op67=0 & op34=3 & regdnb { rotateRight(cntreg, regdnb, 8); }
+:ror.w cntreg,regdnw is op=14 & cntreg & op8=0 & op67=1 & op34=3 & regdnw { rotateRight(cntreg, regdnw, 16); }
+:ror.l cntreg,regdn is op=14 & cntreg & op8=0 & op67=2 & op34=3 & regdn { rotateRight(cntreg, regdn, 32); }
+:ror eaw is (opbig=0xe6 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw {
+ local value:2 = eaw;
+ value = (value << 15) | (value >> 1);
+ getbit(CF, value, 15);
+ resflags(value);
+ eaw = value;
+ VF = 0;
+}
+
+:roxl.b cntreg,regdnb is op=14 & cntreg & op8=1 & op67=0 & op34=2 & regdnb { rotateLeftExtended(cntreg, regdnb, 8); }
+:roxl.w cntreg,regdnw is op=14 & cntreg & op8=1 & op67=1 & op34=2 & regdnw { rotateLeftExtended(cntreg, regdnw, 16); }
+:roxl.l cntreg,regdn is op=14 & cntreg & op8=1 & op67=2 & op34=2 & regdn { rotateLeftExtended(cntreg, regdn, 32); }
+:roxl eaw is (opbig=0xe5 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw {
+ local value:2 = eaw;
+ local xflag = (value & 0x8000) != 0;
+ value = (value << 1) | zext(XF);
+ resflags(value);
+ eaw = value;
+ VF = 0;
+ XF = xflag;
+ CF = XF;
+}
+
+:roxr.b cntreg,regdnb is op=14 & cntreg & op8=0 & op67=0 & op34=2 & regdnb { rotateRightExtended(cntreg, regdnb, 8); }
+:roxr.w cntreg,regdnw is op=14 & cntreg & op8=0 & op67=1 & op34=2 & regdnw { rotateRightExtended(cntreg, regdnw, 16); }
+:roxr.l cntreg,regdn is op=14 & cntreg & op8=0 & op67=2 & op34=2 & regdn { rotateRightExtended(cntreg, regdn, 32); }
+:roxr eaw is (opbig=0xe4 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw {
+ local value:2 = eaw;
+ local xflag = (value & 0x0001) != 0;
+ value = (zext(XF) << 15) | (value >> 1);
+ resflags(value);
+ eaw = value;
+ VF = 0;
+ XF = xflag;
+ CF = XF;
+}
+
+:rtd "#"^d16 is opbig=0x4e & op37=14 & op02=4; d16 { PC = *SP; SP = SP + 4 + d16; return [PC]; }
+:rte is d16=0x4e73 { tmp:4 = 0; return [tmp]; }
+
+:rtm regdn is opbig=0x06 & op37=24 & regdn unimpl
+:rtm regan is opbig=0x06 & op37=25 & regan unimpl
+
+:rtr is opbig=0x4e & op37=14 & op02=7 { SR = *SP; SP = SP+2; PC = *SP; SP = SP+4; unpackflags(SR); return [PC]; }
+
+:rts is opbig=0x4e & op37=14 & op02=5 { PC = *SP; SP = SP+4; return [PC]; }
+
+:sbcd Tyb,Txb is op=8 & op48=16 & Txb & Tyb {
+ CF = (Txb < Tyb) || ( (XF == 1) && (Txb == Tyb) );
+ Txb = Txb - Tyb - XF;
+ Txb = bcdAdjust(Txb);
+ bcdflags(Txb);
+}
+
+:s^cc eab is (op=5 & cc & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eab { eab = -cc; }
+
+:stop "#"^d16 is opbig=0x4e & d8base=0x72; d16 unimpl
+
+:sub.b eab,reg9dnb is (op=9 & reg9dnb & op68=0)... & eab
+ { subflags(reg9dnb, eab); reg9dnb = reg9dnb - eab; resflags(reg9dnb); }
+
+:sub.w eaw,reg9dnw is (op=9 & reg9dnw & op68=1)... & eaw
+ { subflags(reg9dnw, eaw); reg9dnw = reg9dnw - eaw; resflags(reg9dnw); }
+
+:sub.l eal,reg9dn is (op=9 & reg9dn & op68=2)... & eal
+ { subflags(reg9dn, eal); reg9dn = reg9dn - eal; resflags(reg9dn); }
+
+:sub.b reg9dnb,eab is (op=9 & reg9dnb & op68=4 & $(MEM_ALTER_ADDR_MODES))... & eab
+ { subflags(eab, reg9dnb); eab = eab - reg9dnb; resflags(eab); }
+
+:sub.w reg9dnw,eaw is (op=9 & reg9dnw & op68=5 & $(MEM_ALTER_ADDR_MODES))... & eaw
+ { subflags(eaw, reg9dnw); eaw = eaw - reg9dnw; resflags(eaw); }
+
+:sub.l reg9dn,eal is (op=9 & reg9dn & op68=6 & $(MEM_ALTER_ADDR_MODES))... & eal
+ { subflags(eal, reg9dn); eal = eal - reg9dn; resflags(eal); }
+
+:suba.w eaw,reg9an is (op=9 & reg9an & op68=3)... & eaw { reg9an = reg9an - sext(eaw); }
+:suba.l eal,reg9an is (op=9 & reg9an & op68=7)... & eal { reg9an = reg9an - eal; }
+
+:subi.b "#"^d8,e2b is opbig=4 & op67=0 & $(DAT_ALTER_ADDR_MODES); d8; e2b [ savmod2=savmod1; regtsan=regtfan; ]
+ { subflags(e2b, d8); e2b=e2b-d8; resflags(e2b); }
+
+:subi.w "#"^d16,e2w is opbig=4 & op67=1 & $(DAT_ALTER_ADDR_MODES); d16; e2w [ savmod2=savmod1; regtsan=regtfan; ]
+ { subflags(e2w, d16); e2w=e2w-d16; resflags(e2w);}
+
+:subi.l "#"^d32,e2l is opbig=4 & op67=2 & $(DAT_ALTER_ADDR_MODES); d32; e2l [ savmod2=savmod1; regtsan=regtfan; ]
+ { subflags(e2l, d32); e2l=e2l-d32; resflags(e2l);}
+
+:subq.b "#"^quick,eab is (op=5 & quick & op68=4)... & eab
+ { subflags(eab, quick); eab = eab-quick; resflags(eab); }
+
+:subq.w "#"^quick,eaw is (op=5 & quick & op68=5)... & eaw
+ { subflags(eaw, quick); eaw = eaw-quick; resflags(eaw); }
+
+:subq.l "#"^quick,eal is (op=5 & quick & op68=6)... & eal
+ { subflags(eal, quick); eal = eal-quick; resflags(eal); }
+
+# special case for address register destination: condition codes not affected
+:subq.w "#"^quick,regan is op=5 & quick & op68=5 & mode=1 & regan { regan = regan - quick; }
+:subq.l "#"^quick,regan is op=5 & quick & op68=6 & mode=1 & regan { regan = regan - quick; }
+
+
+
+:subx.b Tyb,Txb is op=9 & op8=1 & op67=0 & op45=0 & Tyb & Txb
+ { tmp0:1 = zext(XF); subxflags(Txb, Tyb); local tmp =tmp0+Tyb; Txb=Txb-tmp; extendedResultFlags(Txb); }
+
+:subx.w Tyw,Txw is op=9 & op8=1 & op67=1 & op45=0 & Tyw & Txw
+ { tmp0:2 = zext(XF); subxflags(Txw, Tyw); local tmp =tmp0+Tyw; Txw=Txw-tmp; extendedResultFlags(Txw); }
+
+:subx.l Ty,Tx is op=9 & op8=1 & op67=2 & op45=0 & Ty & Tx
+ { tmp0:4 = zext(XF); subxflags(Tx, Ty); local tmp =tmp0+Ty; Tx=Tx-tmp; extendedResultFlags(Tx); }
+
+
+:swap regdn is opbig=0x48 & op37=8 & regdn { logflags(); regdn = (regdn << 16) | (regdn>>16); resflags(regdn); }
+
+@ifndef COLDFIRE
+:tas eab is (opbig=0x4a & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eab { logflags(); resflags(eab); eab = eab | 0x80; }
+@endif # COLDFIRE
+
+:trap "#"^op03 is opbig=0x4e & op67=1 & op45=0 & op03 { vector:1 = op03; __m68k_trap(vector); }
+:trap^cc is op=5 & cc & op37=31 & op02=4 { if (!cc) goto inst_next; SP = SP - 4; *:4 SP = PC; vector:1 = 7; __m68k_trap(vector); }
+:trap^cc^".w" "#"^d16 is op=5 & cc & op37=31 & op02=2; d16 { if (!cc) goto inst_next; SP = SP - 4; *:4 SP = PC; __m68k_trapv(); }
+:trap^cc^".l" "#"^d32 is op=5 & cc & op37=31 & op02=3; d32 { if (!cc) goto inst_next; SP = SP - 4; *:4 SP = PC; __m68k_trapv(); }
+:trapv is opbig=0x4e & op37=14 & op02=6 { if (!VF) goto inst_next; __m68k_trapv(); }
+
+:tst.b eab is (opbig=0x4a & op67=0)... & eab { logflags(); resflags(eab); }
+:tst.w eaw is (opbig=0x4a & op67=1)... & eaw { logflags(); resflags(eaw); }
+:tst.l eal is (opbig=0x4a & op67=2)... & eal { logflags(); resflags(eal); }
+
+@ifdef COLDFIRE
+:tas eab is (opbig=0x4a & op67=3)... & eab { logflags(); resflags(eab); eab = eab | 0x80; }
+@endif # COLDFIRE
+
+:unlk regan is opbig=0x4e & op37=11 & regan { SP = regan; regan = *SP; SP = SP+4; }
+
+:unpk Tyw,Txw,"#"^d16 is op=8 & Txw & op48=24 & Tyw & rmbit=0; d16 {
+ Txw = (Txw & 0xF0F0) | ((((Tyw & 0x00F0) << 4) | (Tyw & 0x000F)) + d16);
+}
+
+:unpk Tyb,Txw,"#"^d16 is op=8 & Tyb & op48=24 & Txw & rmbit=1; d16 {
+ local source:2 = zext(Tyb);
+ source = (((source & 0x00F0) << 4) | (source & 0x000F)) + d16;
+ Txw = (Txw & 0xF0F0) | source;
+}
+
+# Floating Point Instructions
+
+# 68040 directly implements Floating Point instructions but requires Coprocessor ID be 001
+@ifdef MC68040
+@define FP_COP "copid=1"
+@define FP_FCOP "fcopid=1"
+@else
+@define FP_COP "epsilon"
+@define FP_FCOP "epsilon"
+@endif
+
+# Condition codes
+fcc: "eq" is fcode=0x01 { tmp:1 = $(Z_FP); clearflags_fp(); export tmp; }
+fcc: "ne" is fcode=0x0e { tmp:1 = !($(Z_FP)); clearflags_fp(); export tmp; } # note this is wrong in the manual
+fcc: "gt" is fcode=0x12 { tmp:1 = !($(NAN_FP) || $(Z_FP) || $(N_FP)); clearflags_fp(); export tmp; }
+fcc: "ngt" is fcode=0x1d { tmp:1 = $(NAN_FP) || $(Z_FP) || $(N_FP); clearflags_fp(); export tmp; }
+fcc: "ge" is fcode=0x13 { tmp:1 = $(Z_FP) || !($(NAN_FP) || $(N_FP)); clearflags_fp(); export tmp; }
+fcc: "nge" is fcode=0x1c { tmp:1 = $(NAN_FP) || ($(N_FP) && !$(Z_FP)); clearflags_fp(); export tmp; }
+fcc: "lt" is fcode=0x14 { tmp:1 = $(N_FP) && !($(NAN_FP) || $(Z_FP)); clearflags_fp(); export tmp; }
+fcc: "nlt" is fcode=0x1b { tmp:1 = $(NAN_FP) || ($(Z_FP) || !$(N_FP)); clearflags_fp(); export tmp; }
+fcc: "le" is fcode=0x15 { tmp:1 = $(Z_FP) || ($(N_FP) && !$(NAN_FP)); clearflags_fp(); export tmp; }
+fcc: "nle" is fcode=0x1a { tmp:1 = $(NAN_FP) || !($(N_FP) || $(Z_FP)); clearflags_fp(); export tmp; }
+fcc: "gl" is fcode=0x16 { tmp:1 = !($(NAN_FP) || $(Z_FP)); clearflags_fp(); export tmp; }
+fcc: "ngl" is fcode=0x19 { tmp:1 = $(NAN_FP) || $(Z_FP); clearflags_fp(); export tmp; }
+fcc: "gle" is fcode=0x17 { tmp:1 = $(NAN_FP); clearflags_fp(); export tmp; }
+fcc: "ngle" is fcode=0x18 { tmp:1 = $(NAN_FP); clearflags_fp(); export tmp; }
+
+fcc: "ogt" is fcode=0x02 { tmp:1 = !($(NAN_FP) || $(Z_FP) || $(N_FP)); clearflags_fp(); export tmp; }
+fcc: "ule" is fcode=0x0d { tmp:1 = $(NAN_FP) || $(Z_FP) || $(N_FP); clearflags_fp(); export tmp; }
+fcc: "oge" is fcode=0x03 { tmp:1 = $(Z_FP) || !($(NAN_FP) || $(N_FP)); clearflags_fp(); export tmp; }
+fcc: "ult" is fcode=0x0c { tmp:1 = $(NAN_FP) || ($(N_FP) && !$(Z_FP)); clearflags_fp(); export tmp; }
+fcc: "olt" is fcode=0x04 { tmp:1 = $(N_FP) && !($(NAN_FP) || $(Z_FP)); clearflags_fp(); export tmp; }
+fcc: "uge" is fcode=0x0b { tmp:1 = $(NAN_FP) || $(Z_FP) || $(N_FP); clearflags_fp(); export tmp; }
+fcc: "ole" is fcode=0x05 { tmp:1 = $(Z_FP) || ($(N_FP) && !$(NAN_FP)); clearflags_fp(); export tmp; }
+fcc: "ugt" is fcode=0x0a { tmp:1 = !$(NAN_FP) || !($(N_FP) || $(Z_FP)); clearflags_fp(); export tmp; }
+fcc: "ogl" is fcode=0x06 { tmp:1 = !($(NAN_FP) || $(Z_FP)); clearflags_fp(); export tmp; }
+fcc: "ueq" is fcode=0x09 { tmp:1 = $(NAN_FP) || $(Z_FP); clearflags_fp(); export tmp; }
+fcc: "or" is fcode=0x07 { tmp:1 = $(NAN_FP); clearflags_fp(); export tmp; }
+fcc: "un" is fcode=0x08 { tmp:1 = $(NAN_FP); clearflags_fp(); export tmp; }
+
+fcc: "f" is fcode=0x00 { export 0:1; }
+fcc: "t" is fcode=0x0f { export 1:1; }
+fcc: "sf" is fcode=0x10 { export 0:1; }
+fcc: "st" is fcode=0x1f { export 1:1; }
+fcc: "seq" is fcode=0x11 { tmp:1 = $(Z_FP); clearflags_fp(); export tmp; }
+fcc: "sne" is fcode=0x1e { tmp:1 = $(Z_FP); clearflags_fp(); export tmp; }
+
+@define FormatByteWordLongSimple "( ffmt=0 | ffmt=1 | ffmt=4 | ffmt=6 )"
+
+# The following constraint should be used when using fprec
+@define FPREC_BWLS "fprec & ( ffmt=0 | ffmt=1 | ffmt=4 | ffmt=6 )" # Byte,Word,Long,Simple only
+@define FPREC_DXP "fprec & ( ffmt=2 | ffmt=3 | ffmt=5)" # Double,Extended,Packed only
+@define FPREC_XP "fprec & ( ffmt=2 | ffmt=3)" # Extended,Packed only
+@define FPREC_DX "fprec & ( ffmt=2 | ffmt=5)" # Double,Extended only
+@define FPREC_X "fprec & ffmt=2" # Extended only
+@define FPREC_D "fprec & ffmt=5" # Double only
+@define FPREC_P "fprec & ffmt=3" # Packed only
+@define FPREC_Pd "fprec & ffmt=7" # Packed-dynamic only
+
+fprec: "l" is ffmt=0 {}
+fprec: "s" is ffmt=1 {}
+fprec: "x" is ffmt=2 {}
+fprec: "p" is ffmt=3 {}
+fprec: "w" is ffmt=4 {}
+fprec: "d" is ffmt=5 {}
+fprec: "b" is ffmt=6 {}
+fprec: "p" is ffmt=7 {}
+
+
+:fabs.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x18; e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = abs(tmp); }
+:fabs.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x18; e2x
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = abs(tmp); }
+:fabs.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x18; e2d
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = abs(tmp); }
+:fabs fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x18 { fdst = abs(fsrc); }
+
+@ifdef MC68040
+
+fabsrnd: "s" is fopmode=0x58 {}
+fabsrnd: "d" is fopmode=0x5c {}
+
+:f^fabsrnd^"abs."^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fabsrnd & $(FPREC_BWLS) & (fopmode=0x58 | fopmode=0x5c); e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:f^fabsrnd^"abs."^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fabsrnd & $(FPREC_XP) & (fopmode=0x58 | fopmode=0x5c); e2x
+ [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:f^fabsrnd^"abs."^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fabsrnd & $(FPREC_D) & (fopmode=0x58 | fopmode=0x5c); e2d
+ [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:f^fabsrnd^"abs" fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fabsrnd & (fopmode=0x58 | fopmode=0x5c) unimpl
+
+@endif # MC68040
+
+:facos.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x1c; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = acos(tmp);}
+:facos.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x1c; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = acos(tmp);}
+:facos.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x1c; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = acos(tmp);}
+:facos fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1c { fdst = acos(fsrc);}
+
+:fadd.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x22; e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = fdst f+ tmp; }
+:fadd.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x22; e2x
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = fdst f+ tmp; }
+:fadd.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x22; e2d
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = fdst f+ tmp; }
+:fadd fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x22 { fdst = fdst f+ fsrc; }
+
+@ifdef MC68040
+
+faddrnd: "s" is fopmode=0x62 {}
+faddrnd: "d" is fopmode=0x66 {}
+
+:f^faddrnd^"add."^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & faddrnd & $(FPREC_BWLS) & (fopmode=0x62 | fopmode=0x66); e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:f^faddrnd^"add."^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & faddrnd & $(FPREC_XP) & (fopmode=0x62 | fopmode=0x66); e2x
+ [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:f^faddrnd^"add."^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & faddrnd & $(FPREC_D) & (fopmode=0x62 | fopmode=0x66); e2d
+ [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:f^faddrnd^"add" fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & faddrnd & (fopmode=0x62 | fopmode=0x66) unimpl
+
+@endif # MC68040
+
+:fasin.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x0c; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = asin(tmp);}
+:fasin.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x0c; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = asin(tmp);}
+:fasin.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x0c; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = asin(tmp);}
+:fasin fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x0c { fdst = asin(fsrc);}
+
+:fatan.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x0a; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = atan(tmp);}
+:fatan.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x0a; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = atan(tmp);}
+:fatan.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x0a; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = atan(tmp);}
+:fatan fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x0a { fdst = atan(fsrc);}
+
+:fatanh.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x0d; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = tanh(tmp);}
+:fatanh.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x0d; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = tanh(tmp);}
+:fatanh.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x0d; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = tanh(tmp);}
+:fatanh fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x0d { fdst = tanh(fsrc);}
+
+:fb^fcc^".w" addr16 is fop=15 & $(FP_FCOP) & f0808=0 & f0707=1 & fsize=0 & fcc; addr16 { if (fcc) goto addr16; }
+:fb^fcc^".l" addr32 is fop=15 & $(FP_FCOP) & f0808=0 & f0707=1 & fsize=1 & fcc; addr32 { if (fcc) goto addr32; }
+
+:fcmp.b e2b, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & ffmt=6 & fopmode=0x38; e2b
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = int2float(e2b); local result=fdst f- tmp; resflags_fp(result); }
+
+:fcmp.w e2w, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & ffmt=4 & fopmode=0x38; e2w
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = int2float(e2w); local result=fdst f- tmp; resflags_fp(result); }
+
+:fcmp.l e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & ffmt=0 & fopmode=0x38; e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = int2float(e2l); local result=fdst f- tmp; resflags_fp(result); }
+
+:fcmp.s e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & ffmt=1 & fopmode=0x38; e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); local result=fdst f- tmp; resflags_fp(result); }
+
+:fcmp.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x38; e2x
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); local result=fdst f- tmp; resflags_fp(result); }
+
+:fcmp.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x38; e2d
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); local result=fdst f- tmp; resflags_fp(result); }
+
+:fcmp fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x38
+ { tmp:12 = float2float(fsrc); local result=fdst f- tmp; resflags_fp(result); }
+
+:fcos.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x1d; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = cos(tmp);}
+:fcos.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x1d; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = cos(tmp);}
+:fcos.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x1d; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = cos(tmp);}
+:fcos fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1d { fdst = cos(fsrc);}
+
+:fcosh.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x19; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = cosh(tmp);}
+:fcosh.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x19; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = cosh(tmp);}
+:fcosh.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x19; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = cosh(tmp);}
+:fcosh fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x19 { fdst = cos(fsrc);}
+
+:fdb^fcc fcnt, addr16 is fop=15 & $(FP_FCOP) & f0308=9 & fcnt; f0615=0 & fcc; addr16
+ { if (fcc) goto inst_next;
+ fcnt = fcnt - 1;
+ local tst = (fcnt == -1);
+ if (!tst) goto addr16;
+ }
+
+:fdiv.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x20; e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] { denom:12 = float2float(e2l); fdst = fdst f/ denom;}
+:fdiv.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x20; e2x
+ [ savmod2=savmod1; regtsan=regtfan; ] { denom:12 = float2float(e2x); fdst = fdst f/ denom;}
+:fdiv.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x20; e2d
+ [ savmod2=savmod1; regtsan=regtfan; ] { denom:12 = float2float(e2d); fdst = fdst f/ denom;}
+:fdiv fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x20 { fdst = fdst f/ fsrc;}
+
+@ifdef MC68040
+
+fdivrnd: "s" is fopmode=0x60 {}
+fdivrnd: "d" is fopmode=0x64 {}
+
+:f^fdivrnd^"div."^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fdivrnd & $(FPREC_BWLS) & (fopmode=0x60 | fopmode=0x64); e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:f^fdivrnd^"div."^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fdivrnd & $(FPREC_XP) & (fopmode=0x60 | fopmode=0x64); e2x
+ [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:f^fdivrnd^"div."^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fdivrnd & $(FPREC_D) & (fopmode=0x60 | fopmode=0x64); e2d
+ [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:f^fdivrnd^"div" fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fdivrnd & (fopmode=0x60 | fopmode=0x64) unimpl
+
+@endif # MC68040
+
+:fetox.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x10; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fetox.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x10; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fetox.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x10; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fetox fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x10 unimpl
+
+:fetoxm1.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x08; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fetoxm1.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x08; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fetoxm1.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x08; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fetoxm1 fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x08 unimpl
+
+:fgetexp.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x1e; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fgetexp.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x1e; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fgetexp.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x1e; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fgetexp fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1e unimpl
+
+:fgetman.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x1f; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fgetman.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x1f; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fgetman.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x1f; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fgetman fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1f unimpl
+
+:fint.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x01; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:8 = trunc(e2l); fdst = int2float(tmp); }
+:fint.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x01; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:8 = trunc(e2x); fdst = int2float(tmp); }
+:fint.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x01; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:8 = trunc(e2d); fdst = int2float(tmp); }
+:fint fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x01 { tmp:8 = trunc(fsrc); fdst = int2float(tmp); }
+
+:fintrz.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x03; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fintrz.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x03; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fintrz.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x03; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fintrz fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x03 unimpl
+
+:flog10.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x15; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:flog10.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x15; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:flog10.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x15; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:flog10 fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x15 unimpl
+
+:flog2.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x16; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:flog2.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x16; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:flog2.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x16; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:flog2 fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x16 unimpl
+
+:flogn.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x14; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:flogn.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x14; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:flogn.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x14; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:flogn fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x14 unimpl
+
+:flognp1.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x06; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:flognp1.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x06; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:flognp1.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x06; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:flognp1 fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x06 unimpl
+
+:fmod.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0& fdst & $(FPREC_BWLS) & fopmode=0x21; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fmod.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0& fdst & $(FPREC_XP) & fopmode=0x21; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fmod.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0& fdst & $(FPREC_D) & fopmode=0x21; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fmod fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x21 unimpl
+
+
+:fmove.b e2b, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fopmode=0x00 & ffmt=6; e2b
+ [ savmod2=savmod1; regtsan=regtfan; ] { fdst = int2float(e2b); resflags_fp(fdst); }
+
+:fmove.w e2w, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fopmode=0x00 & ffmt=4; e2w
+ [ savmod2=savmod1; regtsan=regtfan; ] { fdst = int2float(e2w); resflags_fp(fdst); }
+
+:fmove.l e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fopmode=0x00 & ffmt=0; e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] { fdst = int2float(e2l); resflags_fp(fdst); }
+
+# Single float (32-bits)
+:fmove.s e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fopmode=0x00 & ffmt=1; e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] { fdst = float2float(e2l); resflags_fp(fdst); }
+
+# NB- The 68k manual says floating point regs are stored internally as 80 bits, but 96 bits are moved to/from memory
+#
+:fmove.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x00
+ & (ffmt=2 | ffmt=3); e2x
+ [ savmod2=savmod1; regtsan=regtfan; ]
+ { fdst = float2float(e2x); resflags_fp(fdst); }
+
+:fmove.d e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fopmode=0x00 & ffmt=5; e2d
+ [ savmod2=savmod1; regtsan=regtfan; ] { fdst = float2float(e2d); resflags_fp(fdst); }
+
+:fmove fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x00
+ { fdst = fsrc; resflags_fp(fdst); }
+
+@ifdef MC68040
+
+fmovernd: "s" is fopmode=0x40 {}
+fmovernd: "d" is fopmode=0x44 {}
+
+:f^fmovernd^"move."^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fmovernd & $(FPREC_BWLS) & (fopmode=0x40 | fopmode=0x44); e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] { fdst = int2float(e2l); }
+:f^fmovernd^"move."^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fmovernd & $(FPREC_XP) & (fopmode=0x40 | fopmode=0x44); e2x
+ [ savmod2=savmod1; regtsan=regtfan; ] { fdst = int2float(e2x); }
+:f^fmovernd^"move."^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fmovernd & $(FPREC_D) & (fopmode=0x40 | fopmode=0x44); e2d
+ [ savmod2=savmod1; regtsan=regtfan; ] { fdst = int2float(e2d); }
+:f^fmovernd^"move" fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fmovernd & (fopmode=0x40 | fopmode=0x44)
+ { fdst = fsrc; }
+
+@endif # MC68040
+
+#TODO: Documented decoding (w/ coprocess id in bits 10-12) conflicts with ASL instruction and differs from Instruction Format Summary
+# Convert float in fdst to an int and then move to byte
+:fmove.b fdst, e2b is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & ffmt=6; e2b
+ [ savmod2=savmod1; regtsan=regtfan; ] { e2b = trunc(fdst); }
+
+# Convert float in fdst to an int and then move to word 16-bits
+:fmove.w fdst, e2w is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & ffmt=4; e2w
+ [ savmod2=savmod1; regtsan=regtfan; ] { e2w = trunc(fdst); }
+
+# Convert float in fdst to an int and then move to long 32-bits
+:fmove.l fdst, e2l is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & ffmt=0; e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] { e2l = trunc(fdst); }
+
+# destination is single float (32-bits)
+:fmove.s fdst, e2l is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & ffmt=1; e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] { e2l = float2float(fdst); resflags_fp(e2l); }
+
+:fmove.^fprec fdst, e2x is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & $(FPREC_X); e2x
+ [ savmod2=savmod1; regtsan=regtfan; ] { e2x = float2float(fdst); resflags_fp(e2x); }
+
+# Double float (64-bits)
+:fmove.^fprec fdst, e2d is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & $(FPREC_D); e2d
+ [ savmod2=savmod1; regtsan=regtfan; ] { e2d = float2float(fdst); resflags_fp(e2d); }
+
+:fmove.p fdst, e2l {"#"fkfactor} is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfactor & $(FPREC_P); e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] { kfact:4 = fkfactor; e2l = kfactor(fdst, kfact); }
+
+:fmove.p fdst, e2l {fkfacreg} is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & $(FPREC_Pd); e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] { e2l = kfactor(fdst, fkfacreg); }
+
+#Special case for FMOVEM.L and must occur before it within this file
+:fmove.l e2l, FPCR is op=15 & $(FP_COP) & $(DAT_ALTER_ADDR_MODES) & op68=0 & FPCR; f1415=2 & fdr=0 & f1012=4 & f0009=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { FPCR = e2l; }
+:fmove.l FPCR, e2l is op=15 & $(FP_COP) & $(DAT_ALTER_ADDR_MODES) & op68=0 & FPCR; f1415=2 & fdr=1 & f1012=4 & f0009=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { e2l = FPCR; }
+:fmove.l e2l, FPSR is op=15 & $(FP_COP) & $(DAT_ALTER_ADDR_MODES) & op68=0 & FPSR; f1415=2 & fdr=0 & f1012=2 & f0009=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { FPSR = e2l; }
+:fmove.l FPSR, e2l is op=15 & $(FP_COP) & $(DAT_ALTER_ADDR_MODES) & op68=0 & FPSR; f1415=2 & fdr=1 & f1012=2 & f0009=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { e2l = FPSR; }
+:fmove.l e2l, FPIAR is op=15 & $(FP_COP) & op68=0 & FPIAR; f1415=2 & fdr=0 & f1012=1 & f0009=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { FPIAR = e2l; }
+:fmove.l FPIAR, e2l is op=15 & $(FP_COP) & op68=0 & FPIAR; f1415=2 & fdr=1 & f1012=1 & f0009=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { e2l = FPIAR; }
+
+#
+# TODO: this table should contain all the rom constants
+romconst: is fromoffset=0x00 { tmp1:8 = 0x400921FB4D12D84A:8; tmp:12 = float2float(tmp1); export tmp; } # pi=3.14...
+romconst: is fromoffset=0x0f { tmp1:8 = 0x0:8; tmp:12 = int2float(tmp1); export tmp; }
+romconst: is fromoffset=0x32 { tmp1:8 = 0x01:8; tmp:12 = int2float(tmp1); export tmp; }
+romconst: is fromoffset=0x33 { tmp1:8 = 10:8; tmp:12 = int2float(tmp1); export tmp; }
+romconst: is fromoffset=0x34 { tmp1:8 = 100:8; tmp:12 = int2float(tmp1); export tmp; }
+romconst: is fromoffset=0x35 { tmp1:8 = 10000:8; tmp:12 = int2float(tmp1); export tmp; }
+romconst: is fromoffset=0x36 { tmp1:8 = 100000000:8; tmp:12 = int2float(tmp1); export tmp; }
+romconst: is fromoffset { tmp1:8 = 0x0:8; tmp:12 = int2float(tmp1); export tmp; }
+
+:fmovecr.x "#"^fromoffset, fdst is op=15 & $(FP_COP) & op08=0; f1015=0x17 & fdst & fromoffset & romconst { fdst = romconst; }
+
+# Memory to Floating point register, forward direction
+m2fpF7: FP0 is FP0 & frlist7=1 { FP0 = *movemptr; movemptr = movemptr + 12; }
+m2fpF7: is frlist7=0 { }
+m2fpF6: m2fpF7" "FP1 is FP1 & frlist6=1 & m2fpF7 { FP1 = *movemptr; movemptr = movemptr + 12; }
+m2fpF6: m2fpF7 is frlist6=0 & m2fpF7 { }
+m2fpF5: m2fpF6" "FP2 is FP2 & frlist5=1 & m2fpF6 { FP2 = *movemptr; movemptr = movemptr + 12; }
+m2fpF5: m2fpF6 is frlist5=0 & m2fpF6 { }
+m2fpF4: m2fpF5" "FP3 is FP3 & frlist4=1 & m2fpF5 { FP3 = *movemptr; movemptr = movemptr + 12; }
+m2fpF4: m2fpF5 is frlist4=0 & m2fpF5 { }
+m2fpF3: m2fpF4" "FP4 is FP4 & frlist3=1 & m2fpF4 { FP4 = *movemptr; movemptr = movemptr + 12; }
+m2fpF3: m2fpF4 is frlist3=0 & m2fpF4 { }
+m2fpF2: m2fpF3" "FP5 is FP5 & frlist2=1 & m2fpF3 { FP5 = *movemptr; movemptr = movemptr + 12; }
+m2fpF2: m2fpF3 is frlist2=0 & m2fpF3 { }
+m2fpF1: m2fpF2" "FP6 is FP6 & frlist1=1 & m2fpF2 { FP6 = *movemptr; movemptr = movemptr + 12; }
+m2fpF1: m2fpF2 is frlist1=0 & m2fpF2 { }
+m2fpF0: { m2fpF1" "FP7 } is FP7 & frlist0=1 & m2fpF1 { FP7 = *movemptr; movemptr = movemptr + 12; }
+m2fpF0: { m2fpF1 } is frlist0=0 & m2fpF1 { }
+
+# Memory to Floating point register, reverse direction
+m2fpR7: FP7 is FP7 & frlist7=1 { movemptr = movemptr - 12; FP7 = *movemptr; }
+m2fpR7: is frlist7=0 { }
+m2fpR6: m2fpR7" "FP6 is FP6 & frlist6=1 & m2fpR7 { movemptr = movemptr - 12; FP6 = *movemptr; }
+m2fpR6: m2fpR7 is frlist6=0 & m2fpR7 { }
+m2fpR5: m2fpR6" "FP5 is FP5 & frlist5=1 & m2fpR6 { movemptr = movemptr - 12; FP5 = *movemptr; }
+m2fpR5: m2fpR6 is frlist5=0 & m2fpR6 { }
+m2fpR4: m2fpR5" "FP4 is FP4 & frlist4=1 & m2fpR5 { movemptr = movemptr - 12; FP4 = *movemptr; }
+m2fpR4: m2fpR5 is frlist4=0 & m2fpR5 { }
+m2fpR3: m2fpR4" "FP3 is FP3 & frlist3=1 & m2fpR4 { movemptr = movemptr - 12; FP3 = *movemptr; }
+m2fpR3: m2fpR4 is frlist3=0 & m2fpR4 { }
+m2fpR2: m2fpR3" "FP2 is FP2 & frlist2=1 & m2fpR3 { movemptr = movemptr - 12; FP2 = *movemptr; }
+m2fpR2: m2fpR3 is frlist2=0 & m2fpR3 { }
+m2fpR1: m2fpR2" "FP1 is FP1 & frlist1=1 & m2fpR2 { movemptr = movemptr - 12; FP1 = *movemptr; }
+m2fpR1: m2fpR2 is frlist1=0 & m2fpR2 { }
+m2fpR0: { m2fpR1" "FP0 } is FP0 & frlist0=1 & m2fpR1 { movemptr = movemptr - 12; FP0 = *movemptr; }
+m2fpR0: { m2fpR1 } is frlist0=0 & m2fpR1 { }
+
+
+# Floating point register to Memory, forward direction
+fp2mF7: FP0 is FP0 & frlist7=1 { *movemptr = FP0; movemptr = movemptr + 12; }
+fp2mF7: is frlist7=0 { }
+fp2mF6: fp2mF7" "FP1 is FP1 & frlist6=1 & fp2mF7 { *movemptr = FP1; movemptr = movemptr + 12; }
+fp2mF6: fp2mF7 is frlist6=0 & fp2mF7 { }
+fp2mF5: fp2mF6" "FP2 is FP2 & frlist5=1 & fp2mF6 { *movemptr = FP2; movemptr = movemptr + 12; }
+fp2mF5: fp2mF6 is frlist5=0 & fp2mF6 { }
+fp2mF4: fp2mF5" "FP3 is FP3 & frlist4=1 & fp2mF5 { *movemptr = FP3; movemptr = movemptr + 12; }
+fp2mF4: fp2mF5 is frlist4=0 & fp2mF5 { }
+fp2mF3: fp2mF4" "FP4 is FP4 & frlist3=1 & fp2mF4 { *movemptr = FP4; movemptr = movemptr + 12; }
+fp2mF3: fp2mF4 is frlist3=0 & fp2mF4 { }
+fp2mF2: fp2mF3" "FP5 is FP5 & frlist2=1 & fp2mF3 { *movemptr = FP5; movemptr = movemptr + 12; }
+fp2mF2: fp2mF3 is frlist2=0 & fp2mF3 { }
+fp2mF1: fp2mF2" "FP6 is FP6 & frlist1=1 & fp2mF2 { *movemptr = FP6; movemptr = movemptr + 12; }
+fp2mF1: fp2mF2 is frlist1=0 & fp2mF2 { }
+fp2mF0: { fp2mF1" "FP7 } is FP7 & frlist0=1 & fp2mF1 { *movemptr = FP7; movemptr = movemptr + 12; }
+fp2mF0: { fp2mF1 } is frlist0=0 & fp2mF1 { }
+
+# Floating point register to Memory, reverse direction
+fp2mR7: FP7 is FP7 & frlist7=1 { movemptr = movemptr - 12; *movemptr = FP7; }
+fp2mR7: is frlist7=0 { }
+fp2mR6: fp2mR7" "FP6 is FP6 & frlist6=1 & fp2mR7 { movemptr = movemptr - 12; *movemptr = FP6; }
+fp2mR6: fp2mR7 is frlist6=0 & fp2mR7 { }
+fp2mR5: fp2mR6" "FP5 is FP5 & frlist5=1 & fp2mR6 { movemptr = movemptr - 12; *movemptr = FP5; }
+fp2mR5: fp2mR6 is frlist5=0 & fp2mR6 { }
+fp2mR4: fp2mR5" "FP4 is FP4 & frlist4=1 & fp2mR5 { movemptr = movemptr - 12; *movemptr = FP4; }
+fp2mR4: fp2mR5 is frlist4=0 & fp2mR5 { }
+fp2mR3: fp2mR4" "FP3 is FP3 & frlist3=1 & fp2mR4 { movemptr = movemptr - 12; *movemptr = FP3; }
+fp2mR3: fp2mR4 is frlist3=0 & fp2mR4 { }
+fp2mR2: fp2mR3" "FP2 is FP2 & frlist2=1 & fp2mR3 { movemptr = movemptr - 12; *movemptr = FP2; }
+fp2mR2: fp2mR3 is frlist2=0 & fp2mR3 { }
+fp2mR1: fp2mR2" "FP1 is FP1 & frlist1=1 & fp2mR2 { movemptr = movemptr - 12; *movemptr = FP1; }
+fp2mR1: fp2mR2 is frlist1=0 & fp2mR2 { }
+fp2mR0: { fp2mR1" "FP0 } is FP0 & frlist0=1 & fp2mR1 { movemptr = movemptr - 12; *movemptr = FP0; }
+fp2mR0: { fp2mR1 } is frlist0=0 & fp2mR1 { }
+
+
+# NB- when doing preincrement or postincrement modes, the movemptr that is set in e2x is used as the starting address for the move.
+# Then at completion of the move, the reg is set to the movemptr.
+# Note that movem (non-floating point) does this slightly differently)
+#
+# Not a predecrement or postincrement
+:fmovem.x fp2mF0, e2x is op=15 & $(FP_COP) & op68=0 & (mode=2 | mode=5 | mode=6 | mode=7);
+ f1415=3 & fdr=1 & f0810=0 & fp2mF0 & flmode_t=0 & flmode_m=1; e2x
+ [ savmod2=savmod1; regtsan=regtfan; ]
+ { build fp2mF0; }
+
+# When mode=3 it's a postincrement
+:fmovem.x fp2mF0, e2x is regan & op=15 & $(FP_COP) & op68=0 & mode=3; f1415=3 & fdr=1 & f0810=0 & fp2mF0 & flmode_t=0 & flmode_m=1; e2x
+ [ savmod2=savmod1; regtsan=regtfan; ]
+ { build fp2mF0; regan = movemptr; }
+
+# When mode=4 it's a predecrement, and also must update the address register with the new address
+:fmovem.x fp2mR0, e2x is regan & op=15 & $(FP_COP) & op68=0 & mode=4; f1415=3 & fdr=1 & f0810=0 & fp2mR0 & flmode_t=0 & flmode_m=0; e2x
+ [ savmod2=savmod1; regtsan=regtfan; ]
+ { build fp2mR0; regan = movemptr; }
+
+# Not a predecrement or postincrement
+:fmovem.x e2x, m2fpF0 is op=15 & $(FP_COP) & op68=0 & (mode=2 | mode=5 | mode=6 | mode=7);
+ f1415=3 & fdr=0 & f0810=0 & m2fpF0 & flmode_t=0 & flmode_m=1; e2x
+ [ savmod2=savmod1; regtsan=regtfan; ]
+ { build m2fpF0; }
+
+# When mode=3 it's a postincrement
+:fmovem.x e2x, m2fpF0 is regan & op=15 & $(FP_COP) & op68=0 & mode=3;
+ f1415=3 & fdr=0 & f0810=0 & m2fpF0 & flmode_t=0 & flmode_m=1; e2x
+ [ savmod2=savmod1; regtsan=regtfan; ]
+ { build m2fpF0; regan = movemptr; }
+
+# When mode=4 it's a predecrement, and also must update the address register with the new address
+:fmovem.x e2x, m2fpR0 is regan & op=15 & $(FP_COP) & op68=0 & mode=4; f1415=3 & fdr=0 & f0810=0 & m2fpR0 & flmode_t=0 & flmode_m=0; e2x
+ [ savmod2=savmod1; regtsan=regtfan; ]
+ { build m2fpR0; regan = movemptr; }
+
+# TODO: Pcode for dynamic register mask is PITA
+:fmovem.x fldynreg, e2l is op=15 & $(FP_COP) & op68=0 & $(POSTINC_CTL_ADDR_MODES); f1415=3 & fdr=1 & f0810=0 & fldynreg & flmode_t=1 & flmode_m=1; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fmovem.x fldynreg, e2l is op=15 & $(FP_COP) & op68=0 & mode=4; f1415=3 & fdr=1 & f0810=0 & fldynreg & flmode_t=1 & flmode_m=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+
+:fmovem.x e2l, fldynreg is op=15 & $(FP_COP) & op68=0 & $(POSTINC_CTL_ADDR_MODES); f1415=3 & fdr=0 & f0810=0 & fldynreg & flmode_t=1 & flmode_m=1; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fmovem.x e2l, fldynreg is op=15 & $(FP_COP) & op68=0 & mode=4; f1415=3 & fdr=0 & f0810=0 & fldynreg & flmode_t=1 & flmode_m=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+
+# Memory to Floating point control register
+m2fpC2: FPCR is FPCR & f12=1 { FPCR = *movemptr; movemptr = movemptr + 12; }
+m2fpC2: is f12=0 { }
+m2fpC1: m2fpC2" "FPSR is FPSR & f11=1 & m2fpC2 { FPSR = *movemptr; movemptr = movemptr + 12; }
+m2fpC1: m2fpC2 is f11=0 & m2fpC2 { }
+m2fpC0: { m2fpC1" "FPCR } is FPCR & f10=1 & m2fpC1 { FPCR = *movemptr; movemptr = movemptr + 12; }
+m2fpC0: { m2fpC1 } is f10=0 & m2fpC1 { }
+
+# Floating point control register to Memory
+fp2mC2: FPCR is FPCR & f12=1 { *movemptr = FPCR; movemptr = movemptr + 12; }
+fp2mC2: is f12=0 { }
+fp2mC1: fp2mC2" "FPSR is FPSR & f11=1 & fp2mC2 { *movemptr = FPSR; movemptr = movemptr + 12; }
+fp2mC1: fp2mC2 is f11=0 & fp2mC2 { }
+fp2mC0: { fp2mC1" "FPIAR } is FPIAR & f10=1 & fp2mC1 { *movemptr = FPIAR; movemptr = movemptr + 12; }
+fp2mC0: { fp2mC1 } is f10=0 & fp2mC1 { }
+
+:fmovem.l fp2mC0, e2l is op=15 & $(FP_COP) & $(MEM_ALTER_ADDR_MODES) & op68=0; f1315=5 & f0009=0 & fp2mC0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { movemptr = e2l; build fp2mC0; }
+:fmovem.l e2l, m2fpC0 is op=15 & $(FP_COP) & $(MEM_ALTER_ADDR_MODES) & op68=0; f1315=4 & f0009=0 & m2fpC0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { movemptr = e2l; build m2fpC0; }
+
+:fmul.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x23; e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f* float2float(e2l); }
+:fmul.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x23; e2x
+ [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f* float2float(e2x); }
+:fmul.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x23; e2d
+ [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f* float2float(e2d); }
+:fmul fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x23
+ {fdst = fdst f* fsrc; }
+@ifdef MC68040
+
+fmulrnd: "s" is fopmode=0x63 {}
+fmulrnd: "d" is fopmode=0x67 {}
+
+:f^fmulrnd^"mul."^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fmulrnd & (fopmode=0x63 | fopmode=0x67); e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f* float2float(e2l); }
+:f^fmulrnd^"mul."^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fmulrnd & (fopmode=0x63 | fopmode=0x67); e2x
+ [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f* float2float(e2x); }
+:f^fmulrnd^"mul."^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fmulrnd & (fopmode=0x63 | fopmode=0x67); e2d
+ [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f* float2float(e2d); }
+:f^fmulrnd^"mul" fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fmulrnd & (fopmode=0x63 | fopmode=0x67)
+ {fdst = fdst f* fsrc; }
+@endif # MC68040
+
+:fneg.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x1a; e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = -1; fdst = int2float(tmp) f* float2float(e2l); }
+:fneg.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x1a; e2x
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = -1; fdst = int2float(tmp) f* float2float(e2x); }
+:fneg.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x1a; e2d
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = -1; fdst = int2float(tmp) f* float2float(e2d); }
+:fneg fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1a
+ { tmp:12 = -1; fdst = int2float(tmp) f* fsrc; }
+@ifdef MC68040
+
+fnegrnd: "s" is fopmode=0x5a {}
+fnegrnd: "d" is fopmode=0x5e {}
+
+:f^fnegrnd^"neg."^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fnegrnd & (fopmode=0x5a | fopmode=0x5e); e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = -1; fdst = int2float(tmp) f* float2float(e2l); }
+:f^fnegrnd^"neg."^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fnegrnd & (fopmode=0x5a | fopmode=0x5e); e2x
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = -1; fdst = int2float(tmp) f* float2float(e2x); }
+:f^fnegrnd^"neg."^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fnegrnd & (fopmode=0x5a | fopmode=0x5e); e2d
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = -1; fdst = int2float(tmp) f* float2float(e2d); }
+:f^fnegrnd^"neg" fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fnegrnd & (fopmode=0x5a | fopmode=0x5e)
+ { tmp:12 = -1; fdst = int2float(tmp) f* fsrc; }
+@endif # MC68040
+
+:fnop is fop=15 & $(FP_FCOP) & f0008=0x080; fword=0 { }
+
+:frem.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x25; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:frem.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x25; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:frem.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x25; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:frem fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x25 unimpl
+
+:frestore eal is (op=15 & $(FP_COP) & op68=5 & $(POSTINC_CTL_ADDR_MODES))... & eal { restoreFPUStateFrame(eal); }
+
+:fsave eal is (op=15 & $(FP_COP) & op68=4 & $(PREDEC_CTL_ADDR_MODES))... & eal { saveFPUStateFrame(eal); }
+
+:fscale.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x26; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fscale.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x26; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fscale.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x26; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fscale fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x26 unimpl
+
+# Need to set the destination to all 1s if the condition is true, else set to 0
+#
+:fs^fcc e2b is op=15 & $(FP_COP) & op68=1 & $(DAT_ALTER_ADDR_MODES); f0615=0 & fcc; e2b
+ [ savmod2=savmod1; regtsan=regtfan; ]
+ { e2b = fcc * 0xff; }
+
+:fsgldiv.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x24; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fsgldiv.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x24; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fsgldiv.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x24; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fsgldiv fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x24 unimpl
+
+:fsglmul.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fprec & (ffmt=0 | ffmt=4 | ffmt=6) & fopmode=0x27; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+
+# Floating point single precision multiply, source is a 32-bit float, destination is an 80-bit floating point register
+# TODO: set condition flags
+:fsglmul.s e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & ffmt=1 & fopmode=0x27; e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] {
+ tmp:12 = float2float(e2l);
+ fdst = tmp f* fdst;
+}
+
+:fsglmul.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x27; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fsglmul.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x27; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:fsglmul fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x27 unimpl
+
+:fsin.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x0e; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = sin(tmp); }
+:fsin.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x0e; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = sin(tmp); }
+:fsin.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x0e; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = sin(tmp); }
+:fsin fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x0e { tmp:12 = float2float(fsrc); fdst = sin(tmp); }
+
+:fsincos.^fprec e2l, fdcos, fdsin is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdcos & fdsin & $(FPREC_BWLS) & f0306=6; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdsin = sin(tmp); fdcos = cos(tmp); }
+:fsincos.^fprec e2x, fdcos, fdsin is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdcos & fdsin & $(FPREC_XP) & f0306=6; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdsin = sin(tmp); fdcos = cos(tmp); }
+:fsincos.^fprec e2d, fdcos, fdsin is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdcos & fdsin & $(FPREC_D) & f0306=6; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdsin = sin(tmp); fdcos = cos(tmp); }
+:fsincos.x fsrc, fdcos, fdsin is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdcos & fdsin & f0306=6 { tmp:12 = float2float(fsrc); fdsin = sin(tmp); fdcos = cos(tmp); }
+
+:fsinh.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x02; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = sinh(tmp); }
+:fsinh.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x02; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = sinh(tmp); }
+:fsinh.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x02; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = sinh(tmp); }
+:fsinh fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x02 { tmp:12 = float2float(fsrc); fdst = sinh(tmp); }
+
+:fsqrt.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x04; e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = sqrt(tmp); }
+:fsqrt.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x04; e2x
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = sqrt(tmp); }
+:fsqrt.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x04; e2d
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = sqrt(tmp); }
+:fsqrt.x fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x04
+ { tmp:12 = float2float(fsrc); fdst = sqrt(tmp); }
+@ifdef MC68040
+
+fsqrtrnd: "s" is fopmode=0x41 {}
+fsqrtrnd: "d" is fopmode=0x45 {}
+
+:f^fsqrtrnd^"sqrt."^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fsqrtrnd & (fopmode=0x41 | fopmode=0x45); e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = sqrt(tmp); }
+:f^fsqrtrnd^"sqrt."^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fsqrtrnd & (fopmode=0x41 | fopmode=0x45); e2x
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = sqrt(tmp); }
+:f^fsqrtrnd^"sqrt."^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fsqrtrnd & (fopmode=0x41 | fopmode=0x45); e2d
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = sqrt(tmp); }
+:f^fsqrtrnd^"sqrt.x" fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fsqrtrnd & (fopmode=0x41 | fopmode=0x45)
+ { tmp:12 = float2float(fsrc); fdst = sqrt(tmp); }
+@endif # MC68040
+
+:fsub.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x28; e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = fdst f- tmp; }
+:fsub.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x28; e2x
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = fdst f- tmp; }
+:fsub.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x28; e2d
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = fdst f- tmp; }
+:fsub.x fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x28 { tmp:12 = float2float(fsrc); fdst = fdst f- tmp; }
+
+@ifdef MC68040
+
+fsubrnd: "s" is fopmode=0x68 {}
+fsubrnd: "d" is fopmode=0x6c {}
+
+:f^fsubrnd^"sub."^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fsubrnd & $(FPREC_BWLS) & (fopmode=0x68 | fopmode=0x6c); e2l
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = fdst f- tmp; }
+:f^fsubrnd^"sub."^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fsubrnd & $(FPREC_XP) & (fopmode=0x68 | fopmode=0x6c); e2x
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = fdst f- tmp; }
+:f^fsubrnd^"sub."^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & fsubrnd & $(FPREC_D) & (fopmode=0x68 | fopmode=0x6c); e2d
+ [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = fdst f- tmp; }
+:f^fsubrnd^"sub.x" fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fsubrnd & (fopmode=0x68 | fopmode=0x6c) { tmp:12 = float2float(fsrc); fdst = fdst f- tmp; }
+
+@endif # MC68040
+
+:ftan.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x0f; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = tan(tmp); }
+:ftan.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x0f; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = tan(tmp); }
+:ftan.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x0f; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = tan(tmp); }
+:ftan.x fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x0f { tmp:12 = float2float(fsrc); fdst = tan(tmp); }
+
+:ftanh.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x09; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); fdst = tanh(tmp); }
+:ftanh.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x09; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); fdst = tanh(tmp); }
+:ftanh.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x09; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); fdst = tanh(tmp); }
+:ftanh.x fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x09 { tmp:12 = float2float(fsrc); fdst = tanh(tmp); }
+
+:ftentox.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x12; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:ftentox.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x12; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:ftentox.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x12; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:ftentox.x fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x12 unimpl
+
+:ftrap^fcc const16 is fop=15 & $(FP_FCOP) & f0308=0xf & fmode=2; f0615=0 & fcc; const16 { if (!fcc) goto inst_next; ftrap(const16); }
+:ftrap^fcc const32 is fop=15 & $(FP_FCOP) & f0308=0xf & fmode=3; f0615=0 & fcc; const32 { if (!fcc) goto inst_next; ftrap(const32); }
+:ftrap^fcc is fop=15 & $(FP_FCOP) & f0308=0xf & fmode=4; f0615=0 & fcc { if (!fcc) goto inst_next; ftrap(); }
+
+:ftst.^fprec e2l is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x3a; e2l [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2l); resflags_fp(tmp); }
+:ftst.^fprec e2x is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x3a; e2x [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2x); resflags_fp(tmp); }
+:ftst.^fprec e2d is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x3a; e2d [ savmod2=savmod1; regtsan=regtfan; ] { tmp:12 = float2float(e2d); resflags_fp(tmp); }
+:ftst.x fsrc is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x3a { tmp:12 = float2float(fsrc); resflags_fp(tmp); }
+
+:ftwotox.^fprec e2l, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_BWLS) & fopmode=0x11; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:ftwotox.^fprec e2x, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_XP) & fopmode=0x11; e2x [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:ftwotox.^fprec e2d, fdst is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1515=0 & f1313=0 & fdst & $(FPREC_D) & fopmode=0x11; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl
+:ftwotox.x fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x11 unimpl
+
+
+@ifdef COLDFIRE
+
+macregy: reg03ywl is reg03ywl; IS=0 { export reg03ywl; }
+macregy: reg03ywu is reg03ywu; IS=1 { export reg03ywu; }
+macregx: reg9dnl is reg9dnl & op6=0; bs=0 { export reg9dnl; }
+macregx: reg9dnu is reg9dnu & op6=0; bs=1 { export reg9dnu; }
+macregx: reg9anl is reg9anl & op6=1; bs=0 { export reg9anl; }
+macregx: reg9anu is reg9anu & op6=1; bs=1 { export reg9anu; }
+macrw: reg9dn is reg9dn & op6=0 { export reg9dn; }
+macrw: reg9an is reg9an & op6=1 { export reg9an; }
+
+macregy_e: ereg03y is ereg03y { export ereg03y; }
+macregyl: reg03yl is reg03yl & IS=0 { export reg03yl; }
+macregyl: reg03yu is reg03yu & IS=1 { export reg03yu; }
+macregxl: reg12xwl is reg12xwl & bs=0 { export reg12xwl; }
+macregxl: reg12xwu is reg12xwu & bs=1 { export reg12xwu; }
+
+
+scalefactor: "" is sfact=0 { export 0:1; }
+scalefactor: "<<1" is sfact=1 { export 1:1; }
+scalefactor: ">>1" is sfact=3 { export 2:1; }
+
+accreg: ACC0 is ACC0 & acclsb=0 ; accmsb=0 { export ACC0; }
+accreg: ACC1 is ACC1 & acclsb=1 ; accmsb=0 { export ACC1; }
+accreg: ACC2 is ACC2 & acclsb=0 ; accmsb=1 { export ACC2; }
+accreg: ACC3 is ACC3 & acclsb=1 ; accmsb=1 { export ACC3; }
+
+define pcodeop findFirstOne;
+
+:ff1 regdn is reg315=0x98 & regdn {
+ regdn = findFirstOne(regdn);
+ VF = 0;
+ CF = 0;
+ resflags(regdn);
+}
+
+# MAC effective address table
+ # size=long
+m_eal: (regan) is mode=2 & regan { export *:4 regan; }
+m_eal: (regan)+ is mode=3 & regan { local tmp = regan; regan = regan + 4; export *:4 tmp; }
+m_eal: -(regan) is mode=4 & regan { regan = regan - 4; export *:4 regan; }
+m_eal: (d16,regan) is mode=5 & regan; d16 { local tmp = regan + d16; export *:4 tmp; }
+
+:maaac.l reg03y, reg9dn^scalefactor, accreg, accw is (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=0 & wl=1 & scalefactor & accw & odsize=1) ... & accreg ...
+{
+ local tmp = reg03y * reg9dn;
+ tmp = tmp << (scalefactor == 1);
+ tmp = tmp >> (scalefactor == 2);
+ accreg = accreg + tmp;
+ accw = accw + tmp;
+}
+:maaac.l reg03y, reg9an^scalefactor, accreg, accw is (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=0 & wl=1 & scalefactor & accw & odsize=1) ... & accreg ...
+{
+ local tmp = reg03y * reg9an;
+ tmp = tmp << (scalefactor == 1);
+ tmp = tmp >> (scalefactor == 2);
+ accreg = accreg + tmp;
+ accw = accw + tmp;
+}
+
+:maaac.w macregy, macregx^scalefactor, accreg, accw is (op=10 & op8=0 & op45=0 ; fbit=0 & wl=0 & scalefactor & accw & odsize=1) ... & macregy ... & macregx ... & accreg ...
+{
+ local tmp = macregy * macregx;
+ tmp = tmp << (scalefactor == 1);
+ tmp = tmp >> (scalefactor == 2);
+ accreg = accreg + sext(tmp);
+ accw = accw + sext(tmp);
+}
+
+:mac.l reg03y, reg9dn^scalefactor, accreg is (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=0 & wl=1 & scalefactor) ... & accreg ...
+{
+ local tmp = reg03y * reg9dn;
+ tmp = tmp << (scalefactor == 1);
+ tmp = tmp >> (scalefactor == 2);
+ accreg = accreg + tmp;
+}
+:mac.l reg03y, reg9an^scalefactor, accreg is (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=0 & wl=1 & scalefactor) ... & accreg ...
+{
+ local tmp = reg03y * reg9an;
+ tmp = tmp << (scalefactor == 1);
+ tmp = tmp >> (scalefactor == 2);
+ accreg = accreg + tmp;
+}
+
+:mac.w macregy, macregx^scalefactor, accreg is (op=10 & op8=0 & op45=0 ; fbit=0 & wl=0 & scalefactor) ... & macregy ... & macregx ... & accreg ...
+{
+ local tmp = macregy * macregx;
+ tmp = tmp << (scalefactor == 1);
+ tmp = tmp >> (scalefactor == 2);
+ accreg = accreg + sext(tmp);
+}
+
+#mac with load
+:mac.w macregyl, macregxl^scalefactor, m_eal, macrw, accreg is ((op=10 & macrw & op8=0 ; macregxl & fbit=0 & macregyl & wl=0 & scalefactor) ... & accreg ...) ... & m_eal
+{
+ local tmp = macregyl * macregxl;
+ tmp = tmp << (scalefactor == 1);
+ tmp = tmp >> (scalefactor == 2);
+ accreg = accreg + sext(tmp);
+ macrw = m_eal;
+}
+
+:mac.l macregy_e, reg12x^scalefactor, m_eal, macrw, accreg is ((op=10 & macrw & op6=0 & op8=0 ; reg12x & fbit=0 & wl=1 & scalefactor & macregy_e) ... & accreg ...) ... & m_eal
+{
+ local tmp = macregy_e * reg12x;
+ tmp = tmp << (scalefactor == 1);
+ tmp = tmp >> (scalefactor == 2);
+ accreg = accreg + tmp;
+ macrw = m_eal;
+}
+
+:masac.l reg03y, reg9dn^scalefactor, accreg, accw is (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=0 & wl=1 & scalefactor & accw & odsize=3) ... & accreg ...
+{
+ local tmp = reg03y * reg9dn;
+ tmp = tmp << (scalefactor == 1);
+ tmp = tmp >> (scalefactor == 2);
+ accreg = accreg + tmp;
+ accw = accw - tmp;
+}
+:masac.l reg03y, reg9an^scalefactor, accreg, accw is (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=0 & wl=1 & scalefactor & accw & odsize=3) ... & accreg ...
+{
+ local tmp = reg03y * reg9an;
+ tmp = tmp << (scalefactor == 1);
+ tmp = tmp >> (scalefactor == 2);
+ accreg = accreg + tmp;
+ accw = accw - tmp;
+}
+
+:masac.w macregy, macregx^scalefactor, accreg, accw is (op=10 & op8=0 & op45=0 ; fbit=0 & wl=0 & scalefactor & accw & odsize=3) ... & macregy ... & macregx ... & accreg ...
+{
+ local tmp = macregy * macregx;
+ tmp = tmp << (scalefactor == 1);
+ tmp = tmp >> (scalefactor == 2);
+ accreg = accreg + sext(tmp);
+ accw = accw - sext(tmp);
+}
+
+moveaccreg: ACC0 is ACC0 & op0910=0 { export ACC0; }
+moveaccreg: ACC1 is ACC1 & op0910=1 { export ACC1; }
+moveaccreg: ACC2 is ACC2 & op0910=2 { export ACC2; }
+moveaccreg: ACC3 is ACC3 & op0910=3 { export ACC3; }
+
+moveaccreg2: ACC0 is ACC0 & op01=0 { export ACC0; }
+moveaccreg2: ACC1 is ACC1 & op01=1 { export ACC1; }
+moveaccreg2: ACC2 is ACC2 & op01=2 { export ACC2; }
+moveaccreg2: ACC3 is ACC3 & op01=3 { export ACC3; }
+
+:move.l moveaccreg, reg03y is op=0b1010 & op11=0 & moveaccreg & op8=1 & op47=0b1000 & reg03y { reg03y = moveaccreg; }
+
+:move.l ACCext01, eal is (op=0b1010 & op811=0b1011 & op67=0 & ACCext01 & (mode=0 | mode=1 | mode=7)) ... & eal { ACCext01 = eal; }
+:move.l ACCext23, eal is (op=0b1010 & op811=0b1111 & op67=0 & ACCext23 & (mode=0 | mode=1 | mode=7)) ... & eal { ACCext23 = eal; }
+
+:move.l moveaccreg, eal is (op=0b1010 & op11=0 & moveaccreg & op8=1 & op67=0 & (mode=0 | mode=1 | mode=7)) ... & eal { moveaccreg = eal; }
+
+:move.l moveaccreg, moveaccreg2 is op=0b1010 & op11=0 & moveaccreg & op8=1 & op47=1 & moveaccreg2 { moveaccreg2 = moveaccreg; }
+
+:move.l MACSR, reg03y is op=0b1010 & op811=0b1001 & op47=0b1000 & MACSR & reg03y { reg03y = MACSR; }
+:move.l ACCext01, reg03y is op=0b1010 & op811=0b1011 & op47=0b1000 & ACCext01 & reg03y { reg03y = ACCext01; }
+:move.l ACCext23, reg03y is op=0b1010 & op811=0b1111 & op47=0b1000 & ACCext23 & reg03y { reg03y = ACCext23; }
+
+:move.l MASK, reg03y is op=10 & op811=13 & op47=8 & MASK & reg03y { reg03y = MASK; }
+
+:move.l MACSR, "CCR" is op=10 & op811=9 & op47=12 & MACSR { unpackflags(MACSR); }
+
+:move.l eal, MACSR is (op=10 & op611=36 & MACSR & (mode=0 | mode=1 | mode=7)) ... & eal { MACSR = eal; }
+
+:move.l eal, MASK is (op=10 & op611=52 & MASK & (mode=0 | mode=1 | mode=7)) ... & eal { MASK = eal; }
+
+
+:msaac.l reg03y, reg9dn^scalefactor, accreg, accw is (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor & accw & odsize=1) ... & accreg ...
+{
+ local tmp = reg03y * reg9dn;
+ tmp = tmp << (scalefactor == 1);
+ tmp = tmp >> (scalefactor == 2);
+ accreg = accreg - tmp;
+ accw = accw + tmp;
+}
+:msaac.l reg03y, reg9an^scalefactor, accreg, accw is (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor & accw & odsize=1) ... & accreg ...
+{
+ local tmp = reg03y * reg9an;
+ tmp = tmp << (scalefactor == 1);
+ tmp = tmp >> (scalefactor == 2);
+ accreg = accreg - tmp;
+ accw = accw + tmp;
+}
+
+:msaac.w macregy, macregx^scalefactor, accreg, accw is (op=10 & op8=0 & op45=0 ; fbit=1 & wl=0 & scalefactor & accw & odsize=1) ... & macregy ... & macregx ... & accreg ...
+{
+ local tmp = macregy * macregx;
+ tmp = tmp << (scalefactor == 1);
+ tmp = tmp >> (scalefactor == 2);
+ accreg = accreg - sext(tmp);
+ accw = accw + sext(tmp);
+}
+
+:msac.l reg03y, reg9dn^scalefactor, accreg is (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor) ... & accreg ...
+{
+ local tmp = reg03y * reg9dn;
+ tmp = tmp << (scalefactor == 1);
+ tmp = tmp >> (scalefactor == 2);
+ accreg = accreg - tmp;
+}
+:msac.l reg03y, reg9an^scalefactor, accreg is (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor) ... & accreg ...
+{
+ local tmp = reg03y * reg9an;
+ tmp = tmp << (scalefactor == 1);
+ tmp = tmp >> (scalefactor == 2);
+ accreg = accreg - tmp;
+}
+
+:msac.w macregy, macregx^scalefactor, accreg is (op=10 & op6=0 & op8=0 & op45=0 ; fbit=1 & wl=0 & scalefactor) ... & macregy ... & macregx ... & accreg ...
+{
+ local tmp = macregy * macregx;
+ tmp = tmp << (scalefactor == 1);
+ tmp = tmp >> (scalefactor == 2);
+ accreg = accreg - sext(tmp);
+}
+
+
+# MSAC with load
+
+:msac.w macregyl, macregxl^scalefactor, m_eal, macrw, accreg is ((op=10 & macrw & op8=0 ; macregxl & fbit=1 & macregyl & wl=0 & scalefactor) ... & accreg ...) ... & m_eal
+{
+ local tmp = macregyl * macregxl;
+ tmp = tmp << (scalefactor == 1);
+ tmp = tmp >> (scalefactor == 2);
+ accreg = accreg - sext(tmp);
+ macrw = m_eal;
+}
+
+:msac.l macregy_e, reg12x^scalefactor, m_eal, macrw, accreg is ((op=10 & macrw & op8=0 ; reg12x & fbit=1 & wl=1 & scalefactor & macregy_e) ... & accreg ...) ... & m_eal
+{
+ local tmp = macregy_e * reg12x;
+ tmp = tmp << (scalefactor == 1);
+ tmp = tmp >> (scalefactor == 2);
+ accreg = accreg - tmp;
+ macrw = m_eal;
+}
+
+:msaac.l reg03y, reg9dn^scalefactor, accreg, accw is (op=10 & reg9dn & reg03y & op6=0 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor & accw & odsize=3) ... & accreg ...
+{
+ local tmp = reg03y * reg9dn;
+ tmp = tmp << (scalefactor == 1);
+ tmp = tmp >> (scalefactor == 2);
+ accreg = accreg - tmp;
+ accw = accw - tmp;
+}
+:mssac.l reg03y, reg9an^scalefactor, accreg, accw is (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor & accw & odsize=3) ... & accreg ...
+{
+ local tmp = reg03y * reg9an;
+ tmp = tmp << (scalefactor == 1);
+ tmp = tmp >> (scalefactor == 2);
+ accreg = accreg - tmp;
+ accw = accw - tmp;
+}
+
+:mssac.w macregy, macregx^scalefactor, accreg, accw is (op=10 & op8=0 & op45=0 ; fbit=1 & wl=0 & scalefactor & accw & odsize=3) ... & macregy ... & macregx ... & accreg ...
+{
+ local tmp = macregy * macregx;
+ tmp = tmp << (scalefactor == 1);
+ tmp = tmp >> (scalefactor == 2);
+ accreg = accreg - sext(tmp);
+ accw = accw - sext(tmp);
+}
+
+@endif
+
+} # end with : extGUARD=1
diff --git a/python/icicle/Ghidra/Processors/68000/data/languages/68020.slaspec b/python/icicle/Ghidra/Processors/68000/data/languages/68020.slaspec
new file mode 100644
index 0000000..7148419
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/68000/data/languages/68020.slaspec
@@ -0,0 +1 @@
+@include "68000.sinc"
diff --git a/python/icicle/Ghidra/Processors/68000/data/languages/68030.slaspec b/python/icicle/Ghidra/Processors/68000/data/languages/68030.slaspec
new file mode 100644
index 0000000..4c62eb2
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/68000/data/languages/68030.slaspec
@@ -0,0 +1,2 @@
+@define MC68030 ""
+@include "68000.sinc"
diff --git a/python/icicle/Ghidra/Processors/68000/data/languages/68040.slaspec b/python/icicle/Ghidra/Processors/68000/data/languages/68040.slaspec
new file mode 100644
index 0000000..94e2ecf
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/68000/data/languages/68040.slaspec
@@ -0,0 +1,2 @@
+@define MC68040 ""
+@include "68000.sinc"
diff --git a/python/icicle/Ghidra/Processors/68000/data/languages/coldfire.slaspec b/python/icicle/Ghidra/Processors/68000/data/languages/coldfire.slaspec
new file mode 100644
index 0000000..d99ace5
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/68000/data/languages/coldfire.slaspec
@@ -0,0 +1,6 @@
+# Motorola's Coldfire processor
+
+@define COLDFIRE ""
+@define MC68040 ""
+
+@include "68000.sinc"
diff --git a/python/icicle/Ghidra/Processors/8048/data/languages/8048.cspec b/python/icicle/Ghidra/Processors/8048/data/languages/8048.cspec
new file mode 100644
index 0000000..35e8c0a
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/8048/data/languages/8048.cspec
@@ -0,0 +1,31 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/python/icicle/Ghidra/Processors/8048/data/languages/8048.ldefs b/python/icicle/Ghidra/Processors/8048/data/languages/8048.ldefs
new file mode 100644
index 0000000..6533853
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/8048/data/languages/8048.ldefs
@@ -0,0 +1,18 @@
+
+
+
+
+
+ 8048 Microcontroller Family
+
+
+
+
diff --git a/python/icicle/Ghidra/Processors/8048/data/languages/8048.pspec b/python/icicle/Ghidra/Processors/8048/data/languages/8048.pspec
new file mode 100644
index 0000000..edaef33
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/8048/data/languages/8048.pspec
@@ -0,0 +1,49 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/python/icicle/Ghidra/Processors/8048/data/languages/8048.slaspec b/python/icicle/Ghidra/Processors/8048/data/languages/8048.slaspec
new file mode 100644
index 0000000..464bb2c
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/8048/data/languages/8048.slaspec
@@ -0,0 +1,539 @@
+# sleigh specification file for Intel 8048
+
+
+# Do not take BS into account when decompiling
+@define SINGLE_REGISTER_BANK ""
+
+# Treat R0-R7 as not memory mapped (implies SINGLE_REGISTER_BANK)
+@define INTERNAL_REGISTERS ""
+
+
+@ifdef INTERNAL_REGISTERS
+@define SINGLE_REGISTER_BANK ""
+@endif
+
+
+define endian=little;
+define alignment=1;
+
+define space CODE type=ram_space size=2 default;
+define space INTMEM type=ram_space size=1;
+define space EXTMEM type=ram_space size=1;
+define space PORT type=ram_space size=1;
+
+define space register type=register_space size=1;
+
+define register offset=0x00 size=1 [ A SP ];
+@ifdef INTERNAL_REGISTERS
+define register offset=0x10 size=1 [ R0 R1 R2 R3 R4 R5 R6 R7 ];
+@endif
+define register offset=0x20 size=2 [ PC ];
+define register offset=0x30 size=1 [ C AC F0 F1 BS DFB ]; # single bit
+
+
+################################################################
+# Tokens
+################################################################
+
+define token opbyte (8)
+ opfull = (0,7)
+ oplo = (0,3)
+ ophi = (4,7)
+ rn = (0,2) dec
+ rnfill = (3,3)
+ ri = (0,0) dec
+ rifill = (1,3)
+ opaddr = (5,7)
+ addrfill = (4,4)
+ pp = (0,1) dec
+ xpp = (0,1) dec
+ ppfill = (2,3)
+ abit = (5,7) dec
+ abfill = (4,4)
+ dfb = (4,4)
+ bs = (4,4)
+;
+
+define token aopword (16)
+ aoplo = (0,3)
+ aaddrfill = (4,4)
+ aopaddr = (5,7)
+ adata = (8,15)
+;
+
+define token ImmedByte (8) data=(0,7);
+define token AddrOne (8) addr8=(0,7);
+
+@ifdef INTERNAL_REGISTERS
+attach variables rn [ R0 R1 R2 R3 R4 R5 R6 R7 ];
+attach variables ri [ R0 R1 ];
+@else
+attach names rn [ R0 R1 R2 R3 R4 R5 R6 R7 ];
+attach names ri [ R0 R1 ];
+@endif
+attach names dfb [ MB0 MB1 ];
+attach names bs [ RB0 RB1 ];
+attach names pp [ BUS P1 P2 _ ];
+attach names xpp [ P4 P5 P6 P7 ];
+
+
+################################################################
+# Pseudo Instructions
+################################################################
+
+define pcodeop nop;
+define pcodeop enableExtInt;
+define pcodeop enableTCntInt;
+define pcodeop enableClockOutput;
+define pcodeop disableExtInt;
+define pcodeop disableTCntInt;
+define pcodeop startTimer;
+define pcodeop startEventCounter;
+define pcodeop stopTimerAndEventCounter;
+define pcodeop setTmr;
+define pcodeop getTmr;
+define pcodeop getT0;
+define pcodeop getT1;
+define pcodeop getTF;
+define pcodeop getExtInt;
+define pcodeop readPort;
+define pcodeop writePort;
+define pcodeop setBank;
+
+
+################################################################
+# Macros
+################################################################
+
+macro getPSW(reg) {
+ local tmp:1 = 0;
+ tmp[7,1] = C;
+ tmp[6,1] = AC;
+ tmp[5,1] = F0;
+ tmp[4,1] = BS;
+ tmp[3,1] = 1;
+ tmp[0,3] = (SP>>1)&7;
+ reg = tmp;
+}
+
+macro setPSW(reg) {
+ local tmp:1 = reg;
+ C = tmp[7,1];
+ AC = tmp[6,1];
+ F0 = tmp[5,1];
+ BS = tmp[4,1];
+ SP = 2*tmp[0,3] + 8;
+}
+
+macro savePSWtoPC(pc) {
+ pc[15,1] = C;
+ pc[14,1] = AC;
+ pc[13,1] = F0;
+ pc[12,1] = BS;
+}
+
+macro restorePSWfromPC(pc) {
+ C = pc[15,1];
+ AC = pc[14,1];
+ F0 = pc[13,1];
+ BS = pc[12,1];
+}
+
+macro push(v) {
+ *[INTMEM]:2 SP = v;
+ SP = SP + 2;
+}
+
+macro pop(v) {
+ SP = SP - 2;
+ v = *[INTMEM]:2 SP;
+}
+
+macro popPC(pc) {
+ pop(pc);
+ pc = pc & 0xfff;
+}
+
+macro popPCandPSW(pc) {
+ pop(pc);
+ restorePSWfromPC(pc);
+ pc = pc & 0xfff;
+}
+
+macro funcall(target) {
+ ret:2 = inst_next;
+ savePSWtoPC(ret);
+ push(ret);
+ call target;
+}
+
+macro add(dest, op1, op2, cy_in) {
+ local result:1 = op1 + op2 + cy_in;
+ local half_result:1 = (op1 & 0xf) + (op2 & 0xf) + cy_in;
+ C = carry(op1, op2) || carry(op1+op2, cy_in);
+ AC = (half_result > 0xf);
+ dest = result;
+}
+
+macro da(reg) {
+ local tmp:1 = reg;
+ local low:1 = 6*(AC || (tmp&0xf) > 9);
+ local cy1:1 = C || carry(tmp, low);
+ tmp = tmp + low;
+ local high:1 = 0x60*(cy1 || tmp > 0x99);
+ C = C || carry(tmp, high);
+ tmp = tmp + high;
+ reg = tmp;
+}
+
+macro rotc(cy, acc) {
+ local tmp:1 = cy;
+ A = acc;
+ C = tmp;
+}
+
+macro xch(node1, node2) {
+ local tmp:1 = node1;
+ node1 = node2;
+ node2 = tmp;
+}
+
+@ifdef SINGLE_REGISTER_BANK
+macro regbank(r) { r = r; }
+macro setbank(bs) {
+ BS = bs;
+ local tmp:1 = bs;
+ setBank(tmp);
+}
+@else
+macro regbank(r) {
+ r = r + BS*0x18;
+}
+macro setbank(bs) {
+ BS = bs;
+}
+@endif
+
+
+################################################################
+
+Psw: "PSW" is epsilon { }
+ExtInt: "I" is epsilon { }
+TCntInt: "TCNTI" is epsilon { }
+Clk: "CLK" is epsilon { }
+Tmr: "T" is epsilon { }
+Cnt: "CNT" is epsilon { }
+TmrCnt: "TCNT" is epsilon { }
+
+@ifdef INTERNAL_REGISTERS
+Rn: rn is rn & rnfill=1 {
+ export rn;
+}
+Rind: @ri is ri & rifill=0 {
+ export ri;
+}
+@else
+Rn: rn is rn & rnfill=1 {
+ local ptr:1 = rn; regbank(ptr); export *[INTMEM]:1 ptr;
+}
+Rind: @ri is ri & rifill=0 {
+ local ptr:1 = ri; regbank(ptr); export *[INTMEM]:1 ptr;
+}
+@endif
+Ri: Rind is Rind {
+ export *[INTMEM]:1 Rind;
+}
+RiX: Rind is Rind {
+ export *[EXTMEM]:1 Rind;
+}
+PData: @A is A {
+ local addr:2 = inst_next; addr[0,7] = A; export *[CODE]:1 addr;
+}
+P3Data: @A is A {
+ local addr:2 = 0x300; addr[0,7] = A; export *[CODE]:1 addr;
+}
+AddrInd: PData is PData {
+ local addr:2 = inst_next; addr[0,7] = PData; export *[CODE]:1 addr;
+}
+Ab: abit is abit {
+ local bit:1 = (A>>abit)&1; export bit;
+}
+Data: "#"^data is data {
+ export *[const]:1 data;
+}
+Imm: Data is oplo=3; Data {
+ export Data;
+}
+Addr8: addr is addr8 [ addr = (inst_next $and 0xf00)+addr8; ] {
+ export *[CODE]:1 addr;
+}
+Addr12: addr is aopaddr & adata [ addr = (DFB*2048)+(aopaddr*256)+adata; ] {
+ export *[CODE]:1 addr;
+}
+Bus: "BUS" is epsilon {
+ local tmp:1 = 0; export *[PORT]:1 tmp;
+}
+Pp: pp is pp & ppfill=2 {
+ export *[PORT]:1 pp;
+}
+Xpp: xpp is xpp & ppfill=3 {
+ local tmp:1 = xpp+4; export *[PORT]:1 tmp;
+}
+
+Cc: "C" is ophi=15 {
+ export C;
+}
+Cc: "F0" is ophi=11 {
+ export F0;
+}
+Cc: "F1" is ophi=7 {
+ export F1;
+}
+Cc: "NC" is ophi=14 {
+ tmp:1 = !C; export tmp;
+}
+Cc: "NI" is ophi=8 {
+ tmp:1 = getExtInt(); tmp = !tmp; export tmp;
+}
+Cc: "NT0" is ophi=2 {
+ tmp:1 = getT0(); tmp = !tmp; export tmp;
+}
+Cc: "NT1" is ophi=4 {
+ tmp:1 = getT1(); tmp = !tmp; export tmp;
+}
+Cc: "NZ" is ophi=9 {
+ tmp:1 = A!=0; export tmp;
+}
+Cc: "TF" is ophi=1 {
+ tmp:1 = getTF(); export tmp;
+}
+Cc: "T0" is ophi=3 {
+ tmp:1 = getT0(); export tmp;
+}
+Cc: "T1" is ophi=5 {
+ tmp:1 = getT1(); export tmp;
+}
+Cc: "Z" is ophi=12 {
+ tmp:1 = A==0; export tmp;
+}
+
+
+# Conventience tables for opcodes taking both Rn and Ri (and Imm)
+Rni: Rn is Rn {
+ export Rn;
+}
+Rni: Ri is Ri {
+ export Ri;
+}
+RniI: Rni is Rni {
+ export Rni;
+}
+RniI: Imm is Imm {
+ export Imm;
+}
+
+
+:ADD A,Rni is ophi=6 & (rnfill=1 | rifill=0) & A & Rni {
+ add(A,A,Rni,0);
+}
+:ADD A,Imm is (ophi=0 & A)... & Imm {
+ add(A,A,Imm,0);
+}
+:ADDC A,Rni is ophi=7 & A & (rnfill=1 | rifill=0) & Rni {
+ add(A,A,Rni,C);
+}
+:ADDC A,Imm is (ophi=1 & A)... & Imm {
+ add(A,A,Imm,C);
+}
+:ANL A,RniI is (ophi=5 & (rnfill=1 | rifill=0 | oplo=3) & A)... & RniI {
+ A = A & RniI;
+}
+:ANL Pp,Data is ophi=9 & ppfill=2 & Pp; Data {
+ Pp = Pp & Data;
+}
+:ANLD Xpp,A is ophi=9 & ppfill=3 & Xpp & A {
+ Xpp = Xpp & (A & 0xf);
+}
+:CALL Addr12 is aopaddr & aaddrfill=1 & aoplo=4 & Addr12 {
+ funcall(Addr12);
+}
+:CLR A is ophi=2 & oplo=7 & A {
+ A = 0;
+}
+:CLR C is ophi=9 & oplo=7 & C {
+ C = 0;
+}
+:CLR F0 is ophi=8 & oplo=5 & F0 {
+ F0 = 0;
+}
+:CLR F1 is ophi=10 & oplo=5 & F1 {
+ F1 = 0;
+}
+:CPL A is ophi=3 & oplo=7 & A {
+ A = ~A;
+}
+:CPL C is ophi=10 & oplo=7 & C {
+ C = !C;
+}
+:CPL F0 is ophi=9 & oplo=5 & F0 {
+ F0 = !F0;
+}
+:CPL F1 is ophi=11 & oplo=5 & F1 {
+ F1 = !F1;
+}
+:DA A is ophi=5 & oplo=7 & A {
+ da(A);
+}
+:DEC A is ophi=0 & oplo=7 & A {
+ A = A - 1;
+}
+:DEC Rn is ophi=12 & Rn {
+ Rn = Rn - 1;
+}
+:DIS ExtInt is ophi=1 & oplo=5 & ExtInt {
+ disableExtInt();
+}
+:DIS TCntInt is ophi=3 & oplo=5 & TCntInt {
+ disableTCntInt();
+}
+:DJNZ Rn,Addr8 is ophi=14 & Rn; Addr8 {
+ Rn = Rn - 1; if(Rn != 0) goto Addr8;
+}
+:EN ExtInt is ophi=0 & oplo=5 & ExtInt {
+ enableExtInt();
+}
+:EN TCntInt is ophi=2 & oplo=5 & TCntInt {
+ enableTCntInt();
+}
+:ENT0 Clk is ophi=7 & oplo=5 & Clk {
+ enableClockOutput();
+}
+:IN A,Pp is ophi=0 & pp!=0 & A & Pp {
+ A = Pp;
+}
+:INC A is ophi=1 & oplo=7 & A {
+ A = A + 1;
+}
+:INC Rni is ophi=1 & (rnfill=1 | rifill=0) & Rni {
+ Rni = Rni + 1;
+}
+:INS A,Bus is ophi=0 & oplo=8 & A & Bus {
+ A = Bus;
+}
+:JB^Ab Addr8 is oplo=2 & opaddr & abfill=1 & Ab; Addr8 {
+ if(Ab) goto Addr8;
+}
+:J^Cc Addr8 is ophi & oplo=6 & Cc; Addr8 {
+ if(Cc) goto Addr8;
+}
+:JMP Addr12 is aopaddr & aaddrfill=0 & aoplo=4 & Addr12 {
+ goto Addr12;
+}
+:JMPP AddrInd is ophi=11 & oplo=3 & AddrInd {
+ goto AddrInd;
+}
+:MOV A,Imm is (ophi=2 & A)... & Imm {
+ A = Imm;
+}
+:MOV A,Psw is ophi=12 & oplo=7 & A & Psw {
+ getPSW(A);
+}
+:MOV A,Rni is ophi=15 & A & (rnfill=1 | rifill=0) & Rni {
+ A = Rni;
+}
+:MOV A,Tmr is ophi=4 & oplo=2 & A & Tmr {
+ A = getTmr();
+}
+:MOV Psw,A is ophi=13 & oplo=7 & Psw & A {
+ setPSW(A);
+}
+:MOV Rni,A is ophi=10 & (rnfill=1 | rifill=0) & Rni & A {
+ Rni = A;
+}
+:MOV Rni,Data is ophi=11 & (rnfill=1 | rifill=0) & Rni; Data {
+ Rni = Data;
+}
+:MOV Tmr,A is ophi=6 & oplo=2 & Tmr & A {
+ setTmr(A);
+}
+:MOVD A,Xpp is ophi=0 & Xpp & A {
+ A = (Xpp & 0xf);
+}
+:MOVD Xpp,A is ophi=3 & Xpp & A {
+ Xpp = (A & 0xf);
+}
+:MOVP A,PData is ophi=10 & oplo=3 & A & PData {
+ A = PData;
+}
+:MOVP3 A,P3Data is ophi=14 & oplo=3 & A & P3Data {
+ A = P3Data;
+}
+:MOVX A,RiX is ophi=8 & A & RiX {
+ A = RiX;
+}
+:MOVX RiX,A is ophi=9 & RiX & A {
+ RiX = A;
+}
+:NOP is ophi=0 & oplo=0 {
+ nop();
+}
+:ORL A,RniI is (ophi=4 & (rnfill=1 | rifill=0 | oplo=3) & A)... & RniI {
+ A = A | RniI;
+}
+:ORL Pp,Data is ophi=8 & Pp; Data {
+ Pp = Pp | Data;
+}
+:ORLD Xpp,A is ophi=8 & Xpp & A {
+ Xpp = Xpp | (A & 0xf);
+}
+:OUTL Bus,A is ophi=0 & oplo=2 & Bus & A {
+ Bus = A;
+}
+:OUTL Pp,A is ophi=3 & pp!=0 & Pp & A {
+ Pp = A;
+}
+:RET is ophi=8 & oplo=3 {
+ pc:2 = 0; popPC(pc); return[pc];
+}
+:RETR is ophi=9 & oplo=3 {
+ pc:2 = 0; popPCandPSW(pc); return[pc];
+}
+:RL A is ophi=14 & oplo=7 & A {
+ A = (A<<1) | (A>>7);
+}
+:RLC A is ophi=15 & oplo=7 & A {
+ rotc((A&0x80)>>7, (A<<1)|C);
+}
+:RR A is ophi=7 & oplo=7 & A {
+ A = (A>>1) | (A<<7);
+}
+:RRC A is ophi=6 & oplo=7 & A {
+ rotc(A&1, (A>>1)|(C<<7));
+}
+:SEL dfb is (ophi=14 | ophi=15) & oplo=5 & dfb {
+ DFB = dfb;
+}
+:SEL bs is (ophi=12 | ophi=13) & oplo=5 & bs {
+ setbank(bs);
+}
+:STOP TmrCnt is ophi=6 & oplo=5 & TmrCnt {
+ stopTimerAndEventCounter();
+}
+:STRT Cnt is ophi=4 & oplo=5 & Cnt {
+ startEventCounter();
+}
+:STRT Tmr is ophi=5 & oplo=5 & Tmr {
+ startTimer();
+}
+:SWAP A is ophi=4 & oplo=7 & A {
+ A = (A<<4)|(A>>4);
+}
+:XCH A,Rni is ophi=2 & (rnfill=1 | rifill=0) & A & Rni {
+ xch(A, Rni);
+}
+:XCHD A,Ri is ophi=3 & A & Ri {
+ xch(A[0,4], Ri[0,4]);
+}
+:XRL A,RniI is (ophi=13 & (rnfill=1 | rifill=0 | oplo=3) & A)... & RniI {
+ A = A ^ RniI;
+}
diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/80251.cspec b/python/icicle/Ghidra/Processors/8051/data/languages/80251.cspec
new file mode 100644
index 0000000..2ccf8e6
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/8051/data/languages/80251.cspec
@@ -0,0 +1,54 @@
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diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/80251.pspec b/python/icicle/Ghidra/Processors/8051/data/languages/80251.pspec
new file mode 100644
index 0000000..a6b68b5
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/8051/data/languages/80251.pspec
@@ -0,0 +1,1070 @@
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+
+
diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/80251.sinc b/python/icicle/Ghidra/Processors/8051/data/languages/80251.sinc
new file mode 100644
index 0000000..64f7ee5
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/8051/data/languages/80251.sinc
@@ -0,0 +1,662 @@
+# 80251 Instructions
+
+# NOTE! 80251 implementation is preliminary and has not tested !!
+
+define token srcDestByte (8)
+ rm47 = (4,7)
+ rm47_d1 = (4,7)
+ rm47_d2 = (4,7)
+ rm03 = (0,3)
+ wrj47 = (4,7)
+ wrj47_d1 = (4,7)
+ wrj47_d2 = (4,7)
+ wrj03 = (0,3)
+ drk47 = (4,7)
+ drk03 = (0,3)
+ # constraint bits
+ d7 = (7,7)
+ d57 = (5,7)
+ d47 = (4,7)
+ s3 = (3,3)
+ s23 = (2,3)
+ s13 = (1,3)
+ s03 = (0,3)
+ s1 = (1,1)
+ s0 = (0,0)
+ short01 = (0,1)
+ bit02 = (0,2)
+;
+
+define token srcDestByte2 (8)
+ rm47_ = (4,7)
+ rm03_ = (0,3)
+ wrj47_ = (4,7)
+ wrj03_ = (0,3)
+ drk47_ = (4,7)
+ drk03_ = (0,3)
+ # constraint bits
+ d7_ = (7,7)
+ d57_ = (5,7)
+ s3_ = (3,3)
+ s13_ = (1,3)
+ s03_ = (0,3)
+;
+
+define token AddrThree (24)
+ addr24 = (0,23)
+;
+
+define token ImmedThree (24)
+ data24 = (0,23)
+;
+
+attach values short01 [ 1 2 4 _ ];
+
+attach variables [ rm47 rm03 rm47_ rm03_ ] [
+ R0 R1 R2 R3 R4 R5 R6 R7
+ R8 R9 B ACC R12 R13 R14 R15
+];
+
+attach variables [ rm47_d1 ] [
+ R0 R0 R2 R2 R4 R3 R6 R6
+ R8 R8 B B R12 R12 R14 R14
+];
+
+attach variables [ rm47_d2 ] [
+ R1 R1 R3 R3 R5 R5 R7 R7
+ R9 R9 ACC ACC R13 R13 R15 R15
+];
+
+attach variables [ wrj47 wrj03 wrj47_ wrj03_ ] [
+ WR0 WR2 WR4 WR6 WR8 AB WR12 WR14
+ WR16 WR18 WR20 WR22 WR24 WR26 WR28 WR30
+];
+
+attach variables [ wrj47_d1 ] [
+ WR0 WR0 WR4 WR4 WR8 WR8 WR12 WR12
+ WR16 WR16 WR20 WR20 WR24 WR24 WR28 WR28
+];
+
+attach variables [ wrj47_d2 ] [
+ WR2 WR2 WR6 WR6 AB AB WR14 WR14
+ WR18 WR18 WR22 WR22 WR26 WR26 WR30 WR30
+];
+
+# NOTE: must use constraints DRK, DRKD and DRKS
+attach variables [ drk47 drk03 drk47_ drk03_ ] [
+ DR0 DR4 DR8 DR12 DR16 DR20 DR24 DR28
+ DPX SPX _ _ _ _ _ _
+];
+
+@define DRK47 "drk47 & (d7=0 | d57=4)" # constraint for using drk47
+@define DRK03 "drk03 & (s3=0 | s13=4)" # constraint for using drk03
+@define DRK47_ "drk47_ & (d7_=0 | d57_=4)" # constraint for using drk47_
+
+AtWRjb: "@"^wrj47 is wrj47 { ptr:3 = zext(wrj47); export *:1 ptr; }
+AtWRjw: "@"^wrj47 is wrj47 { ptr:3 = zext(wrj47); export *:2 ptr; }
+
+# NOTE: be sure to use the ATDRK constraint on the constructor
+AtDRkb: "@"^drk47 is drk47 { ptr:3 = drk47:3; export *:1 ptr; }
+AtDRkw: "@"^drk47 is drk47 { ptr:3 = drk47:3; export *:2 ptr; }
+AtDRkt: "@"^drk47 is drk47 { ptr:3 = drk47:3; export *:3 ptr; }
+
+@define ATDRK "(d7=0 | d57=4)"
+
+AtWRj47Dis16b: "@"^wrj47^"+"^data16 is wrj47; data16 { ptr:3 = zext(wrj47) + data16; export *:1 ptr; }
+AtWRj47Dis16w: "@"^wrj47^"+"^data16 is wrj47; data16 { ptr:3 = zext(wrj47) + data16; export *:2 ptr; }
+
+AtWRj03Dis16b: "@"^wrj03^"+"^data16 is wrj03; data16 { ptr:3 = zext(wrj03) + data16; export *:1 ptr; }
+AtWRj03Dis16w: "@"^wrj03^"+"^data16 is wrj03; data16 { ptr:3 = zext(wrj03) + data16; export *:2 ptr; }
+
+AtDRk47Dis24b: "@"^drk47^"+"^data24 is drk47; data24 { ptr:3 = drk47:3 + data24; export *:1 ptr; }
+AtDRk47Dis24w: "@"^drk47^"+"^data24 is drk47; data24 { ptr:3 = drk47:3 + data24; export *:2 ptr; }
+
+AtDRk03Dis24b: "@"^drk03^"+"^data24 is drk03; data24 { ptr:3 = drk03:3 + data24; export *:1 ptr; }
+AtDRk03Dis24w: "@"^drk03^"+"^data24 is drk03; data24 { ptr:3 = drk03:3 + data24; export *:2 ptr; }
+
+# TODO: Verify dir8 access restriction for word/dword accesses !!
+Direct8w: mainreg is bank=0 & mainreg { export *:2 mainreg; }
+Direct8w: Direct is bank=1 & Direct { tmp:2 = zext(Direct); export tmp; }
+
+# TODO: The dir16 mode does not map into the SFR's - is this correct ??
+Direct16b: addr16 is addr16 { export *:1 addr16; }
+Direct16w: addr16 is addr16 { export *:2 addr16; }
+Direct16d: addr16 is addr16 { export *:4 addr16; }
+
+Data16x0: "#"data16 is data16 { export *[const]:4 data16; }
+Data16x1: "#"val is data16 [ val = 0xffff0000 + data16; ] { export *[const]:4 val; }
+
+Addr24: addr24 is addr24 { export *:1 addr24; }
+
+# NOTE: use SHORT constraint
+Short: "#"^short01 is short01 { export *[const]:1 short01; }
+@define SHORT "Short & (s0=0 | s1=0)"
+
+#TODO: Figure out new bit addressing for 251 ...
+
+xBitByteAddr: is bitaddr8 { export *:1 bitaddr8; }
+
+xBitAddr: bitaddr^"."^bit02 is bit02; bitaddr8 [ bitaddr = (bitaddr8 << 3) + bit02; ] { export *[BITS]:1 bitaddr; }
+xBitAddr2: "/"^bitaddr^"."^bit02 is bit02; bitaddr8 [ bitaddr = (bitaddr8 << 3) + bit02; ] { export *[BITS]:1 bitaddr; }
+
+
+macro push24(val) {
+ al:1 = val:1;
+ ah:1 = val(1);
+ ax:1 = val(2);
+
+ ptr:3 = SPX:3;
+
+ ptr = ptr + 1;
+ *[RAM]:1 ptr = al;
+ ptr = ptr + 1;
+ *[RAM]:1 ptr = ah;
+ ptr = ptr + 1;
+ *[RAM]:1 ptr = ax;
+
+ SPX = SPX + 3;
+}
+
+macro pop24(val) {
+
+ SPX = SPX - 2;
+
+ ptr:3 = SPX:3;
+ al:1 = *[RAM]:1 ptr;
+ ah:1 = *[RAM]:1 (ptr+1);
+ ax:1 = *[RAM]:1 (ptr+2);
+
+ SPX = SPX - 1;
+
+ val = (zext(ax) << 16) | (zext(ah) << 8) | zext(al);
+}
+
+
+# s s s s Binary representation of m or md
+# S S S S Binary representation of ms
+# t t t t Binary representation of j or jd
+# T T T T Binary representation of js
+# u u u u Binary representation of k or kd
+# U U U U Binary representation of ks
+
+# NOTE: >>>> Find MCS251 instructions by searching for "Binary Mode = [A5][Encoding]" in PDF manual <<<<
+# NOTE: All instructions should include the $(GROUP3) pattern prefix
+
+# ADD Rmd,Rms
+:ADD rm47,rm03 is $(GROUP3) & ophi=2 & oplo=12; rm47 & rm03 { addflags(rm47,rm03); rm47 = rm47 + rm03; resultflags(rm47); }
+
+# ADD WRjd,WRjs
+:ADD wrj47,wrj03 is $(GROUP3) & ophi=2 & oplo=13; wrj47 & wrj03 { addflags(wrj47,wrj03); wrj47 = wrj47 + wrj03; resultflags(wrj47); }
+
+# ADD DRkd,DRks
+:ADD drk47,drk03 is $(GROUP3) & ophi=2 & oplo=15; $(DRK47) & $(DRK03) { addflags(drk47,drk03); drk47 = drk47 + drk03; resultflags(drk47); }
+
+# ADD Rm,#data
+:ADD rm47,Data is $(GROUP3) & ophi=2 & oplo=14; rm47 & s03=0; Data { addflags(rm47,Data); rm47 = rm47 + Data; resultflags(rm47); }
+
+# ADD WRj,#data16
+:ADD wrj47,Data16 is $(GROUP3) & ophi=2 & oplo=14; wrj47 & s03=4; Data16 { addflags(wrj47,Data16); wrj47 = wrj47 + Data16; resultflags(wrj47); }
+
+# ADD DRk,#0data16
+:ADD drk47,Data16x0 is $(GROUP3) & ophi=2 & oplo=14; $(DRK47) & s03=8; Data16x0 { addflags(drk47,Data16x0); drk47 = drk47 + Data16x0; resultflags(drk47); }
+
+# ADD Rm,dir8
+:ADD rm47,Direct is $(GROUP3) & ophi=2 & oplo=14; rm47 & s03=1; Direct { addflags(rm47,Direct); rm47 = rm47 + Direct; resultflags(rm47); }
+
+# ADD WRj,dir8
+:ADD wrj47,Direct8w is $(GROUP3) & ophi=2 & oplo=14; wrj47 & s03=5; Direct8w { addflags(wrj47,Direct8w); wrj47 = wrj47 + Direct8w; resultflags(wrj47); }
+
+# ADD Rm,dir16
+:ADD rm47,Direct16b is $(GROUP3) & ophi=2 & oplo=14; rm47 & s03=3; Direct16b { addflags(rm47,Direct16b); rm47 = rm47 + Direct16b; resultflags(rm47); }
+
+# ADD WRj,dir16
+:ADD wrj47,Direct16w is $(GROUP3) & ophi=2 & oplo=14; wrj47 & s03=7; Direct16w { addflags(wrj47,Direct16w); wrj47 = wrj47 + Direct16w; resultflags(wrj47); }
+
+# ADD Rm,@WRj
+:ADD rm47_,AtWRjb is $(GROUP3) & ophi=2 & oplo=14; AtWRjb & s03=9; rm47_ & s03_=0 { addflags(rm47_,AtWRjb); rm47_ = rm47_ + AtWRjb; resultflags(rm47_); }
+
+# ADD Rm,@DRk
+:ADD rm47_,AtDRkb is $(GROUP3) & ophi=2 & oplo=14; $(ATDRK) & AtDRkb & s03=11; rm47_ & s03_=0 { addflags(rm47_,AtDRkb); rm47_ = rm47_ + AtDRkb; resultflags(rm47_); }
+
+# ANL Rmd,Rms
+:ANL rm47,rm03 is $(GROUP3) & ophi=5 & oplo=12; rm47 & rm03 { rm47 = rm47 & rm03; resultflags(rm47); }
+
+# ANL WRjd,WRjs
+:ANL wrj47,wrj03 is $(GROUP3) & ophi=5 & oplo=13; wrj47 & wrj03 { wrj47 = wrj47 & wrj03; resultflags(wrj47); }
+
+# ANL Rm,#data
+:ADD rm47,Data is $(GROUP3) & ophi=5 & oplo=14; rm47 & s03=0; Data { rm47 = rm47 & Data; resultflags(rm47); }
+
+# ANL WRj,#data16
+:ANL wrj47,Data16 is $(GROUP3) & ophi=5 & oplo=14; wrj47 & s03=4; Data16 { wrj47 = wrj47 & Data16; resultflags(wrj47); }
+
+# ANL Rm,dir8
+:ANL rm47,Direct is $(GROUP3) & ophi=5 & oplo=14; rm47 & s03=1; Direct { rm47 = rm47 & Direct; resultflags(rm47); }
+
+# ANL WRj,dir8
+:ANL wrj47,Direct8w is $(GROUP3) & ophi=5 & oplo=14; wrj47 & s03=5; Direct8w { wrj47 = wrj47 & Direct8w; resultflags(wrj47); }
+
+# ANL Rm,dir16
+:ANL rm47,Direct16b is $(GROUP3) & ophi=5 & oplo=14; rm47 & s03=3; Direct16b { rm47 = rm47 & Direct16b; resultflags(rm47); }
+
+# ANL WRj,dir16
+:ANL wrj47,Direct16w is $(GROUP3) & ophi=5 & oplo=14; wrj47 & s03=7; Direct16w { wrj47 = wrj47 & Direct16w; resultflags(wrj47); }
+
+# ANL Rm,@WRj
+:ANL rm47_,AtWRjb is $(GROUP3) & ophi=5 & oplo=14; AtWRjb & s03=9; rm47_ & s03_=0 { rm47_ = rm47_ & AtWRjb; resultflags(rm47_); }
+
+# ANL Rm,@DRk
+:ANL rm47_,AtDRkb is $(GROUP3) & ophi=5 & oplo=14; $(ATDRK) & AtDRkb & s03=11; rm47_ & s03_=0 { rm47_ = rm47_ & AtDRkb; resultflags(rm47_); }
+
+# ANL C,bit
+:ANL "CY",xBitAddr is $(GROUP3) & ophi=10 & oplo=9; (d47=8 & s3=0 & bit02; xBitByteAddr) & xBitAddr { $(CY)=$(CY)& ((xBitByteAddr>>bit02)&1); resultflags(xBitByteAddr); }
+
+# ANL C,/bit
+:ANL "CY",xBitAddr2 is $(GROUP3) & ophi=10 & oplo=9; (d47=15 & s3=0 & bit02; xBitByteAddr) & xBitAddr2 { $(CY)=$(CY)& (~((xBitByteAddr>>bit02)&1)); resultflags(xBitByteAddr); }
+
+# CLR bit
+:CLR xBitAddr is $(GROUP3) & ophi=10 & oplo=9; (d47=12 & s3=0 & bit02; xBitByteAddr) & xBitAddr { tmp:1 = ~(1<>bit02)&1) == 1:1) goto Rel8; }
+
+# JBC bit,rel
+:JBC xBitAddr,Rel8 is $(GROUP3) & ophi=10 & oplo=9; (d47=1 & s3=0 & bit02; xBitByteAddr) & xBitAddr; Rel8 { tmp:1 = 1<>bit02)&1)==0:1) goto Rel8; }
+
+# JNE rel
+:JNE Rel8 is $(GROUP3) & ophi=7 & oplo=8; Rel8 { if ($(Z)==0) goto Rel8; }
+
+# JSG rel
+:JSG Rel8 is $(GROUP3) & ophi=1 & oplo=8; Rel8 { if ($(Z)==0 && $(N)==$(OV)) goto Rel8; }
+
+# JSGE rel
+:JSGE Rel8 is $(GROUP3) & ophi=5 & oplo=8; Rel8 { if ($(N)==$(OV)) goto Rel8; }
+
+# JSL rel
+:JSL Rel8 is $(GROUP3) & ophi=4 & oplo=8; Rel8 { if ($(N)!=$(OV)) goto Rel8; }
+
+# JSLE rel
+:JSLE Rel8 is $(GROUP3) & ophi=0 & oplo=8; Rel8 { if ($(Z)==1 || $(N)!=$(OV)) goto Rel8; }
+
+# LCALL @WRj
+:LCALL AtWRjw is $(GROUP3) & ophi=9 & oplo=9; AtWRjw & s03=4 { ptr:3 = inst_next; push16(ptr:2); pc:3 = (ptr & 0xff0000) + zext(AtWRjw); call [pc]; }
+
+# LJMP @WRj
+:LJMP AtWRjw is $(GROUP3) & ophi=8 & oplo=9; AtWRjw & s03=4 { ptr:3 = inst_next; pc:3 = (ptr & 0xff0000) + zext(AtWRjw); goto [pc]; }
+
+# MOV Rmd,Rms
+:MOV rm47,rm03 is $(GROUP3) & ophi=7 & oplo=12; rm47 & rm03 { rm47 = rm03; }
+
+# MOV WRjd,WRjs
+:MOV wrj47,wrj03 is $(GROUP3) & ophi=7 & oplo=13; wrj47 & wrj03 { wrj47 = wrj03; }
+
+# MOV DRkd,DRks
+:MOV drk47,drk03 is $(GROUP3) & ophi=7 & oplo=15; drk47 & drk03 { drk47 = drk03; }
+
+# MOV Rm,#data
+:MOV rm47,Data is $(GROUP3) & ophi=7 & oplo=14; rm47 & s03=0; Data { rm47 = Data; }
+
+# MOV WRj,#data16
+:MOV wrj47,Data16 is $(GROUP3) & ophi=7 & oplo=14; wrj47 & s03=4; Data16 { wrj47 = Data16; }
+
+# MOV DRk,#0data16
+:MOV drk47,Data16x0 is $(GROUP3) & ophi=7 & oplo=14; drk47 & s03=8; Data16x0 { drk47 = Data16x0; }
+
+# MOV DRk,#1data16
+:MOV drk47,Data16x1 is $(GROUP3) & ophi=7 & oplo=14; drk47 & s03=12; Data16x1 { drk47 = Data16x1; }
+
+# MOV Rm,dir8
+:MOV rm47,Direct is $(GROUP3) & ophi=7 & oplo=14; rm47 & s03=1; Direct { rm47 = Direct; }
+
+# MOV WRj,dir8
+:MOV wrj47,Direct8w is $(GROUP3) & ophi=7 & oplo=14; wrj47 & s03=5; Direct8w { wrj47 = Direct8w; }
+
+# MOV DRk,dir8
+:MOV drk47,Direct8w is $(GROUP3) & ophi=7 & oplo=14; drk47 & s03=13; Direct8w { drk47 = zext(Direct8w); }
+
+# MOV Rm,dir16
+:MOV rm47,Direct16b is $(GROUP3) & ophi=7 & oplo=14; rm47 & s03=3; Direct16b { rm47 = Direct16b; }
+
+# MOV WRj,dir16
+:MOV wrj47,Direct16w is $(GROUP3) & ophi=7 & oplo=14; wrj47 & s03=7; Direct16w { wrj47 = Direct16w; }
+
+# MOV DRk,dir16
+:MOV drk47,Direct16d is $(GROUP3) & ophi=7 & oplo=14; drk47 & s03=15; Direct16d { drk47 = Direct16d; }
+
+# MOV Rm,@WRj
+:MOV rm47_,AtWRjb is $(GROUP3) & ophi=7 & oplo=14; AtWRjb & s03=9; rm47_ & s03_=0 { rm47_ = AtWRjb; }
+
+# MOV Rm,@DRk
+:MOV rm47_,AtDRkb is $(GROUP3) & ophi=7 & oplo=14; $(ATDRK) & AtDRkb & s03=11; rm47_ & s03_=0 { rm47_ = AtDRkb; }
+
+# MOV WRjd,@WRjs
+:MOV wrj47_,AtWRjw is $(GROUP3) & ophi=0 & oplo=11; AtWRjw & s03=8; wrj47_ & s03_=0 { wrj47_ = AtWRjw; }
+
+# MOV WRj,@DRk
+:MOV wrj47_,AtDRkw is $(GROUP3) & ophi=0 & oplo=11; $(ATDRK) & AtDRkw & s03=10; wrj47_ & s03_=0 { wrj47_ = AtDRkw; }
+
+# MOV dir8,Rm
+:MOV Direct,rm47 is $(GROUP3) & ophi=7 & oplo=10; rm47 & s03=1; Direct { Direct = rm47; }
+
+# MOV dir8,WRj
+# TODO: !! Verify direct byte write restriction to SFR registers
+:MOV Direct8w,wrj47 is $(GROUP3) & ophi=7 & oplo=10; wrj47 & s03=5; bank=0 & Direct8w { Direct8w = wrj47; }
+:MOV Direct,wrj47 is $(GROUP3) & ophi=7 & oplo=10; wrj47 & s03=5; bank=1 & Direct { Direct = wrj47:1; }
+
+# MOV dir8,DRk
+# TODO: !! Verify byte/word write restriction to internal memory (00-7f)
+# TODO: !! Verify byte write restriction to SFR registers
+:MOV Direct8w,drk47 is $(GROUP3) & ophi=7 & oplo=10; $(DRK47) & s03=13; bank=0 & Direct8w { Direct8w = drk47:2; }
+:MOV Direct,drk47 is $(GROUP3) & ophi=7 & oplo=10; $(DRK47) & s03=13; bank=1 & Direct { Direct = drk47:1; }
+
+# MOV dir16,Rm
+:MOV Direct16b,rm47 is $(GROUP3) & ophi=7 & oplo=10; rm47 & s03=3; Direct16b { Direct16b = rm47; }
+
+# MOV dir16,WRj
+:MOV Direct16w,wrj47 is $(GROUP3) & ophi=7 & oplo=10; wrj47 & s03=7; Direct16w { Direct16w = wrj47; }
+
+# MOV dir16,DRk
+:MOV Direct16d,drk47 is $(GROUP3) & ophi=7 & oplo=10; $(DRK47) & s03=15; Direct16d { Direct16d = drk47; }
+
+# MOV @WRj,Rm
+:MOV AtWRjb,rm47_ is $(GROUP3) & ophi=7 & oplo=10; AtWRjb & s03=9; rm47_ & s03_=0 { AtWRjb = rm47_; }
+
+# MOV @DRk,Rm
+:MOV AtDRkb,rm47_ is $(GROUP3) & ophi=7 & oplo=10; $(ATDRK) & AtDRkb & s03=11; rm47_ & s03_=0 { AtDRkb = rm47_; }
+
+# MOV @WRjd,WRjs
+:MOV AtWRjw,wrj47_ is $(GROUP3) & ophi=1 & oplo=11; AtWRjw & s03=8; wrj47_ & s03_=0 { AtWRjw = wrj47_; }
+
+# MOV @DRk,WRj
+:MOV AtDRkw,wrj47_ is $(GROUP3) & ophi=1 & oplo=11; $(ATDRK) & AtDRkw & s03=10; wrj47_ & s03_=0 { AtDRkw = wrj47_; }
+
+# MOV Rm,@WRj+dis16
+:MOV rm47,AtWRj03Dis16b is $(GROUP3) & ophi=0 & oplo=9; rm47 ... & AtWRj03Dis16b { AtWRj03Dis16b = rm47; }
+
+# MOV WRj,@WRj+dis16
+:MOV wrj47,AtWRj03Dis16w is $(GROUP3) & ophi=4 & oplo=9; wrj47 ... & AtWRj03Dis16w { AtWRj03Dis16w = wrj47; }
+
+# MOV Rm,@DRk+dis24
+:MOV rm47,AtDRk03Dis24b is $(GROUP3) & ophi=2 & oplo=9; (rm47 & $(DRK03)) ... & AtDRk03Dis24b { AtDRk03Dis24b = rm47; }
+
+# MOV WRj,@DRk+dis24
+:MOV wrj47,AtDRk03Dis24w is $(GROUP3) & ophi=6 & oplo=9; (wrj47 & $(DRK03)) ... & AtDRk03Dis24w { AtDRk03Dis24w = wrj47; }
+
+# MOV @WRj+dis16,Rm
+:MOV AtWRj47Dis16b,rm03 is $(GROUP3) & ophi=1 & oplo=9; rm03 ... & AtWRj47Dis16b { AtWRj47Dis16b = rm03; }
+
+# MOV @WRj+dis16,WRj
+:MOV AtWRj47Dis16w,wrj03 is $(GROUP3) & ophi=5 & oplo=9; wrj03 ... & AtWRj47Dis16w { AtWRj47Dis16w = wrj03; }
+
+# MOV @DRk+dis24,Rm
+:MOV AtDRk47Dis24b,rm03 is $(GROUP3) & ophi=3 & oplo=9; (rm03 & $(DRK47)) ... & AtDRk47Dis24b { AtDRk47Dis24b = rm03; }
+
+# MOV @DRk+dis24,WRj
+:MOV AtDRk47Dis24w,wrj03 is $(GROUP3) & ophi=7 & oplo=9; (wrj03 & $(DRK47)) ... & AtDRk47Dis24w { AtDRk47Dis24w = wrj03; }
+
+# MOV bit,C
+:MOV xBitAddr,"CY" is $(GROUP3) & ophi=10 & oplo=9; (d47=9 & s3=0 & bit02; xBitByteAddr) & xBitAddr { xBitByteAddr = (xBitByteAddr) | (1<>bit02)&1); }
+
+
+# MOVH DRk,#data16
+:MOVH drk47,Data16x0 is $(GROUP3) & ophi=7 & oplo=14; $(DRK47) & s03=12; Data16x0 { drk47 = (drk47 & 0xffff0000) | (Data16x0 << 16); }
+
+# MOVS WRj,Rm
+:MOVZ wrj47,rm03 is $(GROUP3) & ophi=1 & oplo=10; wrj47 & rm03 { wrj47 = sext(rm03); }
+
+# MOVZ WRj,Rm
+:MOVZ wrj47,rm03 is $(GROUP3) & ophi=0 & oplo=10; wrj47 & rm03 { wrj47 = zext(rm03); }
+
+# MUL Rmd,Rms
+:MUL rm47,rm03 is $(GROUP3) & ophi=10 & oplo=12; rm47 & rm03 & rm47_d1 & rm47_d2 { result:2 = zext(rm47) * zext(rm03); tmp:2 = result>>8; rm47_d1 = tmp:1; rm47_d2 = result:1; }
+
+# MUL WRjd,WRjs
+:MUL wrj47,wrj03 is $(GROUP3) & ophi=10 & oplo=13; wrj47 & wrj03 & wrj47_d1 & wrj47_d2 { result:4 = zext(wrj47) * zext(wrj03); tmp:4 = result>>16; wrj47_d1 = tmp:2; wrj47_d2 = result:2; }
+
+# ORL Rmd,Rms
+:ORL rm47,rm03 is $(GROUP3) & ophi=4 & oplo=12; rm47 & rm03 { rm47 = rm47 | rm03; resultflags(rm47); }
+
+# ORL WRjd,WRjs
+:ORL wrj47,wrj03 is $(GROUP3) & ophi=4 & oplo=13; wrj47 & wrj03 { wrj47 = wrj47 | wrj03; resultflags(wrj47); }
+
+# ORL Rm,#data
+:ORL rm47,Data is $(GROUP3) & ophi=4 & oplo=14; rm47 & s03=0; Data { rm47 = rm47 | Data; resultflags(rm47); }
+
+# ORL WRj,#data16
+:ORL wrj47,Data16 is $(GROUP3) & ophi=4 & oplo=14; wrj47 & s03=4; Data16 { wrj47 = wrj47 | Data16; resultflags(wrj47); }
+
+# ORL Rm,dir8
+:ORL rm47,Direct is $(GROUP3) & ophi=4 & oplo=14; rm47 & s03=1; Direct { rm47 = rm47 | Direct; resultflags(rm47); }
+
+# ORL WRj,dir8
+:ORL wrj47,Direct8w is $(GROUP3) & ophi=4 & oplo=15; wrj47 & s03=5; Direct8w { wrj47 = wrj47 | Direct8w; resultflags(wrj47); }
+
+# ORL Rm,dir16
+:ORL rm47,Direct16b is $(GROUP3) & ophi=4 & oplo=14; rm47 & s03=3; Direct16b { rm47 = rm47 | Direct16b; resultflags(rm47); }
+
+# ORL WRj,dir16
+:ORL wrj47,Direct16w is $(GROUP3) & ophi=4 & oplo=14; wrj47 & s03=7; Direct16w { wrj47 = wrj47 | Direct16w; resultflags(wrj47); }
+
+# ORL Rm,@WRj
+:ORL rm47_,AtWRjb is $(GROUP3) & ophi=4 & oplo=14; AtWRjb & s03=9; rm47_ & s03_=0 { rm47_ = rm47_ | AtWRjb; resultflags(rm47_); }
+
+# ORL Rm,@DRk
+:ORL rm47_,AtDRkb is $(GROUP3) & ophi=4 & oplo=14; $(ATDRK) & AtDRkb & s03=11; rm47_ & s03_=0 { rm47_ = rm47_ | AtDRkb; resultflags(rm47_); }
+
+# ORL C,bit
+:ORL "CY",xBitAddr is $(GROUP3) & ophi=10 & oplo=9; (d47=7 & s3=0 & bit02; xBitByteAddr) & xBitAddr { $(CY) = ((xBitByteAddr>>bit02)&1) | $(CY); }
+
+# ORL bit,C
+:ORL "CY",xBitAddr2 is $(GROUP3) & ophi=10 & oplo=9; (d47=14 & s3=0 & bit02; xBitByteAddr) & xBitAddr2 { $(CY) = ((xBitByteAddr>>bit02)&1) | ($(CY) == 0); }
+
+# POP Rm
+:POP rm47 is $(GROUP3) & ophi=13 & oplo=10; rm47 & s03=8 { pop8(rm47); }
+
+# POP WRj
+:POP wrj47 is $(GROUP3) & ophi=13 & oplo=10; wrj47 & s03=9 { pop16(wrj47); }
+
+# POP DRk
+:POP drk47 is $(GROUP3) & ophi=13 & oplo=10; $(DRK47) & s03=11 { pop16(drk47); }
+
+# PUSH #data
+# TODO: manual did not specify A5 prefix, but would otherwise conflict with the XCH A,Rn instruction (8051)
+:PUSH Data is $(GROUP3) & ophi=12 & oplo=10; d47=0 & s03=2; Data { push8(Data); }
+
+# PUSH #data16
+:PUSH Data16 is $(GROUP3) & ophi=12 & oplo=10; d47=0 & s03=6; Data16 { push16(Data16); }
+
+# PUSH Rm
+:PUSH rm47 is $(GROUP3) & ophi=12 & oplo=10; rm47 & s03=8 { push8(rm47); }
+
+# PUSH WRj
+:PUSH wrj47 is $(GROUP3) & ophi=12 & oplo=10; wrj47 & s03=9 { push16(wrj47); }
+
+# PUSH DRk
+:PUSH drk47 is $(GROUP3) & ophi=12 & oplo=10; $(DRK47) & s03=11 { push16(drk47); }
+
+# SETB bit
+:SETB xBitAddr^"."^xBitByteAddr is $(GROUP3) & ophi=10 & oplo=9; (d47=13 & s3=0 & bit02; xBitByteAddr) & xBitAddr { xBitByteAddr = (xBitByteAddr) | (1 << bit02); }
+
+# SLL Rm
+:SLL rm47 is $(GROUP3) & ophi=3 & oplo=14; rm47 & s03=0 { $(CY) = ((rm47>>7) & 1); rm47 = rm47 << 1; resultflags(rm47); }
+
+# SLL WRj
+:SLL wrj47 is $(GROUP3) & ophi=3 & oplo=14; wrj47 & s03=4 { $(CY) = ((wrj47>>15) & 1) == 1; wrj47 = wrj47 << 1; resultflags(wrj47); }
+
+# SRA Rm
+:SRA rm47 is $(GROUP3) & ophi=0 & oplo=14; rm47 & s03=0 { $(CY) = rm47 & 1; rm47 = rm47 s>> 1; resultflags(rm47); }
+
+# SRA WRj
+:SRA wrj47 is $(GROUP3) & ophi=0 & oplo=14; wrj47 & s03=4 { $(CY) = (wrj47 & 1) == 1; wrj47 = wrj47 s>> 1; resultflags(wrj47); }
+
+# SRL Rm
+:SRL rm47 is $(GROUP3) & ophi=1 & oplo=14; rm47 & s03=0 { $(CY) = rm47 & 1; rm47 = rm47 >> 1; resultflags(rm47); }
+
+# SRL WRj
+:SRL wrj47 is $(GROUP3) & ophi=1 & oplo=14; wrj47 & s03=4 { $(CY) = (wrj47 & 1) == 1; wrj47 = wrj47 >> 1; resultflags(wrj47); }
+
+
+# SUB Rmd,Rms
+:SUB rm47,rm03 is $(GROUP3) & ophi=9 & oplo=12; rm47 & rm03 { subflags(rm47,rm03); rm47 = rm47 - rm03; resultflags(rm47); }
+
+# SUB WRjd,WRjs
+:SUB wrj47,wrj03 is $(GROUP3) & ophi=9 & oplo=13; wrj47 & wrj03 { subflags(wrj47,wrj03); wrj47 = wrj47 - wrj03; resultflags(wrj47); }
+
+# SUB DRkd,DRks
+:SUB drk47,drk03 is $(GROUP3) & ophi=9 & oplo=15; $(DRK47) & $(DRK03) { subflags(drk47,drk03); drk47 = drk47 - drk03; resultflags(drk47);}
+
+# SUB Rm,#data
+:SUB rm47,Data is $(GROUP3) & ophi=9 & oplo=14; rm47 & s03=0; Data { subflags(rm47,Data); rm47 = rm47 - Data; resultflags(rm47);}
+
+# SUB WRj,#data16
+:SUB wrj47,Data16 is $(GROUP3) & ophi=9 & oplo=14; wrj47 & s03=4; Data16 { subflags(wrj47,Data16); wrj47 = wrj47 - Data16; resultflags(wrj47);}
+
+# SUB DRk,#data16
+:SUB drk47,Data16x0 is $(GROUP3) & ophi=9 & oplo=14; $(DRK47) & s03=8; Data16x0 { subflags(drk47,Data16x0); drk47 = drk47 - Data16x0; resultflags(drk47);}
+
+# SUB Rm,dir8
+:SUB rm47,Direct is $(GROUP3) & ophi=9 & oplo=14; rm47 & s03=1; Direct { subflags(rm47,Direct); rm47 = rm47 - Direct; resultflags(rm47);}
+
+# SUB WRj,dir8
+:SUB wrj47,Direct8w is $(GROUP3) & ophi=9 & oplo=14; wrj47 & s03=5; Direct8w { subflags(wrj47,Direct8w); wrj47 = wrj47 - Direct8w; resultflags(wrj47);}
+
+# SUB Rm,dir16
+:SUB rm47,Direct16b is $(GROUP3) & ophi=9 & oplo=14; rm47 & s03=3; Direct16b { subflags(rm47,Direct16b); rm47 = rm47 - Direct16b; resultflags(rm47);}
+
+# SUB WRj,dir16
+:SUB wrj47,Direct16w is $(GROUP3) & ophi=9 & oplo=14; wrj47 & s03=7; Direct16w { subflags(wrj47,Direct16w); wrj47 = wrj47 - Direct16w; resultflags(wrj47);}
+
+# SUB Rm,@WRj
+:SUB rm47_,AtWRjb is $(GROUP3) & ophi=9 & oplo=14; AtWRjb & s03=9; rm47_ & s03_=0 { subflags(rm47_,AtWRjb); rm47_ = rm47_ - AtWRjb; resultflags(rm47_);}
+
+# SUB Rm,@DRk
+:SUB rm47_,AtDRkb is $(GROUP3) & ophi=9 & oplo=14; $(ATDRK) & AtDRkb & s03=11; rm47_ & s03_=0 { subflags(rm47_,AtDRkb); rm47_ = rm47_ - AtDRkb; resultflags(rm47_);}
+
+
+# XRL Rmd,Rms
+:XRL rm47,rm03 is $(GROUP3) & ophi=6 & oplo=12; rm47 & rm03 { rm47 = rm47 ^ rm03; resultflags(rm47); }
+
+# XRL WRjd,WRjs
+:XRL wrj47,wrj03 is $(GROUP3) & ophi=6 & oplo=13; wrj47 & wrj03 { wrj47 = wrj47 ^ wrj03; resultflags(wrj47); }
+
+# XRL Rm,#data
+:XRL rm47,Data is $(GROUP3) & ophi=6 & oplo=14; rm47 & s03=0; Data { rm47 = rm47 ^ Data; resultflags(rm47); }
+
+# XRL WRj,#data16
+:XRL wrj47,Data16 is $(GROUP3) & ophi=6 & oplo=14; wrj47 & s03=4; Data16 { wrj47 = wrj47 ^ Data16; resultflags(wrj47); }
+
+# XRL Rm,dir8
+:XRL rm47,Direct is $(GROUP3) & ophi=6 & oplo=14; rm47 & s03=1; Direct { rm47 = rm47 ^ Direct; resultflags(rm47); }
+
+# XRL WRj,dir8
+:XRL wrj47,Direct8w is $(GROUP3) & ophi=6 & oplo=14; wrj47 & s03=5; Direct8w { wrj47 = wrj47 ^ Direct8w; resultflags(wrj47); }
+
+# XRL Rm,dir16
+:XRL rm47,Direct16b is $(GROUP3) & ophi=6 & oplo=14; rm47 & s03=3; Direct16b { rm47 = rm47 ^ Direct16b; resultflags(rm47); }
+
+# XRL WRj,dir16
+:XRL wrj47,Direct16w is $(GROUP3) & ophi=6 & oplo=14; wrj47 & s03=7; Direct16w { wrj47 = wrj47 ^ Direct16w; resultflags(wrj47); }
+
+# XRL Rm,@Wrj
+:XRL rm47_,AtWRjb is $(GROUP3) & ophi=6 & oplo=14; AtWRjb & s03=9; rm47_ & s03_=0 { rm47_ = rm47_ ^ AtWRjb; resultflags(rm47_); }
+
+# XRL Rm,@Drk
+:XRL rm47_,AtDRkb is $(GROUP3) & ophi=6 & oplo=14; $(ATDRK) & AtDRkb & s03=11; rm47_ & s03_=0 { rm47_ = rm47_ ^ AtDRkb; resultflags(rm47_); }
diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/80251.slaspec b/python/icicle/Ghidra/Processors/8051/data/languages/80251.slaspec
new file mode 100644
index 0000000..14608a9
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/8051/data/languages/80251.slaspec
@@ -0,0 +1,5 @@
+@define MCS251 ""
+
+@include "8051_main.sinc"
+
+@include "80251.sinc"
diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/80390.cspec b/python/icicle/Ghidra/Processors/8051/data/languages/80390.cspec
new file mode 100644
index 0000000..ec23f5e
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/8051/data/languages/80390.cspec
@@ -0,0 +1,62 @@
+
+
+
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diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/80390.slaspec b/python/icicle/Ghidra/Processors/8051/data/languages/80390.slaspec
new file mode 100644
index 0000000..f45e1d7
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/8051/data/languages/80390.slaspec
@@ -0,0 +1,3 @@
+@define MCS80390 ""
+
+@include "8051_main.sinc"
diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/8051.cspec b/python/icicle/Ghidra/Processors/8051/data/languages/8051.cspec
new file mode 100644
index 0000000..ab1b883
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/8051/data/languages/8051.cspec
@@ -0,0 +1,72 @@
+
+
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diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/8051.ldefs b/python/icicle/Ghidra/Processors/8051/data/languages/8051.ldefs
new file mode 100644
index 0000000..7c2700f
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/8051/data/languages/8051.ldefs
@@ -0,0 +1,53 @@
+
+
+
+
+ 8051 Microcontroller Family
+
+
+
+
+
+ 80251 Microcontroller Family
+
+
+
+ 80390 in flat mode
+
+
+
+ NXP/Phillips MX51
+
+
+
+
diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/8051.pspec b/python/icicle/Ghidra/Processors/8051/data/languages/8051.pspec
new file mode 100644
index 0000000..8f2fbad
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/8051/data/languages/8051.pspec
@@ -0,0 +1,413 @@
+
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diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/8051.slaspec b/python/icicle/Ghidra/Processors/8051/data/languages/8051.slaspec
new file mode 100644
index 0000000..e3a4e65
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/8051/data/languages/8051.slaspec
@@ -0,0 +1,3 @@
+@define MCS51 ""
+
+@include "8051_main.sinc"
diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/8051_archimedes.cspec b/python/icicle/Ghidra/Processors/8051/data/languages/8051_archimedes.cspec
new file mode 100644
index 0000000..5747aa6
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/8051/data/languages/8051_archimedes.cspec
@@ -0,0 +1,99 @@
+
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diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/8051_main.sinc b/python/icicle/Ghidra/Processors/8051/data/languages/8051_main.sinc
new file mode 100644
index 0000000..d3d40e0
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/8051/data/languages/8051_main.sinc
@@ -0,0 +1,917 @@
+# sleigh specification file for Intel 8051
+
+#@define BIT_OPS "PCODEOPS"
+#@define BIT_OPS "SHIFTS"
+@define BIT_OPS "BIT_ADDRS"
+
+# It's sometimes clearer for decompilation to omit the pushing and
+# restoring of the return value for function calls.
+#@define OMIT_RETADDR
+
+# TODO !!! need to fully employ resultflags macro after resolving the use of the above BIT_OPS !!!
+# TODO !!! Need to reconcile use of PSW vs. PSW1 for MCS251 !!!
+# TODO !!! Need to fill-out SFR bits in 80251.pspec !!!
+
+@if defined(ENDIAN)
+define endian=$(ENDIAN);
+@else
+define endian=big;
+@endif
+
+define alignment=1;
+
+@if defined(MCS251)
+
+@define PTRSIZE 3
+@define SP_SIZE 3
+
+define space RAM type=ram_space size=3 default;
+define space SFR type=ram_space size=2;
+define space BITS type=ram_space size=2;
+
+# 8051 spaces map to the following regions of the 80251 RAM space:
+# CODE - 0xff0000-0xffffff
+# EXTERNAL - 0x010000-0x01ffff
+# INTERNAL - 0x000000-0x0000ff
+
+@elif defined(MCS51)
+
+@if defined(PTRSIZE)
+@else
+@define PTRSIZE 2
+@endif
+
+# SP stack pointer should be set to the size of the space it is used in, to avoid "issues"
+# This is a minor inconsistency with the model and the actual processor in some cases
+# If pristine SP sizing is required for rollover and such, the model should be changed
+#
+@define SP_SIZE 1
+
+define space CODE type=ram_space size=$(PTRSIZE) default;
+define space INTMEM type=ram_space size=1;
+define space EXTMEM type=ram_space size=2;
+define space SFR type=ram_space size=1;
+define space BITS type=ram_space size=1;
+
+@elif defined(MCS80390)
+
+@define PTRSIZE 3
+@define SP_SIZE 1
+
+define space CODE type=ram_space size=3 default;
+define space INTMEM type=ram_space size=1;
+define space EXTMEM type=ram_space size=3;
+define space SFR type=ram_space size=1;
+define space BITS type=ram_space size=1;
+
+@elif defined(MX51)
+
+@define PTRSIZE 3
+@define SP_SIZE 3
+
+# The right thing for decompilation is to represent these
+# as part of one uniform space, similar to the 80251.
+# Remember to load code at 800000
+#
+# xdata 0 (EXTMEM)
+# data 7f0000 (INTMEM)
+# code 800000
+
+define space RAM type=ram_space size=3 default;
+define space SFR type=ram_space size=1;
+define space ESFR type=ram_space size=1;
+define space BITS type=ram_space size=1;
+define space EBITS type=ram_space size=1;
+
+# Unsure where stack really is, but probably don't want it on normal
+# registers
+#@define STACKBASE 0x7f0100
+@define STACKBASE 0
+
+@else
+# "error Unknown processor"
+@endif
+
+
+
+define space register type=register_space size=1;
+
+# Register File
+define register offset=0x00 size=1 [ R0 R1 R2 R3 R4 R5 R6 R7 ];
+
+# for future jump table fixup
+define register offset=0x70 size=1 [ jumpTableGuard1 jumpTableGuard2 ];
+
+@if defined(MCS251)
+
+define register offset=0x08 size=1 [ R8 R9 B ACC R12 R13 R14 R15
+ R16 R17 R18 R19 R20 R21 R22 R23
+ R24 R25 R26 R27 R28 R29 R30 R31
+];
+define register offset=0x0 size=2 [ WR0 WR2 WR4 WR6 WR8 AB WR12 WR14
+ WR16 WR18 WR20 WR22 WR24 WR26 WR28 WR30
+];
+define register offset=0x0 size=4 [ DR0 DR4 DR8 DR12 DR16 DR20 DR24 DR28 ];
+
+define register offset=0x38 size=1 [ R56 DPXL DPH DPL R60 R61 SPH ];
+define register offset=0x3A size=2 [ DPTR ];
+define register offset=0x38 size=4 [ DPX SPX ];
+
+@elif defined(MCS51) || defined(MCS80390) || defined(MX51)
+
+define register offset=0x00 size=4 [ R0R1R2R3 ];
+define register offset=0x01 size=3 [ R1R2R3 ]; # Used as R3R2R1
+define register offset=0x01 size=2 [ R2R1 ];
+define register offset=0x00 size=2 [ R0R1 R2R3 R4R5 R6R7 ];
+define register offset=0x04 size=4 [ R4R5R6R7 ];
+define register offset=0x05 size=3 [ R5R6R7 ];
+
+define register offset=0x0A size=1 [ B ACC ]; # relocated to facilitate AB 16-bit access
+define register offset=0x0A size=2 [ AB ];
+
+@if defined(MCS51) || defined(MX51)
+define register offset=0x82 size=2 [ DPTR ];
+define register offset=0x82 size=1 [ DPH DPL ]; # relocated to facilitate DPTR 16-bit access
+@elif defined(MCS80390)
+
+# Following existing example, relocated DPX, DPH, and DPL for DPTR
+# access. Rework some direct moves to compensate. Not clear that all
+# cases are covered, thus might be problematic hack in the long term.
+define register offset=0x82 size=3 [ DPTR ];
+define register offset=0x82 size=1 [ DPX DPH DPL ];
+@endif
+
+@else
+# "error Unknown processor"
+@endif
+
+
+define register offset=0x40 size=$(SP_SIZE) [ SP ];
+define register offset=0x44 size=$(PTRSIZE) [ PC ];
+define register offset=0x48 size=1 [ PSW ];
+@if defined(DUAL_DPTR)
+# Dual DPTR
+# Rather than model it as context, we're just going
+# to special case the INC and DEC instructions
+# to swap the register values
+define register offset=0x4a size=2 [ DPTR2 ];
+define register offset=$(DPS_REG_NUM) size=1 [ AUXR1 ]; # Bit 0 is DPS
+@endif
+
+@define CY "PSW[7,1]"
+@define AC "PSW[6,1]"
+@define N "PSW[5,1]"
+@define RS1 "PSW[4,1]"
+@define RS0 "PSW[3,1]"
+@define OV "PSW[2,1]"
+@define Z "PSW[1,1]"
+
+@if defined(MX51)
+# remap these into the normal register file for decompiler use.
+# Really belong on ESFR @0xfc - 0xfe with order EPL EPM EPH
+define register offset=0xc0 size=1 [ EPH EPM EPL ];
+define register offset=0xc0 size=3 [ EPTR ];
+@endif
+
+@if defined(MCS251)
+
+define register offset=0x50 size=4 contextReg;
+
+define context contextReg
+ phase = (0,0)
+ srcMode = (1,1) # (reflects UCONFIG0.0) 1: source mode, 0: binary mode
+ A5Prefix = (2,2) # reflects presence of A5 prefix
+;
+
+# GROUP1 - MCS51 instructions in 0x00-0x5F range
+@define GROUP1 "epsilon"
+
+# GROUP2 - MCS51 instructions in 0x60-0xff range
+@define GROUP2 "((srcMode=0 & A5Prefix=0) | (srcMode=1 & A5Prefix=1))"
+
+# GROUP3 - MCS251 instructions in 0x60-0xff range
+@define GROUP3 "((srcMode=0 & A5Prefix=1) | (srcMode=1 & A5Prefix=0))"
+
+@elif defined(MCS51) || defined(MCS80390) || defined(MX51)
+
+@define GROUP1 "epsilon"
+@define GROUP2 "epsilon"
+@define GROUP3 "epsilon"
+
+@endif
+
+define pcodeop decimal_adjust;
+define pcodeop nop;
+
+@if BIT_OPS == "PCODEOPS"
+define pcodeop get;
+define pcodeop set;
+define pcodeop set_bit_value;
+define pcodeop clr;
+@endif
+
+
+#TOKENS
+
+define token opbyte (8)
+ opfull = (0,7)
+ oplo = (0,3)
+ ophi = (4,7)
+ rn = (0,2)
+ rnfill = (3,3)
+ ri = (0,0)
+ rifill = (1,3)
+ opaddr = (5,7)
+ addrfill = (4,4)
+
+ b_0000 = (0,0)
+ b_0001 = (0,1)
+ b_0002 = (0,2)
+ b_0005 = (0,5)
+ b_0101 = (1,1)
+ b_0107 = (1,7)
+ b_0207 = (2,7)
+ b_0307 = (3,7)
+ b_0607 = (6,7)
+@if defined(MX51)
+ PRi_sel = (2,2)
+ PRi_revend = (2,2) # reverse endian
+ emov_delta = (0,1)
+@endif
+;
+define token AddrByte (8)
+ direct = (0,7)
+ bank = (7,7)
+ sfr = (0,6)
+ sfr6 = (6,6)
+ sfrlo = (0,3)
+ mainreg = (0,6)
+ direct17 = (1,7)
+;
+define token AddrByte2 (8)
+ direct2 = (0,7)
+ bank2 = (7,7)
+ sfr2 = (0,6)
+ sfr26 = (6,6)
+ sfr2lo = (0,3)
+ mainreg2 = (0,6)
+;
+define token BitByte (8)
+ bitaddr8 = (0,7)
+ bitaddr27 = (2,7)
+ bitbank = (7,7)
+ sfrbyte = (3,7)
+ bitaddr57 = (5,7)
+ sfrbit6 = (6,6)
+ sfrbit3 = (3,3)
+ sfrbit = (0,2) dec
+ lowbyte = (3,6)
+ bitaddr0 = (0,0)
+;
+define token AddrTwo (16)
+ addr16 = (0,15)
+;
+@if defined(MCS80390)
+# todo: deconflict with 80251 version
+define token AddrThree (24)
+ addr24 = (0,23)
+;
+@endif
+
+define token RelByte (8) rel8=(0,7) signed;
+define token ImmedByte (8) data=(0,7);
+define token ImmedTwo (16)
+ data16 = (0,15)
+ rel16 = (0,15) signed
+;
+@if defined(MCS80390)
+define token ImmedThree (24)
+ data24 = (0,23)
+;
+@endif
+
+@if defined(MCS80390)
+define token aopword (24)
+ aoplo = (16,19)
+ aopaddr = (21,23)
+ aaddrfill = (20,20)
+ adata = (0,15)
+;
+@else
+define token aopword (16)
+ aoplo = (8,11)
+ aopaddr = (13,15)
+ aaddrfill = (12,12)
+ adata = (0,7)
+;
+@endif
+
+attach variables rn [ R0 R1 R2 R3 R4 R5 R6 R7 ];
+attach variables ri [ R0 R1 ];
+
+# flags macros
+
+#macro addflags(op1, op2) { # Flags set by add instructions
+# PSW = PSW & 0x7b;
+# PSW = PSW | (carry(op1,op2)<<7) # Check for carry
+# | (scarry(op1,op2)<<2); # Check for signed carry
+#}
+
+#macro subflags(op1, op2) { # Flags set by sub instructions
+# PSW = PSW & 0x7b;
+# PSW = PSW | ((op1>sfrbit)&1); resultflags(tmp); }
+:ANL CY,BitAddr2 is $(GROUP1) & CY & ophi=11 & oplo=0; BitAddr2 & bitaddr57=7 & sfrbit3=0 & sfrbit & BitByteAddr {tmp:1 = BitByteAddr; $(CY)=$(CY)& (~((tmp>>sfrbit)&1)); }
+@if BIT_OPS == "BIT_ADDRS"
+:ANL CY,BitAddr is $(GROUP1) & CY & ophi=8 & oplo=2; BitAddr & sfrbit & BitByteAddr {$(CY)=$(CY)& BitAddr; }
+:ANL CY,BitAddr2 is $(GROUP1) & CY & ophi=11 & oplo=0; BitAddr2 & sfrbit & BitByteAddr {$(CY)=$(CY)& ~BitAddr2; }
+@elif BIT_OPS == "PCODEOPS"
+:ANL CY,BitAddr is $(GROUP1) & CY & ophi=8 & oplo=2; BitAddr & sfrbit & BitByteAddr {$(CY)=$(CY)& get(BitAddr, BitByteAddr); }
+:ANL CY,BitAddr2 is $(GROUP1) & CY & ophi=11 & oplo=0; BitAddr2 & sfrbit & BitByteAddr {$(CY)=$(CY)& (get(BitAddr2, BitByteAddr)^1); }
+@elif BIT_OPS == "SHIFTS"
+:ANL CY,BitAddr is $(GROUP1) & CY & ophi=8 & oplo=2; BitAddr & sfrbit & BitByteAddr {$(CY)=$(CY)& ((BitByteAddr>>sfrbit)&1); }
+:ANL CY,BitAddr2 is $(GROUP1) & CY & ophi=11 & oplo=0; BitAddr2 & sfrbit & BitByteAddr {$(CY)=$(CY)& (~((BitByteAddr>>sfrbit)&1)); }
+@endif
+
+:CJNE Areg,Direct,Rel8 is $(GROUP1) & ophi=11 & oplo=5 & Areg; Direct; Rel8 { compflags(ACC,Direct); if (ACC!=Direct) goto Rel8; }
+:CJNE Areg,Data,Rel8 is $(GROUP1) & ophi=11 & oplo=4 & Areg; Data; Rel8 { compflags(ACC,Data); if (ACC!=Data) goto Rel8; }
+:CJNE rn,Data,Rel8 is $(GROUP2) & ophi=11 & rnfill=1 & rn; Data; Rel8 { compflags(rn,Data); if (rn!=Data) goto Rel8; }
+:CJNE Ri,Data,Rel8 is $(GROUP2) & ophi=11 & rifill=3 & Ri; Data; Rel8 { compflags(Ri,Data); if (Ri!=Data) goto Rel8; }
+
+:CLR Areg is $(GROUP1) & ophi=14 & oplo=4 & Areg { ACC = 0; }
+:CLR CY is $(GROUP1) & CY & ophi=12 & oplo=3 {$(CY)= 0; }
+
+:CLR BitAddr is $(GROUP1) & ophi=12 & oplo=2; BitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & BitByteAddr { local tmp = ~(1<>sfrbit)&1) == 1:1) goto Rel8; }
+:JBC BitAddr,Rel8 is $(GROUP1) & ophi=1 & oplo=0; BitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & BitByteAddr; Rel8 { tmp:1 = 1<>sfrbit)&1) == 1:1) goto Rel8; }
+:JBC BitAddr,Rel8 is $(GROUP1) & ophi=1 & oplo=0; BitAddr & sfrbit & BitByteAddr; Rel8 { tmp:1 = 1<>sfrbit)&1)==0:1) goto Rel8; }
+@if BIT_OPS == "BIT_ADDRS"
+:JNB BitAddr,Rel8 is $(GROUP1) & ophi=3 & oplo=0; BitAddr & sfrbit & BitByteAddr; Rel8 { if (BitAddr == 0:1) goto Rel8; }
+@elif BIT_OPS == "PCODEOPS"
+:JNB BitAddr,Rel8 is $(GROUP1) & ophi=3 & oplo=0; BitAddr & sfrbit & BitByteAddr; Rel8 { if (get(BitAddr, BitByteAddr)==0:1) goto Rel8; }
+@elif BIT_OPS == "SHIFTS"
+:JNB BitAddr,Rel8 is $(GROUP1) & ophi=3 & oplo=0; BitAddr & sfrbit & BitByteAddr; Rel8 { if (((BitByteAddr>>sfrbit)&1)==0:1) goto Rel8; }
+@endif
+
+:JNC Rel8 is $(GROUP1) & ophi=5 & oplo=0; Rel8 { if ($(CY) == 0) goto Rel8; }
+:JNZ Rel8 is $(GROUP1) & ophi=7 & oplo=0; Rel8 { if (ACC != 0) goto Rel8; }
+:JZ Rel8 is $(GROUP1) & ophi=6 & oplo=0; Rel8 { if (ACC == 0) goto Rel8; }
+
+@if defined(MCS80390)
+:LCALL Addr24 is $(GROUP1) & ophi=1 & oplo=2; Addr24 { ret:$(PTRSIZE) = inst_next; push24(ret); call Addr24; }
+:LJMP Addr24 is $(GROUP1) & ophi=0 & oplo=2; Addr24 { goto Addr24; }
+@elif defined(MX51)
+:LCALL Addr16 is $(GROUP1) & ophi=1 & oplo=2; Addr16 { ret:2 = inst_next; push16(ret); call Addr16; }
+:LJMP Addr16 is $(GROUP1) & ophi=0 & oplo=2; Addr16 { goto Addr16; }
+@else
+:LCALL Addr16 is $(GROUP1) & ophi=1 & oplo=2; Addr16 { ret:$(PTRSIZE) = inst_next; push16(ret); call Addr16; }
+:LJMP Addr16 is $(GROUP1) & ophi=0 & oplo=2; Addr16 { goto Addr16; }
+@endif
+
+:MOV Areg,rn is $(GROUP2) & ophi=14 & rnfill=1 & rn & Areg { ACC = rn; }
+:MOV Areg,Direct is $(GROUP1) & ophi=14 & oplo=5 & Areg; Direct { ACC = Direct; }
+:MOV Areg,Ri is $(GROUP2) & ophi=14 & Areg & rifill=3 & Ri { ACC = Ri; }
+:MOV Areg,Data is $(GROUP1) & ophi=7 & oplo=4 & Areg; Data { ACC = Data; }
+:MOV rn,Areg is $(GROUP2) & ophi=15 & rnfill=1 & rn & Areg { rn = ACC; }
+:MOV rn,Direct is $(GROUP2) & ophi=10 & rnfill=1 & rn; Direct { rn = Direct; }
+:MOV rn,Data is $(GROUP2) & ophi=7 & rnfill=1 & rn; Data { rn = Data; }
+:MOV Direct,Areg is $(GROUP1) & ophi=15 & oplo=5 & Areg; Direct { Direct = ACC; }
+:MOV Direct,rn is $(GROUP2) & ophi=8 & rnfill=1 & rn; Direct { Direct = rn; }
+:MOV Direct2,Direct is $(GROUP1) & ophi=8 & oplo=5; Direct; Direct2 { Direct2 = Direct; }
+:MOV Direct,Ri is $(GROUP2) & ophi=8 & rifill=3 & Ri; Direct { Direct = Ri; }
+:MOV Direct,Data is $(GROUP1) & ophi=7 & oplo=5; Direct; Data { Direct = Data; }
+:MOV Ri,Areg is $(GROUP2) & ophi=15 & rifill=3 & Ri & Areg { Ri = ACC; }
+:MOV Ri,Direct is $(GROUP2) & ophi=10 & rifill=3 & Ri; Direct { Ri = Direct; }
+:MOV Ri,Data is $(GROUP2) & ophi=7 & rifill=3 & Ri; Data { Ri = Data; }
+@if defined(MCS80390)
+:MOV DPTRreg,Data24 is $(GROUP1) & ophi=9 & oplo=0 & DPTRreg; Data24 { DPTR = Data24; }
+@else
+:MOV DPTRreg,Data16 is $(GROUP1) & ophi=9 & oplo=0 & DPTRreg; Data16 { DPTR = Data16; }
+@endif
+
+:MOV CY,BitAddr is $(GROUP1) & CY & ophi=10 & oplo=2; BitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & BitByteAddr {$(CY)= (BitByteAddr>>sfrbit)&1; }
+:MOV BitAddr,CY is $(GROUP1) & CY & ophi=9 & oplo=2; BitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & BitByteAddr { BitByteAddr = BitByteAddr & (~(1<>sfrbit)&1; }
+:MOV BitAddr,CY is $(GROUP1) & CY & ophi=9 & oplo=2; BitAddr & sfrbit & BitByteAddr { BitByteAddr = BitByteAddr & (~(1<>sfrbit)&1); }
+:ORL CY,BitAddr2 is $(GROUP1) & CY & ophi=10 & oplo=0; BitAddr2 & bitaddr57=7 & sfrbit3=0 & sfrbit & BitByteAddr {$(CY)=$(CY)| (((BitByteAddr>>sfrbit)&1)^1); }
+@if BIT_OPS == "BIT_ADDRS"
+:ORL CY,BitAddr is $(GROUP1) & CY & ophi=7 & oplo=2; BitAddr & sfrbit & BitByteAddr {$(CY)=$(CY)| BitAddr; }
+:ORL CY,BitAddr2 is $(GROUP1) & CY & ophi=10 & oplo=0; BitAddr2 & sfrbit & BitByteAddr {$(CY)=$(CY)| (BitAddr2^1); }
+@elif BIT_OPS == "PCODEOPS"
+:ORL CY,BitAddr is $(GROUP1) & CY & ophi=7 & oplo=2; BitAddr & sfrbit & BitByteAddr {$(CY)=$(CY)| get(BitAddr, BitByteAddr); }
+:ORL CY,BitAddr2 is $(GROUP1) & CY & ophi=10 & oplo=0; BitAddr2 & sfrbit & BitByteAddr {$(CY)=$(CY)| (get(BitAddr2, BitByteAddr)^1); }
+@elif BIT_OPS == "SHIFTS"
+:ORL CY,BitAddr is $(GROUP1) & CY & ophi=7 & oplo=2; BitAddr & sfrbit & BitByteAddr {$(CY)=$(CY)| ((BitByteAddr>>sfrbit)&1); }
+:ORL CY,BitAddr2 is $(GROUP1) & CY & ophi=10 & oplo=0; BitAddr2 & sfrbit & BitByteAddr {$(CY)=$(CY)| (((BitByteAddr>>sfrbit)&1)^1); }
+@endif
+
+:POP Direct is $(GROUP1) & ophi=13 & oplo=0; Direct { pop8(Direct); }
+
+:PUSH Direct is $(GROUP1) & ophi=12 & oplo=0; Direct { push8(Direct); }
+
+:RET is $(GROUP1) & ophi=2 & oplo=2 {
+@if defined(MCS251) || defined(MX51)
+pc:2 = 0; pop16(pc); pc3:3 = (inst_next & 0xff0000) + zext(pc); return[pc3];
+@elif defined(MCS51)
+pc:2 = 0; pop16(pc); return[pc];
+@elif defined(MCS80390)
+pc:3 = 0; pop24(pc); return[pc];
+@endif
+}
+
+:RETI is $(GROUP1) & ophi=3 & oplo=2 {
+@if defined(MCS251) || defined(MX51)
+pc:2 = 0; pop16(pc); pc3:3 = (inst_next & 0xff0000) + zext(pc); return[pc3];
+@elif defined(MCS51)
+pc:2 = 0; pop16(pc); return[pc];
+@elif defined(MCS80390)
+pc:3 = 0; pop24(pc); return[pc];
+@endif
+}
+
+:RL Areg is $(GROUP1) & ophi=2 & oplo=3 & Areg { ACC = (ACC<<1) | (ACC>>7); }
+:RLC Areg is $(GROUP1) & ophi=3 & oplo=3 & Areg { tmp : 1 = (ACC&0x80)>>7; ACC = (ACC<<1) | $(CY);$(CY)= tmp; }
+:RR Areg is $(GROUP1) & ophi=0 & oplo=3 & Areg { ACC = (ACC>>1) | (ACC<<7); }
+:RRC Areg is $(GROUP1) & ophi=1 & oplo=3 & Areg { tmp : 1 = ACC&1; ACC = (ACC>>1) | ($(CY)<<7);$(CY)= tmp; }
+
+:SETB CY is $(GROUP1) & CY & ophi=13 & oplo=3 { $(CY)=1; }
+
+:SETB BitAddr is $(GROUP1) & ophi=13 & oplo=2; BitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & BitByteAddr { BitByteAddr = BitByteAddr | (1<>4) | (ACC<<4); }
+
+:XCH Areg,rn is $(GROUP2) & ophi=12 & rnfill=1 & rn & Areg { tmp : 1 = ACC; ACC = rn; rn = tmp; }
+:XCH Areg,Direct is $(GROUP1) & ophi=12 & oplo=5 & Areg; Direct { tmp : 1 = ACC; ACC = Direct; Direct = tmp; }
+:XCH Areg,Ri is $(GROUP2) & ophi=12 & rifill=3 & Ri & Areg { tmp : 1 = ACC; ACC = Ri; Ri = tmp; }
+
+# TODO: This instruction appears to be in both GROUP2 & GROUP3 (always available)
+:XCHD Areg,Ri is ophi=13 & Areg & rifill=3 & Ri { tmp : 1 = ACC & 0xf; ACC = (ACC&0xf0) | (Ri&0xf); Ri = (Ri&0xf0) | tmp; }
+
+:XRL Areg,rn is $(GROUP2) & ophi=6 & rnfill=1 & rn & Areg { ACC = ACC ^ rn; }
+:XRL Areg,Direct is $(GROUP1) & ophi=6 & oplo=5 & Areg; Direct { ACC = ACC ^ Direct; }
+:XRL Areg,Ri is $(GROUP2) & ophi=6 & rifill=3 & Ri & Areg { ACC = ACC ^ Ri; }
+:XRL Areg,Data is $(GROUP1) & ophi=6 & oplo=4 & Areg; Data { ACC = ACC ^ Data; }
+:XRL Direct,Areg is $(GROUP1) & ophi=6 & oplo=2 & Areg; Direct { Direct = Direct ^ ACC; }
+:XRL Direct,Data is $(GROUP1) & ophi=6 & oplo=3; Direct; Data { Direct = Direct ^ Data; }
+
diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/mx51.cspec b/python/icicle/Ghidra/Processors/8051/data/languages/mx51.cspec
new file mode 100644
index 0000000..2af7a38
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/8051/data/languages/mx51.cspec
@@ -0,0 +1,73 @@
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diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/mx51.pspec b/python/icicle/Ghidra/Processors/8051/data/languages/mx51.pspec
new file mode 100644
index 0000000..ea50e2c
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/8051/data/languages/mx51.pspec
@@ -0,0 +1,423 @@
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diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/mx51.sinc b/python/icicle/Ghidra/Processors/8051/data/languages/mx51.sinc
new file mode 100644
index 0000000..9279c1e
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/8051/data/languages/mx51.sinc
@@ -0,0 +1,332 @@
+# Extended mx51 instructions live here, so as to avoid further
+# complicating the main 8051 file.
+
+# All have 0xa5 as prefix, so subtract one
+define token TwoByteOp (8)
+ b2op = (0,7)
+;
+define token ThreeByteOp (16)
+ b3op = (8,15)
+;
+define token FourByteOp (24)
+ b4op = (16,23)
+;
+
+define token EcallDispTok (24)
+ imm24 = (0,23)
+;
+
+####################
+
+# Note that PRi is used in little endian format, as R3 is the MSB
+attach variables PRi_revend [ R1R2R3 R5R6R7 ];
+@define ENDIANSWAPFUNC ""
+@if defined(ENDIANSWAPFUNC)
+define pcodeop endian_swap;
+PRi: PRi_revend is PRi_revend { tmp:3 = endian_swap(PRi_revend); export tmp; }
+@else
+PRi: PRi_revend is PRi_sel=0 & PRi_revend { tmp:3 = (zext(R3) << 16) | (zext(R2) << 8) | zext(R1); export tmp; }
+PRi: PRi_revend is PRi_sel=1 & PRi_revend { tmp:3 = (zext(R7) << 16) | (zext(R6) << 8) | zext(R5); export tmp; }
+@endif
+####################
+
+@ifdef OMIT_RETADDR
+macro push24(val) { val = val; }
+macro pop24(val) { val = val; }
+
+@else
+# stack grows up.
+macro push24(val) {
+ ptr:3 = zext(SP) + 1 + $(STACKBASE);
+ *[RAM]:3 ptr = val;
+ SP = SP + 2;
+}
+macro pop24(val) {
+ ptr:3 = zext(SP - 2) + $(STACKBASE);
+ val = *[RAM]:3 ptr;
+ SP = SP - 3;
+}
+@endif
+
+####################
+
+eptrReg: EPTR is EPTR { export EPTR; }
+APlusEptr: "@"Areg"+"eptrReg is Areg & eptrReg { tmp:3 = EPTR + zext(ACC); export tmp; }
+ecallImmAddr: imm24 is imm24 { export *:1 imm24; }
+add_with_pr_const: emov_delta is emov_delta { tmp:1 = emov_delta; export tmp; }
+add_with_pr_const: "4" is emov_delta = 0 { tmp:1 = 4; export tmp; }
+
+EDirect: mainreg is bank=0 & mainreg { tmp:3 = mainreg + 0x7f0000; export *[RAM]:1 tmp; }
+EDirect: direct is bank=1 & direct { export *[ESFR]:1 direct; }
+EDirect: EPL is bank=1 & direct=0xfc & EPL { export EPL; }
+EDirect: EPM is bank=1 & direct=0xfd & EPM { export EPM; }
+EDirect: EPH is bank=1 & direct=0xfe & EPH { export EPH; }
+
+EDirect2: mainreg2 is bank2=0 & mainreg2 { tmp:3 = mainreg2 + 0x7f0000; export *[RAM]:1 tmp; }
+EDirect2: direct2 is bank2=1 & direct2 { export *[ESFR]:1 direct2; }
+EDirect2: EPL is bank2=1 & direct2=0xfc & EPL { export EPL; }
+EDirect2: EPM is bank2=1 & direct2=0xfd & EPM { export EPM; }
+EDirect2: EPH is bank2=1 & direct2=0xfe & EPH { export EPH; }
+
+# Continuing with pattern via copying from stock 8051 sleighspec.
+# Note that there is a known bug with the Bit addressing of the SFR.
+EBitAddr: bitaddr is bitbank=1 & sfrbyte & sfrbit [ bitaddr =(sfrbyte << 3)+sfrbit; ] { export *[EBITS]:1 bitaddr; }
+EBitAddr: bitaddr is bitbank=0 & lowbyte & sfrbit [ bitaddr =(lowbyte << 3)+sfrbit; ] { export *[EBITS]:1 bitaddr; }
+EBitAddr2: "/"bitaddr is bitbank=1 & sfrbyte & sfrbit [ bitaddr =(sfrbyte << 3)+sfrbit; ] { export *[EBITS]:1 bitaddr; }
+EBitAddr2: "/"bitaddr is bitbank=0 & lowbyte & sfrbit [ bitaddr =(lowbyte << 3)+sfrbit; ] { export *[EBITS]:1 bitaddr; }
+
+EBitByteAddr: byteaddr is bitbank=1 & sfrbyte & sfrbit [ byteaddr =(sfrbyte << 3); ] { export *[ESFR]:1 byteaddr; }
+EBitByteAddr: byteaddr is bitbank=0 & lowbyte & sfrbit [ byteaddr = lowbyte + 0x20; ] { tmp:3 = byteaddr + 0x7f0000; export *[RAM]:1 tmp; }
+
+
+####################
+
+:inc EDirect is opfull=0xa5; ophi=0 & oplo=5; EDirect {
+ EDirect = EDirect + 1;
+}
+:dec EDirect is opfull=0xa5; opfull=0x15; EDirect {
+ EDirect = EDirect - 1;
+}
+:add Areg,EDirect is opfull=0xa5; opfull=0x25 & Areg; EDirect {
+ addflags(ACC,EDirect); ACC = ACC + EDirect; resultflags(ACC);
+}
+:addc Areg,EDirect is opfull=0xa5; opfull=0x35 & Areg; EDirect {
+ tmp:1 =$(CY)+ EDirect; addflags(ACC,tmp); ACC = ACC + tmp; resultflags(ACC);
+}
+:orl Areg,EDirect is opfull=0xa5; opfull=0x45 & Areg; EDirect {
+ ACC = ACC | EDirect;
+}
+:anl Areg,EDirect is opfull=0xa5; opfull=0x55 & Areg; EDirect {
+ ACC = ACC & EDirect; resultflags(ACC);
+}
+:xrl Areg,EDirect is opfull=0xa5; opfull=0x65 & Areg; EDirect {
+ ACC = ACC ^ EDirect;
+}
+:subb Areg,EDirect is opfull=0xa5; opfull=0x95 & Areg; EDirect {
+ tmp:1 = EDirect+$(CY); subflags(ACC,tmp); ACC = ACC - tmp;
+}
+:xch Areg,EDirect is opfull=0xa5; opfull=0xc5 & Areg; EDirect {
+ tmp:1 = ACC; ACC = EDirect; EDirect = tmp;
+}
+:mov Areg,EDirect is opfull=0xa5; opfull=0xe5 & Areg; EDirect {
+ ACC = EDirect;
+}
+:mov EDirect,Areg is opfull=0xa5; opfull=0xf5 & Areg; EDirect {
+ EDirect = ACC;
+}
+:mov EDirect,rn is opfull=0xa5; ophi=0x8 & rnfill=1 & rn; EDirect {
+ EDirect = rn;
+}
+:mov rn,EDirect is opfull=0xa5; ophi=0xa & rnfill=1 & rn; EDirect {
+ rn = EDirect;
+}
+:mov EDirect2,EDirect is opfull=0xa5; ophi=8 & oplo=5; EDirect; EDirect2 {
+ EDirect2 = EDirect;
+}
+:mov EDirect,Data is opfull=0xa5; ophi=7 & oplo=5; EDirect; Data {
+ EDirect = Data;
+}
+:mov EDirect,Ri is opfull=0xa5; ophi=8 & rifill=3 & Ri; EDirect {
+ EDirect = Ri;
+}
+:mov Ri,EDirect is opfull=0xa5; ophi=10 & rifill=3 & Ri; EDirect {
+ Ri = EDirect;
+}
+:orl EDirect,Areg is opfull=0xa5; ophi=4 & oplo=2 & Areg; EDirect {
+ EDirect = EDirect | ACC;
+}
+:anl EDirect,Areg is opfull=0xa5; ophi=5 & oplo=2 & Areg; EDirect {
+ tmp:1 = EDirect & ACC; EDirect = tmp; resultflags(tmp);
+}
+:xrl EDirect,Areg is opfull=0xa5; ophi=6 & oplo=2 & Areg; EDirect {
+ EDirect = EDirect ^ ACC;
+}
+:xrl EDirect,Data is opfull=0xa5; ophi=6 & oplo=3; EDirect; Data {
+ EDirect = EDirect ^ Data;
+}
+:anl EDirect,Data is opfull=0xa5; ophi=5 & oplo=3; EDirect; Data {
+ tmp:1 = EDirect & Data; EDirect = tmp; resultflags(tmp);
+}
+:orl EDirect,Data is opfull=0xa5; ophi=4 & oplo=3 & Areg; EDirect; Data {
+ EDirect = EDirect | Data;
+}
+:push EDirect is opfull=0xa5; opfull=0xc0; EDirect {
+ push8(EDirect);
+}
+:pop EDirect is opfull=0xa5; opfull=0xd0; EDirect {
+ pop8(EDirect);
+}
+:cjne Areg,EDirect,Rel8 is opfull=0xa5; ophi=11 & oplo=5 & Areg; EDirect; Rel8 {
+ compflags(ACC,EDirect); if (ACC!=EDirect) goto Rel8;
+}
+:djnz EDirect,Rel8 is opfull=0xa5; ophi=13 & oplo=5; EDirect; Rel8 {
+ EDirect = EDirect - 1;
+ if (EDirect!=0) goto Rel8;
+}
+
+
+# EPTR operations
+:ejmp ecallImmAddr is opfull=0xa5; opfull=0x02; ecallImmAddr {
+ goto ecallImmAddr;
+}
+:ecall ecallImmAddr is opfull=0xa5; opfull=0x12; ecallImmAddr {
+ ret:3 = inst_next; push24(ret); call ecallImmAddr;
+}
+:mov eptrReg,ecallImmAddr is opfull=0xa5; opfull=0x90; ecallImmAddr & eptrReg & imm24 {
+ EPTR = imm24;
+}
+:eret is opfull=0xa5; opfull=0x22 {
+ pc:3 = 0; pop24(pc); return[pc];
+}
+:jmp APlusEptr is opfull=0xa5; opfull=0x73 & APlusEptr {
+ # this is correct, but causes disassembler problems
+ # goto APlusEptr;
+ # added additional indirection to stop disassembler problems.
+ goto [APlusEptr];
+}
+:movx Areg",@"eptrReg is opfull=0xa5; opfull=0xe0 & Areg & eptrReg {
+ ACC = *:1 EPTR;
+}
+:movx "@"eptrReg,Areg is opfull=0xa5; opfull=0xf0 & Areg & eptrReg {
+ *:1 EPTR = ACC;
+}
+:movc Areg,APlusEptr is opfull=0xa5; opfull=0x93 & Areg & APlusEptr {
+ ACC = *:1 APlusEptr;
+}
+:inc EPTR is opfull=0xa5; opfull=0xa3 & EPTR {
+ EPTR = EPTR + 1;
+}
+
+# PRi operations
+:emov Areg",@"PRi"+"emov_delta is opfull=0xa5; ophi=4 & PRi & emov_delta & Areg {
+ tmp:3 = zext(PRi) + emov_delta;
+ ACC = *:1 tmp;
+}
+:emov "@"PRi"+"emov_delta,Areg is opfull=0xa5; ophi=5 & PRi & emov_delta & Areg {
+ tmp:3 = PRi + emov_delta;
+ *:1 tmp = ACC;
+}
+:add PRi_revend,add_with_pr_const is opfull=0xa5; ophi=6 & PRi_revend & PRi & add_with_pr_const {
+ x:3 = zext(add_with_pr_const);
+ tmp:3 = PRi + x;
+@if defined(ENDIANSWAPFUNC)
+ y:3 = endian_swap(tmp);
+@else
+ y:3 = (tmp << 16) | (tmp & 0x00ff00) | zext(tmp >> 16);
+@endif
+ PRi_revend = y;
+}
+
+# bit operations
+:anl CY,EBitAddr is opfull=0xa5; CY & ophi=8 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr {tmp:1 = EBitByteAddr; $(CY)=$(CY)& ((tmp>>sfrbit)&1); resultflags(tmp); }
+:anl CY,EBitAddr2 is opfull=0xa5; CY & ophi=11 & oplo=0; EBitAddr2 & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr {tmp:1 = EBitByteAddr; $(CY)=$(CY)& (~((tmp>>sfrbit)&1)); }
+@if BIT_OPS == "BIT_ADDRS"
+:anl CY,EBitAddr is opfull=0xa5; CY & ophi=8 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)& EBitAddr; }
+:anl CY,EBitAddr2 is opfull=0xa5; CY & ophi=11 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)& ~EBitAddr2; }
+@elif BIT_OPS == "PCODEOPS"
+:anl CY,EBitAddr is opfull=0xa5; CY & ophi=8 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)& get(EBitAddr, EBitByteAddr); }
+:anl CY,EBitAddr2 is opfull=0xa5; CY & ophi=11 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)& (get(EBitAddr2, EBitByteAddr)^1); }
+@elif BIT_OPS == "SHIFTS"
+:anl CY,EBitAddr is opfull=0xa5; CY & ophi=8 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)& ((EBitByteAddr>>sfrbit)&1); }
+:anl CY,EBitAddr2 is opfull=0xa5; CY & ophi=11 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)& (~((EBitByteAddr>>sfrbit)&1)); }
+@endif
+
+:clr EBitAddr is opfull=0xa5; ophi=12 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr { tmp:1 = ~(1<>sfrbit)&1) == 1:1) goto Rel8; }
+:jbc EBitAddr,Rel8 is opfull=0xa5; ophi=1 & oplo=0; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr; Rel8 { tmp:1 = 1<>sfrbit)&1) == 1:1) goto Rel8; }
+:jbc EBitAddr,Rel8 is opfull=0xa5; ophi=1 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { tmp:1 = 1<>sfrbit)&1)==0:1) goto Rel8; }
+@if BIT_OPS == "BIT_ADDRS"
+:jnb EBitAddr,Rel8 is opfull=0xa5; ophi=3 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { if (EBitAddr == 0:1) goto Rel8; }
+@elif BIT_OPS == "PCODEOPS"
+:jnb EBitAddr,Rel8 is opfull=0xa5; ophi=3 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { if (get(EBitAddr, EBitByteAddr)==0:1) goto Rel8; }
+@elif BIT_OPS == "SHIFTS"
+:jnb EBitAddr,Rel8 is opfull=0xa5; ophi=3 & oplo=0; EBitAddr & sfrbit & EBitByteAddr; Rel8 { if (((EBitByteAddr>>sfrbit)&1)==0:1) goto Rel8; }
+@endif
+
+:mov CY,EBitAddr is opfull=0xa5; CY & ophi=10 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr {$(CY)= (EBitByteAddr>>sfrbit)&1; }
+:mov EBitAddr,CY is opfull=0xa5; CY & ophi=9 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr { EBitByteAddr = EBitByteAddr & (~(1<>sfrbit)&1; }
+:mov EBitAddr,CY is opfull=0xa5; CY & ophi=9 & oplo=2; EBitAddr & sfrbit & EBitByteAddr { EBitByteAddr = EBitByteAddr & (~(1<>sfrbit)&1); }
+:orl CY,EBitAddr2 is opfull=0xa5; CY & ophi=10 & oplo=0; EBitAddr2 & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr {$(CY)=$(CY)| (((EBitByteAddr>>sfrbit)&1)^1); }
+@if BIT_OPS == "BIT_ADDRS"
+:orl CY,EBitAddr is opfull=0xa5; CY & ophi=7 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)| EBitAddr; }
+:orl CY,EBitAddr2 is opfull=0xa5; CY & ophi=10 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)| (EBitAddr2^1); }
+@elif BIT_OPS == "PCODEOPS"
+:orl CY,EBitAddr is opfull=0xa5; CY & ophi=7 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)| get(EBitAddr, EBitByteAddr); }
+:orl CY,EBitAddr2 is opfull=0xa5; CY & ophi=10 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)| (get(EBitAddr2, EBitByteAddr)^1); }
+@elif BIT_OPS == "SHIFTS"
+:orl CY,EBitAddr is opfull=0xa5; CY & ophi=7 & oplo=2; EBitAddr & sfrbit & EBitByteAddr {$(CY)=$(CY)| ((EBitByteAddr>>sfrbit)&1); }
+:orl CY,EBitAddr2 is opfull=0xa5; CY & ophi=10 & oplo=0; EBitAddr2 & sfrbit & EBitByteAddr {$(CY)=$(CY)| (((EBitByteAddr>>sfrbit)&1)^1); }
+@endif
+
+:setb EBitAddr is opfull=0xa5; ophi=13 & oplo=2; EBitAddr & bitaddr57=7 & sfrbit3=0 & sfrbit & EBitByteAddr { EBitByteAddr = EBitByteAddr | (1<
+
+
+ 8051:BE:16:default
+ 8051
+ default
+ 16
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/python/icicle/Ghidra/Processors/8051/data/languages/old/8051v1.trans b/python/icicle/Ghidra/Processors/8051/data/languages/old/8051v1.trans
new file mode 100644
index 0000000..b89b870
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/8051/data/languages/old/8051v1.trans
@@ -0,0 +1,8 @@
+
+
+ 8051:BE:16:default
+ 8051:BE:16:default
+
+
+
+
diff --git a/python/icicle/Ghidra/Processors/8085/data/languages/8085.cspec b/python/icicle/Ghidra/Processors/8085/data/languages/8085.cspec
new file mode 100644
index 0000000..cfd08b5
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/8085/data/languages/8085.cspec
@@ -0,0 +1,28 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/python/icicle/Ghidra/Processors/8085/data/languages/8085.ldefs b/python/icicle/Ghidra/Processors/8085/data/languages/8085.ldefs
new file mode 100644
index 0000000..85c72dc
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/8085/data/languages/8085.ldefs
@@ -0,0 +1,15 @@
+
+
+
+
+ Intel 8085
+
+
+
diff --git a/python/icicle/Ghidra/Processors/8085/data/languages/8085.pspec b/python/icicle/Ghidra/Processors/8085/data/languages/8085.pspec
new file mode 100644
index 0000000..8e13263
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/8085/data/languages/8085.pspec
@@ -0,0 +1,30 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/python/icicle/Ghidra/Processors/8085/data/languages/8085.slaspec b/python/icicle/Ghidra/Processors/8085/data/languages/8085.slaspec
new file mode 100644
index 0000000..e69108a
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/8085/data/languages/8085.slaspec
@@ -0,0 +1,551 @@
+# sleigh specification file for Intel 8085
+
+define endian=little;
+define alignment=1;
+
+define space ram type=ram_space size=2 default;
+define space io type=ram_space size=1;
+define space register type=register_space size=1;
+
+define register offset=0x00 size=1 [ F A C B E D L H ];
+define register offset=0x00 size=2 [ AF BC DE HL ];
+define register offset=0x10 size=1 [ A_ F_ B_ C_ D_ E_ H_ L_ ]; # Alternate registers
+define register offset=0x10 size=2 [ AF_ BC_ DE_ HL_ ]; # Alternate registers
+define register offset=0x20 size=2 [ PC SP ];
+
+# Flag bits
+# CY: Carry
+# P: Parity/Overflow
+# AC: Half Carry (Auxiliary flag)
+# Z: Zero
+# S: Sign
+define register offset=0x30 size=1 [ S_flag Z_flag AC_flag P_flag CY_flag ];
+
+define token opbyte (8)
+ op0_8 = (0,7)
+ op6_2 = (6,7)
+
+ dRegPair4_2 = (4,5)
+ pRegPair4_2 = (4,5)
+ sRegPair4_2 = (4,5)
+ qRegPair4_2 = (4,5)
+ rRegPair4_2 = (4,5)
+
+ reg3_3 = (3,5)
+ bits3_3 = (3,5)
+
+ bits0_4 = (0,3)
+
+ reg0_3 = (0,2)
+ bits0_3 = (0,2)
+;
+
+define token data8 (8)
+ imm8 = (0,7)
+ sign8 = (7,7)
+ simm8 = (0,7) signed
+;
+
+define token data16 (16)
+ imm16 = (0,15)
+ sign16 = (15,15)
+ simm16 = (0,15) signed
+;
+
+attach variables [ reg0_3 reg3_3 ] [ B C D E H L _ A ];
+
+attach variables [ sRegPair4_2 dRegPair4_2 ] [ BC DE HL SP ];
+attach variables [ qRegPair4_2 ] [ BC DE HL AF ];
+
+################################################################
+# Pseudo Instructions
+################################################################
+
+define pcodeop BCDadjust;
+define pcodeop hasEvenParity;
+define pcodeop disableMaskableInterrupts;
+define pcodeop enableMaskableInterrupts;
+define pcodeop readInterruptMask;
+define pcodeop setInterruptMask;
+
+################################################################
+# Macros
+################################################################
+
+macro setResultFlags(result) {
+ Z_flag = (result == 0);
+ S_flag = (result s< 0);
+}
+
+macro setAddCarryFlags(op1,op2) {
+ CY_flag = (carry(op1,zext(CY_flag)) || carry(op2,op1 + zext(CY_flag)));
+# P_flag = (scarry(op1,CY_flag) || scarry(op2,op1 + CY_flag));
+# AC_flag = ??
+}
+
+macro setAddFlags(op1,op2) {
+ CY_flag = carry(op1,op2);
+# P_flag = scarry(op1,op2);
+# AC_flag = ??
+}
+
+macro setSubtractCarryFlags(op1,op2) {
+ local notC = ~CY_flag;
+ CY_flag = ((op1 < sext(notC)) || (op2 < (op1 - sext(notC))));
+}
+
+macro setSubtractFlags(op1,op2) {
+ CY_flag = (op1 < op2);
+}
+
+macro push16(val16) {
+ SP = SP - 2;
+ *:2 SP = val16;
+}
+
+macro pop16(ret16) {
+ ret16 = *:2 SP;
+ SP = SP + 2;
+}
+
+################################################################
+
+Mem8: (imm16) is imm16 { export *:1 imm16; }
+Mem16: (imm16) is imm16 { export *:2 imm16; }
+
+Addr16: imm16 is imm16 { export *:1 imm16; }
+
+RstAddr: loc is bits3_3 [ loc = bits3_3 << 3; ] { export *:1 loc; }
+
+IOAddr8: (imm8) is imm8 { export *[io]:1 imm8; }
+
+cc: "NZ" is bits3_3=0x0 { c:1 = (Z_flag == 0); export c; }
+cc: "Z" is bits3_3=0x1 { export Z_flag; }
+cc: "NC" is bits3_3=0x2 { c:1 = (CY_flag == 0); export c; }
+cc: "C" is bits3_3=0x3 { export CY_flag; }
+cc: "PO" is bits3_3=0x4 { c:1 = (P_flag == 0); export c; }
+cc: "PE" is bits3_3=0x5 { export P_flag; }
+cc: "P" is bits3_3=0x6 { c:1 = (S_flag == 0); export c; }
+cc: "M" is bits3_3=0x7 { export S_flag; }
+
+################################################################
+
+:MOV reg3_3,reg0_3 is op6_2=0x1 & reg3_3 & reg0_3 {
+ reg3_3 = reg0_3;
+}
+
+:MVI reg3_3,imm8 is op6_2=0x0 & reg3_3 & bits0_3=0x6; imm8 {
+ reg3_3 = imm8;
+}
+
+:MOV reg3_3,(HL) is op6_2=0x1 & reg3_3 & bits0_3=0x6 & HL {
+ ptr:2 = HL;
+ reg3_3 = *:1 ptr;
+}
+
+:MOV (HL),reg0_3 is op6_2=0x1 & bits3_3=0x6 & reg0_3 & HL {
+ ptr:2 = HL;
+ *:1 ptr = reg0_3;
+}
+
+:MVI (HL),imm8 is op0_8=0x36 & HL; imm8 {
+ ptr:2 = HL;
+ *:1 ptr = imm8;
+}
+
+:LDAX (BC) is op0_8=0x0a & BC {
+ ptr:2 = BC;
+ A = *:1 ptr;
+}
+
+:LDAX (DE) is op0_8=0x1a & DE {
+ ptr:2 = DE;
+ A = *:1 ptr;
+}
+
+:LDA Mem8 is op0_8=0x3a; Mem8 {
+ A = Mem8;
+}
+
+:STAX (BC) is op0_8=0x2 & BC {
+ ptr:2 = BC;
+ *:1 ptr = A;
+}
+
+:STAX (DE) is op0_8=0x12 & DE {
+ ptr:2 = DE;
+ *:1 ptr = A;
+}
+
+:STA Mem8 is op0_8=0x32; Mem8 {
+ Mem8 = A;
+}
+
+:LXI dRegPair4_2,imm16 is op6_2=0x0 & dRegPair4_2 & bits0_4=0x1; imm16 {
+ dRegPair4_2 = imm16;
+}
+
+:LHLD Mem16 is op0_8=0x2a; Mem16 {
+ HL = Mem16;
+}
+
+:SHLD Mem16 is op0_8=0x22; Mem16 {
+ Mem16 = HL;
+}
+
+:SPHL is op0_8=0xf9 {
+ SP = HL;
+}
+
+:PUSH qRegPair4_2 is op6_2=0x3 & qRegPair4_2 & bits0_4=0x5 {
+ push16(qRegPair4_2);
+}
+
+:POP qRegPair4_2 is op6_2=0x3 & qRegPair4_2 & bits0_4=0x1 {
+ pop16(qRegPair4_2);
+}
+
+:XCHG is op0_8=0xeb {
+ tmp:2 = DE;
+ DE = HL;
+ HL = tmp;
+}
+
+:XTHL is op0_8=0xe3 {
+ tmp:2 = *:2 SP;
+ *:2 SP = HL;
+ HL = tmp;
+}
+
+:ADD reg0_3 is op6_2=0x2 & bits3_3=0x0 & reg0_3 {
+ setAddFlags(A,reg0_3);
+ A = A + reg0_3;
+ setResultFlags(A);
+}
+
+:ADI imm8 is op0_8=0xc6; imm8 {
+ setAddFlags(A,imm8);
+ A = A + imm8;
+ setResultFlags(A);
+}
+
+:ADD (HL) is op0_8=0x86 & HL {
+ val:1 = *:1 HL;
+ setAddFlags(A,val);
+ A = A + val;
+ setResultFlags(A);
+}
+
+:ADC reg0_3 is op6_2=0x2 & bits3_3=0x1 & reg0_3 {
+ setAddCarryFlags(A,reg0_3);
+ A = A + reg0_3 + CY_flag;
+ setResultFlags(A);
+}
+
+:ACI imm8 is op0_8=0xce; imm8 {
+ setAddCarryFlags(A,imm8);
+ A = A + imm8 + CY_flag;
+ setResultFlags(A);
+}
+
+:ADC (HL) is op0_8=0x8e & HL {
+ val:1 = *:1 HL;
+ setAddCarryFlags(A,val);
+ A = A + val + CY_flag;
+ setResultFlags(A);
+}
+
+:SUB reg0_3 is op6_2=0x2 & bits3_3=0x2 & reg0_3 {
+ setSubtractFlags(A,reg0_3);
+ A = A - reg0_3;
+ setResultFlags(A);
+}
+
+:SUI imm8 is op0_8=0xd6; imm8 {
+ setSubtractFlags(A,imm8);
+ A = A - imm8;
+ setResultFlags(A);
+}
+
+:SUB (HL) is op0_8=0x96 & HL {
+ val:1 = *:1 HL;
+ setSubtractFlags(A,val);
+ A = A - val;
+ setResultFlags(A);
+}
+
+:SBB reg0_3 is op6_2=0x2 & bits3_3=0x3 & reg0_3 {
+ setSubtractCarryFlags(A,reg0_3);
+ A = A - reg0_3 - CY_flag;
+ setResultFlags(A);
+}
+
+:SBI imm8 is op0_8=0xde; imm8 {
+ setSubtractCarryFlags(A,imm8);
+ A = A - imm8 - CY_flag;
+ setResultFlags(A);
+}
+
+:SBB (HL) is op0_8=0x9e & HL {
+ val:1 = *:1 HL;
+ setSubtractCarryFlags(A,val);
+ A = A - val - CY_flag;
+ setResultFlags(A);
+}
+
+:ANA reg0_3 is op6_2=0x2 & bits3_3=0x4 & reg0_3 {
+ AC_flag = 1;
+ CY_flag = 0;
+ P_flag = 0;
+ A = A & reg0_3;
+ setResultFlags(A);
+}
+
+:ANI imm8 is op0_8=0xe6; imm8 {
+ AC_flag = 1;
+ CY_flag = 0;
+ P_flag = 0;
+ A = A & imm8;
+ setResultFlags(A);
+}
+
+:ANA (HL) is op0_8=0xa6 & HL {
+ AC_flag = 1;
+ CY_flag = 0;
+ P_flag = 0;
+ A = A & *:1 HL;
+ setResultFlags(A);
+}
+
+:ORA reg0_3 is op6_2=0x2 & bits3_3=0x6 & reg0_3 {
+ AC_flag = 0;
+ CY_flag = 0;
+ P_flag = 0;
+ A = A | reg0_3;
+ setResultFlags(A);
+}
+
+:ORI imm8 is op0_8=0xf6; imm8 {
+ AC_flag = 0;
+ CY_flag = 0;
+ P_flag = 0;
+ A = A | imm8;
+ setResultFlags(A);
+}
+
+:ORA (HL) is op0_8=0xb6 & HL {
+ AC_flag = 0;
+ CY_flag = 0;
+ P_flag = 0;
+ A = A | *:1 HL;
+ setResultFlags(A);
+}
+
+:XRA reg0_3 is op6_2=0x2 & bits3_3=0x5 & reg0_3 {
+ AC_flag = 0;
+ CY_flag = 0;
+ P_flag = 0;
+ A = A ^ reg0_3;
+ setResultFlags(A);
+}
+
+:XRA (HL) is op0_8=0xae & HL {
+ AC_flag = 0;
+ CY_flag = 0;
+ P_flag = 0;
+ A = A ^ *:1 HL;
+ setResultFlags(A);
+}
+
+:XRI imm8 is op0_8=0xee; imm8 {
+ AC_flag = 0;
+ CY_flag = 0;
+ P_flag = 0;
+ A = A ^ imm8;
+ setResultFlags(A);
+}
+
+:CMP reg0_3 is op6_2=0x2 & bits3_3=0x7 & reg0_3 {
+ setSubtractFlags(A,reg0_3);
+ cmp:1 = A - reg0_3;
+ setResultFlags(cmp);
+}
+
+:CPI imm8 is op0_8=0xfe; imm8 {
+ setSubtractFlags(A,imm8);
+ cmp:1 = A - imm8;
+ setResultFlags(cmp);
+}
+
+:CMP (HL) is op0_8=0xbe & HL {
+ val:1 = *:1 HL;
+ setSubtractFlags(A,val);
+ cmp:1 = A - val;
+ setResultFlags(cmp);
+}
+
+:INR reg3_3 is op6_2=0x0 & reg3_3 & bits0_3=0x4 {
+ P_flag = (reg3_3 == 0x7f);
+ reg3_3 = reg3_3 + 1;
+ setResultFlags(reg3_3);
+}
+
+:INR (HL) is op0_8=0x34 & HL {
+ val:1 = *:1 HL;
+ P_flag = (val == 0x7f);
+ val = val + 1;
+ *:1 HL = val;
+ setResultFlags(val);
+}
+
+:DCR reg3_3 is op6_2=0x0 & reg3_3 & bits0_3=0x5 {
+ P_flag = (reg3_3 == 0x80);
+ reg3_3 = reg3_3 - 1;
+ setResultFlags(reg3_3);
+}
+
+:DCR (HL) is op0_8=0x35 & HL {
+ val:1 = *:1 HL;
+ P_flag = (val == 0x80);
+ val = val - 1;
+ *:1 HL = val;
+ setResultFlags(val);
+}
+
+:DAA is op0_8=0x27 {
+ A = BCDadjust(A);
+ setResultFlags(A);
+ P_flag = hasEvenParity(A);
+}
+
+:CMA is op0_8=0x2f {
+ A = ~A;
+}
+
+:CMC is op0_8=0x3f {
+ CY_flag = !CY_flag;
+}
+
+:STC is op0_8=0x37 {
+ CY_flag = 1;
+ AC_flag = 0;
+}
+
+:NOP is op0_8=0x0 {
+}
+
+:HALT is op0_8=0x76 {
+ goto inst_start;
+}
+
+:DI is op0_8=0xf3 {
+# IFF1 = 0;
+# IFF2 = 0;
+ disableMaskableInterrupts();
+}
+
+:EI is op0_8=0xfb {
+# IFF1 = 1;
+# IFF2 = 1;
+ enableMaskableInterrupts();
+}
+
+:RIM is op0_8=0x20 {
+ A = readInterruptMask();
+}
+
+:SIM is op0_8=0x30 {
+ setInterruptMask(A);
+}
+
+:DAD HL,sRegPair4_2 is op6_2=0x0 & sRegPair4_2 & bits0_4=0x9 & HL {
+ setAddFlags(HL,sRegPair4_2);
+ HL = HL + sRegPair4_2;
+}
+
+:INX sRegPair4_2 is op6_2=0x0 & sRegPair4_2 & bits0_4=0x3 {
+ sRegPair4_2 = sRegPair4_2 + 1;
+}
+
+:DCX sRegPair4_2 is op6_2=0x0 & sRegPair4_2 & bits0_4=0xb {
+ sRegPair4_2 = sRegPair4_2 - 1;
+}
+
+:RLC is op0_8=0x07 {
+ CY_flag = (A >> 7);
+ A = (A << 1) | CY_flag;
+ AC_flag = 0;
+}
+
+:RAL is op0_8=0x17 {
+ nextC:1 = (A >> 7);
+ A = (A << 1) | CY_flag;
+ CY_flag = nextC;
+ AC_flag = 0;
+}
+
+:RRC is op0_8=0x0f {
+ CY_flag = (A & 1);
+ A = (A >> 1) | (CY_flag << 7);
+ AC_flag = 0;
+}
+
+:RAR is op0_8=0x1f {
+ nextC:1 = (A & 1);
+ A = (A >> 1) | (CY_flag << 7);
+ CY_flag = nextC;
+ AC_flag = 0;
+}
+
+:JMP Addr16 is op0_8=0xc3; Addr16 {
+ goto Addr16;
+}
+
+:J^cc Addr16 is op6_2=0x3 & cc & bits0_3=0x2; Addr16 {
+ if (cc) goto Addr16;
+}
+
+:PCHL is op0_8=0xe9 {
+ goto [HL];
+}
+
+:CALL Addr16 is op0_8=0xcd; Addr16 {
+ tmp:2 = inst_next;
+ push16(tmp);
+ call Addr16;
+}
+
+:C^cc Addr16 is op6_2=0x3 & cc & bits0_3=0x4; Addr16 {
+ if (!cc) goto inst_next;
+ tmp:2 = inst_next;
+ push16(tmp);
+ call Addr16;
+}
+
+:RET is op0_8=0xc9 {
+ tmp:2 = 0;
+ pop16(tmp);
+ return [tmp];
+}
+
+:R^cc is op6_2=0x3 & cc & bits0_3=0x0 {
+ if (!cc) goto inst_next;
+ tmp:2 = 0;
+ pop16(tmp);
+ return [tmp];
+}
+
+:RST RstAddr is op6_2=0x3 & RstAddr & bits0_3=0x7 {
+ tmp:2 = inst_next;
+ push16(tmp);
+ call RstAddr;
+}
+
+:IN IOAddr8 is op0_8=0xdb; IOAddr8 {
+ A = IOAddr8;
+}
+
+:OUT IOAddr8 is op0_8=0xd3; IOAddr8 {
+ IOAddr8 = A;
+}
+
diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.cspec b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.cspec
new file mode 100644
index 0000000..72c97be
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.cspec
@@ -0,0 +1,205 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.dwarf b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.dwarf
new file mode 100644
index 0000000..c3ba26e
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.dwarf
@@ -0,0 +1,8 @@
+
+
+
+
+
+
+
+
diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.ldefs b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.ldefs
new file mode 100644
index 0000000..a33d0ca
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.ldefs
@@ -0,0 +1,64 @@
+
+
+
+ Generic ARM64 v8.5-A LE instructions, LE data, missing some 8.5 vector
+
+
+
+
+
+
+ Generic ARM64 v8.5-A LE instructions, BE data, missing some 8.5 vector
+
+
+
+
+
+ Generic ARM64 v8.5-A LE instructions, LE data, ilp32
+
+
+
+
+
+
+ Generic ARM64 v8.5-A LE instructions, BE data, ilp32
+
+
+
+
+
+
diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.opinion b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.opinion
new file mode 100644
index 0000000..f0f5c99
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.opinion
@@ -0,0 +1,17 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.pspec b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.pspec
new file mode 100644
index 0000000..47aeecd
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.pspec
@@ -0,0 +1,101 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.slaspec b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.slaspec
new file mode 100644
index 0000000..12cedc1
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64.slaspec
@@ -0,0 +1,5 @@
+
+@define DATA_ENDIAN "little"
+
+@include "AARCH64instructions.sinc"
+
diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64BE.slaspec b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64BE.slaspec
new file mode 100644
index 0000000..e1f3970
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64BE.slaspec
@@ -0,0 +1,5 @@
+
+@define DATA_ENDIAN "big"
+
+@include "AARCH64instructions.sinc"
+
diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_AMXext.sinc b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_AMXext.sinc
new file mode 100644
index 0000000..2082b6f
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_AMXext.sinc
@@ -0,0 +1,171 @@
+#
+# Apple AARCH64 extended matrix instructions
+# Contents based on evolving information published on Web
+#
+#
+
+define pcodeop __amx_ldx;
+define pcodeop __amx_ldy;
+define pcodeop __amx_stx;
+define pcodeop __amx_sty;
+define pcodeop __amx_ldz;
+define pcodeop __amx_stz;
+define pcodeop __amx_ldzi;
+define pcodeop __amx_stzi;
+define pcodeop __amx_extrx;
+define pcodeop __amx_extry;
+define pcodeop __amx_fma64;
+define pcodeop __amx_fms64;
+define pcodeop __amx_fma32;
+define pcodeop __amx_fms32;
+define pcodeop __amx_mac16;
+define pcodeop __amx_fma16;
+define pcodeop __amx_fms16;
+define pcodeop __amx_enable;
+define pcodeop __amx_disable;
+define pcodeop __amx_vecint;
+define pcodeop __amx_vecfp;
+define pcodeop __amx_matint;
+define pcodeop __amx_matfp;
+define pcodeop __amx_genlut;
+
+
+with : ImmS_ImmR_TestSet=1 {
+
+AMXAddr: is Rd_GPR64 {
+ addr:8 = Rd_GPR64 & 0x00FFFFFFFFFFFFFF;
+ export addr;
+}
+
+AMXRegOff: is Rd_GPR64 {
+ registerOff:8 = (Rd_GPR64 >> 56) & 0x1F;
+ export registerOff;
+}
+
+AMXSize: is Rd_GPR64 {
+ local size = ((Rd_GPR64 >> 62) & 1);
+ size = zext(size == 0) * 0x40 | zext(size ==1 ) * 0x80;
+ export size;
+}
+
+:__amx_ldx Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=0 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
+{
+ __amx_ldx(Rd_GPR64);
+}
+
+:__amx_ldy Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=1 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
+{
+ __amx_ldy(Rd_GPR64);
+}
+
+:__amx_stx Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=2 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
+{
+ __amx_stx(Rd_GPR64);
+}
+
+:__amx_sty Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=3 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
+{
+ __amx_sty(Rd_GPR64);
+}
+
+:__amx_ldz Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=4 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
+{
+ __amx_ldz(Rd_GPR64);
+}
+
+:__amx_stz Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=5 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
+{
+ __amx_stz(Rd_GPR64);
+}
+
+:__amx_ldzi Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=6 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
+{
+ __amx_ldzi(Rd_GPR64);
+}
+
+:__amx_stzi Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=7 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
+{
+ __amx_stzi(Rd_GPR64);
+}
+
+:__amx_extrx Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=8 & Rd_GPR64
+{
+ __amx_extrx(Rd_GPR64);
+}
+
+:__amx_extry Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=9 & Rd_GPR64
+{
+ __amx_extry(Rd_GPR64);
+}
+
+:__amx_fma64 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=10 & Rd_GPR64
+{
+ __amx_fma64(Rd_GPR64);
+}
+
+:__amx_fms64 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=11 & Rd_GPR64
+{
+ __amx_fms64(Rd_GPR64);
+}
+
+:__amx_fma32 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=12 & Rd_GPR64
+{
+ __amx_fma32(Rd_GPR64);
+}
+
+:__amx_fms32 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=13 & Rd_GPR64
+{
+ __amx_fms32(Rd_GPR64);
+}
+
+:__amx_mac16 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=14 & Rd_GPR64
+{
+ __amx_mac16(Rd_GPR64);
+}
+
+:__amx_fma16 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=15 & Rd_GPR64
+{
+ __amx_fma16(Rd_GPR64);
+}
+
+:__amx_fms16 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=16 & Rd_GPR64
+{
+ __amx_fms16(Rd_GPR64);
+}
+
+:__amxdisable is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=17 & b_0004=1
+{
+ __amx_disable();
+}
+
+:__amxenable is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=17 & b_0004=0
+{
+ __amx_enable();
+}
+
+:__amx_vecint Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=18 & Rd_GPR64
+{
+ __amx_vecint(Rd_GPR64);
+}
+
+:__amx_vecfp Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=19 & Rd_GPR64
+{
+ __amx_vecfp(Rd_GPR64);
+}
+
+:__amx_matint Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=20 & Rd_GPR64
+{
+ __amx_matint(Rd_GPR64);
+}
+
+:__amx_matfp Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=21 & Rd_GPR64
+{
+ __amx_matfp(Rd_GPR64);
+}
+
+:__amx_genlut Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=22 & Rd_GPR64
+{
+ __amx_genlut(Rd_GPR64);
+}
+
+}
\ No newline at end of file
diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_AppleSilicon.slaspec b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_AppleSilicon.slaspec
new file mode 100644
index 0000000..f1290bb
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_AppleSilicon.slaspec
@@ -0,0 +1,6 @@
+
+@define DATA_ENDIAN "little"
+
+@include "AARCH64instructions.sinc"
+@include "AARCH64_AMXext.sinc"
+
diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_base_PACoptions.sinc b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_base_PACoptions.sinc
new file mode 100644
index 0000000..fcefee0
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_base_PACoptions.sinc
@@ -0,0 +1,164 @@
+autda__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = AuthDA(Rd_GPR64, Rn_GPR64xsp); }
+autda__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { AuthDA(Rd_GPR64, Rn_GPR64xsp); }
+autda__PACpart: "hide" is ShowPAC=0 { }
+
+autdza__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = AuthDA(Rd_GPR64, xzr); }
+autdza__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { AuthDA(Rd_GPR64, xzr); }
+autdza__PACpart: "hide" is ShowPAC=0 { }
+
+autdb__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = AuthDB(Rd_GPR64, Rn_GPR64xsp); }
+autdb__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { AuthDB(Rd_GPR64, Rn_GPR64xsp); }
+autdb__PACpart: "hide" is ShowPAC=0 { }
+
+autdzb__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = AuthDB(Rd_GPR64, xzr); }
+autdzb__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { AuthDB(Rd_GPR64, xzr); }
+autdzb__PACpart: "hide" is ShowPAC=0 { }
+
+autia__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = AuthIA(Rd_GPR64, Rn_GPR64xsp); }
+autia__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { AuthIA(Rd_GPR64, Rn_GPR64xsp); }
+autia__PACpart: "hide" is ShowPAC=0 { }
+
+autiza__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = AuthIA(Rd_GPR64, xzr); }
+autiza__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { AuthIA(Rd_GPR64, xzr); }
+autiza__PACpart: "hide" is ShowPAC=0 { }
+
+autia1716__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x17 = AuthIA(x17, x16); }
+autia1716__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIA(x17, x16); }
+autia1716__PACpart: "hide" is ShowPAC=0 { }
+
+autiasp__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = AuthIA(x30, sp); }
+autiasp__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIA(x30, sp); }
+autiasp__PACpart: "hide" is ShowPAC=0 { }
+
+autiaz__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = AuthIA(x30, xzr); }
+autiaz__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIA(x30, xzr); }
+autiaz__PACpart: "hide" is ShowPAC=0 { }
+
+autib__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = AuthIB(Rd_GPR64, Rn_GPR64xsp); }
+autib__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { AuthIB(Rd_GPR64, Rn_GPR64xsp); }
+autib__PACpart: "hide" is ShowPAC=0 { }
+
+autizb__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = AuthIB(Rd_GPR64, xzr); }
+autizb__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { AuthIB(Rd_GPR64, xzr); }
+autizb__PACpart: "hide" is ShowPAC=0 { }
+
+autib1716__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x17 = AuthIB(x17, x16); }
+autib1716__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIB(x17, x16); }
+autib1716__PACpart: "hide" is ShowPAC=0 { }
+
+autibsp__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = AuthIB(x30, sp); }
+autibsp__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIB(x30, sp); }
+autibsp__PACpart: "hide" is ShowPAC=0 { }
+
+autibz__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = AuthIB(x30, xzr); }
+autibz__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIB(x30, xzr); }
+autibz__PACpart: "hide" is ShowPAC=0 { }
+
+b_blinkop__raaz___PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64 { AuthIA(Rn_GPR64, xzr); }
+b_blinkop__raaz___PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64 { AuthIA(Rn_GPR64, xzr); }
+b_blinkop__raaz___PACpart: "hide" is ShowPAC=0 { }
+
+b_blinkop__raa___PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64xsp & Rn_GPR64 { AuthIA(Rn_GPR64, Rd_GPR64xsp); }
+b_blinkop__raa___PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64xsp & Rn_GPR64 { AuthIA(Rn_GPR64, Rd_GPR64xsp); }
+b_blinkop__raa___PACpart: "hide" is ShowPAC=0 { }
+
+b_blinkop__rabz___PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64 { AuthIB(Rn_GPR64, xzr); }
+b_blinkop__rabz___PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64 { AuthIB(Rn_GPR64, xzr); }
+b_blinkop__rabz___PACpart: "hide" is ShowPAC=0 { }
+
+b_blinkop__rab___PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64xsp & Rn_GPR64 { AuthIB(Rn_GPR64, Rd_GPR64xsp); }
+b_blinkop__rab___PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64xsp & Rn_GPR64 { AuthIB(Rn_GPR64, Rd_GPR64xsp); }
+b_blinkop__rab___PACpart: "hide" is ShowPAC=0 { }
+
+eretaa__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { AuthIA(pc, sp); }
+eretaa__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIA(pc, sp); }
+eretaa__PACpart: "hide" is ShowPAC=0 { }
+
+eretab__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { AuthIB(pc, sp); }
+eretab__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIB(pc, sp); }
+eretab__PACpart: "hide" is ShowPAC=0 { }
+
+ldraa__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp { AuthDA(Rn_GPR64xsp, xzr); }
+ldraa__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp { AuthDA(Rn_GPR64xsp, xzr); }
+ldraa__PACpart: "hide" is ShowPAC=0 { }
+
+ldrab__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp { AuthDB(Rn_GPR64xsp, xzr); }
+ldrab__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp { AuthDB(Rn_GPR64xsp, xzr); }
+ldrab__PACpart: "hide" is ShowPAC=0 { }
+
+pacda__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = pacda(Rd_GPR64, Rn_GPR64xsp); }
+pacda__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { pacda(Rd_GPR64, Rn_GPR64xsp); }
+pacda__PACpart: "hide" is ShowPAC=0 { }
+
+pacdza__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = pacdza(Rd_GPR64); }
+pacdza__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { pacdza(Rd_GPR64); }
+pacdza__PACpart: "hide" is ShowPAC=0 { }
+
+pacdb__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = pacdb(Rd_GPR64, Rn_GPR64xsp); }
+pacdb__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { pacdb(Rd_GPR64, Rn_GPR64xsp); }
+pacdb__PACpart: "hide" is ShowPAC=0 { }
+
+pacdzb__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = pacdzb(Rd_GPR64); }
+pacdzb__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { pacdzb(Rd_GPR64); }
+pacdzb__PACpart: "hide" is ShowPAC=0 { }
+
+pacia__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = pacia(Rd_GPR64, Rn_GPR64xsp); }
+pacia__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { pacia(Rd_GPR64, Rn_GPR64xsp); }
+pacia__PACpart: "hide" is ShowPAC=0 { }
+
+paciza__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = paciza(Rd_GPR64); }
+paciza__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { paciza(Rd_GPR64); }
+paciza__PACpart: "hide" is ShowPAC=0 { }
+
+pacia1716__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x17 = pacia(x17, x16); }
+pacia1716__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { pacia(x17, x16); }
+pacia1716__PACpart: "hide" is ShowPAC=0 { }
+
+paciasp__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = pacia(x30, sp); }
+paciasp__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { pacia(x30, sp); }
+paciasp__PACpart: "hide" is ShowPAC=0 { }
+
+paciaz__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = paciza(x30); }
+paciaz__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { paciza(x30); }
+paciaz__PACpart: "hide" is ShowPAC=0 { }
+
+pacib__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rn_GPR64xsp & Rd_GPR64 { Rd_GPR64 = pacib(Rd_GPR64, Rn_GPR64xsp); }
+pacib__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rn_GPR64xsp & Rd_GPR64 { pacib(Rd_GPR64, Rn_GPR64xsp); }
+pacib__PACpart: "hide" is ShowPAC=0 { }
+
+pacizb__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = pacizb(Rd_GPR64); }
+pacizb__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { pacizb(Rd_GPR64); }
+pacizb__PACpart: "hide" is ShowPAC=0 { }
+
+pacib1716__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x17 = pacib(x17, x16); }
+pacib1716__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { pacib(x17, x16); }
+pacib1716__PACpart: "hide" is ShowPAC=0 { }
+
+pacibsp__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = pacib(x30, sp); }
+pacibsp__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { pacib(x30, sp); }
+pacibsp__PACpart: "hide" is ShowPAC=0 { }
+
+pacibz__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = pacizb(x30); }
+pacibz__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { pacizb(x30); }
+pacibz__PACpart: "hide" is ShowPAC=0 { }
+
+retaa__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { AuthIA(x30, sp); }
+retaa__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIA(x30, sp); }
+retaa__PACpart: "hide" is ShowPAC=0 { }
+
+retab__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { AuthIB(x30, sp); }
+retab__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { AuthIB(x30, sp); }
+retab__PACpart: "hide" is ShowPAC=0 { }
+
+xpacd__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = xpac(Rd_GPR64, 1:1); }
+xpacd__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { xpac(Rd_GPR64, 1:1); }
+xpacd__PACpart: "hide" is ShowPAC=0 { }
+
+xpaci__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 & Rd_GPR64 { Rd_GPR64 = xpac(Rd_GPR64, 0:1); }
+xpaci__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 & Rd_GPR64 { xpac(Rd_GPR64, 0:1); }
+xpaci__PACpart: "hide" is ShowPAC=0 { }
+
+xpaclri__PACpart: "show_and_clobber" is ShowPAC=1 & PAC_clobber=1 { x30 = xpac(x30, 0:1); }
+xpaclri__PACpart: "show_noclobber" is ShowPAC=1 & PAC_clobber=0 { xpac(x30, 0:1); }
+xpaclri__PACpart: "hide" is ShowPAC=0 { }
+
diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_ilp32.cspec b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_ilp32.cspec
new file mode 100644
index 0000000..4629571
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_ilp32.cspec
@@ -0,0 +1,207 @@
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diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_win.cspec b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_win.cspec
new file mode 100644
index 0000000..8e02453
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64_win.cspec
@@ -0,0 +1,214 @@
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diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc
new file mode 100644
index 0000000..194b37a
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc
@@ -0,0 +1,8392 @@
+# C6.2.1 ADC page C6-1144 line 67905 MATCH x1a000000/mask=x7fe0fc00
+# C6.2.2 ADCS page C6-1146 line 67991 MATCH x3a000000/mask=x7fe0fc00
+# CONSTRUCT x1a000000/mask=xdfe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x1a000000/mask=xdfe0fc00 --status pass --comment "flags"
+
+:adc^SBIT_CZNO Rd_GPR32, Rn_GPR32, Rm_GPR32
+is sf=0 & b_30=0 & S & SBIT_CZNO & b_2428=0x1a & b_2123=0 & Rm_GPR32 & b_1015=0 & Rd_GPR32 & Rd_GPR64 & Rn_GPR32
+{
+ add_with_carry_flags(Rn_GPR32, Rm_GPR32);
+ tmp:4 = Rm_GPR32 + Rn_GPR32 + zext(CY);
+ Rd_GPR64 = zext(tmp);
+ resultflags(tmp);
+ build SBIT_CZNO;
+}
+
+# C6.2.1 ADC page C6-1144 line 67905 MATCH x1a000000/mask=x7fe0fc00
+# C6.2.2 ADCS page C6-1146 line 67991 MATCH x3a000000/mask=x7fe0fc00
+# CONSTRUCT x9a000000/mask=xdfe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x9a000000/mask=xdfe0fc00 --status pass --comment "flags"
+
+:adc^SBIT_CZNO Rd_GPR64, Rn_GPR64, Rm_GPR64
+is sf=1 & b_30=0 & S & SBIT_CZNO & b_2428=0x1a & b_2123=0 & Rm_GPR64 & b_1015=0 & Rd_GPR64 & Rn_GPR64
+{
+ add_with_carry_flags(Rn_GPR64, Rm_GPR64);
+ Rd_GPR64 = Rn_GPR64 + Rm_GPR64 + zext(CY);
+ resultflags(Rd_GPR64);
+ build SBIT_CZNO;
+}
+
+# C6.2.3 ADD (extended register) page C6-1148 line 68081 MATCH x0b200000/mask=x7fe00000
+# C6.2.7 ADDS (extended register) page C6-1156 line 68516 MATCH x2b200000/mask=x7fe00000
+# C6.2.59 CMN (extended register) page C6-1246 line 73092 MATCH x2b20001f/mask=x7fe0001f
+# CONSTRUCT x0b200000/mask=xdfe00000 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst x0b200000/mask=xdfe00000 --status pass --comment "flags"
+
+:add^SBIT_CZNO Rd_GPR32wsp, Rn_GPR32wsp, ExtendRegShift32
+is sf=0 & op=0 & S & SBIT_CZNO & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift32 & Rn_GPR32wsp & Rd_GPR32wsp & Rd_GPR64xsp
+{
+ tmp_2:4 = ExtendRegShift32;
+ addflags(Rn_GPR32wsp, tmp_2);
+ tmp_1:4 = Rn_GPR32wsp + tmp_2;
+ resultflags(tmp_1);
+ Rd_GPR64xsp = zext(tmp_1);
+ build SBIT_CZNO;
+}
+
+# C6.2.3 ADD (extended register) page C6-1148 line 68081 MATCH x0b200000/mask=x7fe00000
+# C6.2.7 ADDS (extended register) page C6-1156 line 68516 MATCH x2b200000/mask=x7fe00000
+# C6.2.59 CMN (extended register) page C6-1246 line 73092 MATCH x2b20001f/mask=x7fe0001f
+# CONSTRUCT x8b200000/mask=xdfe00000 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst x8b200000/mask=xdfe00000 --status pass --comment "flags"
+
+:add^SBIT_CZNO Rd_GPR64xsp, Rn_GPR64xsp, ExtendRegShift64
+is sf=1 & op=0 & S & SBIT_CZNO & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift64 & Rn_GPR64xsp & Rd_GPR64xsp
+{
+ tmp_2:8 = ExtendRegShift64;
+ addflags(Rn_GPR64xsp, tmp_2);
+ tmp_1:8 = Rn_GPR64xsp + tmp_2;
+ resultflags(tmp_1);
+ Rd_GPR64xsp = tmp_1;
+ build SBIT_CZNO;
+}
+
+# C6.2.4 ADD (immediate) page C6-1151 line 68228 MATCH x11000000/mask=x7f800000
+# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000
+# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f
+# C6.2.220 MOV (to/from SP) page C6-1668 line 98876 MATCH x11000000/mask=x7ffffc00
+# CONSTRUCT x11000000/mask=xdf000000 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst x11000000/mask=xdf000000 --status pass --comment "flags"
+
+:add^SBIT_CZNO Rd_GPR32xsp, Rn_GPR32xsp, ImmShift32
+is sf=0 & b_30=0 & S & SBIT_CZNO & b_2428=0x011 & ImmShift32 & Rn_GPR32xsp & Rd_GPR32xsp & Rd_GPR64xsp
+{
+ addflags(Rn_GPR32xsp, ImmShift32);
+ tmp:4 = Rn_GPR32xsp + ImmShift32;
+ resultflags(tmp);
+ build SBIT_CZNO;
+ Rd_GPR64xsp = zext(tmp);
+}
+
+# C6.2.4 ADD (immediate) page C6-1151 line 68228 MATCH x11000000/mask=x7f800000
+# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000
+# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f
+# C6.2.220 MOV (to/from SP) page C6-1668 line 98876 MATCH x11000000/mask=x7ffffc00
+# CONSTRUCT x91000000/mask=xdf000000 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst x91000000/mask=xdf000000 --status pass --comment "flags"
+
+:add^SBIT_CZNO Rd_GPR64xsp, Rn_GPR64xsp, ImmShift64
+is sf=1 & b_30=0 & S & SBIT_CZNO & b_2428=0x11 & ImmShift64 & Rn_GPR64xsp & Rd_GPR64xsp
+{
+ addflags(Rn_GPR64xsp, ImmShift64);
+ Rd_GPR64xsp = Rn_GPR64xsp + ImmShift64;
+ resultflags(Rd_GPR64xsp);
+ build SBIT_CZNO;
+}
+
+# C6.2.4 ADD (immediate) page C6-1151 line 68228 MATCH x11000000/mask=x7f800000
+# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000
+# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f
+# C6.2.220 MOV (to/from SP) page C6-1668 line 98876 MATCH x11000000/mask=x7ffffc00
+# CONSTRUCT x11000000/mask=xdfc00000 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst x11000000/mask=xdfc00000 --status pass --comment "flags"
+
+:add^SBIT_CZNO Rd_GPR32wsp, Rn_GPR32wsp, Imm12_addsubimm_operand_i32_posimm_lsl0
+is sf=0 & op=0 & S & SBIT_CZNO & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i32_posimm_lsl0 & Rn_GPR32wsp & Rd_GPR32wsp & Rd_GPR64xsp
+{
+ tmp_2:4 = Imm12_addsubimm_operand_i32_posimm_lsl0;
+ addflags(Rn_GPR32wsp, tmp_2);
+ tmp_1:4 = Rn_GPR32wsp + tmp_2;
+ resultflags(tmp_1);
+ Rd_GPR64xsp = zext(tmp_1);
+ build SBIT_CZNO;
+}
+
+# C6.2.4 ADD (immediate) page C6-1151 line 68228 MATCH x11000000/mask=x7f800000
+# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000
+# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f
+# CONSTRUCT x11400000/mask=xdfc00000 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst x11400000/mask=xdfc00000 --status pass --comment "flags"
+
+:add^SBIT_CZNO Rd_GPR32wsp, Rn_GPR32wsp, Imm12_addsubimm_operand_i32_posimm_lsl12
+is sf=0 & op=0 & S & SBIT_CZNO & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i32_posimm_lsl12 & Rn_GPR32wsp & Rd_GPR32wsp & Rd_GPR64xsp
+{
+ tmp_2:4 = Imm12_addsubimm_operand_i32_posimm_lsl12;
+ addflags(Rn_GPR32wsp, tmp_2);
+ tmp_1:4 = Rn_GPR32wsp + tmp_2;
+ resultflags(tmp_1);
+ Rd_GPR64xsp = zext(tmp_1);
+ build SBIT_CZNO;
+}
+
+# C6.2.4 ADD (immediate) page C6-1151 line 68228 MATCH x11000000/mask=x7f800000
+# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000
+# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f
+# C6.2.220 MOV (to/from SP) page C6-1668 line 98876 MATCH x11000000/mask=x7ffffc00
+# CONSTRUCT x91000000/mask=xdfc00000 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst x91000000/mask=xdfc00000 --status pass --comment "flags"
+
+:add^SBIT_CZNO Rd_GPR64xsp, Rn_GPR64xsp, Imm12_addsubimm_operand_i64_posimm_lsl0
+is sf=1 & op=0 & S & SBIT_CZNO & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i64_posimm_lsl0 & Rn_GPR64xsp & Rd_GPR64xsp
+{
+ tmp_2:8 = Imm12_addsubimm_operand_i64_posimm_lsl0;
+ addflags(Rn_GPR64xsp, tmp_2);
+ tmp_1:8 = Rn_GPR64xsp + tmp_2;
+ resultflags(tmp_1);
+ Rd_GPR64xsp = tmp_1;
+ build SBIT_CZNO;
+}
+
+# C6.2.4 ADD (immediate) page C6-1151 line 68228 MATCH x11000000/mask=x7f800000
+# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000
+# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f
+# CONSTRUCT x91400000/mask=xdfc00000 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst x91400000/mask=xdfc00000 --status pass --comment "flags"
+
+:add^SBIT_CZNO Rd_GPR64xsp, Rn_GPR64xsp, Imm12_addsubimm_operand_i64_posimm_lsl12
+is sf=1 & op=0 & S & SBIT_CZNO & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i64_posimm_lsl12 & Rn_GPR64xsp & Rd_GPR64xsp
+{
+ tmp_2:8 = Imm12_addsubimm_operand_i64_posimm_lsl12;
+ addflags(Rn_GPR64xsp, tmp_2);
+ tmp_1:8 = Rn_GPR64xsp + tmp_2;
+ resultflags(tmp_1);
+ Rd_GPR64xsp = tmp_1;
+ build SBIT_CZNO;
+}
+
+# C6.2.5 ADD (shifted register) page C6-1153 line 68340 MATCH x0b000000/mask=x7f200000
+# C6.2.9 ADDS (shifted register) page C6-1161 line 68775 MATCH x2b000000/mask=x7f200000
+# C6.2.61 CMN (shifted register) page C6-1250 line 73309 MATCH x2b00001f/mask=x7f20001f
+# CONSTRUCT x0b000000/mask=xdf208000 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst x0b000000/mask=xdf208000 --status pass --comment "flags"
+# if shift == '11' then ReservedValue();
+
+:add^SBIT_CZNO Rd_GPR32, Rn_GPR32, RegShift32
+is sf=0 & op=0 & S & SBIT_CZNO & b_2428=0xb & b_2121=0 & b_15=0 & RegShift32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp_2:4 = RegShift32;
+ addflags(Rn_GPR32, tmp_2);
+ tmp_1:4 = Rn_GPR32 + tmp_2;
+ resultflags(tmp_1);
+ Rd_GPR64 = zext(tmp_1);
+ build SBIT_CZNO;
+}
+
+# C6.2.5 ADD (shifted register) page C6-1153 line 68340 MATCH x0b000000/mask=x7f200000
+# C6.2.9 ADDS (shifted register) page C6-1161 line 68775 MATCH x2b000000/mask=x7f200000
+# C6.2.61 CMN (shifted register) page C6-1250 line 73309 MATCH x2b00001f/mask=x7f20001f
+# CONSTRUCT x8b000000/mask=xdf200000 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst x8b000000/mask=xdf200000 --status pass --comment "flags"
+
+:add^SBIT_CZNO Rd_GPR64, Rn_GPR64, RegShift64
+is sf=1 & op=0 & S & SBIT_CZNO & b_2428=0xb & b_2121=0 & RegShift64 & Rn_GPR64 & Rd_GPR64
+{
+ tmp_2:8 = RegShift64;
+ addflags(Rn_GPR64, tmp_2);
+ tmp_1:8 = Rn_GPR64 + tmp_2;
+ resultflags(tmp_1);
+ Rd_GPR64 = tmp_1;
+ build SBIT_CZNO;
+}
+
+# C6.2.10 ADR page C6-1163 line 68896 MATCH x10000000/mask=x9f000000
+# CONSTRUCT x10000000/mask=x9f000000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x10000000/mask=x9f000000 --status nodest --comment "qemuerr(illegal addresses cause qemu exit)"
+
+:adr Rd_GPR64, AdrReloff
+is b_31=0 & AdrReloff & b_2428=0x10 & Rd_GPR64
+{
+ Rd_GPR64 = &AdrReloff;
+}
+
+# C6.2.11 ADRP page C6-1164 line 68943 MATCH x90000000/mask=x9f000000
+# CONSTRUCT x90000000/mask=x9f000000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x90000000/mask=x9f000000 --status nodest --comment "qemuerr(illegal addresses cause qemu exit)"
+
+:adrp Rd_GPR64, AdrReloff
+is b_31=1 & AdrReloff & b_2428=0x10 & Rd_GPR64
+{
+ Rd_GPR64 = &AdrReloff;
+}
+
+# C6.2.12 AND (immediate) page C6-1165 line 68992 MATCH x12000000/mask=x7f800000
+# CONSTRUCT x12000000/mask=xff800000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x12000000/mask=xff800000 --status pass
+
+:and Rd_GPR32wsp, Rn_GPR32, DecodeWMask32
+is sf=0 & opc=0 & b_2428=0x12 & b_2323=0 & DecodeWMask32 & Rn_GPR32 & Rd_GPR32wsp & Rd_GPR64xsp
+{
+ tmp_1:4 = Rn_GPR32 & DecodeWMask32;
+ Rd_GPR64xsp = zext(tmp_1);
+}
+
+# C6.2.12 AND (immediate) page C6-1165 line 68992 MATCH x12000000/mask=x7f800000
+# CONSTRUCT x92000000/mask=xff800000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x92000000/mask=xff800000 --status pass
+
+:and Rd_GPR64xsp, Rn_GPR64, DecodeWMask64
+is sf=1 & opc=0 & b_2428=0x12 & b_2323=0 & DecodeWMask64 & Rn_GPR64 & Rd_GPR64xsp
+{
+ tmp_1:8 = Rn_GPR64 & DecodeWMask64;
+ Rd_GPR64xsp = tmp_1;
+}
+
+# C6.2.13 AND (shifted register) page C6-1167 line 69083 MATCH x0a000000/mask=x7f200000
+# CONSTRUCT x0a000000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x0a000000/mask=xff200000 --status pass
+
+:and Rd_GPR32, Rn_GPR32, RegShift32Log
+is sf=0 & opc=0 & b_2428=0xa & N=0 & RegShift32Log & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp_2:4 = RegShift32Log;
+ tmp_1:4 = Rn_GPR32 & tmp_2;
+ Rd_GPR64 = zext(tmp_1);
+}
+
+# C6.2.13 AND (shifted register) page C6-1167 line 69083 MATCH x0a000000/mask=x7f200000
+# CONSTRUCT x8a000000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x8a000000/mask=xff200000 --status pass
+
+:and Rd_GPR64, Rn_GPR64, RegShift64Log
+is sf=1 & opc=0 & b_2428=0xa & N=0 & RegShift64Log & Rn_GPR64 & Rd_GPR64
+{
+ tmp_2:8 = RegShift64Log;
+ tmp_1:8 = Rn_GPR64 & tmp_2;
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.14 ANDS (immediate) page C6-1169 line 69185 MATCH x72000000/mask=x7f800000
+# C6.2.382 TST (immediate) page C6-1983 line 116255 MATCH x7200001f/mask=x7f80001f
+# CONSTRUCT x72000000/mask=xff800000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x72000000/mask=xff800000 --status pass --comment "flags"
+
+:ands Rd_GPR32, Rn_GPR32, DecodeWMask32
+is sf=0 & opc=3 & b_2428=0x12 & b_2323=0 & DecodeWMask32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp_1:4 = Rn_GPR32 & DecodeWMask32;
+ resultflags(tmp_1);
+ Rd_GPR64 = zext(tmp_1);
+ affectLflags();
+}
+
+# C6.2.14 ANDS (immediate) page C6-1169 line 69185 MATCH x72000000/mask=x7f800000
+# C6.2.382 TST (immediate) page C6-1983 line 116255 MATCH x7200001f/mask=x7f80001f
+# CONSTRUCT xf2000000/mask=xff800000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xf2000000/mask=xff800000 --status pass --comment "flags"
+
+:ands Rd_GPR64, Rn_GPR64, DecodeWMask64
+is sf=1 & opc=3 & b_2428=0x12 & b_2323=0 & DecodeWMask64 & Rn_GPR64 & Rd_GPR64
+{
+ tmp_1:8 = Rn_GPR64 & DecodeWMask64;
+ resultflags(tmp_1);
+ Rd_GPR64 = tmp_1;
+ affectLflags();
+}
+
+# C6.2.15 ANDS (shifted register) page C6-1171 line 69286 MATCH x6a000000/mask=x7f200000
+# C6.2.383 TST (shifted register) page C6-1984 line 116319 MATCH x6a00001f/mask=x7f20001f
+# CONSTRUCT x6a000000/mask=xff200000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x6a000000/mask=xff200000 --status pass --comment "flags"
+
+:ands Rd_GPR32, Rn_GPR32, RegShift32Log
+is sf=0 & opc=3 & b_2428=0xa & N=0 & RegShift32Log & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp_2:4 = RegShift32Log;
+ tmp_1:4 = Rn_GPR32 & tmp_2;
+ resultflags(tmp_1);
+ Rd_GPR64 = zext(tmp_1);
+ affectLflags();
+}
+
+# C6.2.15 ANDS (shifted register) page C6-1171 line 69286 MATCH x6a000000/mask=x7f200000
+# C6.2.383 TST (shifted register) page C6-1984 line 116319 MATCH x6a00001f/mask=x7f20001f
+# CONSTRUCT xea000000/mask=xff200000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xea000000/mask=xff200000 --status pass --comment "flags"
+
+:ands Rd_GPR64, Rn_GPR64, RegShift64Log
+is sf=1 & opc=3 & b_2428=0xa & N=0 & RegShift64Log & Rn_GPR64 & Rd_GPR64
+{
+ tmp_2:8 = RegShift64Log;
+ tmp_1:8 = Rn_GPR64 & tmp_2;
+ resultflags(tmp_1);
+ Rd_GPR64 = tmp_1;
+ affectLflags();
+}
+
+# C6.2.16 ASR (register) page C6-1173 line 69404 MATCH x1ac02800/mask=x7fe0fc00
+# C6.2.18 ASRV page C6-1177 line 69588 MATCH x1ac02800/mask=x7fe0fc00
+# CONSTRUCT x1ac02800/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x1ac02800/mask=xffe0fc00 --status pass
+
+:asr Rd_GPR32, Rn_GPR32, Rm_GPR32
+is sf=0 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR32 & b_1015=0xa & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp_2:4 = Rm_GPR32 & 0x1f;
+ tmp_1:4 = Rn_GPR32 s>> tmp_2;
+ Rd_GPR64 = zext(tmp_1);
+}
+
+# C6.2.16 ASR (register) page C6-1173 line 69404 MATCH x1ac02800/mask=x7fe0fc00
+# C6.2.18 ASRV page C6-1177 line 69588 MATCH x1ac02800/mask=x7fe0fc00
+# CONSTRUCT x9ac02800/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x9ac02800/mask=xffe0fc00 --status pass
+
+:asr Rd_GPR64, Rn_GPR64, Rm_GPR64
+is sf=1 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR64 & b_1015=0xa & Rn_GPR64 & Rd_GPR64
+{
+ tmp_2:8 = Rm_GPR64 & 0x3f;
+ tmp_1:8 = Rn_GPR64 s>> tmp_2;
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00
+# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000
+# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000
+# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000
+# CONSTRUCT x13007c00/mask=xffe0fc02 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst x13007c00/mask=xffe0fc02 --status pass
+# Alias for sbfm when imms == '011111'
+# imms is MAX_INT5, so it will never be less than immr. Note that immr is limited to [0,31]
+# Ha! Two explicit cases passes -l
+# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue();
+
+:asr Rd_GPR32, Rn_GPR32, ImmRConst32
+is ImmS=0x1f & ImmS_LT_ImmR=0 & (ImmS_EQ_ImmR=0 | ImmS_EQ_ImmR=1) & sf=0 & opc=0 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp_2:4 = ImmRConst32;
+ tmp_1:4 = Rn_GPR32 s>> tmp_2;
+ Rd_GPR64 = zext(tmp_1);
+}
+
+# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00
+# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000
+# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000
+# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000
+# CONSTRUCT x9340fc00/mask=xffc0fc02 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst x9340fc00/mask=xffc0fc02 --status pass
+# Alias for sbfm when imms == '111111'
+# imms is MAX_INT6, so it will never be less than immr (6-bit field)
+# Ha! Two explicit cases passes -l
+
+:asr Rd_GPR64, Rn_GPR64, ImmRConst64
+is ImmS=0x3f & ImmS_LT_ImmR=0 & (ImmS_EQ_ImmR=0 | ImmS_EQ_ImmR=1) & sf=1 & opc=0 & b_2428=0x13 & b_2323=0 & n=1 & ImmRConst64 & Rn_GPR64 & Rd_GPR64
+{
+ tmp_2:8 = ImmRConst64;
+ tmp_1:8 = Rn_GPR64 s>> tmp_2;
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5087800/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst xd5087800/mask=xffffffe0 --status noqemu
+
+:at "S1E1R", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b000 & Rt_GPR64
+{ par_el1 = AT_S1E1R(Rt_GPR64); }
+
+# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50c7800/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst xd50c7800/mask=xffffffe0 --status noqemu
+
+:at "S1E2R", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b000 & Rt_GPR64
+{ par_el1 = AT_S1E2R(Rt_GPR64); }
+
+# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50e7800/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst xd50e7800/mask=xffffffe0 --status noqemu
+
+:at "S1E3R", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b110 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b000 & Rt_GPR64
+{ par_el1 = AT_S1E3R(Rt_GPR64); }
+
+# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5087820/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst xd5087820/mask=xffffffe0 --status noqemu
+
+:at "S1E1W", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b001 & Rt_GPR64
+{ par_el1 = AT_S1E1W(Rt_GPR64); }
+
+# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50c7820/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst xd50c7820/mask=xffffffe0 --status noqemu
+
+:at "S1E2W", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b001 & Rt_GPR64
+{ par_el1 = AT_S1E2W(Rt_GPR64); }
+
+# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50e7820/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst xd50e7820/mask=xffffffe0 --status noqemu
+
+:at "S1E3W", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b110 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b001 & Rt_GPR64
+{ par_el1 = AT_S1E3W(Rt_GPR64); }
+
+# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5087840/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst xd5087840/mask=xffffffe0 --status noqemu
+
+:at "S1E0R", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b010 & Rt_GPR64
+{ par_el1 = AT_S1E0R(Rt_GPR64); }
+
+# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5087860/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst xd5087860/mask=xffffffe0 --status noqemu
+
+:at "S1E0W", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b011 & Rt_GPR64
+{ par_el1 = AT_S1E0W(Rt_GPR64); }
+
+# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50c7880/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst xd50c7880/mask=xffffffe0 --status noqemu
+
+:at "S12E1R", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b100 & Rt_GPR64
+{ par_el1 = AT_S12E1R(Rt_GPR64); }
+
+# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50c78a0/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst xd50c78a0/mask=xffffffe0 --status noqemu
+
+:at "S12E1W", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b101 & Rt_GPR64
+{ par_el1 = AT_S12E1W(Rt_GPR64); }
+
+# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50c78c0/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst xd50c78c0/mask=xffffffe0 --status noqemu
+
+:at "S12E0R", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b110 & Rt_GPR64
+{ par_el1 = AT_S12E0R(Rt_GPR64); }
+
+# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50c78e0/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst xd50c78e0/mask=xffffffe0 --status noqemu
+
+:at "S12E0W", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b0111 & b_0811=0b1000 & b_0507=0b111 & Rt_GPR64
+{ par_el1 = AT_S12E0W(Rt_GPR64); }
+
+# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5087900/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst xd5087900/mask=xffffffe0 --status noqemu
+
+:at "S1E1RP", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1001 & b_0507=0b000 & Rt_GPR64
+{ par_el1 = AT_S1E1RP(Rt_GPR64); }
+
+# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5087920/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst xd5087920/mask=xffffffe0 --status noqemu
+
+:at "S1E1WP", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1001 & b_0507=0b001 & Rt_GPR64
+{ par_el1 = AT_S1E1WP(Rt_GPR64); }
+
+# C6.2.20 AUTDA, AUTDZA page C6-1181 line 69758 MATCH xdac11800/mask=xffffdc00
+# CONSTRUCT xdac11800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xdac11800/mask=xfffffc00 --status noqemu
+
+:autda Rd_GPR64, Rn_GPR64xsp
+is autda__PACpart & b_1431=0b110110101100000100 & b_1012=0b110 & b_13=0 & Rn_GPR64xsp & Rd_GPR64
+{
+ build autda__PACpart;
+}
+
+# C6.2.20 AUTDA, AUTDZA page C6-1181 line 69758 MATCH xdac11800/mask=xffffdc00
+# CONSTRUCT xdac13be0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xdac13be0/mask=xffffffe0 --status noqemu
+
+:autdza Rd_GPR64
+is autdza__PACpart & b_1431=0b110110101100000100 & b_1012=0b110 & b_13=1 & b_0509=0b11111 & Rd_GPR64
+{
+ build autdza__PACpart;
+}
+
+# C6.2.21 AUTDB, AUTDZB page C6-1182 line 69833 MATCH xdac11c00/mask=xffffdc00
+# CONSTRUCT xdac11c00/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xdac11c00/mask=xfffffc00 --status noqemu
+
+:autdb Rd_GPR64, Rn_GPR64xsp
+is autdb__PACpart & b_1431=0b110110101100000100 & b_1012=0b111 & b_13=0 & Rn_GPR64xsp & Rd_GPR64
+{
+ build autdb__PACpart;
+}
+
+# C6.2.21 AUTDB, AUTDZB page C6-1182 line 69833 MATCH xdac11c00/mask=xffffdc00
+# CONSTRUCT xdac13fe0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xdac13fe0/mask=xffffffe0 --status noqemu
+
+:autdzb Rd_GPR64
+is autdzb__PACpart & b_1431=0b110110101100000100 & b_1012=0b111 & b_13=1 & b_0509=0b11111 & Rd_GPR64
+{
+ build autdzb__PACpart;
+}
+
+# C6.2.22 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA page C6-1183 line 69908 MATCH xdac11000/mask=xffffdc00
+# CONSTRUCT xdac11000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xdac11000/mask=xfffffc00 --status noqemu
+
+:autia Rd_GPR64, Rn_GPR64xsp
+is autia__PACpart & b_1431=0b110110101100000100 & b_1012=0b100 & b_13=0 & Rn_GPR64xsp & Rd_GPR64
+{
+ build autia__PACpart;
+}
+
+# C6.2.22 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA page C6-1183 line 69908 MATCH xdac11000/mask=xffffdc00
+# CONSTRUCT xdac133e0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xdac133e0/mask=xffffffe0 --status noqemu
+
+:autiza Rd_GPR64
+is autiza__PACpart & b_1431=0b110110101100000100 & b_1012=0b100 & b_13=1 & b_0509=0b11111 & Rd_GPR64
+{
+ build autiza__PACpart;
+}
+
+# C6.2.22 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA page C6-1183 line 69908 MATCH xd503219f/mask=xfffffddf
+# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f
+# CONSTRUCT xd503219f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd503219f/mask=xffffffff --status nodest
+
+:autia1716
+is autia1716__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0001 & b_0507=0b100 & b_0004=0b11111
+{
+ build autia1716__PACpart;
+}
+
+# C6.2.22 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA page C6-1183 line 69908 MATCH xd503219f/mask=xfffffddf
+# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f
+# CONSTRUCT xd50323bf/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50323bf/mask=xffffffff --status nodest
+
+:autiasp
+is autiasp__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0011 & b_0507=0b101 & b_0004=0b11111
+{
+ build autiasp__PACpart;
+}
+
+# C6.2.22 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA page C6-1183 line 69908 MATCH xd503219f/mask=xfffffddf
+# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f
+# CONSTRUCT xd503239f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd503239f/mask=xffffffff --status nodest
+
+:autiaz
+is autiaz__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0011 & b_0507=0b100 & b_0004=0b11111
+{
+ build autiaz__PACpart;
+}
+
+# C6.2.23 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB page C6-1186 line 70065 MATCH xdac11400/mask=xffffdc00
+# CONSTRUCT xdac11400/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xdac11400/mask=xfffffc00 --status noqemu
+
+:autib Rd_GPR64, Rn_GPR64xsp
+is autib__PACpart & b_1431=0b110110101100000100 & b_1012=0b101 & b_13=0 & Rn_GPR64xsp & Rd_GPR64
+{
+ build autib__PACpart;
+}
+
+# C6.2.23 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB page C6-1186 line 70065 MATCH xdac11400/mask=xffffdc00
+# CONSTRUCT xdac137e0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xdac137e0/mask=xffffffe0 --status noqemu
+
+:autizb Rd_GPR64
+is autizb__PACpart & b_1431=0b110110101100000100 & b_1012=0b101 & b_13=1 & b_0509=0b11111 & Rd_GPR64
+{
+ build autizb__PACpart;
+}
+
+# C6.2.23 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB page C6-1186 line 70065 MATCH xd50321df/mask=xfffffddf
+# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f
+# CONSTRUCT xd50321df/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50321df/mask=xffffffff --status nodest
+
+:autib1716
+is autib1716__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0001 & b_0507=0b110 & b_0004=0b11111
+{
+ build autib1716__PACpart;
+}
+
+# C6.2.23 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB page C6-1186 line 70065 MATCH xd50321df/mask=xfffffddf
+# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f
+# CONSTRUCT xd50323ff/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50323ff/mask=xffffffff --status nodest
+
+:autibsp
+is autibsp__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0011 & b_0507=0b111 & b_0004=0b11111
+{
+ build autibsp__PACpart;
+}
+
+# C6.2.23 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB page C6-1186 line 70065 MATCH xd50321df/mask=xfffffddf
+# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f
+# CONSTRUCT xd50323df/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50323df/mask=xffffffff --status nodest
+
+:autibz
+is autibz__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0011 & b_0507=0b110 & b_0004=0b11111
+{
+ build autibz__PACpart;
+}
+
+# C6.2.26 B.cond page C6-1191 line 70305 MATCH x54000000/mask=xff000010
+# CONSTRUCT x5400000f/mask=xff00001f MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x5400000f/mask=xff00001f --status nodest --comment "noflags qemuerr(illegal addresses cause qemu exit)"
+
+:b^"."^BranchCondOp Addr19
+is b_2531=0x2a & o1=0 & Addr19 & o0=0 & br_cond_op=15 & BranchCondOp
+{
+ goto Addr19;
+}
+
+# C6.2.26 B.cond page C6-1191 line 70305 MATCH x54000000/mask=xff000010
+# CONSTRUCT x54000000/mask=xff000010 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x54000000/mask=xff000010 --status nodest --comment "flags qemuerr(illegal addresses cause qemu exit)"
+
+:b^"."^BranchCondOp Addr19
+is b_2531=0x2a & o1=0 & Addr19 & o0=0 & br_cond_op & BranchCondOp
+{
+ if (BranchCondOp) goto Addr19;
+}
+
+# C6.2.25 B page C6-1190 line 70265 MATCH x14000000/mask=xfc000000
+# CONSTRUCT x14000000/mask=xfc000000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x14000000/mask=xfc000000 --status nodest --comment "flags qemuerr(illegal addresses cause qemu exit)"
+
+:b Addr26
+is b_31=0 & b_2630=0x05 & Addr26
+{
+ goto Addr26;
+}
+
+# C6.2.27 BC.cond page C6-1192 line 70348 MATCH x54000010/mask=xff000010
+# CONSTRUCT x54000010/mask=xff000010 MATCHED 1 DOCUMENTED OPCODES
+# b_0031=01010100...................1....
+
+:bc^"."^BranchCondOp Addr19
+is b_2531=0x2a & o1=0 & Addr19 & o0=1 & br_cond_op=15 & BranchCondOp
+{
+ goto Addr19;
+}
+
+:bc^"."^BranchCondOp Addr19
+is b_2531=0x2a & o1=0 & Addr19 & o0=1 & BranchCondOp
+{
+ if (BranchCondOp) goto Addr19;
+}
+
+
+# C6.2.30 BFM page C6-1197 line 70576 MATCH x33000000/mask=x7f800000
+# C6.2.28 BFC page C6-1193 line 70394 MATCH x330003e0/mask=x7f8003e0
+# C6.2.29 BFI page C6-1195 line 70484 MATCH x33000000/mask=x7f800000
+# C6.2.31 BFXIL page C6-1199 line 70700 MATCH x33000000/mask=x7f800000
+# CONSTRUCT x33000000/mask=xffe08000 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst x33000000/mask=xffe08000 --status pass
+# if sf == '0' && (N != '0' || immr<5> (b_21) != '0' || imms<5> (b_15) != '0') then ReservedValue();
+
+:bfm Rd_GPR32, Rn_GPR32, ImmR_bitfield32_imm, ImmS_bitfield32_imm
+is sf=0 & opc=1 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmR_bitfield32_imm & ImmS_bitfield32_imm & ImmRConst32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 & DecodeWMask32 & DecodeTMask32
+{
+ local wmask:4 = DecodeWMask32;
+ local tmask:4 = DecodeTMask32;
+ local dst:4 = Rd_GPR32;
+ local src:4 = Rn_GPR32;
+ local bot:4 = (dst & ~(wmask)) | (((src>>ImmRConst32)|(src<<(32-ImmRConst32))) & wmask);
+ Rd_GPR64 = zext((dst & ~(tmask)) | (bot & tmask));
+}
+
+# C6.2.30 BFM page C6-1197 line 70576 MATCH x33000000/mask=x7f800000
+# C6.2.28 BFC page C6-1193 line 70394 MATCH x330003e0/mask=x7f8003e0
+# C6.2.29 BFI page C6-1195 line 70484 MATCH x33000000/mask=x7f800000
+# C6.2.31 BFXIL page C6-1199 line 70700 MATCH x33000000/mask=x7f800000
+# CONSTRUCT xb3400002/mask=xffc00002 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst xb3400002/mask=xffc00002 --status pass
+
+:bfm Rd_GPR64, Rn_GPR64, ImmR_bitfield64_imm, ImmS_bitfield64_imm
+is ImmS_LT_ImmR=1 & sf=1 & opc=1 & b_2428=0x13 & b_2323=0 & n=1 & ImmR_bitfield64_imm & ImmRConst64 & ImmS_bitfield64_imm & Rn_GPR64 & Rd_GPR64 & DecodeWMask64 & DecodeTMask64
+{
+ local wmask:8 = DecodeWMask64;
+ local tmask:8 = DecodeTMask64;
+ local dst:8 = Rd_GPR64;
+ local src:8 = Rn_GPR64;
+ local bot:8 = (dst & ~(wmask)) | (((src>>ImmRConst64)|(src<<(64-ImmRConst64))) & wmask);
+ Rd_GPR64 = (dst & ~(tmask)) | (bot & tmask);
+}
+
+# C6.2.28 BFXIL page C6-567 line 33333 KEEPWITH
+
+BFextractWidth32: "#"^imm is ImmR & ImmS [ imm = ImmS - ImmR + 1; ] { export *[const]:4 imm; }
+BFextractWidth64: "#"^imm is ImmR & ImmS [ imm = ImmS - ImmR + 1; ] { export *[const]:8 imm; }
+
+# C6.2.31 BFXIL page C6-1199 line 70700 MATCH x33000000/mask=x7f800000
+# C6.2.28 BFC page C6-1193 line 70394 MATCH x330003e0/mask=x7f8003e0
+# C6.2.29 BFI page C6-1195 line 70484 MATCH x33000000/mask=x7f800000
+# C6.2.30 BFM page C6-1197 line 70576 MATCH x33000000/mask=x7f800000
+# CONSTRUCT x33000000/mask=xffe08002 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst x33000000/mask=xffe08002 --status pass
+
+# Alias for bfm where UInt(imms) >= UInt(immr)
+
+:bfxil Rd_GPR32, Rn_GPR32, ImmRConst32, BFextractWidth32
+is ImmS_LT_ImmR=0 & sf=0 & opc=1 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & BFextractWidth32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ dst:4 = Rd_GPR32;
+ src:4 = Rn_GPR32;
+ mask:4 = (0xffffffff >> (32 - BFextractWidth32));
+ tmp:4 = (src >> ImmRConst32) & mask;
+ Rd_GPR64 = zext((dst & ~(mask)) | tmp);
+}
+
+# C6.2.31 BFXIL page C6-1199 line 70700 MATCH x33000000/mask=x7f800000
+# C6.2.28 BFC page C6-1193 line 70394 MATCH x330003e0/mask=x7f8003e0
+# C6.2.29 BFI page C6-1195 line 70484 MATCH x33000000/mask=x7f800000
+# C6.2.30 BFM page C6-1197 line 70576 MATCH x33000000/mask=x7f800000
+# CONSTRUCT xb3400000/mask=xffc00002 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst xb3400000/mask=xffc00002 --status pass
+
+# Alias for bfm where UInt(imms) >= UInt(immr)
+
+:bfxil Rd_GPR64, Rn_GPR64, ImmRConst64, BFextractWidth64
+is ImmS_LT_ImmR=0 & sf=1 & opc=1 & b_2428=0x13 & b_2323=0 & n=1 & ImmRConst64 & BFextractWidth64 & Rn_GPR64 & Rd_GPR64
+{
+ dst:8 = Rd_GPR64;
+ src:8 = Rn_GPR64;
+ mask:8 = (0xffffffffffffffff >> (64 - BFextractWidth64));
+ tmp:8 = (src >> ImmRConst64) & mask;
+ Rd_GPR64 = ((dst & ~(mask)) | tmp);
+}
+
+# C6.2.32 BIC (shifted register) page C6-1201 line 70793 MATCH x0a200000/mask=x7f200000
+# CONSTRUCT x0a200000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x0a200000/mask=xff200000 --status pass
+
+:bic Rd_GPR32, Rn_GPR32, RegShift32Log
+is sf=0 & opc=0 & b_2428=0xa & N=1 & RegShift32Log & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp_3:4 = RegShift32Log;
+ tmp_2:4 = tmp_3 ^ -1:4;
+ tmp_1:4 = Rn_GPR32 & tmp_2;
+ Rd_GPR64 = zext(tmp_1);
+}
+
+# C6.2.32 BIC (shifted register) page C6-1201 line 70793 MATCH x0a200000/mask=x7f200000
+# CONSTRUCT x8a200000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x8a200000/mask=xff200000 --status pass
+
+:bic Rd_GPR64, Rn_GPR64, RegShift64Log
+is sf=1 & opc=0 & b_2428=0xa & N=1 & RegShift64Log & Rn_GPR64 & Rd_GPR64
+{
+ tmp_3:8= RegShift64Log;
+ tmp_2:8 = tmp_3 ^ -1:8;
+ tmp_1:8 = Rn_GPR64 & tmp_2;
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.33 BICS (shifted register) page C6-1203 line 70897 MATCH x6a200000/mask=x7f200000
+# CONSTRUCT x6a200000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x6a200000/mask=xff200000 --status pass --comment "flags"
+
+:bics Rd_GPR32, Rn_GPR32, RegShift32Log
+is sf=0 & opc=3 & b_2428=0xa & N=1 & RegShift32Log & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp_3:4 = RegShift32Log;
+ tmp_2:4 = tmp_3 ^ -1:4;
+ tmp_1:4 = Rn_GPR32 & tmp_2;
+ resultflags(tmp_1);
+ Rd_GPR64 = zext(tmp_1);
+ affectLflags();
+}
+
+# C6.2.33 BICS (shifted register) page C6-1203 line 70897 MATCH x6a200000/mask=x7f200000
+# CONSTRUCT xea200000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xea200000/mask=xff200000 --status pass --comment "flags"
+
+:bics Rd_GPR64, Rn_GPR64, RegShift64Log
+is sf=1 & opc=3 & b_2428=0xa & N=1 & RegShift64Log & Rn_GPR64 & Rd_GPR64
+{
+ tmp_3:8= RegShift64Log;
+ tmp_2:8 = tmp_3 ^ -1:8;
+ tmp_1:8 = Rn_GPR64 & tmp_2;
+ resultflags(tmp_1);
+ Rd_GPR64 = tmp_1;
+ affectLflags();
+}
+
+# C6.2.34 BL page C6-1205 line 71008 MATCH x94000000/mask=xfc000000
+# CONSTRUCT x94000000/mask=xfc000000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x94000000/mask=xfc000000 --status nodest --comment "qemuerr(illegal addresses cause qemu exit)"
+
+:bl Addr26
+is b_31=1 & b_2630=0x05 & Addr26
+{
+ x30 = inst_start + 4;
+ call Addr26;
+}
+
+# C6.2.35 BLR page C6-1206 line 71050 MATCH xd63f0000/mask=xfffffc1f
+# CONSTRUCT xd63f0000/mask=xfffffc1f MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd63f0000/mask=xfffffc1f --status nodest --comment "qemuerr(illegal addresses cause qemu exit)"
+
+:blr Rn_GPR64
+is b_2531=0x6b & b_2324=0 & b_2122=1 & b_1620=0x1f & b_1015=0 & Rn_GPR64 & b_0004=0
+{
+ pc = Rn_GPR64;
+ x30 = inst_start + 4;
+ call [pc];
+}
+
+# C6.2.33 BLRAA, BLRAAZ, BLRAB, BLRABZ page C6-574 line 33668 KEEPWITH
+
+# Z == 0 && M == 0 && Rm = 11111 Key A, zero modifier variant
+
+blinkop: "l" is b_2122=0b01 { x30 = inst_start + 4; call [pc]; }
+blinkop: "" is b_2122=0b00 { goto[pc]; }
+
+# C6.2.36 BLRAA, BLRAAZ, BLRAB, BLRABZ page C6-1207 line 71095 MATCH xd63f0800/mask=xfefff800
+# C6.2.38 BRAA, BRAAZ, BRAB, BRABZ page C6-1210 line 71251 MATCH xd61f0800/mask=xfefff800
+# C6.2.255 RETAA, RETAB page C6-1731 line 102135 MATCH xd65f0bff/mask=xfffffbff
+# CONSTRUCT xd61f081f/mask=xff9ffc1f MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst xd61f081f/mask=xff9ffc1f --status nodest
+
+:b^blinkop^"raaz" Rn_GPR64
+is b_blinkop__raaz___PACpart & b_2531=0b1101011 & b_24=0 & b_23=0 & blinkop & b_1220=0b111110000 & b_11=1 & b_10=0 & b_0004=0b11111 & Rn_GPR64
+{
+ build b_blinkop__raaz___PACpart;
+ pc = Rn_GPR64;
+ build blinkop;
+}
+
+# C6.2.36 BLRAA, BLRAAZ, BLRAB, BLRABZ page C6-1207 line 71095 MATCH xd63f0800/mask=xfefff800
+# C6.2.38 BRAA, BRAAZ, BRAB, BRABZ page C6-1210 line 71251 MATCH xd61f0800/mask=xfefff800
+# CONSTRUCT xd71f0800/mask=xff9ffc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd71f0800/mask=xff9ffc00 --status nodest
+# Z == 1 && M == 0 Key A, register modifier variant
+
+:b^blinkop^"raa" Rn_GPR64, Rd_GPR64xsp
+is b_blinkop__raa___PACpart & b_2531=0b1101011 & b_24=1 & b_23=0 & blinkop & b_1220=0b111110000 & b_11=1 & b_10=0 & Rd_GPR64xsp & Rn_GPR64
+{
+ build b_blinkop__raa___PACpart;
+ pc = Rn_GPR64;
+ build blinkop;
+}
+
+# C6.2.36 BLRAA, BLRAAZ, BLRAB, BLRABZ page C6-1207 line 71095 MATCH xd63f0800/mask=xfefff800
+# C6.2.38 BRAA, BRAAZ, BRAB, BRABZ page C6-1210 line 71251 MATCH xd61f0800/mask=xfefff800
+# C6.2.255 RETAA, RETAB page C6-1731 line 102135 MATCH xd65f0bff/mask=xfffffbff
+# CONSTRUCT xd61f0c1f/mask=xff9ffc1f MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst xd61f0c1f/mask=xff9ffc1f --status nodest
+# Z == 0 && M == 1 && Rm = 11111 Key B, zero modifier variant
+
+:b^blinkop^"rabz" Rn_GPR64
+is b_blinkop__rabz___PACpart & b_2531=0b1101011 & b_24=0 & b_23=0 & blinkop & b_1220=0b111110000 & b_11=1 & b_10=1 & b_0004=0b11111 & Rn_GPR64
+{
+ build b_blinkop__rabz___PACpart;
+ pc = Rn_GPR64;
+ build blinkop;
+}
+
+# C6.2.36 BLRAA, BLRAAZ, BLRAB, BLRABZ page C6-1207 line 71095 MATCH xd63f0800/mask=xfefff800
+# C6.2.38 BRAA, BRAAZ, BRAB, BRABZ page C6-1210 line 71251 MATCH xd61f0800/mask=xfefff800
+# CONSTRUCT xd71f0c00/mask=xff9ffc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd71f0c00/mask=xff9ffc00 --status nodest
+# Z == 1 && M == 1 Key B, register modifier variant
+
+:b^blinkop^"rab" Rn_GPR64, Rd_GPR64xsp
+is b_blinkop__rab___PACpart & b_2531=0b1101011 & b_24=1 & b_23=0 & blinkop & b_1220=0b111110000 & b_11=1 & b_10=1 & Rd_GPR64xsp & Rn_GPR64
+{
+ build b_blinkop__rab___PACpart;
+ pc = Rn_GPR64;
+ build blinkop;
+}
+
+# C6.2.37 BR page C6-1209 line 71202 MATCH xd61f0000/mask=xfffffc1f
+# CONSTRUCT xd61f0000/mask=xfffffc1f MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd61f0000/mask=xfffffc1f --status nodest
+
+:br Rn_GPR64
+is b_2531=0x6b & b_2324=0 & b_2122=0 & b_1620=0x1f & b_1015=0 & Rn_GPR64 & b_0004=0
+{
+ pc = Rn_GPR64;
+ goto [pc];
+}
+
+# C6.2.40 BRK page C6-1213 line 71415 MATCH xd4200000/mask=xffe0001f
+# CONSTRUCT xd4200000/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd4200000/mask=xffe0001f --status nodest
+
+:brk "#"^imm16
+is ALL_BTITARGETS & b_2431=0xd4 & b_2123=1 & imm16 & b_0204=0 & b_0001=0
+{
+ tmp:2 = imm16;
+ preferred_exception_return:8 = inst_next;
+ pc = SoftwareBreakpoint(tmp, preferred_exception_return);
+ goto [pc];
+}
+
+# C6.2.37 CASB, CASAB, CASALB, CASLB page C6-580 line 33952 KEEPWITH
+
+cas_var: "a" is b_22=1 & b_15=0 { }
+cas_var: "al" is b_22=1 & b_15=1 { }
+cas_var: "" is b_22=0 & b_15=0 { }
+cas_var: "l" is b_22=0 & b_15=1 { }
+
+# C6.2.42 CASB, CASAB, CASALB, CASLB page C6-1216 line 71570 MATCH x08a07c00/mask=xffa07c00
+# CONSTRUCT x08a07c00/mask=xffa07c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x08a07c00/mask=xffa07c00 --status nomem
+
+# CAS{,A,AL,L}B size=0b10 (b_3031)
+
+:cas^cas_var^"b" aa_Ws, aa_Wt, [Rn_GPR64xsp]
+is b_3031=0b00 & b_2329=0b0010001 & b_21=1 & b_1014=0b11111 & cas_var & aa_Wt & Rn_GPR64xsp & aa_Ws
+{
+ comparevalue:1 = aa_Ws:1;
+ newvalue:1 = aa_Wt:1;
+ data:1 = *:1 Rn_GPR64xsp;
+ if (data != comparevalue) goto ;
+ *:1 Rn_GPR64xsp = newvalue;
+
+ aa_Ws = zext(data);
+}
+
+# C6.2.43 CASH, CASAH, CASALH, CASLH page C6-1218 line 71692 MATCH x48a07c00/mask=xffa07c00
+# CONSTRUCT x48a07c00/mask=xffa07c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x48a07c00/mask=xffa07c00 --status nomem
+
+# CAS{,A,AL,L}H size=0b10 (b_3031)
+
+:cas^cas_var^"h" aa_Ws, aa_Wt, [Rn_GPR64xsp]
+is b_3031=0b01 & b_2329=0b0010001 & b_21=1 & b_1014=0b11111 & cas_var & aa_Wt & Rn_GPR64xsp & aa_Ws
+{
+ comparevalue:2 = aa_Ws:2;
+ newvalue:2 = aa_Wt:2;
+ data:2 = *:2 Rn_GPR64xsp;
+ if (data != comparevalue) goto ;
+ *:2 Rn_GPR64xsp = newvalue;
+
+ aa_Ws = zext(data);
+}
+
+# C6.2.44 CASP, CASPA, CASPAL, CASPL page C6-1220 line 71814 MATCH x08207c00/mask=xbfa07c00
+# CONSTRUCT x08207c00/mask=xffa17c01 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x08207c00/mask=xffa17c01 --status nomem
+
+# CASP{,A,AL,L} size=0b00 (b_3031)
+
+:casp^cas_var aa_Ws, aa_Wss, aa_Wt, aa_Wtt, [Rn_GPR64xsp]
+is b_3031=0b00 & b_2329=0b0010000 & b_21=1 & b_1014=0b11111 & b_16=0 & b_00=0 & cas_var & aa_Ws & aa_Wss & aa_Wt & aa_Wtt & Rn_GPR64xsp
+{
+@if DATA_ENDIAN == "big"
+ comparevalue:8 = (zext(aa_Ws) << 32) | zext(aa_Wss);
+ newvalue:8 = (zext(aa_Wt) << 32) | zext(aa_Wtt);
+@else
+ comparevalue:8 = (zext(aa_Wss) << 32) | zext(aa_Ws);
+ newvalue:8 = (zext(aa_Wtt) << 32) | zext(aa_Wt);
+@endif
+ data:8 = *:8 Rn_GPR64xsp;
+ if (data != comparevalue) goto ;
+ *:8 Rn_GPR64xsp = newvalue;
+
+@if DATA_ENDIAN == "big"
+ aa_Ws = data(4);
+ aa_Wss = data:4;
+@else
+ aa_Ws = data:4;
+ aa_Wss = data(4);
+@endif
+}
+
+# C6.2.44 CASP, CASPA, CASPAL, CASPL page C6-1220 line 71814 MATCH x08207c00/mask=xbfa07c00
+# CONSTRUCT x48207c00/mask=xffa17c01 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x48207c00/mask=xffa17c01 --status nomem
+
+# CASP{,A,AL,L} size=0b01 (b_3031)
+
+:casp^cas_var aa_Xs, aa_Xss, aa_Xt, aa_Xtt, [Rn_GPR64xsp]
+is b_3031=0b01 & b_2329=0b0010000 & b_21=1 & b_1014=0b11111 & b_16=0 & b_00=0 & cas_var & aa_Xs & aa_Xss & aa_Xt & aa_Xtt & Rn_GPR64xsp
+{
+ local tmp_s:8 = aa_Xs;
+ local tmp_ss:8 = aa_Xss;
+ local tmp_t:8 = aa_Xt;
+ local tmp_tt:8 = aa_Xtt;
+
+@if DATA_ENDIAN == "little"
+ # for little endian, swap Xss/Xs and Xtt/Xt
+ tmp_s = aa_Xss;
+ tmp_ss = aa_Xs;
+ tmp_t = aa_Xtt;
+ tmp_tt = aa_Xt;
+@endif
+
+ local tmp_addr:8 = Rn_GPR64xsp;
+ local tmp_d:8 = *:8 tmp_addr;
+ tmp_addr = tmp_addr + 8;
+ local tmp_dd:8 = *:8 tmp_addr;
+
+ if (tmp_d != tmp_s) goto ;
+ if (tmp_dd != tmp_ss) goto ;
+
+ tmp_addr = Rn_GPR64xsp;
+ *:8 tmp_addr = tmp_t;
+ tmp_addr = tmp_addr + 8;
+ *:8 tmp_addr = tmp_tt;
+
+ aa_Xs = tmp_d;
+ aa_Xss = tmp_dd;
+}
+
+# C6.2.45 CAS, CASA, CASAL, CASL page C6-1223 line 71996 MATCH x88a07c00/mask=xbfa07c00
+# CONSTRUCT x88a07c00/mask=xffa07c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x88a07c00/mask=xffa07c00 --status nomem
+# CAS{,A,AL,L} size=0b10 (b_3031)
+
+:cas^cas_var aa_Ws, aa_Wt, [Rn_GPR64xsp]
+is b_3031=0b10 & b_2329=0b0010001 & b_21=1 & b_1014=0b11111 & cas_var & aa_Wt & Rn_GPR64xsp & aa_Ws
+{
+ comparevalue:4 = aa_Ws;
+ newvalue:4 = aa_Wt;
+ data:4 = *:4 Rn_GPR64xsp;
+ if (data != comparevalue) goto ;
+ *:4 Rn_GPR64xsp = newvalue;
+
+ aa_Ws = data;
+}
+
+# C6.2.45 CAS, CASA, CASAL, CASL page C6-1223 line 71996 MATCH x88a07c00/mask=xbfa07c00
+# CONSTRUCT xc8a07c00/mask=xffa07c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xc8a07c00/mask=xffa07c00 --status nomem
+
+# CAS{,A,AL,L} size=0b11 (b_3031)
+
+:cas^cas_var aa_Xs, aa_Xt, [Rn_GPR64xsp]
+is b_3031=0b11 & b_2329=0b0010001 & b_21=1 & b_1014=0b11111 & cas_var & aa_Xt & Rn_GPR64xsp & aa_Xs
+{
+ comparevalue:8 = aa_Xs;
+ newvalue:8 = aa_Xt;
+ data:8 = *:8 Rn_GPR64xsp;
+ if (data != comparevalue) goto ;
+ *:8 Rn_GPR64xsp = newvalue;
+
+ aa_Xs = data;
+}
+
+# C6.2.41 CBNZ page C6-589 line 34530 KEEPWITH
+
+ZeroOp: "z" is cmpr_op=0 { export 1:1; }
+ZeroOp: "nz" is cmpr_op=1 { export 0:1; }
+
+BitPos: "#"^bitpos is sf=1 & b_31 & b_1923 & Rt_GPR64 [ bitpos = b_31 << 5 | b_1923; ]
+{
+ tmp:1 = ((Rt_GPR64 >> bitpos) & 1) == 0;
+ export tmp;
+}
+
+BitPos: "#"^bitpos is sf=0 & b_31 & b_1923 & Rt_GPR32 [ bitpos = b_31 << 5 | b_1923; ]
+{
+ tmp:1 = ((Rt_GPR32 >> bitpos) & 1) == 0;
+ export tmp;
+}
+
+# C6.2.46 CBNZ page C6-1226 line 72159 MATCH x35000000/mask=x7f000000
+# C6.2.47 CBZ page C6-1227 line 72216 MATCH x34000000/mask=x7f000000
+# CONSTRUCT xb4000000/mask=xfe000000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xb4000000/mask=xfe000000 --status nodest --comment "qemuerr(illegal addresses cause qemu exit)"
+
+:cb^ZeroOp Rd_GPR64, Addr19
+is sf=1 & b_2530=0x1a & ZeroOp & Addr19 & Rd_GPR64
+{
+ tmp:1 = Rd_GPR64 == 0;
+ if (tmp == ZeroOp) goto Addr19;
+}
+
+# C6.2.46 CBNZ page C6-1226 line 72159 MATCH x35000000/mask=x7f000000
+# C6.2.47 CBZ page C6-1227 line 72216 MATCH x34000000/mask=x7f000000
+# CONSTRUCT x34000000/mask=xfe000000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x34000000/mask=xfe000000 --status nodest --comment "qemuerr(illegal addresses cause qemu exit)"
+
+:cb^ZeroOp Rd_GPR32, Addr19
+is sf=0 & b_2530=0x1a & ZeroOp & Addr19 & Rd_GPR32
+{
+ tmp:1 = Rd_GPR32 == 0;
+ if (tmp == ZeroOp) goto Addr19;
+}
+
+# C6.2.46 CBNZ page C6-1226 line 72159 MATCH x35000000/mask=x7f000000
+# CONSTRUCT x35000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x35000000/mask=xff000000 --status nodest --comment "qemuerr(illegal addresses cause qemu exit)"
+
+:cbnz Rt_GPR32, Addr19
+is sf=0 & b_2530=0x1a & cmpr_op=1 & Addr19 & Rt_GPR32
+{
+ if (Rt_GPR32 != 0) goto Addr19;
+}
+
+# C6.2.46 CBNZ page C6-1226 line 72159 MATCH x35000000/mask=x7f000000
+# CONSTRUCT xb5000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xb5000000/mask=xff000000 --status nodest --comment "qemuerr(illegal addresses cause qemu exit)"
+
+:cbnz Rt_GPR64, Addr19
+is sf=1 & b_2530=0x1a & cmpr_op=1 & Addr19 & Rt_GPR64
+{
+ if (Rt_GPR64 != 0) goto Addr19;
+}
+
+# C6.2.47 CBZ page C6-1227 line 72216 MATCH x34000000/mask=x7f000000
+# CONSTRUCT x34000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x34000000/mask=xff000000 --status nodest --comment "qemuerr(illegal addresses cause qemu exit)"
+
+:cbz Rt_GPR32, Addr19
+is sf=0 & b_2530=0x1a & cmpr_op=0 & Addr19 & Rt_GPR32
+{
+ if (Rt_GPR32 == 0) goto Addr19;
+}
+
+# C6.2.47 CBZ page C6-1227 line 72216 MATCH x34000000/mask=x7f000000
+# CONSTRUCT xb4000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xb4000000/mask=xff000000 --status nodest --comment "qemuerr(illegal addresses cause qemu exit)"
+
+:cbz Rt_GPR64, Addr19
+is sf=1 & b_2530=0x1a & cmpr_op=0 & Addr19 & Rt_GPR64
+{
+ if (Rt_GPR64 == 0) goto Addr19;
+}
+
+# C6.2.48 CCMN (immediate) page C6-1228 line 72273 MATCH x3a400800/mask=x7fe00c10
+# CONSTRUCT x3a400800/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x3a400800/mask=xffe00c10 --status pass --comment "flags"
+
+:ccmn Rn_GPR32, UImm5, NZCVImm_uimm4, CondOp
+is sf=0 & op=0 & s=1 & b_2428=0x1a & b_2123=2 & UImm5 & CondOp & b_1111=1 & o2=0 & Rn_GPR32 & o3=0 & NZCVImm_uimm4
+{
+ condition:1 = CondOp;
+ condMask:1 = NZCVImm_uimm4;
+ setCC_NZCV(condMask);
+ if (!condition) goto inst_next;
+ tmp:4 = UImm5;
+ addflags(Rn_GPR32, tmp);
+ result:4 = Rn_GPR32 + tmp;
+ resultflags(result);
+ affectflags();
+}
+
+# C6.2.48 CCMN (immediate) page C6-1228 line 72273 MATCH x3a400800/mask=x7fe00c10
+# CONSTRUCT xba400800/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xba400800/mask=xffe00c10 --status pass --comment "flags"
+
+:ccmn Rn_GPR64, UImm5, NZCVImm_uimm4, CondOp
+is sf=1 & op=0 & s=1 & b_2428=0x1a & b_2123=2 & UImm5 & CondOp & b_1111=1 & o2=0 & Rn_GPR64 & o3=0 & NZCVImm_uimm4
+{
+ condition:1 = CondOp;
+ condMask:1 = NZCVImm_uimm4;
+ setCC_NZCV(condMask);
+ if (!condition) goto inst_next;
+ tmp:8 = zext(UImm5);
+ addflags(Rn_GPR64, tmp);
+ result:8 = Rn_GPR64 + tmp;
+ resultflags(result);
+ affectflags();
+}
+
+# C6.2.49 CCMN (register) page C6-1230 line 72358 MATCH x3a400000/mask=x7fe00c10
+# CONSTRUCT x3a400000/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x3a400000/mask=xffe00c10 --status pass --comment "flags"
+
+:ccmn Rn_GPR32, Rm_GPR32, NZCVImm_uimm4, CondOp
+is sf=0 & op=0 & s=1 & b_2428=0x1a & b_2123=2 & Rm_GPR32 & CondOp & b_1111=0 & o2=0 & Rn_GPR32 & o3=0 & NZCVImm_uimm4
+{
+ condition:1 = CondOp;
+ condMask:1 = NZCVImm_uimm4;
+ setCC_NZCV(condMask);
+ if (!condition) goto inst_next;
+ tmp:4 = Rm_GPR32;
+ addflags(Rn_GPR32, tmp);
+ result:4 = Rn_GPR32 + tmp;
+ resultflags(result);
+ affectflags();
+}
+
+# C6.2.49 CCMN (register) page C6-1230 line 72358 MATCH x3a400000/mask=x7fe00c10
+# CONSTRUCT xba400000/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xba400000/mask=xffe00c10 --status pass --comment "flags"
+
+:ccmn Rn_GPR64, Rm_GPR64, NZCVImm_uimm4, CondOp
+is sf=1 & op=0 & s=1 & b_2428=0x1a & b_2123=2 & Rm_GPR64 & CondOp & b_1111=0 & o2=0 & Rn_GPR64 & o3=0 & NZCVImm_uimm4
+{
+ condition:1 = CondOp;
+ condMask:1 = NZCVImm_uimm4;
+ setCC_NZCV(condMask);
+ if (!condition) goto inst_next;
+ tmp:8 = Rm_GPR64;
+ addflags(Rn_GPR64, tmp);
+ result:8 = Rn_GPR64 + tmp;
+ resultflags(result);
+ affectflags();
+}
+
+# C6.2.50 CCMP (immediate) page C6-1232 line 72446 MATCH x7a400800/mask=x7fe00c10
+# CONSTRUCT x7a400800/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x7a400800/mask=xffe00c10 --status pass --comment "flags"
+
+:ccmp Rn_GPR32, UImm5, NZCVImm_uimm4, CondOp
+is sf=0 & op=1 & s=1 & b_2428=0x1a & b_2123=2 & UImm5 & CondOp & b_1111=1 & o2=0 & Rn_GPR32 & o3=0 & NZCVImm_uimm4
+{
+ condition:1 = CondOp;
+ condMask:1 = NZCVImm_uimm4;
+ setCC_NZCV(condMask);
+ if (!condition) goto inst_next;
+ subflags(Rn_GPR32, UImm5);
+ tmp:4 = Rn_GPR32 - UImm5;
+ resultflags(tmp);
+ affectflags();
+}
+
+# C6.2.50 CCMP (immediate) page C6-1232 line 72446 MATCH x7a400800/mask=x7fe00c10
+# CONSTRUCT xfa400800/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xfa400800/mask=xffe00c10 --status pass --comment "flags"
+
+:ccmp Rn_GPR64, UImm5, NZCVImm_uimm4, CondOp
+is sf=1 & op=1 & s=1 & b_2428=0x1a & b_2123=2 & UImm5 & CondOp & b_1111=1 & o2=0 & Rn_GPR64 & o3=0 & NZCVImm_uimm4
+{
+ condition:1 = CondOp;
+ condMask:1 = NZCVImm_uimm4;
+ setCC_NZCV(condMask);
+ if (!condition) goto inst_next;
+ tmp:8 = zext(UImm5);
+ subflags(Rn_GPR64, tmp);
+ tmp = Rn_GPR64 - tmp;
+ resultflags(tmp);
+ affectflags();
+}
+
+# C6.2.51 CCMP (register) page C6-1234 line 72531 MATCH x7a400000/mask=x7fe00c10
+# CONSTRUCT x7a400000/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x7a400000/mask=xffe00c10 --status pass --comment "flags"
+
+:ccmp Rn_GPR32, Rm_GPR32, NZCVImm_uimm4, CondOp
+is sf=0 & op=1 & s=1 & b_2428=0x1a & b_2123=2 & Rm_GPR32 & CondOp & b_1111=0 & o2=0 & Rn_GPR32 & o3=0 & NZCVImm_uimm4
+{
+ condition:1 = CondOp;
+ condMask:1 = NZCVImm_uimm4;
+ setCC_NZCV(condMask);
+ if (!condition) goto inst_next;
+ subflags(Rn_GPR32, Rm_GPR32);
+ tmp:4 = Rn_GPR32 - Rm_GPR32;
+ resultflags(tmp);
+ affectflags();
+}
+
+# C6.2.51 CCMP (register) page C6-1234 line 72531 MATCH x7a400000/mask=x7fe00c10
+# CONSTRUCT xfa400000/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xfa400000/mask=xffe00c10 --status pass --comment "flags"
+
+:ccmp Rn_GPR64, Rm_GPR64, NZCVImm_uimm4, CondOp
+is sf=1 & op=1 & s=1 & b_2428=0x1a & b_2123=2 & Rm_GPR64 & CondOp & b_1111=0 & o2=0 & Rn_GPR64 & o3=0 & NZCVImm_uimm4
+{
+ condition:1 = CondOp;
+ condMask:1 = NZCVImm_uimm4;
+ setCC_NZCV(condMask);
+ if (!condition) goto inst_next;
+ subflags(Rn_GPR64, Rm_GPR64);
+ tmp:8 = Rn_GPR64 - Rm_GPR64;
+ resultflags(tmp);
+ affectflags();
+}
+
+# C6.2.52 CFINV page C6-1236 line 72619 MATCH xd500401f/mask=xfffff0ff
+# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f
+# CONSTRUCT xd500401f/mask=xfffff0ff MATCHED 2 DOCUMENTED OPCODES
+# xd500401f/mask=xfffff0ff NOT MATCHED BY ANY CONSTRUCTOR
+
+:cfinv
+is b_1231=0b11010101000000000100 & b_0811 & b_0007=0b00011111
+{
+ CY = !CY;
+}
+
+# C6.2.54 CINC page C6-1238 line 72719 MATCH x1a800400/mask=x7fe00c00
+# C6.2.104 CSET page C6-1445 line 86209 MATCH x1a9f07e0/mask=x7fff0fe0
+# C6.2.106 CSINC page C6-1449 line 86382 MATCH x1a800400/mask=x7fe00c00
+# CONSTRUCT x1a800400/mask=xffe00c00 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst x1a800400/mask=xffe00c00 --status pass --comment "flags"
+
+:cinc Rd_GPR32, Rn_GPR32, InvCondOp
+is sf=0 & op=0 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR32 & InvCondOp & b_1011=1 & Rn=Rm & (Rn!=0x1f) & (b_15=0 | b_14=0 | b_13=0) & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ condition:1 = InvCondOp;
+ tmp:4 = Rn_GPR32;
+ if (!condition) goto ;
+ tmp = Rn_GPR32 + 1;
+
+ Rd_GPR64 = zext(tmp);
+}
+
+# C6.2.54 CINC page C6-1238 line 72719 MATCH x1a800400/mask=x7fe00c00
+# C6.2.104 CSET page C6-1445 line 86209 MATCH x1a9f07e0/mask=x7fff0fe0
+# C6.2.106 CSINC page C6-1449 line 86382 MATCH x1a800400/mask=x7fe00c00
+# CONSTRUCT x9a800400/mask=xffe00c00 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst x9a800400/mask=xffe00c00 --status pass --comment "flags"
+
+:cinc Rd_GPR64, Rn_GPR64, InvCondOp
+is sf=1 & op=0 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & InvCondOp & b_1011=1 & Rn=Rm & (Rn!=0x1f) & (b_15=0 | b_14=0 | b_13=0) & Rn_GPR64 & Rd_GPR64
+{
+ condition:1 = InvCondOp;
+ tmp:8 = Rn_GPR64;
+ if (!condition) goto ;
+ tmp = Rn_GPR64 + 1;
+
+ Rd_GPR64 = tmp;
+}
+
+# C6.2.55 CINV page C6-1240 line 72809 MATCH x5a800000/mask=x7fe00c00
+# C6.2.105 CSETM page C6-1447 line 86295 MATCH x5a9f03e0/mask=x7fff0fe0
+# C6.2.107 CSINV page C6-1451 line 86486 MATCH x5a800000/mask=x7fe00c00
+# CONSTRUCT x5a800000/mask=xffe00c00 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst x5a800000/mask=xffe00c00 --status pass --comment "flags"
+
+:cinv Rd_GPR32, Rn_GPR32, InvCondOp
+is sf=0 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR32 & InvCondOp & b_1011=0 & Rn=Rm & (Rn!=0x1f) & (b_15=0 | b_14=0 | b_13=0) & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ condition:1 = InvCondOp;
+ tmp:4 = Rn_GPR32;
+ if (!condition) goto ;
+ tmp = ~Rn_GPR32;
+
+ Rd_GPR64 = zext(tmp);
+}
+
+# C6.2.55 CINV page C6-1240 line 72809 MATCH x5a800000/mask=x7fe00c00
+# C6.2.105 CSETM page C6-1447 line 86295 MATCH x5a9f03e0/mask=x7fff0fe0
+# C6.2.107 CSINV page C6-1451 line 86486 MATCH x5a800000/mask=x7fe00c00
+# CONSTRUCT xda800000/mask=xffe00c00 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst xda800000/mask=xffe00c00 --status pass --comment "flags"
+
+:cinv Rd_GPR64, Rn_GPR64, InvCondOp
+is sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & InvCondOp & b_1011=0 & Rn=Rm & (Rn!=0x1f) & (b_15=0 | b_14=0 | b_13=0) & Rn_GPR64 & Rd_GPR64
+{
+ condition:1 = InvCondOp;
+ tmp:8 = Rn_GPR64;
+ if (!condition) goto ;
+ tmp = ~Rn_GPR64;
+
+ Rd_GPR64 = tmp;
+}
+
+# C6.2.56 CLREX page C6-1242 line 72899 MATCH xd503305f/mask=xfffff0ff
+# CONSTRUCT xd503305f/mask=xfffff0ff MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd503305f/mask=xfffff0ff --status nodest
+
+:clrex CRm_uimm4_def15
+is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_uimm4_def15 & Op2=2 & Rt=0x1f
+{
+ ClearExclusiveLocal();
+}
+
+# C6.2.57 CLS page C6-1243 line 72939 MATCH x5ac01400/mask=x7ffffc00
+# CONSTRUCT x5ac01400/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x5ac01400/mask=xfffffc00 --status pass
+
+:cls Rd_GPR32, Rn_GPR32
+is sf=0 & b_3030=1 & S=0 & b_2428=0x1a & b_2123=6 & dp1.opcode2=0x0 & b_1015=0x5 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ local tmp:4 = (Rn_GPR32 ^ (Rn_GPR32<<1))|0x1;
+ # first make all lower bits =1
+ tmp = tmp | (tmp >> 1);
+ tmp = tmp | (tmp >> 2);
+ tmp = tmp | (tmp >> 4);
+ tmp = tmp | (tmp >> 8);
+ tmp = tmp | (tmp >> 16);
+ # now add the 1 bits together, voila
+ tmp = ((tmp & 0xaaaaaaaa)>>1) + (tmp & 0x55555555);
+ tmp = ((tmp & 0xcccccccc)>>2) + (tmp & 0x33333333);
+ tmp = ((tmp & 0xf0f0f0f0)>>4) + (tmp & 0x0f0f0f0f);
+ tmp = ((tmp & 0xff00ff00)>>8) + (tmp & 0x00ff00ff);
+ tmp = ((tmp & 0xffff0000)>>16) + (tmp & 0x0000ffff);
+ Rd_GPR64 = zext(32 - (tmp & 0x3f));
+}
+
+# C6.2.57 CLS page C6-1243 line 72939 MATCH x5ac01400/mask=x7ffffc00
+# CONSTRUCT xdac01400/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xdac01400/mask=xfffffc00 --status pass
+
+:cls Rd_GPR64, Rn_GPR64
+is sf=1 & b_3030=1 & S=0 & b_2428=0x1a & b_2123=6 & dp1.opcode2=0x0 & b_1015=0x5 & Rn_GPR64 & Rd_GPR64
+{
+ local tmp:8 = (Rn_GPR64 ^ (Rn_GPR64<<1))|0x1;
+ # first make all lower bits =1
+ tmp = tmp | (tmp >> 1);
+ tmp = tmp | (tmp >> 2);
+ tmp = tmp | (tmp >> 4);
+ tmp = tmp | (tmp >> 8);
+ tmp = tmp | (tmp >> 16);
+ tmp = tmp | (tmp >> 32);
+ # now add the 1 bits together, voila
+ tmp = ((tmp & 0xaaaaaaaaaaaaaaaa)>>1) + (tmp & 0x5555555555555555);
+ tmp = ((tmp & 0xcccccccccccccccc)>>2) + (tmp & 0x3333333333333333);
+ tmp = ((tmp & 0xf0f0f0f0f0f0f0f0)>>4) + (tmp & 0x0f0f0f0f0f0f0f0f);
+ tmp = ((tmp & 0xff00ff00ff00ff00)>>8) + (tmp & 0x00ff00ff00ff00ff);
+ tmp = ((tmp & 0xffff0000ffff0000)>>16) + (tmp & 0x0000ffff0000ffff);
+ tmp = ((tmp & 0xffffffff00000000)>>32) + (tmp & 0x00000000ffffffff);
+ Rd_GPR64 = 64 - (tmp & 0x7f);
+}
+
+# C6.2.58 CLZ page C6-1245 line 73022 MATCH x5ac01000/mask=x7ffffc00
+# CONSTRUCT x5ac01000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x5ac01000/mask=xfffffc00 --status pass
+
+:clz Rd_GPR32, Rn_GPR32
+is sf=0 & b_3030=1 & S=0 & b_2428=0x1a & b_2123=6 & dp1.opcode2=0x0 & b_1015=0x4 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ local tmp:4 = Rn_GPR32;
+ # first make all lower bits =1
+ tmp = tmp | (tmp >> 1);
+ tmp = tmp | (tmp >> 2);
+ tmp = tmp | (tmp >> 4);
+ tmp = tmp | (tmp >> 8);
+ tmp = tmp | (tmp >> 16);
+ # now add the 1 bits together, voila
+ tmp = ((tmp & 0xaaaaaaaa)>>1) + (tmp & 0x55555555);
+ tmp = ((tmp & 0xcccccccc)>>2) + (tmp & 0x33333333);
+ tmp = ((tmp & 0xf0f0f0f0)>>4) + (tmp & 0x0f0f0f0f);
+ tmp = ((tmp & 0xff00ff00)>>8) + (tmp & 0x00ff00ff);
+ tmp = ((tmp & 0xffff0000)>>16) + (tmp & 0x0000ffff);
+ Rd_GPR64 = zext(32 - (tmp & 0x3f));
+}
+
+# C6.2.58 CLZ page C6-1245 line 73022 MATCH x5ac01000/mask=x7ffffc00
+# CONSTRUCT xdac01000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xdac01000/mask=xfffffc00 --status pass
+
+:clz Rd_GPR64, Rn_GPR64
+is sf=1 & b_3030=1 & S=0 & b_2428=0x1a & b_2123=6 & dp1.opcode2=0x0 & b_1015=0x4 & Rn_GPR64 & Rd_GPR64
+{
+ local tmp:8 = Rn_GPR64;
+ # first make all lower bits =1
+ tmp = tmp | (tmp >> 1);
+ tmp = tmp | (tmp >> 2);
+ tmp = tmp | (tmp >> 4);
+ tmp = tmp | (tmp >> 8);
+ tmp = tmp | (tmp >> 16);
+ tmp = tmp | (tmp >> 32);
+ # now add the 1 bits together, voila
+ tmp = ((tmp & 0xaaaaaaaaaaaaaaaa)>>1) + (tmp & 0x5555555555555555);
+ tmp = ((tmp & 0xcccccccccccccccc)>>2) + (tmp & 0x3333333333333333);
+ tmp = ((tmp & 0xf0f0f0f0f0f0f0f0)>>4) + (tmp & 0x0f0f0f0f0f0f0f0f);
+ tmp = ((tmp & 0xff00ff00ff00ff00)>>8) + (tmp & 0x00ff00ff00ff00ff);
+ tmp = ((tmp & 0xffff0000ffff0000)>>16) + (tmp & 0x0000ffff0000ffff);
+ tmp = ((tmp & 0xffffffff00000000)>>32) + (tmp & 0x00000000ffffffff);
+ Rd_GPR64 = 64 - (tmp & 0x7f);
+}
+
+# C6.2.59 CMN (extended register) page C6-1246 line 73092 MATCH x2b20001f/mask=x7fe0001f
+# C6.2.7 ADDS (extended register) page C6-1156 line 68516 MATCH x2b200000/mask=x7fe00000
+# CONSTRUCT x2b20001f/mask=xffe0001f MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x2b20001f/mask=xffe0001f --status pass --comment "flags"
+
+:cmn Rn_GPR32wsp, ExtendRegShift32
+is sf=0 & op=0 & S=1 & SBIT_CZNO & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift32 & Rn_GPR32wsp & Rd=0x1f
+{
+ tmp_1:4 = ExtendRegShift32;
+ addflags(Rn_GPR32wsp, tmp_1);
+ result:4 = Rn_GPR32wsp + tmp_1;
+ resultflags(result);
+ build SBIT_CZNO;
+}
+
+# C6.2.59 CMN (extended register) page C6-1246 line 73092 MATCH x2b20001f/mask=x7fe0001f
+# C6.2.7 ADDS (extended register) page C6-1156 line 68516 MATCH x2b200000/mask=x7fe00000
+# CONSTRUCT xab20001f/mask=xffe0001f MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xab20001f/mask=xffe0001f --status pass --comment "flags"
+
+:cmn Rn_GPR64xsp, ExtendRegShift64
+is sf=1 & op=0 & S=1 & SBIT_CZNO & b_2428=0xb & b_2121=1 & opt=0 & ExtendRegShift64 & Rn_GPR64xsp & Rd=0x1f
+{
+ tmp_1:8 = ExtendRegShift64;
+ addflags(Rn_GPR64xsp, tmp_1);
+ result:8 = Rn_GPR64xsp + tmp_1;
+ resultflags(result);
+ build SBIT_CZNO;
+}
+
+# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f
+# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000
+# CONSTRUCT x3100001f/mask=xff00001f MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x3100001f/mask=xff00001f --status pass --comment "flags"
+
+:cmn Rn_GPR32xsp, ImmShift32
+is sf=0 & b_30=0 & b_29=1 & aa_Xd=31 & b_2428=0x11 & ImmShift32 & Rn_GPR32xsp
+{
+ addflags(Rn_GPR32xsp, ImmShift32);
+ tmp:4 = Rn_GPR32xsp + ImmShift32;
+ resultflags(tmp);
+ affectflags();
+}
+
+# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f
+# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000
+# CONSTRUCT xb100001f/mask=xff00001f MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xb100001f/mask=xff00001f --status pass --comment "flags"
+
+:cmn Rn_GPR64xsp, ImmShift64
+is sf=1 & b_30=0 & b_29=1 & aa_Xd=31 & b_2428=0x11 & ImmShift64 & Rn_GPR64xsp
+{
+ addflags(Rn_GPR64xsp, ImmShift64);
+ tmp:8 = Rn_GPR64xsp + ImmShift64;
+ resultflags(tmp);
+ affectflags();
+}
+
+# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f
+# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000
+# CONSTRUCT x3100001f/mask=xffc0001f MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x3100001f/mask=xffc0001f --status pass --comment "flags"
+
+:cmn Rn_GPR32wsp, Imm12_addsubimm_operand_i32_posimm_lsl0
+is sf=0 & op=0 & S=1 & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i32_posimm_lsl0 & Rn_GPR32wsp & Rd=0x1f
+{
+ tmp_1:4 = Imm12_addsubimm_operand_i32_posimm_lsl0;
+ addflags(Rn_GPR32wsp, tmp_1);
+ result:4 = Rn_GPR32wsp + tmp_1;
+ resultflags(result);
+ affectflags();
+}
+
+# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f
+# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000
+# CONSTRUCT x3140001f/mask=xffc0001f MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x3140001f/mask=xffc0001f --status pass --comment "flags"
+
+:cmn Rn_GPR32wsp, Imm12_addsubimm_operand_i32_posimm_lsl12
+is sf=0 & op=0 & S=1 & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i32_posimm_lsl12 & Rn_GPR32wsp & Rd=0x1f
+{
+ tmp_1:4 = Imm12_addsubimm_operand_i32_posimm_lsl12;
+ addflags(Rn_GPR32wsp, tmp_1);
+ result:4 = Rn_GPR32wsp + tmp_1;
+ resultflags(result);
+ affectflags();
+}
+
+# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f
+# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000
+# CONSTRUCT xb100001f/mask=xffc0001f MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xb100001f/mask=xffc0001f --status pass --comment "flags"
+
+:cmn Rn_GPR64xsp, Imm12_addsubimm_operand_i64_posimm_lsl0
+is sf=1 & op=0 & S=1 & SBIT_CZNO & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i64_posimm_lsl0 & Rn_GPR64xsp & Rd=0x1f
+{
+ tmp_1:8 = Imm12_addsubimm_operand_i64_posimm_lsl0;
+ addflags(Rn_GPR64xsp, tmp_1);
+ result:8 = Rn_GPR64xsp + tmp_1;
+ resultflags(result);
+ build SBIT_CZNO;
+}
+
+# C6.2.60 CMN (immediate) page C6-1248 line 73219 MATCH x3100001f/mask=x7f80001f
+# C6.2.8 ADDS (immediate) page C6-1159 line 68669 MATCH x31000000/mask=x7f800000
+# CONSTRUCT xb140001f/mask=xffc0001f MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xb140001f/mask=xffc0001f --status pass --comment "flags"
+
+:cmn Rn_GPR64xsp, Imm12_addsubimm_operand_i64_posimm_lsl12
+is sf=1 & op=0 & S=1 & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i64_posimm_lsl12 & Rn_GPR64xsp & Rd=0x1f
+{
+ tmp_1:8 = Imm12_addsubimm_operand_i64_posimm_lsl12;
+ addflags(Rn_GPR64xsp, tmp_1);
+ result:8 = Rn_GPR64xsp + tmp_1;
+ resultflags(result);
+ affectflags();
+}
+
+# C6.2.61 CMN (shifted register) page C6-1250 line 73309 MATCH x2b00001f/mask=x7f20001f
+# C6.2.9 ADDS (shifted register) page C6-1161 line 68775 MATCH x2b000000/mask=x7f200000
+# CONSTRUCT x2b00001f/mask=xff20801f MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x2b00001f/mask=xff20801f --status pass --comment "flags"
+# if shift == '11' then ReservedValue();
+
+:cmn Rn_GPR32, RegShift32
+is sf=0 & op=0 & S=1 & SBIT_CZNO & b_2428=0xb & b_2121=0 & b_15=0 & RegShift32 & Rn_GPR32 & Rd=0x1f
+{
+ tmp_1:4 = RegShift32;
+ addflags(Rn_GPR32, tmp_1);
+ result:4 = Rn_GPR32 + tmp_1;
+ resultflags(result);
+ build SBIT_CZNO;
+}
+
+# C6.2.61 CMN (shifted register) page C6-1250 line 73309 MATCH x2b00001f/mask=x7f20001f
+# C6.2.9 ADDS (shifted register) page C6-1161 line 68775 MATCH x2b000000/mask=x7f200000
+# CONSTRUCT xab00001f/mask=xff20001f MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xab00001f/mask=xff20001f --status pass --comment "flags"
+
+:cmn Rn_GPR64, RegShift64
+is sf=1 & op=0 & S=1 & SBIT_CZNO & b_2428=0xb & b_2121=0 & RegShift64 & Rn_GPR64 & Rd=0x1f
+{
+ tmp_1:8 = RegShift64;
+ addflags(Rn_GPR64, tmp_1);
+ result:8 = Rn_GPR64 + tmp_1;
+ resultflags(result);
+ build SBIT_CZNO;
+}
+
+# C6.2.62 CMP (extended register) page C6-1252 line 73406 MATCH x6b20001f/mask=x7fe0001f
+# C6.2.362 SUBS (extended register) page C6-1950 line 114543 MATCH x6b200000/mask=x7fe00000
+# CONSTRUCT x6b20001f/mask=xffe0001f MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x6b20001f/mask=xffe0001f --status pass --comment "flags"
+
+:cmp Rn_GPR32wsp, ExtendRegShift32
+is sf=0 & op=1 & S=1 & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift32 & Rn_GPR32wsp & Rd=0x1f
+{
+ subflags(Rn_GPR32wsp, ExtendRegShift32);
+ tmp:4 = Rn_GPR32wsp - ExtendRegShift32;
+ resultflags(tmp);
+ affectflags();
+}
+
+# C6.2.62 CMP (extended register) page C6-1252 line 73406 MATCH x6b20001f/mask=x7fe0001f
+# C6.2.362 SUBS (extended register) page C6-1950 line 114543 MATCH x6b200000/mask=x7fe00000
+# CONSTRUCT xeb20001f/mask=xffe0001f MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xeb20001f/mask=xffe0001f --status pass --comment "flags"
+
+:cmp Rn_GPR64xsp, ExtendRegShift64
+is sf=1 & op=1 & S=1 & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift64 & Rn_GPR64xsp & Rd=0x1f
+{
+ subflags(Rn_GPR64xsp, ExtendRegShift64);
+ tmp:8 = Rn_GPR64xsp - ExtendRegShift64;
+ resultflags(tmp);
+ affectflags();
+}
+
+# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f
+# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000
+# CONSTRUCT x7100001f/mask=xff00001f MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x7100001f/mask=xff00001f --status pass --comment "flags"
+
+:cmp Rn_GPR32xsp, ImmShift32
+is sf=0 & b_30=1 & b_29=1 & b_2428=0x11 & ImmShift32 & Rn_GPR32xsp & aa_Wd=31
+{
+ subflags(Rn_GPR32xsp, ImmShift32);
+ tmp:4 = Rn_GPR32xsp - ImmShift32;
+ resultflags(tmp);
+ affectflags();
+}
+
+# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f
+# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000
+# CONSTRUCT xf100001f/mask=xff00001f MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xf100001f/mask=xff00001f --status pass --comment "flags"
+
+:cmp Rn_GPR64xsp, ImmShift64
+is sf=1 & b_30=1 & b_29=1 & b_2428=0x11 & ImmShift64 & Rn_GPR64xsp & aa_Wd=31
+{
+ subflags(Rn_GPR64xsp, ImmShift64);
+ tmp:8 = Rn_GPR64xsp - ImmShift64;
+ resultflags(tmp);
+ affectflags();
+}
+
+# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f
+# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000
+# CONSTRUCT x7100001f/mask=xffc0001f MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x7100001f/mask=xffc0001f --status pass --comment "flags"
+
+:cmp Rn_GPR32wsp, Imm12_addsubimm_operand_i32_negimm_lsl0
+is sf=0 & op=1 & S=1 & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i32_negimm_lsl0 & Rn_GPR32wsp & Rd=0x1f
+{
+ tmp_1:4 = Imm12_addsubimm_operand_i32_negimm_lsl0;
+ subflags(Rn_GPR32wsp, Imm12_addsubimm_operand_i32_negimm_lsl0);
+ result:4 = Rn_GPR32wsp - tmp_1;
+ resultflags(result);
+ affectflags();
+}
+
+# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f
+# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000
+# CONSTRUCT x7140001f/mask=xffc0001f MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x7140001f/mask=xffc0001f --status pass --comment "flags"
+
+:cmp Rn_GPR32wsp, Imm12_addsubimm_operand_i32_negimm_lsl12
+is sf=0 & op=1 & S=1 & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i32_negimm_lsl12 & Rn_GPR32wsp & Rd=0x1f
+{
+ tmp_2:4 = Imm12_addsubimm_operand_i32_negimm_lsl12;
+ subflags(Rn_GPR32wsp, tmp_2);
+ tmp_1:4 = Rn_GPR32wsp - tmp_2;
+ resultflags(tmp_1);
+ affectflags();
+}
+
+# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f
+# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000
+# CONSTRUCT xf100001f/mask=xffc0001f MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xf100001f/mask=xffc0001f --status pass --comment "flags"
+
+:cmp Rn_GPR64xsp, Imm12_addsubimm_operand_i64_negimm_lsl0
+is sf=1 & op=1 & S=1 & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i64_negimm_lsl0 & Rn_GPR64xsp & Rd=0x1f
+{
+ tmp_2:8 = Imm12_addsubimm_operand_i64_negimm_lsl0;
+ subflags(Rn_GPR64xsp, tmp_2);
+ tmp_1:8 = Rn_GPR64xsp - tmp_2;
+ resultflags(tmp_1);
+ affectflags();
+}
+
+# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f
+# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000
+# CONSTRUCT xf140001f/mask=xffc0001f MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xf140001f/mask=xffc0001f --status pass --comment "flags"
+
+:cmp Rn_GPR64xsp, Imm12_addsubimm_operand_i64_negimm_lsl12
+is sf=1 & op=1 & S=1 & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i64_negimm_lsl12 & Rn_GPR64xsp & Rd=0x1f
+{
+ tmp_2:8 = Imm12_addsubimm_operand_i64_negimm_lsl12;
+ subflags(Rn_GPR64xsp, tmp_2);
+ tmp_1:8 = Rn_GPR64xsp - tmp_2;
+ resultflags(tmp_1);
+ affectflags();
+}
+
+# C6.2.64 CMP (shifted register) page C6-1256 line 73623 MATCH x6b00001f/mask=x7f20001f
+# C6.2.235 NEGS page C6-1696 line 100340 MATCH x6b0003e0/mask=x7f2003e0
+# C6.2.364 SUBS (shifted register) page C6-1955 line 114807 MATCH x6b000000/mask=x7f200000
+# CONSTRUCT x6b00001f/mask=xff20001f MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst x6b00001f/mask=xff20001f --status pass --comment "flags"
+
+:cmp Rn_GPR32, RegShift32
+is sf=0 & op=1 & S=1 & b_2428=0xb & b_2121=0 & RegShift32 & Rn!=0x1f & Rn_GPR32 & Rd=0x1f
+{
+ subflags(Rn_GPR32, RegShift32);
+ tmp:4 = Rn_GPR32 - RegShift32;
+ resultflags(tmp);
+ affectflags();
+}
+
+# C6.2.64 CMP (shifted register) page C6-1256 line 73623 MATCH x6b00001f/mask=x7f20001f
+# C6.2.235 NEGS page C6-1696 line 100340 MATCH x6b0003e0/mask=x7f2003e0
+# C6.2.364 SUBS (shifted register) page C6-1955 line 114807 MATCH x6b000000/mask=x7f200000
+# CONSTRUCT xeb00001f/mask=xff20001f MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst xeb00001f/mask=xff20001f --status pass --comment "flags"
+
+:cmp Rn_GPR64, RegShift64
+is sf=1 & op=1 & S=1 & b_2428=0xb & b_2121=0 & Rm_GPR64 & RegShift64 & Rn!=0x1f & Rn_GPR64 & Rd=0x1f
+{
+ subflags(Rn_GPR64, RegShift64);
+ tmp:8 = Rn_GPR64 - RegShift64;
+ resultflags(tmp);
+ affectflags();
+}
+
+# C6.2.66 CNEG page C6-1259 line 73771 MATCH x5a800400/mask=x7fe00c00
+# C6.2.108 CSNEG page C6-1453 line 86590 MATCH x5a800400/mask=x7fe00c00
+# CONSTRUCT x5a800400/mask=xffe00c00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x5a800400/mask=xffe00c00 --status pass --comment "flags"
+
+:cneg Rd_GPR32, Rn_GPR32, InvCondOp
+is sf=0 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR32 & InvCondOp & b_1011=1 & Rn=Rm & (b_15=0 | b_14=0 | b_13=0) & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ condition:1 = InvCondOp;
+ tmp:4 = -Rn_GPR32;
+ if (condition) goto ;
+ tmp = Rn_GPR32;
+
+ Rd_GPR64 = zext(tmp);
+}
+
+# C6.2.66 CNEG page C6-1259 line 73771 MATCH x5a800400/mask=x7fe00c00
+# C6.2.108 CSNEG page C6-1453 line 86590 MATCH x5a800400/mask=x7fe00c00
+# CONSTRUCT xda800400/mask=xffe00c00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xda800400/mask=xffe00c00 --status pass --comment "flags"
+
+:cneg Rd_GPR64, Rn_GPR64, InvCondOp
+is sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & InvCondOp & b_1011=1 & Rn=Rm & (b_15=0 | b_14=0 | b_13=0) & Rn_GPR64 & Rd_GPR64
+{
+ condition:1 = InvCondOp;
+ tmp:8 = -Rn_GPR64;
+ if (condition) goto ;
+ tmp = Rn_GPR64;
+
+ Rd_GPR64 = tmp;
+}
+
+# C6.2.68 CPYFP, CPYFM, CPYFE page C6-1262 line 73913 MATCH x19000400/mask=x3f20fc00
+# C6.2.69 CPYFPN, CPYFMN, CPYFEN page C6-1267 line 74246 MATCH x1900c400/mask=x3f20fc00
+# C6.2.70 CPYFPRN, CPYFMRN, CPYFERN page C6-1272 line 74579 MATCH x19008400/mask=x3f20fc00
+# C6.2.79 CPYFPWN, CPYFMWN, CPYFEWN page C6-1317 line 77576 MATCH x19004400/mask=x3f20fc00
+# CONSTRUCT x19000400/mask=x3f20fc00 MATCHED 2 DOCUMENTED OPCODES
+
+cpyPhase:"p" is opt=0 {export 0:1;}
+cpyPhase:"m" is opt=1 {export 1:1;}
+cpyPhase:"e" is opt=2 {export 2:1;}
+
+cpyType: "" is b_1015=0x01 {export 0x01:1; }
+cpyType: "n" is b_1015=0x31 {export 0x31:1; }
+cpyType: "rn" is b_1015=0x21 {export 0x21:1; }
+cpyType: "wn" is b_1015=0x11 {export 0x11:1; }
+
+cpyType: "rt" is b_1015=0x09 {export 0x09:1; }
+cpyType: "rtn" is b_1015=0x39 {export 0x39:1; }
+cpyType: "rtrn" is b_1015=0x29 {export 0x29:1; }
+cpyType: "rtwn" is b_1015=0x19 {export 0x19:1; }
+
+cpyType: "t" is b_1015=0x0d {export 0x0d:1; }
+cpyType: "tn" is b_1015=0x3d {export 0x3d:1; }
+cpyType: "trn" is b_1015=0x2d {export 0x2d:1; }
+cpyType: "twn" is b_1015=0x1d {export 0x1d:1; }
+
+cpyType: "wt" is b_1015=0x03 {export 0x03:1; }
+cpyType: "wtn" is b_1015=0x33 {export 0x33:1; }
+cpyType: "wtrn" is b_1015=0x23 {export 0x23:1; }
+cpyType: "wtwn" is b_1015=0x13 {export 0x13:1; }
+
+
+define pcodeop MemoryCopyForward;
+# Memory Copy Forward-only
+:cpyf^cpyPhase^cpyType [Rd_GPR64]!, [Rs_GPR64]!, Rn_GPR64^"!"
+is size.ldstr & b_2429=0x19 & opt != 3 & cpyPhase & b_2121=0 & Rs_GPR64 & cpyType & Rn_GPR64 & Rd_GPR64
+{
+ MemoryCopyForward(Rd_GPR64, Rs_GPR64, Rn_GPR64, cpyType, cpyPhase);
+}
+define pcodeop MemoryCopy;
+:cpy^cpyPhase^cpyType [Rd_GPR64]!, [Rs_GPR64]!, Rn_GPR64^"!"
+is size.ldstr & b_2429=0x1d & opt != 3 & cpyPhase & b_2121=0 & Rs_GPR64 & cpyType & Rn_GPR64 & Rd_GPR64
+{
+ MemoryCopy(Rd_GPR64, Rs_GPR64, Rn_GPR64, cpyType, cpyPhase);
+}
+
+# C6.2.59 CRC32B, CRC32H, CRC32W, CRC32X page C6-611 line 35802 KEEPWITH
+# sf == 0 && sz = 00 CRC32CB variant
+
+crcpoly: "" is b_12=0 {tmp:4 = 0x04C11DB7; export *[const]:4 tmp; }
+crcpoly: "c" is b_12=1 { tmp:4 = 0x1EDC6F41; export *[const]:4 tmp; }
+
+# C6.2.100 CRC32B, CRC32H, CRC32W, CRC32X page C6-1438 line 85850 MATCH x1ac04000/mask=x7fe0f000
+# C6.2.101 CRC32CB, CRC32CH, CRC32CW, CRC32CX page C6-1440 line 85958 MATCH x1ac05000/mask=x7fe0f000
+# CONSTRUCT x1ac04000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x1ac04000/mask=xffe0ec00 --status noqemu
+
+:crc32^crcpoly^"b" Rd_GPR32, Rn_GPR32, Rm_GPR32
+is b_31=0 & b_2130=0b0011010110 & b_1315=0b010 & b_1011=0b00 & crcpoly & Rm_GPR32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ local tmp_Rd:4 = crc32b(Rn_GPR32, Rm_GPR32, crcpoly);
+ Rd_GPR64 = zext(tmp_Rd);
+}
+
+# C6.2.100 CRC32B, CRC32H, CRC32W, CRC32X page C6-1438 line 85850 MATCH x1ac04000/mask=x7fe0f000
+# C6.2.101 CRC32CB, CRC32CH, CRC32CW, CRC32CX page C6-1440 line 85958 MATCH x1ac05000/mask=x7fe0f000
+# CONSTRUCT x1ac04400/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x1ac04400/mask=xffe0ec00 --status noqemu
+# sf == 0 && sz = 01 CRC32CH variant
+
+:crc32^crcpoly^"h" Rd_GPR32, Rn_GPR32, Rm_GPR32
+is b_31=0 & b_2130=0b0011010110 & b_1315=0b010 & b_1011=0b01 & crcpoly & Rm_GPR32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ local tmp_Rd:4 = crc32h(Rn_GPR32, Rm_GPR32, crcpoly);
+ Rd_GPR64 = zext(tmp_Rd);
+}
+
+# C6.2.100 CRC32B, CRC32H, CRC32W, CRC32X page C6-1438 line 85850 MATCH x1ac04000/mask=x7fe0f000
+# C6.2.101 CRC32CB, CRC32CH, CRC32CW, CRC32CX page C6-1440 line 85958 MATCH x1ac05000/mask=x7fe0f000
+# CONSTRUCT x1ac04800/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x1ac04800/mask=xffe0ec00 --status noqemu
+# sf == 0 && sz = 10 CRC32CW variant
+
+:crc32^crcpoly^"w" Rd_GPR32, Rn_GPR32, Rm_GPR32
+is b_31=0 & b_2130=0b0011010110 & b_1315=0b010 & b_1011=0b10 & crcpoly & Rm_GPR32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ local tmp_Rd:4 = crc32w(Rn_GPR32, Rm_GPR32, crcpoly);
+ Rd_GPR64 = zext(tmp_Rd);
+}
+
+# C6.2.100 CRC32B, CRC32H, CRC32W, CRC32X page C6-1438 line 85850 MATCH x1ac04000/mask=x7fe0f000
+# C6.2.101 CRC32CB, CRC32CH, CRC32CW, CRC32CX page C6-1440 line 85958 MATCH x1ac05000/mask=x7fe0f000
+# CONSTRUCT x9ac04c00/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x9ac04c00/mask=xffe0ec00 --status noqemu
+# sf == 1 && sz = 11 CRC32CX variant
+
+:crc32^crcpoly^"x" Rd_GPR32, Rn_GPR32, Rm_GPR64
+is b_31=1 & b_2130=0b0011010110 & b_1315=0b010 & b_1011=0b11 & crcpoly & Rm_GPR64 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ local tmp_Rd:4 = crc32x(Rn_GPR32, Rm_GPR64, crcpoly);
+ Rd_GPR64 = zext(tmp_Rd);
+}
+
+# C6.2.103 CSEL page C6-1443 line 86120 MATCH x1a800000/mask=x7fe00c00
+# CONSTRUCT x1a800000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x1a800000/mask=xffe00c00 --status pass --comment "flags"
+
+:csel Rd_GPR32, Rn_GPR32, Rm_GPR32, CondOp
+is sf=0 & op=0 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR32 & CondOp & b_1011=0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ condition:1 = CondOp;
+ tmp:4 = Rn_GPR32;
+ if (condition) goto ;
+ tmp = Rm_GPR32;
+
+ Rd_GPR64 = zext(tmp);
+}
+
+# C6.2.103 CSEL page C6-1443 line 86120 MATCH x1a800000/mask=x7fe00c00
+# CONSTRUCT x9a800000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x9a800000/mask=xffe00c00 --status pass --comment "flags"
+
+:csel Rd_GPR64, Rn_GPR64, Rm_GPR64, CondOp
+is sf=1 & op=0 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & CondOp & b_1011=0 & Rn_GPR64 & Rd_GPR64
+{
+ condition:1 = CondOp;
+ tmp:8 = Rn_GPR64;
+ if (condition) goto ;
+ tmp = Rm_GPR64;
+
+ Rd_GPR64 = tmp;
+}
+
+# C6.2.104 CSET page C6-1445 line 86209 MATCH x1a9f07e0/mask=x7fff0fe0
+# C6.2.54 CINC page C6-1238 line 72719 MATCH x1a800400/mask=x7fe00c00
+# C6.2.106 CSINC page C6-1449 line 86382 MATCH x1a800400/mask=x7fe00c00
+# CONSTRUCT x1a9f07e0/mask=xffff0fe0 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst x1a9f07e0/mask=xffff0fe0 --status pass --comment "flags"
+
+:cset Rd_GPR32, InvCondOp
+is sf=0 & op=0 & s=0 & b_2428=0x1a & b_2123=4 & InvCondOp & b_1011=1 & Rn=0x1f & Rm=0x1f & (b_15=0 | b_14=0 | b_13=0) & Rd_GPR32 & Rd_GPR64
+{
+ condition:1 = InvCondOp;
+ Rd_GPR64 = zext(condition);
+}
+
+# C6.2.104 CSET page C6-1445 line 86209 MATCH x1a9f07e0/mask=x7fff0fe0
+# C6.2.54 CINC page C6-1238 line 72719 MATCH x1a800400/mask=x7fe00c00
+# C6.2.106 CSINC page C6-1449 line 86382 MATCH x1a800400/mask=x7fe00c00
+# CONSTRUCT x9a9f07e0/mask=xffff0fe0 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst x9a9f07e0/mask=xffff0fe0 --status pass --comment "flags"
+
+:cset Rd_GPR64, InvCondOp
+is sf=1 & op=0 & s=0 & b_2428=0x1a & b_2123=4 & InvCondOp & b_1011=1 & Rn=0x1f & Rm=0x1f & (b_15=0 | b_14=0 | b_13=0) & Rd_GPR64
+{
+ condition:1 = InvCondOp;
+ Rd_GPR64 = zext(condition);
+}
+
+# C6.2.105 CSETM page C6-1447 line 86295 MATCH x5a9f03e0/mask=x7fff0fe0
+# C6.2.55 CINV page C6-1240 line 72809 MATCH x5a800000/mask=x7fe00c00
+# C6.2.107 CSINV page C6-1451 line 86486 MATCH x5a800000/mask=x7fe00c00
+# CONSTRUCT x5a9f03e0/mask=xffff0fe0 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst x5a9f03e0/mask=xffff0fe0 --status pass --comment "flags"
+
+:csetm Rd_GPR32, InvCondOp
+is sf=0 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR32 & InvCondOp & b_1011=0 & Rn=0x1f & Rm=0x1f & (b_15=0 | b_14=0 | b_13=0) & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ condition:1 = InvCondOp;
+ tmp:4 = zext(condition) * -1;
+ Rd_GPR64 = zext(tmp);
+}
+
+# C6.2.105 CSETM page C6-1447 line 86295 MATCH x5a9f03e0/mask=x7fff0fe0
+# C6.2.55 CINV page C6-1240 line 72809 MATCH x5a800000/mask=x7fe00c00
+# C6.2.107 CSINV page C6-1451 line 86486 MATCH x5a800000/mask=x7fe00c00
+# CONSTRUCT xda9f03e0/mask=xffff0fe0 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst xda9f03e0/mask=xffff0fe0 --status pass --comment "flags"
+
+:csetm Rd_GPR64, InvCondOp
+is sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & InvCondOp & b_1011=0 & Rn=0x1f & Rm=0x1f & (b_15=0 | b_14=0 | b_13=0) & Rn_GPR64 & Rd_GPR64
+{
+ condition:1 = InvCondOp;
+ Rd_GPR64 = zext(condition) * -1;
+}
+
+# C6.2.106 CSINC page C6-1449 line 86382 MATCH x1a800400/mask=x7fe00c00
+# C6.2.54 CINC page C6-1238 line 72719 MATCH x1a800400/mask=x7fe00c00
+# C6.2.104 CSET page C6-1445 line 86209 MATCH x1a9f07e0/mask=x7fff0fe0
+# CONSTRUCT x1a800400/mask=xffe00c00 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst x1a800400/mask=xffe00c00 --status pass --comment "flags"
+
+:csinc Rd_GPR32, Rn_GPR32, Rm_GPR32, CondOp
+is sf=0 & op=0 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR32 & CondOp & b_1011=1 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ condition:1 = CondOp;
+ tmp:4 = Rn_GPR32;
+ if (condition) goto ;
+ tmp = Rm_GPR32 + 1;
+
+ Rd_GPR64 = zext(tmp);
+}
+
+# C6.2.106 CSINC page C6-1449 line 86382 MATCH x1a800400/mask=x7fe00c00
+# C6.2.54 CINC page C6-1238 line 72719 MATCH x1a800400/mask=x7fe00c00
+# C6.2.104 CSET page C6-1445 line 86209 MATCH x1a9f07e0/mask=x7fff0fe0
+# CONSTRUCT x9a800400/mask=xffe00c00 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst x9a800400/mask=xffe00c00 --status pass --comment "flags"
+
+:csinc Rd_GPR64, Rn_GPR64, Rm_GPR64, CondOp
+is sf=1 & op=0 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & CondOp & b_1011=1 & Rn_GPR64 & Rd_GPR64
+{
+ condition:1 = CondOp;
+ tmp:8 = Rn_GPR64;
+ if (condition) goto ;
+ tmp = Rm_GPR64 + 1;
+
+ Rd_GPR64 = tmp;
+}
+
+# C6.2.107 CSINV page C6-1451 line 86486 MATCH x5a800000/mask=x7fe00c00
+# C6.2.55 CINV page C6-1240 line 72809 MATCH x5a800000/mask=x7fe00c00
+# C6.2.105 CSETM page C6-1447 line 86295 MATCH x5a9f03e0/mask=x7fff0fe0
+# CONSTRUCT x5a800000/mask=xffe00c00 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst x5a800000/mask=xffe00c00 --status pass --comment "flags"
+
+:csinv Rd_GPR32, Rn_GPR32, Rm_GPR32, CondOp
+is sf=0 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR32 & CondOp & b_1011=0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ condition:1 = CondOp;
+ tmp:4 = Rn_GPR32;
+ if (condition) goto ;
+ tmp = ~Rm_GPR32;
+
+ Rd_GPR64 = zext(tmp);
+}
+
+# C6.2.107 CSINV page C6-1451 line 86486 MATCH x5a800000/mask=x7fe00c00
+# C6.2.55 CINV page C6-1240 line 72809 MATCH x5a800000/mask=x7fe00c00
+# C6.2.105 CSETM page C6-1447 line 86295 MATCH x5a9f03e0/mask=x7fff0fe0
+# CONSTRUCT xda800000/mask=xffe00c00 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst xda800000/mask=xffe00c00 --status pass --comment "flags"
+
+:csinv Rd_GPR64, Rn_GPR64, Rm_GPR64, CondOp
+is sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & CondOp & b_1011=0 & Rn_GPR64 & Rd_GPR64
+{
+ condition:1 = CondOp;
+ tmp:8 = Rn_GPR64;
+ if (condition) goto ;
+ tmp = ~Rm_GPR64;
+
+ Rd_GPR64 = tmp;
+}
+
+# C6.2.108 CSNEG page C6-1453 line 86590 MATCH x5a800400/mask=x7fe00c00
+# C6.2.66 CNEG page C6-1259 line 73771 MATCH x5a800400/mask=x7fe00c00
+# CONSTRUCT x5a800400/mask=xffe00c00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x5a800400/mask=xffe00c00 --status pass --comment "flags"
+
+:csneg Rd_GPR32, Rn_GPR32, Rm_GPR32, CondOp
+is sf=0 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR32 & CondOp & b_1011=1 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ condition:1 = CondOp;
+ tmp:4 = Rn_GPR32;
+ if (condition) goto ;
+ tmp = -Rm_GPR32;
+
+ Rd_GPR64 = zext(tmp);
+}
+
+# C6.2.108 CSNEG page C6-1453 line 86590 MATCH x5a800400/mask=x7fe00c00
+# C6.2.66 CNEG page C6-1259 line 73771 MATCH x5a800400/mask=x7fe00c00
+# CONSTRUCT xda800400/mask=xffe00c00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xda800400/mask=xffe00c00 --status pass --comment "flags"
+
+:csneg Rd_GPR64, Rn_GPR64, Rm_GPR64, CondOp
+is sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=4 & Rm_GPR64 & CondOp & b_1011=1 & Rn_GPR64 & Rd_GPR64
+{
+ condition:1 = CondOp;
+ tmp:8 = Rn_GPR64;
+ if (condition) goto ;
+ tmp = -Rm_GPR64;
+
+ Rd_GPR64 = tmp;
+}
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50b7420/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst xd50b7420/mask=xffffffe0 --status nodest
+
+:dc "ZVA", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b0100 & b_0507=0b001 & Rt_GPR64
+{ DC_ZVA(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5087620/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst xd5087620/mask=xffffffe0 --status nodest
+
+:dc "IVAC", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b0110 & b_0507=0b001 & Rt_GPR64
+{ DC_IVAC(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5087640/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst xd5087640/mask=xffffffe0 --status nodest
+
+:dc "ISW", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b0110 & b_0507=0b010 & Rt_GPR64
+{ DC_ISW(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50b7a20/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst xd50b7a20/mask=xffffffe0 --status nopcodeop
+
+:dc "CVAC", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1010 & b_0507=0b001 & Rt_GPR64
+{ DC_CVAC(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5087a40/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst xd5087a40/mask=xffffffe0 --status nodest
+
+:dc "CSW", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1010 & b_0507=0b010 & Rt_GPR64
+{ DC_CSW(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50b7b20/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst xd50b7b20/mask=xffffffe0 --status nodest
+
+:dc "CVAU", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1011 & b_0507=0b001 & Rt_GPR64
+{ DC_CVAU(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50b7e20/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst xd50b7e20/mask=xffffffe0 --status nodest
+
+:dc "CIVAC", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1110 & b_0507=0b001 & Rt_GPR64
+{ DC_CIVAC(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5087e40/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst xd5087e40/mask=xffffffe0 --status nodest
+
+:dc "CISW", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1110 & b_0507=0b010 & Rt_GPR64
+{ DC_CISW(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50b7c20/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst xd50b7c20/mask=xffffffe0 --status nodest
+
+:dc "CVAP", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1100 & b_0507=0b001 & Rt_GPR64
+{ DC_CVAP(Rt_GPR64); }
+
+# C6.2.110 DCPS1 page C6-1457 line 86790 MATCH xd4a00001/mask=xffe0001f
+# CONSTRUCT xd4a00001/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd4a00001/mask=xffe0001f --status nodest
+
+:dcps1 imm16
+is b_2431=0xd4 & excCode=5 & imm16 & excCode2=0 & ll=1
+{
+ DCPSInstruction(1:2, imm16:2);
+}
+
+# C6.2.111 DCPS2 page C6-1458 line 86856 MATCH xd4a00002/mask=xffe0001f
+# CONSTRUCT xd4a00002/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd4a00002/mask=xffe0001f --status nodest
+
+:dcps2 imm16
+is b_2431=0xd4 & excCode=5 & imm16 & excCode2=0 & ll=2
+{
+ DCPSInstruction(2:2, imm16:2);
+}
+
+# C6.2.112 DCPS3 page C6-1459 line 86927 MATCH xd4a00003/mask=xffe0001f
+# CONSTRUCT xd4a00003/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd4a00003/mask=xffe0001f --status nodest
+
+:dcps3 imm16
+is b_2431=0xd4 & excCode=5 & imm16 & excCode2=0 & ll=3
+{
+ DCPSInstruction(3:2, imm16:2);
+}
+
+# C6.2.114 DMB page C6-1461 line 87029 MATCH xd50330bf/mask=xfffff0ff
+# CONSTRUCT xd50330bf/mask=xfffff3ff MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd50330bf/mask=xfffff3ff --status nodest
+
+:dmb CRm_CRx
+is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CRm_CRx & CRm_32 & CRm_10=0 & Op2=5 & Rt=0x1f
+{
+ types:1 = 0x0;
+ domain:1 = CRm_32;
+ DataMemoryBarrier(domain, types);
+}
+
+# C6.2.114 DMB page C6-1461 line 87029 MATCH xd50330bf/mask=xfffff0ff
+# CONSTRUCT xd50330bf/mask=xfffff0ff MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd50330bf/mask=xfffff0ff --status nodest
+
+:dmb CRm_dbarrier_op
+is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CRm_32 & CRm_10 & Op2=5 & Rt=0x1f
+{
+ types:1 = CRm_10;
+ domain:1 = CRm_32;
+ DataMemoryBarrier(domain, types);
+}
+
+# C6.2.115 DRPS page C6-1463 line 87125 MATCH xd6bf03e0/mask=xffffffff
+# CONSTRUCT xd6bf03e0/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd6bf03e0/mask=xffffffff --status nodest
+
+:drps
+is b_2531=0x6b & b_2324=1 & b_2122=1 & b_1620=0x1f & b_1015=0 & aa_Xn=31 & b_0004=0
+{
+ pc = DRPSInstruction();
+ return [pc];
+}
+
+# C6.2.116 DSB page C6-1464 line 87160 MATCH xd503309f/mask=xfffff0ff
+# C6.2.252 PSSBB page C6-1727 line 101951 MATCH xd503349f/mask=xffffffff
+# C6.2.290 SSBB page C6-1810 line 106930 MATCH xd503309f/mask=xffffffff
+# CONSTRUCT xd503309f/mask=xfffff3ff MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst xd503309f/mask=xfffff3ff --status nodest
+
+:dsb CRm_CRx
+is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CRm_CRx & CRm_32 & CRm_10=0 & Op2=4 & Rt=0x1f
+{
+ types:1 = 0x0;
+ domain:1 = CRm_32;
+ DataSynchronizationBarrier(domain, types);
+}
+
+# C6.2.116 DSB page C6-1464 line 87160 MATCH xd503309f/mask=xfffff0ff
+# CONSTRUCT xd503309f/mask=xfffff0ff MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd503309f/mask=xfffff0ff --status nodest
+
+:dsb CRm_dbarrier_op
+is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CRm_32 & CRm_10=2 & Op2=4 & Rt=0x1f
+{
+ types:1 = 0x3; #MBReqTypes_All
+ domain:1 = CRm_32;
+ DataSynchronizationBarrier(domain, types);
+}
+
+# C6.2.116 DSB page C6-1464 line 87160 MATCH xd503323f/mask=xfffff3ff
+# CONSTRUCT xd503323f/mask=xfffff3ff MATCHED 1 DOCUMENTED OPCODES
+# xd503323f/mask=xfffff3ff NOT MATCHED BY ANY CONSTRUCTOR
+# b_0031=11010101000000110011..1000111111
+
+:dsb CRm_32
+is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & CRm_dbarrier_op & CRm_32 & CRm_10 & Op2=1 & Rt=0x1f
+{
+ types:1 = CRm_10;
+ domain:1 = CRm_32;
+ DataSynchronizationBarrier(domain, types);
+}
+
+# C6.2.118 EON (shifted register) page C6-1468 line 87407 MATCH x4a200000/mask=x7f200000
+# CONSTRUCT x4a200000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x4a200000/mask=xff200000 --status pass
+
+:eon Rd_GPR32, Rn_GPR32, RegShift32Log
+is sf=0 & opc=2 & b_2428=0xa & N=1 & RegShift32Log & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp_3:4 = RegShift32Log;
+ tmp_2:4 = tmp_3 ^ -1:4;
+ tmp_1:4 = Rn_GPR32 ^ tmp_2;
+ Rd_GPR64 = zext(tmp_1);
+}
+
+# C6.2.118 EON (shifted register) page C6-1468 line 87407 MATCH x4a200000/mask=x7f200000
+# CONSTRUCT xca200000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xca200000/mask=xff200000 --status pass
+
+:eon Rd_GPR64, Rn_GPR64, RegShift64Log
+is sf=1 & opc=2 & b_2428=0xa & N=1 & Rm_GPR64 & RegShift64Log & Rn_GPR64 & Rd_GPR64
+{
+ tmp_3:8= RegShift64Log;
+ tmp_2:8 = tmp_3 ^ -1:8;
+ tmp_1:8 = Rn_GPR64 ^ tmp_2;
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.119 EOR (immediate) page C6-1470 line 87512 MATCH x52000000/mask=x7f800000
+# CONSTRUCT x52000000/mask=xff800000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x52000000/mask=xff800000 --status pass
+
+:eor Rd_GPR32wsp, Rn_GPR32, DecodeWMask32
+is sf=0 & opc=2 & b_2428=0x12 & b_2323=0 & DecodeWMask32 & Rn_GPR32 & Rd_GPR32wsp & Rd_GPR64xsp
+{
+ tmp_1:4 = Rn_GPR32 ^ DecodeWMask32;
+ Rd_GPR64xsp = zext(tmp_1);
+}
+
+# C6.2.119 EOR (immediate) page C6-1470 line 87512 MATCH x52000000/mask=x7f800000
+# CONSTRUCT xd2000000/mask=xff800000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd2000000/mask=xff800000 --status pass
+
+:eor Rd_GPR64xsp, Rn_GPR64, DecodeWMask64
+is sf=1 & opc=2 & b_2428=0x12 & b_2323=0 & DecodeWMask64 & Rn_GPR64 & Rd_GPR64xsp
+{
+ tmp_1:8 = Rn_GPR64 ^ DecodeWMask64;
+ Rd_GPR64xsp = tmp_1;
+}
+
+# C6.2.120 EOR (shifted register) page C6-1472 line 87604 MATCH x4a000000/mask=x7f200000
+# CONSTRUCT x4a000000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x4a000000/mask=xff200000 --status pass
+
+:eor Rd_GPR32, Rn_GPR32, RegShift32Log
+is sf=0 & opc=2 & b_2428=0xa & N=0 & RegShift32Log & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp_2:4 = RegShift32Log;
+ tmp_1:4 = Rn_GPR32 ^ tmp_2;
+ Rd_GPR64 = zext(tmp_1);
+}
+
+# C6.2.120 EOR (shifted register) page C6-1472 line 87604 MATCH x4a000000/mask=x7f200000
+# CONSTRUCT xca000000/mask=xff200000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xca000000/mask=xff200000 --status pass
+
+:eor Rd_GPR64, Rn_GPR64, RegShift64Log
+is sf=1 & opc=2 & b_2428=0xa & N=0 & Rm_GPR64 & RegShift64Log & Rn_GPR64 & Rd_GPR64
+{
+ tmp_2:8 = RegShift64Log;
+ tmp_1:8 = Rn_GPR64 ^ tmp_2;
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.121 ERET page C6-1474 line 87707 MATCH xd69f03e0/mask=xffffffff
+# CONSTRUCT xd69f03e0/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd69f03e0/mask=xffffffff --status nodest
+
+:eret
+is b_2531=0x6b & b_2324=1 & b_2122=0 & b_1620=0x1f & b_1015=0 & aa_Xn=31 & b_0004=0
+{
+ pc = ExceptionReturn();
+ return [pc];
+}
+
+# C6.2.122 ERETAA, ERETAB page C6-1475 line 87749 MATCH xd69f0bff/mask=xfffffbff
+# CONSTRUCT xd69f0bff/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd69f0bff/mask=xffffffff --status nodest
+
+:eretaa
+is eretaa__PACpart & b_0031=0xd69f0bff
+{
+ pc = ExceptionReturn();
+ build eretaa__PACpart;
+ return [pc];
+}
+
+# C6.2.122 ERETAA, ERETAB page C6-1475 line 87749 MATCH xd69f0bff/mask=xfffffbff
+# CONSTRUCT xd69f0fff/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd69f0fff/mask=xffffffff --status nodest
+
+:eretab
+is eretab__PACpart & b_0031=0xd69f0fff
+{
+ pc = ExceptionReturn();
+ build eretab__PACpart;
+ return [pc];
+}
+
+# C6.2.124 EXTR page C6-1477 line 87864 MATCH x13800000/mask=x7fa00000
+# C6.2.261 ROR (immediate) page C6-1740 line 102633 MATCH x13800000/mask=x7fa00000
+# CONSTRUCT x13800000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x13800000/mask=xffe00000 --status pass
+
+:extr Rd_GPR32, Rn_GPR32, Rm_GPR32, LSB_bitfield32_imm
+is sf=0 & b_2930=0 & b_2428=0x13 & b_2323=1 & n=0 & b_21=0 & Rm_GPR32 & LSB_bitfield32_imm & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ lsb:8 = LSB_bitfield32_imm;
+ result:8 = (zext(Rn_GPR32) << 32) | zext(Rm_GPR32);
+ result = (result >> lsb);
+ Rd_GPR64 = zext(result:4);
+}
+
+# C6.2.124 EXTR page C6-1477 line 87864 MATCH x13800000/mask=x7fa00000
+# C6.2.261 ROR (immediate) page C6-1740 line 102633 MATCH x13800000/mask=x7fa00000
+# CONSTRUCT x93c00000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x93c00000/mask=xffe00000 --status pass
+
+:extr Rd_GPR64, Rn_GPR64, Rm_GPR64, LSB_bitfield64_imm
+is sf=1 & b_2930=0 & b_2428=0x13 & b_2323=1 & n=1 & b_21=0 & Rm_GPR64 & LSB_bitfield64_imm & Rn_GPR64 & Rd_GPR64
+{
+ local tmp:8 = (Rm_GPR64 >> LSB_bitfield64_imm:1);
+ Rd_GPR64 = tmp | (Rn_GPR64 << (64:1 - LSB_bitfield64_imm:1));
+}
+
+# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f
+# C6.2.22 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA page C6-1183 line 69908 MATCH xd503219f/mask=xfffffddf
+# C6.2.23 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB page C6-1186 line 70065 MATCH xd50321df/mask=xfffffddf
+# C6.2.102 CSDB page C6-1442 line 86066 MATCH xd503229f/mask=xffffffff
+# C6.2.113 DGH page C6-1460 line 86992 MATCH xd50320df/mask=xffffffff
+# C6.2.123 ESB page C6-1476 line 87816 MATCH xd503221f/mask=xffffffff
+# C6.2.245 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA page C6-1712 line 101196 MATCH xd503211f/mask=xfffffddf
+# C6.2.246 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB page C6-1715 line 101358 MATCH xd503215f/mask=xfffffddf
+# C6.2.251 PSB CSYNC page C6-1726 line 101911 MATCH xd503223f/mask=xffffffff
+# C6.2.381 TSB CSYNC page C6-1982 line 116218 MATCH xd503225f/mask=xffffffff
+# CONSTRUCT xd503201f/mask=xfffff01f MATCHED 10 DOCUMENTED OPCODES
+# AUNIT --inst xd503201f/mask=xfffff01f --status nodest
+
+:hint imm7Low
+is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low & Rt=0x1f {}
+
+# C6.2.127 HLT page C6-1482 line 88176 MATCH xd4400000/mask=xffe0001f
+# CONSTRUCT xd4400000/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd4400000/mask=xffe0001f --status nodest
+
+:hlt imm16
+is ALL_BTITARGETS & b_2431=0xd4 & excCode=2 & imm16 & excCode2=0 & ll=0
+{
+ HaltBreakPoint();
+}
+
+# C6.2.128 HVC page C6-1483 line 88218 MATCH xd4000002/mask=xffe0001f
+# CONSTRUCT xd4000002/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd4000002/mask=xffe0001f --status nodest
+
+:hvc imm16
+is b_2431=0xd4 & excCode=0 & imm16 & excCode2=0 & ll=2
+{
+ CallHyperVisor(imm16:2);
+}
+
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5087100/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst xd5087100/mask=xffffffe0 --status nodest
+
+:ic "IALLUIS"
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b0001 & b_0507=0b000
+{ IC_IALLUIS(); }
+
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5087500/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst xd5087500/mask=xffffffe0 --status nodest
+
+:ic "IALLU"
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b0101 & b_0507=0b000
+{ IC_IALLU(); }
+
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50b7520/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst xd50b7520/mask=xffffffe0 --status nopcodeop
+
+:ic "IVAU", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b0101 & b_0507=0b001 & Rt_GPR64
+{ IC_IVAU(Rt_GPR64); }
+
+# C6.2.85 ISB page C6-647 line 37682 KEEPWITH
+
+IsbOption: "#"^CRm_isb_op is CRm_isb_op { export *[const]:4 CRm_isb_op; }
+IsbOption: "" is CRm_isb_op=0xf { tmp:4 = 0xf; export tmp; }
+
+# C6.2.131 ISB page C6-1487 line 88428 MATCH xd50330df/mask=xfffff0ff
+# CONSTRUCT xd50330df/mask=xfffff0ff MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd50330df/mask=xfffff0ff --status nodest
+
+:isb IsbOption
+is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x3 & IsbOption & Op2=6 & Rt=0x1f
+{
+ InstructionSynchronizationBarrier();
+}
+
+# C6.2.86 LDADDB, LDADDAB, LDADDALB, LDADDLB page C6-648 line 37726 KEEPWITH
+
+# variants, a=acquire, al=acquire+release, l=release
+# build ls_loa to acquire and ls_lor to release
+
+ls_loa: "a" is b_23=1 & b_22=0 { LOAcquire(); }
+ls_loa: "al" is b_23=1 & b_22=1 { LOAcquire(); }
+ls_loa: "" is b_23=0 & b_22=0 { }
+ls_loa: "l" is b_23=0 & b_22=1 { }
+
+ls_lor: "a" is b_23=1 & b_22=0 { }
+ls_lor: "al" is b_23=1 & b_22=1 { LORelease(); }
+ls_lor: "" is b_23=0 & b_22=0 { }
+ls_lor: "l" is b_23=0 & b_22=1 { LORelease(); }
+
+ls_data1: is b_3031=0b00 & Rn_GPR64xsp { tmp_ldWn = zext(*:1 Rn_GPR64xsp); }
+ls_data2: is b_3031=0b01 & Rn_GPR64xsp { tmp_ldWn = zext(*:2 Rn_GPR64xsp); }
+ls_data4: is b_3031=0b10 & Rn_GPR64xsp { tmp_ldWn = *:4 Rn_GPR64xsp; }
+ls_data8: is b_3031=0b11 & Rn_GPR64xsp { tmp_ldXn = *:8 Rn_GPR64xsp; }
+
+ls_mem1: is Rn_GPR64xsp { *:1 Rn_GPR64xsp = tmp_stWn:1; }
+ls_mem2: is Rn_GPR64xsp { *:2 Rn_GPR64xsp = tmp_stWn:2; }
+ls_mem4: is Rn_GPR64xsp { *:4 Rn_GPR64xsp = tmp_stWn; }
+ls_mem8: is Rn_GPR64xsp { *:8 Rn_GPR64xsp = tmp_stXn; }
+
+macro ls_opc_add (data, value, dest) { dest = data + value; }
+macro ls_opc_clr (data, value, dest) { dest = data & (~ value); }
+macro ls_opc_eor (data, value, dest) { dest = data ^ value; }
+macro ls_opc_set (data, value, dest) { dest = data | value; }
+macro ls_opc_smax(data, value, dest) { dest = zext(data s> value) * data + zext(data s<= value) * value; }
+macro ls_opc_smin(data, value, dest) { dest = zext(data s> value) * value + zext(data s<= value) * data; }
+macro ls_opc_umax(data, value, dest) { dest = zext(data > value) * data + zext(data <= value) * value; }
+macro ls_opc_umin(data, value, dest) { dest = zext(data > value) * value + zext(data <= value) * data; }
+macro ls_opc_swp (data, value, dest) { dest = value; }
+
+ls_opc1: "add" is b_3031=0b00 & b_1215=0b0000 & aa_Ws & ls_data1 & ls_mem1 { build ls_data1; ls_opc_add(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; }
+ls_opc2: "add" is b_3031=0b01 & b_1215=0b0000 & aa_Ws & ls_data2 & ls_mem2 { build ls_data2; ls_opc_add(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; }
+ls_opc4: "add" is b_3031=0b10 & b_1215=0b0000 & aa_Ws & ls_data4 & ls_mem4 { build ls_data4; ls_opc_add(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; }
+ls_opc8: "add" is b_3031=0b11 & b_1215=0b0000 & aa_Xs & ls_data8 & ls_mem8 { build ls_data8; ls_opc_add(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; }
+
+ls_opc1: "clr" is b_3031=0b00 & b_1215=0b0001 & aa_Ws & ls_data1 & ls_mem1 { build ls_data1; ls_opc_clr(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; }
+ls_opc2: "clr" is b_3031=0b01 & b_1215=0b0001 & aa_Ws & ls_data2 & ls_mem2 { build ls_data2; ls_opc_clr(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; }
+ls_opc4: "clr" is b_3031=0b10 & b_1215=0b0001 & aa_Ws & ls_data4 & ls_mem4 { build ls_data4; ls_opc_clr(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; }
+ls_opc8: "clr" is b_3031=0b11 & b_1215=0b0001 & aa_Xs & ls_data8 & ls_mem8 { build ls_data8; ls_opc_clr(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; }
+
+ls_opc1: "eor" is b_3031=0b00 & b_1215=0b0010 & aa_Ws & ls_data1 & ls_mem1 { build ls_data1; ls_opc_eor(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; }
+ls_opc2: "eor" is b_3031=0b01 & b_1215=0b0010 & aa_Ws & ls_data2 & ls_mem2 { build ls_data2; ls_opc_eor(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; }
+ls_opc4: "eor" is b_3031=0b10 & b_1215=0b0010 & aa_Ws & ls_data4 & ls_mem4 { build ls_data4; ls_opc_eor(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; }
+ls_opc8: "eor" is b_3031=0b11 & b_1215=0b0010 & aa_Xs & ls_data8 & ls_mem8 { build ls_data8; ls_opc_eor(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; }
+
+ls_opc1: "set" is b_3031=0b00 & b_1215=0b0011 & aa_Ws & ls_data1 & ls_mem1 { build ls_data1; ls_opc_set(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; }
+ls_opc2: "set" is b_3031=0b01 & b_1215=0b0011 & aa_Ws & ls_data2 & ls_mem2 { build ls_data2; ls_opc_set(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; }
+ls_opc4: "set" is b_3031=0b10 & b_1215=0b0011 & aa_Ws & ls_data4 & ls_mem4 { build ls_data4; ls_opc_set(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; }
+ls_opc8: "set" is b_3031=0b11 & b_1215=0b0011 & aa_Xs & ls_data8 & ls_mem8 { build ls_data8; ls_opc_set(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; }
+
+ls_opc1: "smax" is b_3031=0b00 & b_1215=0b0100 & aa_Ws & ls_data1 & ls_mem1 { build ls_data1; ls_opc_smax(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; }
+ls_opc2: "smax" is b_3031=0b01 & b_1215=0b0100 & aa_Ws & ls_data2 & ls_mem2 { build ls_data2; ls_opc_smax(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; }
+ls_opc4: "smax" is b_3031=0b10 & b_1215=0b0100 & aa_Ws & ls_data4 & ls_mem4 { build ls_data4; ls_opc_smax(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; }
+ls_opc8: "smax" is b_3031=0b11 & b_1215=0b0100 & aa_Xs & ls_data8 & ls_mem8 { build ls_data8; ls_opc_smax(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; }
+
+ls_opc1: "smin" is b_3031=0b00 & b_1215=0b0101 & aa_Ws & ls_data1 & ls_mem1 { build ls_data1; ls_opc_smin(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; }
+ls_opc2: "smin" is b_3031=0b01 & b_1215=0b0101 & aa_Ws & ls_data2 & ls_mem2 { build ls_data2; ls_opc_smin(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; }
+ls_opc4: "smin" is b_3031=0b10 & b_1215=0b0101 & aa_Ws & ls_data4 & ls_mem4 { build ls_data4; ls_opc_smin(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; }
+ls_opc8: "smin" is b_3031=0b11 & b_1215=0b0101 & aa_Xs & ls_data8 & ls_mem8 { build ls_data8; ls_opc_smin(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; }
+
+ls_opc1: "umax" is b_3031=0b00 & b_1215=0b0110 & aa_Ws & ls_data1 & ls_mem1 { build ls_data1; ls_opc_umax(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; }
+ls_opc2: "umax" is b_3031=0b01 & b_1215=0b0110 & aa_Ws & ls_data2 & ls_mem2 { build ls_data2; ls_opc_umax(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; }
+ls_opc4: "umax" is b_3031=0b10 & b_1215=0b0110 & aa_Ws & ls_data4 & ls_mem4 { build ls_data4; ls_opc_umax(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; }
+ls_opc8: "umax" is b_3031=0b11 & b_1215=0b0110 & aa_Xs & ls_data8 & ls_mem8 { build ls_data8; ls_opc_umax(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; }
+
+ls_opc1: "umin" is b_3031=0b00 & b_1215=0b0111 & aa_Ws & ls_data1 & ls_mem1 { build ls_data1; ls_opc_umin(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; }
+ls_opc2: "umin" is b_3031=0b01 & b_1215=0b0111 & aa_Ws & ls_data2 & ls_mem2 { build ls_data2; ls_opc_umin(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; }
+ls_opc4: "umin" is b_3031=0b10 & b_1215=0b0111 & aa_Ws & ls_data4 & ls_mem4 { build ls_data4; ls_opc_umin(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; }
+ls_opc8: "umin" is b_3031=0b11 & b_1215=0b0111 & aa_Xs & ls_data8 & ls_mem8 { build ls_data8; ls_opc_umin(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; }
+
+# Nearly all of these instructions have the same "operation" in the
+# manual, the differences being load vs store, the operation (o3:opc),
+# the data size, and the load store semantics of the atomic load and
+# store types (AccType). The opcode mnemonic varies, however. And to
+# facilitate reading, the LD/ST/SWP variants have been separated out.
+
+# C6.2.133 LDADDB, LDADDAB, LDADDALB, LDADDLB page C6-1489 line 88545 MATCH x38200000/mask=xff20fc00
+# C6.2.152 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB page C6-1524 line 90495 MATCH x38201000/mask=xff20fc00
+# C6.2.155 LDEORB, LDEORAB, LDEORALB, LDEORLB page C6-1531 line 90916 MATCH x38202000/mask=xff20fc00
+# C6.2.181 LDSETB, LDSETAB, LDSETALB, LDSETLB page C6-1590 line 94403 MATCH x38203000/mask=xff20fc00
+# C6.2.184 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB page C6-1597 line 94824 MATCH x38204000/mask=xff20fc00
+# C6.2.187 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB page C6-1604 line 95245 MATCH x38205000/mask=xff20fc00
+# C6.2.196 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB page C6-1623 line 96362 MATCH x38206000/mask=xff20fc00
+# C6.2.199 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB page C6-1630 line 96783 MATCH x38207000/mask=xff20fc00
+# CONSTRUCT x38200000/mask=xff208c00 MATCHED 8 DOCUMENTED OPCODES
+# AUNIT --inst x38200000/mask=xff208c00 --status nomem
+
+# size=0b00 (3031)
+
+:ld^ls_opc1^ls_lor^"b" aa_Ws, aa_Wt, [Rn_GPR64xsp]
+is b_3031=0b00 & b_2429=0b111000 & b_21=1 & b_1515=0 & b_1011=0b00 & ls_opc1 & ls_loa & ls_lor & aa_Wt & aa_Ws & Rn_GPR64xsp
+{ build ls_loa; build ls_opc1; aa_Wt = tmp_ldWn; build ls_lor; }
+
+# C6.2.134 LDADDH, LDADDAH, LDADDALH, LDADDLH page C6-1491 line 88670 MATCH x78200000/mask=xff20fc00
+# C6.2.153 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH page C6-1526 line 90621 MATCH x78201000/mask=xff20fc00
+# C6.2.156 LDEORH, LDEORAH, LDEORALH, LDEORLH page C6-1533 line 91042 MATCH x78202000/mask=xff20fc00
+# C6.2.182 LDSETH, LDSETAH, LDSETALH, LDSETLH page C6-1592 line 94529 MATCH x78203000/mask=xff20fc00
+# C6.2.185 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH page C6-1599 line 94950 MATCH x78204000/mask=xff20fc00
+# C6.2.188 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH page C6-1606 line 95371 MATCH x78205000/mask=xff20fc00
+# C6.2.197 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH page C6-1625 line 96488 MATCH x78206000/mask=xff20fc00
+# C6.2.200 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH page C6-1632 line 96909 MATCH x78207000/mask=xff20fc00
+# CONSTRUCT x78200000/mask=xff208c00 MATCHED 8 DOCUMENTED OPCODES
+# AUNIT --inst x78200000/mask=xff208c00 --status nomem
+
+# size=0b01 (3031)
+
+:ld^ls_opc2^ls_lor^"h" aa_Ws, aa_Wt, [Rn_GPR64xsp]
+is b_3031=0b01 & b_2429=0b111000 & b_21=1 & b_1515=0 & b_1011=0b00 & ls_opc2 & ls_loa & ls_lor & aa_Wt & aa_Ws & Rn_GPR64xsp
+{ build ls_loa; build ls_opc2; aa_Wt = tmp_ldWn; build ls_lor; }
+
+# C6.2.135 LDADD, LDADDA, LDADDAL, LDADDL page C6-1493 line 88796 MATCH xb8200000/mask=xbf20fc00
+# C6.2.154 LDCLR, LDCLRA, LDCLRAL, LDCLRL page C6-1528 line 90747 MATCH xb8201000/mask=xbf20fc00
+# C6.2.157 LDEOR, LDEORA, LDEORAL, LDEORL page C6-1535 line 91168 MATCH xb8202000/mask=xbf20fc00
+# C6.2.183 LDSET, LDSETA, LDSETAL, LDSETL page C6-1594 line 94655 MATCH xb8203000/mask=xbf20fc00
+# C6.2.186 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL page C6-1601 line 95076 MATCH xb8204000/mask=xbf20fc00
+# C6.2.189 LDSMIN, LDSMINA, LDSMINAL, LDSMINL page C6-1608 line 95497 MATCH xb8205000/mask=xbf20fc00
+# C6.2.198 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL page C6-1627 line 96614 MATCH xb8206000/mask=xbf20fc00
+# C6.2.201 LDUMIN, LDUMINA, LDUMINAL, LDUMINL page C6-1634 line 97035 MATCH xb8207000/mask=xbf20fc00
+# C6.2.297 STADD, STADDL page C6-1822 line 107555 MATCH xb820001f/mask=xbfa0fc1f
+# C6.2.300 STCLR, STCLRL page C6-1828 line 107842 MATCH xb820101f/mask=xbfa0fc1f
+# C6.2.303 STEOR, STEORL page C6-1834 line 108128 MATCH xb820201f/mask=xbfa0fc1f
+# C6.2.330 STSET, STSETL page C6-1890 line 111216 MATCH xb820301f/mask=xbfa0fc1f
+# C6.2.333 STSMAX, STSMAXL page C6-1896 line 111508 MATCH xb820401f/mask=xbfa0fc1f
+# C6.2.336 STSMIN, STSMINL page C6-1902 line 111801 MATCH xb820501f/mask=xbfa0fc1f
+# C6.2.342 STUMAX, STUMAXL page C6-1914 line 112409 MATCH xb820601f/mask=xbfa0fc1f
+# C6.2.345 STUMIN, STUMINL page C6-1920 line 112703 MATCH xb820701f/mask=xbfa0fc1f
+# CONSTRUCT xb8200000/mask=xff208c00 MATCHED 16 DOCUMENTED OPCODES
+# AUNIT --inst xb8200000/mask=xff208c00 --status nomem
+
+# size=0b10 (3031)
+
+:ld^ls_opc4^ls_lor aa_Ws, aa_Wt, [Rn_GPR64xsp]
+is b_3031=0b10 & b_2429=0b111000 & b_21=1 & b_1515=0 & b_1011=0b00 & ls_opc4 & ls_loa & ls_lor & aa_Wt & aa_Ws & Rn_GPR64xsp
+{ build ls_loa; build ls_opc4; aa_Wt = tmp_ldWn; build ls_lor; }
+
+# C6.2.135 LDADD, LDADDA, LDADDAL, LDADDL page C6-1493 line 88796 MATCH xb8200000/mask=xbf20fc00
+# C6.2.154 LDCLR, LDCLRA, LDCLRAL, LDCLRL page C6-1528 line 90747 MATCH xb8201000/mask=xbf20fc00
+# C6.2.157 LDEOR, LDEORA, LDEORAL, LDEORL page C6-1535 line 91168 MATCH xb8202000/mask=xbf20fc00
+# C6.2.183 LDSET, LDSETA, LDSETAL, LDSETL page C6-1594 line 94655 MATCH xb8203000/mask=xbf20fc00
+# C6.2.186 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL page C6-1601 line 95076 MATCH xb8204000/mask=xbf20fc00
+# C6.2.189 LDSMIN, LDSMINA, LDSMINAL, LDSMINL page C6-1608 line 95497 MATCH xb8205000/mask=xbf20fc00
+# C6.2.198 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL page C6-1627 line 96614 MATCH xb8206000/mask=xbf20fc00
+# C6.2.201 LDUMIN, LDUMINA, LDUMINAL, LDUMINL page C6-1634 line 97035 MATCH xb8207000/mask=xbf20fc00
+# C6.2.297 STADD, STADDL page C6-1822 line 107555 MATCH xb820001f/mask=xbfa0fc1f
+# C6.2.300 STCLR, STCLRL page C6-1828 line 107842 MATCH xb820101f/mask=xbfa0fc1f
+# C6.2.303 STEOR, STEORL page C6-1834 line 108128 MATCH xb820201f/mask=xbfa0fc1f
+# C6.2.330 STSET, STSETL page C6-1890 line 111216 MATCH xb820301f/mask=xbfa0fc1f
+# C6.2.333 STSMAX, STSMAXL page C6-1896 line 111508 MATCH xb820401f/mask=xbfa0fc1f
+# C6.2.336 STSMIN, STSMINL page C6-1902 line 111801 MATCH xb820501f/mask=xbfa0fc1f
+# C6.2.342 STUMAX, STUMAXL page C6-1914 line 112409 MATCH xb820601f/mask=xbfa0fc1f
+# C6.2.345 STUMIN, STUMINL page C6-1920 line 112703 MATCH xb820701f/mask=xbfa0fc1f
+# CONSTRUCT xf8200000/mask=xff208c00 MATCHED 16 DOCUMENTED OPCODES
+# AUNIT --inst xf8200000/mask=xff208c00 --status nomem
+
+# size=0b11 (3031)
+
+:ld^ls_opc8^ls_lor aa_Xs, aa_Xt, [Rn_GPR64xsp]
+is b_3031=0b11 & b_2429=0b111000 & b_21=1 & b_1515=0 & b_1011=0b00 & ls_opc8 & ls_loa & ls_lor & aa_Xt & aa_Xs & Rn_GPR64xsp
+{ build ls_loa; build ls_opc8; aa_Xt = tmp_ldXn; build ls_lor; }
+
+# C6.2.136 LDAPR page C6-1496 line 88965 MATCH xb8a0c000/mask=xbfe0fc00
+# CONSTRUCT xb8a0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xb8a0c000/mask=xffe0fc00 --status nomem
+# TODO unsure of load/release semantics for this instruction
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111
+# size == 10 32-bit variant
+
+:ldapr aa_Wt, [Rn_GPR64xsp]
+is b_3031=0b10 & b_2129=0b111000101 & b_1015=0b110000 & Rn_GPR64xsp & aa_Wt & ls_data4
+{
+ aa_Wt = tmp_ldWn;
+}
+
+# C6.2.136 LDAPR page C6-1496 line 88965 MATCH xb8a0c000/mask=xbfe0fc00
+# CONSTRUCT xf8a0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xf8a0c000/mask=xffe0fc00 --status nomem
+# TODO unsure of load/release semantics for this instruction
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111
+# size == 11 64-bit variant
+
+:ldapr aa_Xt, [Rn_GPR64xsp]
+is b_3031=0b11 & b_2129=0b111000101 & b_1015=0b110000 & Rn_GPR64xsp & aa_Xt
+{
+ aa_Xt = tmp_ldXn;
+}
+
+# C6.2.137 LDAPRB page C6-1498 line 89064 MATCH x38a0c000/mask=xffe0fc00
+# CONSTRUCT x38a0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x38a0c000/mask=xffe0fc00 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111
+# TODO unsure of load/release semantics for this instruction
+
+:ldaprb aa_Wt, [Rn_GPR64xsp]
+is b_3031=0b00 & b_2129=0b111000101 & b_1015=0b110000 & Rn_GPR64xsp & aa_Wt & ls_data1
+{
+ aa_Wt = tmp_ldWn;
+}
+
+# C6.2.138 LDAPRH page C6-1500 line 89148 MATCH x78a0c000/mask=xffe0fc00
+# CONSTRUCT x78a0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x78a0c000/mask=xffe0fc00 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111
+
+:ldaprh aa_Wt, [Rn_GPR64xsp]
+is b_3031=0b01 & b_2129=0b111000101 & b_1015=0b110000 & Rn_GPR64xsp & aa_Wt & ls_data2
+{
+ aa_Wt = tmp_ldWn;
+}
+
+
+# C6.2.139 LDAPUR page C6-1502 line 89232 MATCH x99400000/mask=xbfe00c00
+# CONSTRUCT x99400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# The following commands are not yet implemented.
+
+
+# x99400000/mask=xbfe00c00 NOT MATCHED BY ANY CONSTRUCTOR
+
+:ldapur aa_Wt, addr_SIMM9
+is b_3031=0b10 & b_2129=0b011001010 & b_1011=0b00 & addr_SIMM9 & aa_Wt & aa_Xt
+{
+ aa_Xt = zext(*:4 addr_SIMM9);
+}
+
+# C6.2.139 LDAPUR page C6-1502 line 89232 MATCH x99400000/mask=xbfe00c00
+# CONSTRUCT xd9400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+
+:ldapur aa_Xt, addr_SIMM9
+is b_3031=0b11 & b_2129=0b011001010 & b_1011=0b00 & addr_SIMM9 & aa_Xt
+{
+ aa_Xt = *addr_SIMM9;
+}
+
+# C6.2.140 LDAPURB page C6-1504 line 89343 MATCH x19400000/mask=xffe00c00
+# CONSTRUCT x19400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# x19400000/mask=xffe00c00 NOT MATCHED BY ANY CONSTRUCTOR
+
+:ldapurb aa_Wt, addr_SIMM9
+is b_3031=0b00 & b_2129=0b011001010 & b_1011=0b00 & addr_SIMM9 & aa_Wt & aa_Xt
+{
+ aa_Xt = zext(*:1 addr_SIMM9);
+}
+
+# C6.2.141 LDAPURH page C6-1506 line 89439 MATCH x59400000/mask=xffe00c00
+# CONSTRUCT x59400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# x59400000/mask=xffe00c00 NOT MATCHED BY ANY CONSTRUCTOR
+
+:ldapurh aa_Wt, addr_SIMM9
+is b_3031=0b01 & b_2129=0b011001010 & b_1011=0b00 & addr_SIMM9 & aa_Wt & aa_Xt
+{
+ aa_Xt = zext(*:2 addr_SIMM9);
+}
+
+
+# C6.2.142 LDAPURSB page C6-1508 line 89535 MATCH x19800000/mask=xffa00c00
+# CONSTRUCT x19c00000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# x19800000/mask=xffa00c00 NOT MATCHED BY ANY CONSTRUCTOR
+
+:ldapursb aa_Wt, addr_SIMM9
+is b_3031=0b00 & b_2329=0b0110011 & b_22=1 & b_2121=0b0 & b_1011=0b00 & addr_SIMM9 & aa_Wt & aa_Xt
+{
+ aa_Xt = 0;
+ aa_Wt = sext(*:1 addr_SIMM9);
+}
+
+# C6.2.142 LDAPURSB page C6-1508 line 89535 MATCH x19800000/mask=xffa00c00
+# CONSTRUCT x19800000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+
+:ldapursb aa_Xt, addr_SIMM9
+is b_3031=0b00 & b_2329=0b0110011 & b_22=0 & b_2121=0b0 & b_1011=0b00 & addr_SIMM9 & aa_Xt
+{
+ aa_Xt = sext(*:1 addr_SIMM9);
+}
+
+# C6.2.143 LDAPURSH page C6-1510 line 89667 MATCH x59800000/mask=xffa00c00
+# CONSTRUCT x59c00000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# x59800000/mask=xffa00c00 NOT MATCHED BY ANY CONSTRUCTOR
+
+:ldapursh aa_Wt, addr_SIMM9
+is b_3031=0b01 & b_2329=0b0110011 & b_22=1 & b_2121=0b0 & b_1011=0b00 & addr_SIMM9 & aa_Wt & aa_Xt
+{
+ aa_Xt = 0;
+ aa_Wt = sext(*:2 addr_SIMM9);
+}
+
+# C6.2.143 LDAPURSH page C6-1510 line 89667 MATCH x59800000/mask=xffa00c00
+# CONSTRUCT x59800000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+
+:ldapursh aa_Xt, addr_SIMM9
+is b_3031=0b01 & b_2329=0b0110011 & b_22=0 & b_2121=0b0 & b_1011=0b00 & addr_SIMM9 & aa_Xt
+{
+ aa_Xt = sext(*:2 addr_SIMM9);
+}
+
+# C6.2.144 LDAPURSW page C6-1512 line 89799 MATCH x99800000/mask=xffe00c00
+# CONSTRUCT x99800000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# x99800000/mask=xffe00c00 NOT MATCHED BY ANY CONSTRUCTOR
+
+:ldapursw aa_Xt, addr_SIMM9
+is b_3031=0b10 & b_2129=0b011001100 & b_1011=0b00 & addr_SIMM9 & aa_Xt
+{
+ aa_Xt = sext(*:4 addr_SIMM9);
+}
+
+# C6.2.145 LDAR page C6-1514 line 89895 MATCH x88c08000/mask=xbfe08000
+# CONSTRUCT xc8c08000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xc8c08000/mask=xffe08000 --status nomem
+# The manual states that Rs and Rt2 should be all ones, which is
+# optionally enforced.
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111
+
+:ldar Rt_GPR64, addrReg
+is size.ldstr=3 & b_2429=0x8 & b_23=1 & L=1 & b_21=0 & b_15=1 & addrReg & Rt_GPR64
+{
+ Rt_GPR64 = *addrReg;
+}
+
+# C6.2.145 LDAR page C6-1514 line 89895 MATCH x88c08000/mask=xbfe08000
+# CONSTRUCT x88dffc00/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x88dffc00/mask=xfffffc00 --status nomem
+# Enforce SHOULD BE ONE fields b_1620 & b_1014
+
+:ldar Rt_GPR32, addrReg
+is size.ldstr=2 & b_2429=0x8 & b_23=1 & L=1 & b_21=0 & b_1620=0b11111 & b_15=1 & b_1014=0b11111 & addrReg & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = *addrReg;
+}
+
+# C6.2.146 LDARB page C6-1516 line 89986 MATCH x08c08000/mask=xffe08000
+# CONSTRUCT x08c08000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x08c08000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111
+
+:ldarb Rt_GPR32, addrReg
+is size.ldstr=0 & b_2429=0x8 & b_23=1 & L=1 & b_21=0 & b_15=1 & addrReg & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = zext(*:1 addrReg);
+}
+
+# C6.2.147 LDARH page C6-1517 line 90054 MATCH x48c08000/mask=xffe08000
+# CONSTRUCT x48dffc00/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x48dffc00/mask=xfffffc00 --status nomem
+# Enforce SHOULD BE ONE fields b_1620 & b_1014
+
+:ldarh Rt_GPR32, addrReg
+is size.ldstr=1 & b_2429=0x8 & b_23=1 & L=1 & b_21=0 & b_1620=0b11111 & b_15=1 & b_1014=0b11111 & addrReg & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = zext(*:2 addrReg);
+}
+
+# C6.2.148 LDAXP page C6-1518 line 90122 MATCH x88608000/mask=xbfe08000
+# CONSTRUCT xc8608000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xc8608000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111
+
+:ldaxp Rt_GPR64, Rt2_GPR64, addrReg
+is size.ldstr=3 & b_2429=0x8 & b_23=0 & L=1 & b_21=1 & b_15=1 & Rt2_GPR64 & addrReg & Rt_GPR64
+{
+ Rt_GPR64 = *(addrReg);
+ Rt2_GPR64 = *(addrReg+8);
+}
+
+# C6.2.148 LDAXP page C6-1518 line 90122 MATCH x88608000/mask=xbfe08000
+# CONSTRUCT x88608000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x88608000/mask=xffe08000 --status nomem
+
+:ldaxp Rt_GPR32, Rt2_GPR32, addrReg
+is size.ldstr=2 & b_2429=0x8 & b_23=0 & L=1 & b_21=1 & b_1620 & b_15=1 & Rt2_GPR32 & addrReg & Rt_GPR32 & Rt_GPR64 & Rt2_GPR64
+{
+ Rt_GPR64 = zext(*:4(addrReg));
+ Rt2_GPR64 = zext(*:4(addrReg+4));
+}
+
+# C6.2.149 LDAXR page C6-1520 line 90256 MATCH x88408000/mask=xbfe08000
+# CONSTRUCT xc8408000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xc8408000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111
+
+:ldaxr Rt_GPR64, addrReg
+is size.ldstr=3 & b_2429=0x8 & b_23=0 & L=1 & b_21=0 & b_15=1 & addrReg & Rt_GPR64
+{
+ Rt_GPR64 = *addrReg;
+}
+
+# C6.2.149 LDAXR page C6-1520 line 90256 MATCH x88408000/mask=xbfe08000
+# CONSTRUCT x88408000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x88408000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111
+
+:ldaxr Rt_GPR32, addrReg
+is size.ldstr=2 & b_2429=0x8 & b_23=0 & L=1 & b_21=0 & b_15=1 & addrReg & Rt_GPR32 & Rt_GPR64
+{
+ tmp:4 = *addrReg;
+ Rt_GPR64 = zext(tmp);
+}
+
+# C6.2.150 LDAXRB page C6-1522 line 90351 MATCH x08408000/mask=xffe08000
+# CONSTRUCT x08408000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x08408000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111
+
+:ldaxrb Rt_GPR32, addrReg
+is size.ldstr=0 & b_2429=0x8 & b_23=0 & L=1 & b_21=0 & b_15=1 & addrReg & Rt_GPR32 & Rt_GPR64
+{
+ tmp:1 = *addrReg;
+ Rt_GPR64 = zext(tmp);
+}
+
+# C6.2.151 LDAXRH page C6-1523 line 90423 MATCH x48408000/mask=xffe08000
+# CONSTRUCT x48408000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x48408000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111
+
+:ldaxrh Rt_GPR32, addrReg
+is size.ldstr=1 & b_2429=0x8 & b_23=0 & L=1 & b_21=0 & b_15=1 & addrReg & Rt_GPR32 & Rt_GPR64
+{
+ tmp:2 = *addrReg;
+ Rt_GPR64 = zext(tmp);
+}
+
+# C6.2.160 LDLARB page C6-1540 line 91472 MATCH x08c00000/mask=xffe08000
+# CONSTRUCT x08c00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x08c00000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111
+# size=0b00 (3031)
+
+:ldlarb aa_Wt, [Rn_GPR64xsp]
+is b_3031=0b00 & b_2329=0b0010001 & b_22=1 & b_21=0 & b_15=0 & aa_Wt & Rn_GPR64xsp
+{ LOAcquire(); aa_Wt = zext(*:1 Rn_GPR64xsp); }
+
+# C6.2.161 LDLARH page C6-1541 line 91541 MATCH x48c00000/mask=xffe08000
+# CONSTRUCT x48c00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x48c00000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111
+# size=0b01 (3031)
+
+:ldlarh aa_Wt, [Rn_GPR64xsp]
+is b_3031=0b01 & b_2329=0b0010001 & b_22=1 & b_21=0 & b_15=0 & aa_Wt & Rn_GPR64xsp
+{ LOAcquire(); aa_Wt = zext(*:2 Rn_GPR64xsp); }
+
+# C6.2.162 LDLAR page C6-1542 line 91610 MATCH x88c00000/mask=xbfe08000
+# CONSTRUCT x88c00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x88c00000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111
+# size=0b10 (3031)
+
+:ldlar aa_Wt, [Rn_GPR64xsp]
+is b_3031=0b10 & b_2329=0b0010001 & b_22=1 & b_21=0 & b_15=0 & aa_Wt & Rn_GPR64xsp
+{ LOAcquire(); aa_Wt = *:4 Rn_GPR64xsp; }
+
+# C6.2.162 LDLAR page C6-1542 line 91610 MATCH x88c00000/mask=xbfe08000
+# CONSTRUCT xc8c00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xc8c00000/mask=xffe08000 --status nomem
+# size=0b11 (3031)
+
+:ldlar aa_Xt, [Rn_GPR64xsp]
+is b_3031=0b11 & b_2329=0b0010001 & b_22=1 & b_21=0 & b_15=0 & aa_Xt & Rn_GPR64xsp
+{ LOAcquire(); aa_Xt = *:8 Rn_GPR64xsp; }
+
+# C6.2.163 LDNP page C6-1544 line 91702 MATCH x28400000/mask=x7fc00000
+# CONSTRUCT x28400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x28400000/mask=xffc00000 --status nomem
+
+:ldnp Rt_GPR32, Rt2_GPR32, addrPairIndexed
+is b_3031=0b00 & b_2229=0b10100001 & Rt2_GPR32 & addrPairIndexed & Rt_GPR32 & Rt_GPR64 & Rt2_GPR64
+{
+ Rt_GPR64 = zext(*:4 addrPairIndexed);
+ Rt2_GPR64 = zext(*:4 (addrPairIndexed + 4));
+}
+
+# C6.2.163 LDNP page C6-1544 line 91702 MATCH x28400000/mask=x7fc00000
+# CONSTRUCT xa8400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xa8400000/mask=xffc00000 --status nomem
+
+:ldnp Rt_GPR64, Rt2_GPR64, addrPairIndexed
+is b_3031=0b10 & b_2229=0b10100001 & Rt2_GPR64 & addrPairIndexed & Rt_GPR64
+{
+ Rt_GPR64 = *addrPairIndexed;
+ Rt2_GPR64 = *(addrPairIndexed + 8);
+}
+
+# C6.2.164 LDP page C6-1546 line 91841 MATCH x28c00000/mask=x7fc00000
+# C6.2.164 LDP page C6-1546 line 91841 MATCH x29c00000/mask=x7fc00000
+# C6.2.164 LDP page C6-1546 line 91841 MATCH x29400000/mask=x7fc00000
+# C6.2.163 LDNP page C6-1544 line 91702 MATCH x28400000/mask=x7fc00000
+# CONSTRUCT x28400000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst x28400000/mask=xfe400000 --status nomem
+# opc == 00 post-index, pre-index, and signed 32-bit variant
+
+:ldp Rt_GPR32, Rt2_GPR32, addrPairIndexed
+is b_3031=0b00 & b_2529=0b10100 & (b_24=1 | b_23=1) & b_22=1 & Rt2_GPR32 & addrPairIndexed & Rt_GPR32 & Rt_GPR64 & Rt2_GPR64
+{
+ Rt_GPR64 = zext(*:4 addrPairIndexed);
+ Rt2_GPR64 = zext(*:4 (addrPairIndexed + 4));
+}
+
+# C6.2.164 LDP page C6-1546 line 91841 MATCH x28c00000/mask=x7fc00000
+# C6.2.164 LDP page C6-1546 line 91841 MATCH x29c00000/mask=x7fc00000
+# C6.2.164 LDP page C6-1546 line 91841 MATCH x29400000/mask=x7fc00000
+# C6.2.163 LDNP page C6-1544 line 91702 MATCH x28400000/mask=x7fc00000
+# CONSTRUCT xa8400000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst xa8400000/mask=xfe400000 --status nomem
+# opc == 10 post-index, pre-index, and signed 64-bit variant
+
+:ldp Rt_GPR64, Rt2_GPR64, addrPairIndexed
+is b_3031=0b10 & b_2529=0b10100 & (b_24=1 | b_23=1) & b_22=1 & Rt2_GPR64 & addrPairIndexed & Rt_GPR64
+{
+ Rt_GPR64 = *addrPairIndexed;
+ Rt2_GPR64 = *(addrPairIndexed + 8);
+}
+
+# C6.2.165 LDPSW page C6-1550 line 92077 MATCH x68c00000/mask=xffc00000
+# C6.2.165 LDPSW page C6-1550 line 92077 MATCH x69c00000/mask=xffc00000
+# C6.2.165 LDPSW page C6-1550 line 92077 MATCH x69400000/mask=xffc00000
+# CONSTRUCT x68400000/mask=xfe400000 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst x68400000/mask=xfe400000 --status nomem
+
+:ldpsw Rt_GPR64, Rt2_GPR64, addrPairIndexed
+is b_2531=0b0110100 & (b_24=1 | b_23=1) & b_22=1 & Rt2_GPR64 & addrPairIndexed & Rt_GPR64
+{
+ Rt_GPR64 = *(addrPairIndexed);
+ Rt2_GPR64 = *(addrPairIndexed+8);
+}
+
+# C6.2.166 LDR (immediate) page C6-1553 line 92262 MATCH xb9400000/mask=xbfc00000
+# CONSTRUCT xb9400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xb9400000/mask=xffc00000 --status nomem
+
+:ldr Rt_GPR32, addrUIMM
+is size.ldstr=2 & b_2729=7 & v=0 & b_2425=1 & b_23=0 & b_2222=1 & addrUIMM & Rn_GPR64xsp & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = zext(*:4 addrUIMM);
+}
+
+# C6.2.166 LDR (immediate) page C6-1553 line 92262 MATCH xb8400400/mask=xbfe00c00
+# C6.2.166 LDR (immediate) page C6-1553 line 92262 MATCH xb8400c00/mask=xbfe00c00
+# C6.2.190 LDTR page C6-1611 line 95666 MATCH xb8400800/mask=xbfe00c00
+# C6.2.202 LDUR page C6-1637 line 97204 MATCH xb8400000/mask=xbfe00c00
+# CONSTRUCT xb8400000/mask=xffe00000 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst xb8400000/mask=xffe00000 --status nomem
+
+:ld^UnscPriv^"r" Rt_GPR32, addrIndexed
+is size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = zext(*:4 addrIndexed);
+}
+
+# C6.2.166 LDR (immediate) page C6-1553 line 92262 MATCH xb8400400/mask=xbfe00c00
+# C6.2.166 LDR (immediate) page C6-1553 line 92262 MATCH xb8400c00/mask=xbfe00c00
+# CONSTRUCT xb8400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xb8400400/mask=xffe00400 --status nomem
+
+:ldr Rt_GPR32, addrIndexed
+is size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = zext(*:4 addrIndexed);
+}
+
+# C6.2.166 LDR (immediate) page C6-1553 line 92262 MATCH xb9400000/mask=xbfc00000
+# CONSTRUCT xf9400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xf9400000/mask=xffc00000 --status nomem
+
+:ldr Rt_GPR64, addrUIMM
+is size.ldstr=3 & b_2729=7 & v=0 & b_2425=1 & b_23=0 & b_2222=1 & addrUIMM & Rn_GPR64xsp & Rt_GPR64
+{
+ Rt_GPR64 = *addrUIMM;
+}
+
+# C6.2.166 LDR (immediate) page C6-1553 line 92262 MATCH xb8400400/mask=xbfe00c00
+# C6.2.166 LDR (immediate) page C6-1553 line 92262 MATCH xb8400c00/mask=xbfe00c00
+# CONSTRUCT xf8400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xf8400400/mask=xffe00400 --status nomem
+
+:ldr Rt_GPR64, addrIndexed
+is size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR64
+{
+ Rt_GPR64 = *addrIndexed;
+}
+
+# C6.2.167 LDR (literal) page C6-1556 line 92457 MATCH x18000000/mask=xbf000000
+# CONSTRUCT x18000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x18000000/mask=xff000000 --status nomem
+
+:ldr Rt_GPR32, AddrLoc19
+is size.ldstr=0 & b_2729=3 & v=0 & b_2425=0 & AddrLoc19 & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = zext(*:4 AddrLoc19);
+}
+
+# C6.2.167 LDR (literal) page C6-1556 line 92457 MATCH x18000000/mask=xbf000000
+# CONSTRUCT x58000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x58000000/mask=xff000000 --status nomem
+
+:ldr Rt_GPR64, AddrLoc19
+is size.ldstr=1 & b_2729=3 & v=0 & b_2425=0 & AddrLoc19 & Rt_GPR64
+{
+ Rt_GPR64 = *:4 AddrLoc19;
+}
+
+# C6.2.168 LDR (register) page C6-1558 line 92557 MATCH xb8600800/mask=xbfe00c00
+# CONSTRUCT xb8600800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xb8600800/mask=xffe00c00 --status nomem
+
+:ldr Rt_GPR32, addrIndexed
+is size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = zext(*:4 addrIndexed);
+}
+
+# C6.2.168 LDR (register) page C6-1558 line 92557 MATCH xb8600800/mask=xbfe00c00
+# CONSTRUCT xf8600800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xf8600800/mask=xffe00c00 --status nomem
+
+:ldr Rt_GPR64, addrIndexed
+is size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR64
+{
+ Rt_GPR64 = *addrIndexed;
+}
+
+
+# C6.2.169 LDRAA, LDRAB page C6-1560 line 92679 MATCH xf8200400/mask=xff200400
+# CONSTRUCT xf8200400/mask=xffa00400 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xf8200400/mask=xffa00400 --status nomem
+# M == 0 && W == 0 key A, offset variant
+# M == 0 && W == 1 key A, offset variant
+
+:ldraa Rt_GPR64, addrIndexed
+is ldraa__PACpart & b_2431=0b11111000 & b_23=0 & b_21=1 & b_10=1 & addrIndexed & Rn_GPR64xsp & Rt_GPR64
+{
+ build ldraa__PACpart;
+ build addrIndexed;
+ # Note: if writeback is used, the writeback'd value doesn't have a PAC code! It's the output of AuthDA.
+ Rt_GPR64 = *:8 addrIndexed;
+}
+
+# C6.2.169 LDRAA, LDRAB page C6-1560 line 92679 MATCH xf8200400/mask=xff200400
+# CONSTRUCT xf8a00400/mask=xffa00400 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xf8a00400/mask=xffa00400 --status nomem
+# M == 1 && W == 0 key B, offset variant
+# M == 1 && W == 1 key B, offset variant
+
+:ldrab Rt_GPR64, addrIndexed
+is ldrab__PACpart & b_2431=0b11111000 & b_23=1 & b_21=1 & b_10=1 & addrIndexed & Rn_GPR64xsp & Rt_GPR64
+{
+ build ldrab__PACpart;
+ build addrIndexed;
+ # Note: if writeback is used, the writeback'd value doesn't have a PAC code! It's the output of AuthDB.
+ Rt_GPR64 = *:8 addrIndexed;
+}
+
+# C6.2.170 LDRB (immediate) page C6-1562 line 92814 MATCH x38400400/mask=xffe00c00
+# C6.2.170 LDRB (immediate) page C6-1562 line 92814 MATCH x38400c00/mask=xffe00c00
+# CONSTRUCT x38400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x38400400/mask=xffe00400 --status nomem
+# post-index and pre-index variants
+
+:ldrb Rt_GPR32, addrIndexed
+is b_2131=0b00111000010 & b_10=1 & addrIndexed & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = zext(*:1 addrIndexed);
+}
+
+# C6.2.170 LDRB (immediate) page C6-1562 line 92814 MATCH x39400000/mask=xffc00000
+# CONSTRUCT x39400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x39400000/mask=xffc00000 --status nomem
+# unsigned offset variant
+
+:ldrb Rt_GPR32, addrIndexed
+is b_2231=0b0011100101 & addrIndexed & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = zext(*:1 addrIndexed);
+}
+
+# C6.2.171 LDRB (register) page C6-1565 line 92976 MATCH x38600800/mask=xffe00c00
+# CONSTRUCT x38600800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x38600800/mask=xffe00c00 --status nomem
+# extended register and shifted register variant
+# determined in addrIndexed subtable
+
+:ldrb Rt_GPR32, addrIndexed
+is b_2131=0b00111000011 & b_1011=2 & addrIndexed & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = zext(*:1 addrIndexed);
+}
+
+# C6.2.172 LDRH (immediate) page C6-1567 line 93076 MATCH x79400000/mask=xffc00000
+# CONSTRUCT x79400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x79400000/mask=xffc00000 --status nomem
+
+:ldrh Rt_GPR32, addrUIMM
+is size.ldstr=1 & b_2729=7 & v=0 & b_2425=1 & b_23=0 & b_2222=1 & addrUIMM & Rn_GPR64xsp & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = zext(*:2 addrUIMM);
+}
+
+# C6.2.172 LDRH (immediate) page C6-1567 line 93076 MATCH x78400400/mask=xffe00c00
+# C6.2.172 LDRH (immediate) page C6-1567 line 93076 MATCH x78400c00/mask=xffe00c00
+# CONSTRUCT x78400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x78400400/mask=xffe00400 --status nomem
+
+:ldrh Rt_GPR32, addrIndexed
+is size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = zext(*:2 addrIndexed);
+}
+
+# C6.2.173 LDRH (register) page C6-1570 line 93238 MATCH x78600800/mask=xffe00c00
+# CONSTRUCT x78600800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x78600800/mask=xffe00c00 --status nomem
+
+:ldrh Rt_GPR32, addrIndexed
+is size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = zext(*:2 addrIndexed);
+}
+
+# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x39800000/mask=xff800000
+# CONSTRUCT x39c00000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x39c00000/mask=xffc00000 --status nomem
+
+:ldrsb Rt_GPR32, addrIndexed
+is size.ldstr=0 & b_2729=7 & v=0 & b_2425=1 & b_2223=3 & addrIndexed & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = sext(*:1 addrIndexed);
+}
+
+# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x38800400/mask=xffa00c00
+# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x38800c00/mask=xffa00c00
+# C6.2.193 LDTRSB page C6-1617 line 95984 MATCH x38800800/mask=xffa00c00
+# C6.2.205 LDURSB page C6-1641 line 97443 MATCH x38800000/mask=xffa00c00
+# CONSTRUCT x38c00000/mask=xffe00000 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst x38c00000/mask=xffe00000 --status nomem
+
+:ld^UnscPriv^"rsb" Rt_GPR32, addrIndexed
+is size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_2223=3 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = zext(*:1 addrIndexed);
+}
+
+# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x38800400/mask=xffa00c00
+# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x38800c00/mask=xffa00c00
+# CONSTRUCT x38c00400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x38c00400/mask=xffe00400 --status nomem
+
+:ldrsb Rt_GPR32, addrIndexed
+is size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_2223=3 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = sext(*:1 addrIndexed);
+}
+
+# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x39800000/mask=xff800000
+# CONSTRUCT x39800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x39800000/mask=xffc00000 --status nomem
+
+:ldrsb Rt_GPR64, addrIndexed
+is size.ldstr=0 & b_2729=7 & v=0 & b_2425=1 & b_2223=2 & addrIndexed & Rt_GPR64
+{
+ Rt_GPR64 = sext(*:1 addrIndexed);
+}
+
+# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x38800400/mask=xffa00c00
+# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x38800c00/mask=xffa00c00
+# C6.2.193 LDTRSB page C6-1617 line 95984 MATCH x38800800/mask=xffa00c00
+# C6.2.205 LDURSB page C6-1641 line 97443 MATCH x38800000/mask=xffa00c00
+# CONSTRUCT x38800000/mask=xffe00000 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst x38800000/mask=xffe00000 --status nomem
+
+:ld^UnscPriv^"rsb" Rt_GPR64, addrIndexed
+is size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR64
+{
+ Rt_GPR64 = sext(*:1 addrIndexed);
+}
+
+# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x38800400/mask=xffa00c00
+# C6.2.174 LDRSB (immediate) page C6-1572 line 93336 MATCH x38800c00/mask=xffa00c00
+# CONSTRUCT x38800400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x38800400/mask=xffe00400 --status nomem
+
+:ldrsb Rt_GPR64, addrIndexed
+is size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR64
+{
+ Rt_GPR64 = sext(*:1 addrIndexed);
+}
+
+# C6.2.175 LDRSB (register) page C6-1576 line 93573 MATCH x38a00800/mask=xffa00c00
+# CONSTRUCT x38e00800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x38e00800/mask=xffe00c00 --status nomem
+
+:ldrsb Rt_GPR32, addrIndexed
+is size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_2223=3 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = sext(*:1 addrIndexed);
+}
+
+# C6.2.175 LDRSB (register) page C6-1576 line 93573 MATCH x38a00800/mask=xffa00c00
+# CONSTRUCT x38a00800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x38a00800/mask=xffe00c00 --status nomem
+
+:ldrsb Rt_GPR64, addrIndexed
+is size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR64
+{
+ Rt_GPR64 = sext(*:1 addrIndexed);
+}
+
+# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x79800000/mask=xff800000
+# CONSTRUCT x79c00000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x79c00000/mask=xffc00000 --status nomem
+
+:ldrsh Rt_GPR32, addrUIMM
+is size.ldstr=1 & b_2729=7 & v=0 & b_2425=1 & b_2223=3 & addrUIMM & Rn_GPR64xsp & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = sext(*:2 addrUIMM);
+}
+
+# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x78800400/mask=xffa00c00
+# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x78800c00/mask=xffa00c00
+# C6.2.194 LDTRSH page C6-1619 line 96122 MATCH x78800800/mask=xffa00c00
+# C6.2.206 LDURSH page C6-1643 line 97560 MATCH x78800000/mask=xffa00c00
+# CONSTRUCT x78c00000/mask=xffe00000 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst x78c00000/mask=xffe00000 --status nomem
+
+:ld^UnscPriv^"rsh" Rt_GPR32, addrIndexed
+is size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_2223=3 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = sext(*:2 addrIndexed);
+}
+
+# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x78800400/mask=xffa00c00
+# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x78800c00/mask=xffa00c00
+# CONSTRUCT x78c00400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x78c00400/mask=xffe00400 --status nomem
+
+:ldrsh Rt_GPR32, addrIndexed
+is size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_2223=3 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = sext(*:2 addrIndexed);
+}
+
+# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x79800000/mask=xff800000
+# CONSTRUCT x79800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x79800000/mask=xffc00000 --status nomem
+
+:ldrsh Rt_GPR64, addrUIMM
+is size.ldstr=1 & b_2729=7 & v=0 & b_2425=1 & b_2223=2 & addrUIMM & Rn_GPR64xsp & Rt_GPR64
+{
+ Rt_GPR64 = sext(*:2 addrUIMM);
+}
+
+# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x78800400/mask=xffa00c00
+# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x78800c00/mask=xffa00c00
+# C6.2.194 LDTRSH page C6-1619 line 96122 MATCH x78800800/mask=xffa00c00
+# C6.2.206 LDURSH page C6-1643 line 97560 MATCH x78800000/mask=xffa00c00
+# CONSTRUCT x78800000/mask=xffe00000 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst x78800000/mask=xffe00000 --status nomem
+
+:ld^UnscPriv^"rsh" Rt_GPR64, addrIndexed
+is size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR64
+{
+ Rt_GPR64 = sext(*:2 addrIndexed);
+}
+
+# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x78800400/mask=xffa00c00
+# C6.2.176 LDRSH (immediate) page C6-1578 line 93714 MATCH x78800c00/mask=xffa00c00
+# CONSTRUCT x78800400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x78800400/mask=xffe00400 --status nomem
+
+:ldrsh Rt_GPR64, addrIndexed
+is size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR64
+{
+ Rt_GPR64 = sext(*:2 addrIndexed);
+}
+
+# C6.2.177 LDRSH (register) page C6-1582 line 93951 MATCH x78a00800/mask=xffa00c00
+# CONSTRUCT x78e00800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x78e00800/mask=xffe00c00 --status nomem
+
+:ldrsh Rt_GPR32, addrIndexed
+is size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_2223=3 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = sext(*:2 addrIndexed);
+}
+
+# C6.2.177 LDRSH (register) page C6-1582 line 93951 MATCH x78a00800/mask=xffa00c00
+# CONSTRUCT x78a00800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x78a00800/mask=xffe00c00 --status nomem
+
+:ldrsh Rt_GPR64, addrIndexed
+is size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR64
+{
+ Rt_GPR64 = sext(*:2 addrIndexed);
+}
+
+# C6.2.178 LDRSW (immediate) page C6-1584 line 94088 MATCH xb8800400/mask=xffe00c00
+# C6.2.178 LDRSW (immediate) page C6-1584 line 94088 MATCH xb8800c00/mask=xffe00c00
+# CONSTRUCT xb8800400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xb8800400/mask=xffe00400 --status nomem
+
+:ldrsw Rt_GPR64, addrIndexed
+is size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR64
+{
+ Rt_GPR64 = sext(*:4 addrIndexed);
+}
+
+# C6.2.178 LDRSW (immediate) page C6-1584 line 94088 MATCH xb9800000/mask=xffc00000
+# CONSTRUCT xb9800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xb9800000/mask=xffc00000 --status nomem
+
+:ldrsw Rt_GPR64, addrIndexed
+is size.ldstr=2 & b_2729=7 & v=0 & b_2425=1 & b_2223=2 & addrIndexed & Rt_GPR64
+{
+ Rt_GPR64 = sext(*:4 addrIndexed);
+}
+
+# C6.2.179 LDRSW (literal) page C6-1587 line 94246 MATCH x98000000/mask=xff000000
+# CONSTRUCT x98000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x98000000/mask=xff000000 --status nomem
+
+:ldrsw Rt_GPR64, AddrLoc19
+is b_2431=0b10011000 & AddrLoc19 & Rt_GPR64
+{
+ Rt_GPR64 = sext(*:4 AddrLoc19);
+}
+
+# C6.2.180 LDRSW (register) page C6-1588 line 94304 MATCH xb8a00800/mask=xffe00c00
+# CONSTRUCT xb8a00800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xb8a00800/mask=xffe00c00 --status nomem
+
+:ldrsw Rt_GPR64, addrIndexed
+is size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR64
+{
+ Rt_GPR64 = sext(*:4 addrIndexed);
+}
+
+# C6.2.190 LDTR page C6-1611 line 95666 MATCH xb8400800/mask=xbfe00c00
+# CONSTRUCT xf8400800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xf8400800/mask=xffe00c00 --status nomem
+
+:ld^UnscPriv^"r" Rt_GPR64, addrIndexed
+is size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_2223=1 & b_2121=0 & b_1011=2 & UnscPriv & addrIndexed & Rt_GPR64
+{
+ Rt_GPR64 = *addrIndexed;
+}
+
+# C6.2.191 LDTRB page C6-1613 line 95782 MATCH x38400800/mask=xffe00c00
+# C6.2.203 LDURB page C6-1639 line 97301 MATCH x38400000/mask=xffe00c00
+# CONSTRUCT x38400000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x38400000/mask=xffe00000 --status nomem
+
+:ld^UnscPriv^"rb" Rt_GPR32, addrIndexed
+is size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = zext(*:1 addrIndexed);
+}
+
+# C6.2.192 LDTRH page C6-1615 line 95883 MATCH x78400800/mask=xffe00c00
+# C6.2.204 LDURH page C6-1640 line 97372 MATCH x78400000/mask=xffe00c00
+# CONSTRUCT x78400000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x78400000/mask=xffe00000 --status nomem
+
+:ld^UnscPriv^"rh" Rt_GPR32, addrIndexed
+is size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = zext(*:2 addrIndexed);
+}
+
+# C6.2.195 LDTRSW page C6-1621 line 96261 MATCH xb8800800/mask=xffe00c00
+# C6.2.207 LDURSW page C6-1645 line 97677 MATCH xb8800000/mask=xffe00c00
+# CONSTRUCT xb8800000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xb8800000/mask=xffe00000 --status nomem
+
+:ld^UnscPriv^"rsw" Rt_GPR64, addrIndexed
+is size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR64
+{
+ Rt_GPR64 = sext(*:4 addrIndexed);
+}
+
+# C6.2.202 LDUR page C6-1637 line 97204 MATCH xb8400000/mask=xbfe00c00
+# CONSTRUCT xf8400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xf8400000/mask=xffe00c00 --status nomem
+
+:ld^UnscPriv^"r" Rt_GPR64, addrIndexed
+is size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2122=2 & b_1011=0 & UnscPriv & addrIndexed & Rt_GPR64
+{
+ Rt_GPR64 = *addrIndexed;
+}
+
+# C6.2.208 LDXP page C6-1646 line 97748 MATCH x88600000/mask=xbfe08000
+# CONSTRUCT xc8600000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xc8600000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111
+
+:ldxp Rt_GPR64, Rt2_GPR64, addrReg
+is size.ldstr=3 & b_2429=0x8 & b_23=0 & L=1 & b_21=1 & b_15=0 & Rt2_GPR64 & addrReg & Rt_GPR64
+{
+ Rt_GPR64 = *addrReg;
+ Rt2_GPR64 = *(addrReg + 8);
+}
+
+# C6.2.208 LDXP page C6-1646 line 97748 MATCH x88600000/mask=xbfe08000
+# CONSTRUCT x88600000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x88600000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111
+
+:ldxp Rt_GPR32, Rt2_GPR32, addrReg
+is size.ldstr=2 & b_2429=0x8 & b_23=0 & L=1 & b_21=1 & b_15=0 & Rt2_GPR32 & addrReg & Rt_GPR32 & Rt_GPR64 & Rt2_GPR64
+{
+ Rt_GPR64 = zext(*:4 addrReg);
+ Rt2_GPR64 = zext(*:4 (addrReg + 4));
+}
+
+# C6.2.209 LDXR page C6-1648 line 97882 MATCH x88400000/mask=xbfe08000
+# CONSTRUCT xc8400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xc8400000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111
+
+:ldxr Rt_GPR64, addrReg
+is size.ldstr=3 & b_2429=0x8 & b_23=0 & L=1 & b_21=0 & b_15=0 & addrReg & Rt_GPR64
+{
+ Rt_GPR64 = *addrReg;
+}
+
+# C6.2.209 LDXR page C6-1648 line 97882 MATCH x88400000/mask=xbfe08000
+# CONSTRUCT x88400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x88400000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111
+
+:ldxr Rt_GPR32, addrReg
+is size.ldstr=2 & b_2429=0x8 & b_23=0 & L=1 & b_21=0 & b_15=0 & addrReg & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = zext(*:4 addrReg);
+}
+
+# C6.2.210 LDXRB page C6-1650 line 97976 MATCH x08400000/mask=xffe08000
+# CONSTRUCT x08400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x08400000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111
+
+:ldxrb Rt_GPR32, addrReg
+is size.ldstr=0 & b_2429=0x8 & b_23=0 & L=1 & b_21=0 & b_15=0 & addrReg & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = zext(*:1 addrReg);
+}
+
+# C6.2.211 LDXRH page C6-1651 line 98048 MATCH x48400000/mask=xffe08000
+# CONSTRUCT x48400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x48400000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111
+
+:ldxrh Rt_GPR32, addrReg
+is size.ldstr=1 & b_2429=0x8 & b_23=0 & L=1 & b_21=0 & b_15=0 & addrReg & Rt_GPR32 & Rt_GPR64
+{
+ Rt_GPR64 = zext(*:2 addrReg);
+}
+
+# C6.2.212 LSL (register) page C6-1652 line 98120 MATCH x1ac02000/mask=x7fe0fc00
+# C6.2.214 LSLV page C6-1656 line 98305 MATCH x1ac02000/mask=x7fe0fc00
+# CONSTRUCT x1ac02000/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x1ac02000/mask=xffe0fc00 --status pass
+
+:lsl Rd_GPR32, Rn_GPR32, Rm_GPR32
+is sf=0 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR32 & b_1015=0x8 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ shiftval:8 = zext(Rm_GPR32 & 0x1f);
+ tmp_1:4 = Rn_GPR32 << shiftval;
+ Rd_GPR64 = zext(tmp_1);
+}
+
+# C6.2.212 LSL (register) page C6-1652 line 98120 MATCH x1ac02000/mask=x7fe0fc00
+# C6.2.214 LSLV page C6-1656 line 98305 MATCH x1ac02000/mask=x7fe0fc00
+# CONSTRUCT x9ac02000/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x9ac02000/mask=xffe0fc00 --status pass
+
+:lsl Rd_GPR64, Rn_GPR64, Rm_GPR64
+is sf=1 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR64 & b_1015=0x8 & Rn_GPR64 & Rd_GPR64
+{
+ shiftval:8 = (Rm_GPR64 & 0x3f);
+ tmp_1:8 = Rn_GPR64 << shiftval;
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.158 LSL (immediate) page C6-784 line 45779 KEEPWITH
+
+ubfiz_lsb: "#"^imm is ImmR [ imm = 32 - ImmR; ] { export *[const]:4 imm; }
+ubfiz_width: "#"^imm is ImmS [ imm = ImmS + 1; ] { export *[const]:4 imm; }
+ubfiz_lsb64: "#"^imm is ImmR [ imm = 64 - ImmR; ] { export *[const]:4 imm; }
+ubfx_width: "#"^imm is ImmR & ImmS [ imm = ImmS - ImmR + 1; ] { export *[const]:4 imm; }
+
+# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000
+# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00
+# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000
+# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000
+# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000
+# C6.2.394 UXTB page C6-2002 line 117228 MATCH x53001c00/mask=xfffffc00
+# C6.2.395 UXTH page C6-2003 line 117288 MATCH x53003c00/mask=xfffffc00
+# CONSTRUCT x53000012/mask=xffe0801e MATCHED 7 DOCUMENTED OPCODES
+# AUNIT --inst x53000012/mask=xffe0801e --status pass
+# Alias for ubfm where imms+1=immr and imms != '011111'
+# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue();
+
+:lsl Rd_GPR32, Rn_GPR32, LSB_bitfield32_imm_shift
+is ImmR=ImmS+1 & ImmS_ne_1f=1 & ImmS_LT_ImmR_minus_1=0 & ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=1 & sf=0 & opc=2 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & LSB_bitfield32_imm_shift & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ local tmp:4 = Rn_GPR32 << LSB_bitfield32_imm_shift;
+ Rd_GPR64 = zext(tmp);
+}
+
+# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000
+# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00
+# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000
+# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000
+# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000
+# CONSTRUCT xd3400022/mask=xffc0002e MATCHED 5 DOCUMENTED OPCODES
+# AUNIT --inst xd3400022/mask=xffc0002e --status pass
+# Alias for ubfm where imms+1=immr and imms != '111111'
+
+:lsl Rd_GPR64, Rn_GPR64, LSB_bitfield64_imm_shift
+is ImmR=ImmS+1 & ImmS_ne_3f=1 & ImmS_LT_ImmR_minus_1=0 & ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=1 & sf=1 & opc=2 & b_2428=0x13 & b_2323=0 & n=1 & LSB_bitfield64_imm_shift & Rn_GPR64 & Rd_GPR64
+{
+ Rd_GPR64 = Rn_GPR64 << LSB_bitfield64_imm_shift;
+}
+
+# C6.2.215 LSR (register) page C6-1658 line 98396 MATCH x1ac02400/mask=x7fe0fc00
+# C6.2.217 LSRV page C6-1662 line 98580 MATCH x1ac02400/mask=x7fe0fc00
+# CONSTRUCT x1ac02400/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x1ac02400/mask=xffe0fc00 --status pass
+
+:lsr Rd_GPR32, Rn_GPR32, Rm_GPR32
+is sf=0 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR32 & b_1015=0x9 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ shiftval:8 = zext(Rm_GPR32 & 0x1f);
+ tmp_1:4 = Rn_GPR32 >> shiftval;
+ Rd_GPR64 = zext(tmp_1);
+}
+
+# C6.2.215 LSR (register) page C6-1658 line 98396 MATCH x1ac02400/mask=x7fe0fc00
+# C6.2.217 LSRV page C6-1662 line 98580 MATCH x1ac02400/mask=x7fe0fc00
+# CONSTRUCT x9ac02400/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x9ac02400/mask=xffe0fc00 --status pass
+
+:lsr Rd_GPR64, Rn_GPR64, Rm_GPR64
+is sf=1 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR64 & b_1015=0x9 & Rn_GPR64 & Rd_GPR64
+{
+ shiftval:8 = Rm_GPR64 & 0x3f;
+ tmp_1:8 = Rn_GPR64 >> shiftval;
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00
+# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000
+# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000
+# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000
+# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000
+# CONSTRUCT x53007c00/mask=xffe0fc1a MATCHED 5 DOCUMENTED OPCODES
+# AUNIT --inst x53007c00/mask=xffe0fc1a --status pass
+# Alias for ubfm where imms=='011111'
+# imms is MAX_INT5, so it will never be less than immr. Note that immr is limited to [0,31]
+# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue();
+
+:lsr Rd_GPR32, Rn_GPR32, ImmRConst32
+is ImmS=0x1f & ImmS_ne_1f=0 & ImmS_LT_ImmR=0 & ImmS_LT_ImmR_minus_1=0 & sf=0 & opc=2 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp_2:4 = ImmRConst32;
+ tmp_1:4 = Rn_GPR32 >> tmp_2;
+ Rd_GPR64 = zext(tmp_1);
+}
+
+# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00
+# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000
+# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000
+# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000
+# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000
+# CONSTRUCT xd340fc00/mask=xffc0fc2a MATCHED 5 DOCUMENTED OPCODES
+# AUNIT --inst xd340fc00/mask=xffc0fc2a --status pass
+# Alias for ubfm where imms=='111111'
+# imms is MAX_INT6, so it will never be less than immr.
+
+:lsr Rd_GPR64, Rn_GPR64, ImmRConst64
+is ImmS=0x3f & ImmS_ne_3f=0 & ImmS_LT_ImmR=0 & ImmS_LT_ImmR_minus_1=0 & sf=1 & opc=2 & b_2428=0x13 & b_2323=0 & n=1 & ImmRConst64 & Rn_GPR64 & Rd_GPR64
+{
+ tmp_2:8 = ImmRConst64;
+ tmp_1:8 = Rn_GPR64 >> tmp_2;
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.218 MADD page C6-1664 line 98671 MATCH x1b000000/mask=x7fe08000
+# C6.2.232 MUL page C6-1691 line 100073 MATCH x1b007c00/mask=x7fe0fc00
+# CONSTRUCT x1b000000/mask=xffe08000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x1b000000/mask=xffe08000 --status pass
+
+:madd Rd_GPR32, Rn_GPR32, Rm_GPR32, Ra_GPR32
+is sf=0 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=0 & Rm_GPR32 & op.dp3_o0=0 & Ra_GPR32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp_2:4 = Rn_GPR32 * Rm_GPR32;
+ addflags(Ra_GPR32, tmp_2);
+ tmp_1:4 = Ra_GPR32 + tmp_2;
+ Rd_GPR64 = zext(tmp_1);
+}
+
+# C6.2.218 MADD page C6-1664 line 98671 MATCH x1b000000/mask=x7fe08000
+# C6.2.232 MUL page C6-1691 line 100073 MATCH x1b007c00/mask=x7fe0fc00
+# CONSTRUCT x9b000000/mask=xffe08000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x9b000000/mask=xffe08000 --status pass
+
+:madd Rd_GPR64, Rn_GPR64, Rm_GPR64, Ra_GPR64
+is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=0 & Rm_GPR64 & op.dp3_o0=0 & Ra_GPR64 & Rn_GPR64 & Rd_GPR64
+{
+ tmp_2:8 = Rn_GPR64 * Rm_GPR64;
+ tmp_1:8 = Ra_GPR64 + tmp_2;
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.219 MNEG page C6-1666 line 98782 MATCH x1b00fc00/mask=x7fe0fc00
+# C6.2.231 MSUB page C6-1689 line 99963 MATCH x1b008000/mask=x7fe08000
+# CONSTRUCT x9b00fc00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x9b00fc00/mask=xffe0fc00 --status pass
+
+:mneg Rd_GPR64, Rn_GPR64, Rm_GPR64
+is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=0 & Rm_GPR64 & op.dp3_o0=1 & Ra=0x1f & Rn_GPR64 & Rd_GPR64
+{
+ tmp_2:8 = Rn_GPR64 * Rm_GPR64;
+ tmp_1:8 = -tmp_2;
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.219 MNEG page C6-1666 line 98782 MATCH x1b00fc00/mask=x7fe0fc00
+# C6.2.231 MSUB page C6-1689 line 99963 MATCH x1b008000/mask=x7fe08000
+# CONSTRUCT x1b00fc00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x1b00fc00/mask=xffe0fc00 --status pass
+
+:mneg Rd_GPR32, Rn_GPR32, Rm_GPR32
+is sf=0 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=0 & Rm_GPR32 & op.dp3_o0=1 & Ra=0x1f & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp_2:4 = Rn_GPR32 * Rm_GPR32;
+ tmp_1:4 = -tmp_2;
+ Rd_GPR64 = zext(tmp_1);
+}
+
+# C6.2.220 MOV (to/from SP) page C6-1668 line 98876 MATCH x11000000/mask=x7ffffc00
+# C6.2.4 ADD (immediate) page C6-1151 line 68228 MATCH x11000000/mask=x7f800000
+# CONSTRUCT x11000000/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x11000000/mask=xfffffc00 --status pass
+
+:mov Rd_GPR32xsp, Rn_GPR32xsp
+is sf=0 & b_30=0 & S=0 & b_2428=0x011 & (aa_Xn=31 | aa_Xd=31) & shift=0 & imm12=0 & Rn_GPR32xsp & Rd_GPR32xsp & Rd_GPR64xsp
+{
+ Rd_GPR64xsp = zext(Rn_GPR32xsp);
+}
+
+# C6.2.220 MOV (to/from SP) page C6-1668 line 98876 MATCH x11000000/mask=x7ffffc00
+# C6.2.4 ADD (immediate) page C6-1151 line 68228 MATCH x11000000/mask=x7f800000
+# CONSTRUCT x91000000/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x91000000/mask=xfffffc00 --status pass
+
+:mov Rd_GPR64xsp, Rn_GPR64xsp
+is sf=1 & b_30=0 & S=0 & b_2428=0x11 & (aa_Xn=31 | aa_Xd=31) & shift=0 & imm12=0 & Rn_GPR64xsp & Rd_GPR64xsp
+{
+ Rd_GPR64xsp = Rn_GPR64xsp;
+}
+
+# C6.2.166 MOV (inverted wide immediate) page C6-793 line 46366 KEEPWITH
+
+FullImm_movz32_imm: "#"^val is imm16 & aa_hw=0 [ val = (imm16 << 0) & 0xffffffff; ] { export *[const]:8 val; }
+FullImm_movz32_imm: "#"^val is imm16 & aa_hw=1 [ val = (imm16 << 16) & 0xffffffff; ] { export *[const]:8 val; }
+
+FullImm_movz64_imm: "#"^val is imm16 & aa_hw [ val = imm16 << (aa_hw * 16); ] { export *[const]:8 val; }
+
+FullImm_movn32_imm: "#"^val is imm16 & aa_hw=0 [ val = ~(imm16 << 0) & 0xffffffff; ] { export *[const]:8 val; }
+FullImm_movn32_imm: "#"^val is imm16 & aa_hw=1 [ val = ~(imm16 << 16) & 0xffffffff; ] { export *[const]:8 val; }
+
+FullImm_movn64_imm: "#"^val is imm16 & aa_hw [ val = ~(imm16 << (aa_hw * 16)); ] { export *[const]:8 val; }
+
+FullImm_movk32_mask: mask is aa_hw [ mask = (~(0xffff << (aa_hw * 16))) & 0xffffffff; ] { export *[const]:4 mask; }
+FullImm_movk32_shift: tmp is imm16 & aa_hw [ tmp = (imm16 << (aa_hw * 16)) & 0xffffffff; ] { export *[const]:4 tmp; }
+FullImm_movk32_imm: "#"^imm16 is imm16 & aa_hw=0 { export *[const]:4 imm16; }
+FullImm_movk32_imm: "#"^imm16, "LSL #16" is imm16 & aa_hw=1 & FullImm_movk32_shift { export FullImm_movk32_shift; }
+
+FullImm_movk64_mask: mask is aa_hw [ mask = ~(0xffff << (aa_hw * 16)); ] { export *[const]:8 mask; }
+FullImm_movk64_shift: tmp is imm16 & aa_hw [ tmp = (imm16 << (aa_hw * 16)); ] { export *[const]:8 tmp; }
+FullImm_movk64_imm: "#"^imm16 is imm16 & aa_hw=0 { export *[const]:8 imm16; }
+FullImm_movk64_imm: "#"^imm16, "LSL #16" is imm16 & aa_hw=1 & FullImm_movk64_shift { export FullImm_movk64_shift; }
+FullImm_movk64_imm: "#"^imm16, "LSL #32" is imm16 & aa_hw=2 & FullImm_movk64_shift { export FullImm_movk64_shift; }
+FullImm_movk64_imm: "#"^imm16, "LSL #48" is imm16 & aa_hw=3 & FullImm_movk64_shift { export FullImm_movk64_shift; }
+
+# C6.2.221 MOV (inverted wide immediate) page C6-1669 line 98943 MATCH x12800000/mask=x7f800000
+# C6.2.226 MOVN page C6-1679 line 99388 MATCH x12800000/mask=x7f800000
+# CONSTRUCT x12800000/mask=xff800000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x12800000/mask=xff800000 --status pass
+
+:mov Rd_GPR32, FullImm_movn32_imm
+is sf=0 & opc=0 & b_2428=0x12 & b_2323=1 & FullImm_movn32_imm & Rd_GPR32 & Rd_GPR64
+{
+ # Special case MOVN
+ Rd_GPR64 = FullImm_movn32_imm;
+}
+
+# C6.2.221 MOV (inverted wide immediate) page C6-1669 line 98943 MATCH x12800000/mask=x7f800000
+# C6.2.226 MOVN page C6-1679 line 99388 MATCH x12800000/mask=x7f800000
+# CONSTRUCT x92800000/mask=xff800000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x92800000/mask=xff800000 --status pass
+
+:mov Rd_GPR64, FullImm_movn64_imm
+is sf=1 & opc=0 & b_2428=0x12 & b_2323=1 & FullImm_movn64_imm & Rd_GPR64
+{
+ # Special case MOVN
+ Rd_GPR64 = FullImm_movn64_imm;
+}
+
+# C6.2.222 MOV (wide immediate) page C6-1671 line 99035 MATCH x52800000/mask=x7f800000
+# C6.2.227 MOVZ page C6-1681 line 99489 MATCH x52800000/mask=x7f800000
+# CONSTRUCT x52800000/mask=xff800000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x52800000/mask=xff800000 --status pass
+
+:mov Rd_GPR32, FullImm_movz32_imm
+is sf=0 & opc=2 & b_2428=0x12 & b_2323=1 & FullImm_movz32_imm & Rd_GPR32 & Rd_GPR64
+{
+ Rd_GPR64 = FullImm_movz32_imm;
+}
+
+# C6.2.222 MOV (wide immediate) page C6-1671 line 99035 MATCH x52800000/mask=x7f800000
+# C6.2.227 MOVZ page C6-1681 line 99489 MATCH x52800000/mask=x7f800000
+# CONSTRUCT xd2800000/mask=xff800000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd2800000/mask=xff800000 --status pass
+
+:mov Rd_GPR64, FullImm_movz64_imm
+is sf=1 & opc=2 & b_2428=0x12 & b_2323=1 & FullImm_movz64_imm & Rd_GPR64
+{
+ Rd_GPR64 = FullImm_movz64_imm;
+}
+
+# C6.2.223 MOV (bitmask immediate) page C6-1673 line 99125 MATCH x320003e0/mask=x7f8003e0
+# C6.2.240 ORR (immediate) page C6-1705 line 100779 MATCH x32000000/mask=x7f800000
+# CONSTRUCT x320003e0/mask=xffe0ffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x320003e0/mask=xffe0ffe0 --status pass
+
+:mov Rd_GPR32wsp, DecodeWMask32
+is sf=0 & opc=1 & b_2428=0x12 & b_2223=0 & N=0 & imm6=0 & DecodeWMask32 & aa_Xn=31 & Rd_GPR32wsp & Rd_GPR64xsp
+{
+ # special case ORR
+ tmp_1:4 = DecodeWMask32;
+ Rd_GPR64xsp = zext(tmp_1);
+}
+
+# C6.2.223 MOV (bitmask immediate) page C6-1673 line 99125 MATCH x320003e0/mask=x7f8003e0
+# C6.2.240 ORR (immediate) page C6-1705 line 100779 MATCH x32000000/mask=x7f800000
+# CONSTRUCT xb20003e0/mask=xffc0ffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xb20003e0/mask=xffc0ffe0 --status pass
+
+:mov Rd_GPR64xsp, DecodeWMask64
+is sf=1 & opc=1 & b_2428=0x12 & b_2223=0 & imm6=0 & DecodeWMask64 & aa_Xn=31 & Rd_GPR64xsp
+{
+ # special case of ORR
+ tmp_1:8 = DecodeWMask64;
+ Rd_GPR64xsp = tmp_1;
+}
+
+# C6.2.224 MOV (register) page C6-1675 line 99214 MATCH x2a0003e0/mask=x7fe0ffe0
+# C6.2.241 ORR (shifted register) page C6-1707 line 100882 MATCH x2a000000/mask=x7f200000
+# CONSTRUCT x2a0003e0/mask=xff2003e0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x2a0003e0/mask=xff2003e0 --status pass
+
+:mov Rd_GPR32, RegShift32Log
+is b_31=0 & b_2430=0b0101010 & b_21=0 & b_0509=0b11111 & RegShift32Log & Rd_GPR32 & Rd_GPR64
+{
+ # special case ORR
+ tmp_1:4 = RegShift32Log;
+ Rd_GPR64 = zext(tmp_1);
+}
+
+# C6.2.224 MOV (register) page C6-1675 line 99214 MATCH x2a0003e0/mask=x7fe0ffe0
+# C6.2.241 ORR (shifted register) page C6-1707 line 100882 MATCH x2a000000/mask=x7f200000
+# CONSTRUCT xaa0003e0/mask=xff2003e0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xaa0003e0/mask=xff2003e0 --status pass
+
+:mov Rd_GPR64, RegShift64Log
+is b_31=1 & b_2430=0b0101010 & b_21=0 & b_0509=0b11111 & RegShift64Log & Rd_GPR64
+{
+ # special case of ORR
+ tmp_1:8 = RegShift64Log;
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.225 MOVK page C6-1677 line 99301 MATCH x72800000/mask=x7f800000
+# CONSTRUCT x72800000/mask=xff800000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x72800000/mask=xff800000 --status pass
+
+:movk Rd_GPR32, FullImm_movk32_imm
+is sf=0 & opc=3 & b_2428=0x12 & b_2323=1 & FullImm_movk32_imm & Rd_GPR32 & Rd_GPR64 & FullImm_movk32_mask
+{
+ local tmp:4 = Rd_GPR32 & FullImm_movk32_mask;
+ tmp = tmp | FullImm_movk32_imm;
+ Rd_GPR64 = zext(tmp);
+}
+
+# C6.2.225 MOVK page C6-1677 line 99301 MATCH x72800000/mask=x7f800000
+# CONSTRUCT xf2800000/mask=xff800000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xf2800000/mask=xff800000 --status pass
+
+:movk Rd_GPR64, FullImm_movk64_imm
+is sf=1 & opc=3 & b_2428=0x12 & b_2323=1 & FullImm_movk64_imm & Rd_GPR64 & FullImm_movk64_mask
+{
+ Rd_GPR64 = Rd_GPR64 & FullImm_movk64_mask;
+ Rd_GPR64 = Rd_GPR64 | FullImm_movk64_imm;
+}
+
+# C6.2.173 MRS page C6-802 line 46877 MATCH KEEPWITH
+
+with : (l=0 | l=1) {
+CopReg: spsr_el1 is Op0=3 & Op1_uimm3=0 & CRn=4 & CRm=0 & Op2_uimm3=0 & spsr_el1 { export spsr_el1; }
+CopReg: elr_el1 is Op0=3 & Op1_uimm3=0 & CRn=4 & CRm=0 & Op2_uimm3=1 & elr_el1 { export elr_el1; }
+CopReg: sp_el0 is Op0=3 & Op1_uimm3=0 & CRn=4 & CRm=1 & Op2_uimm3=0 & sp_el0 { export sp_el0; }
+CopReg: spsel is Op0=3 & Op1_uimm3=0 & CRn=4 & CRm=2 & Op2_uimm3=0 & spsel { export spsel; }
+CopReg: daif is Op0=3 & Op1_uimm3=3 & CRn=4 & CRm=2 & Op2_uimm3=1 & daif { export daif; }
+CopReg: currentel is Op0=3 & Op1_uimm3=0 & CRn=4 & CRm=2 & Op2_uimm3=2 & currentel { export currentel; }
+CopReg: nzcv is Op0=3 & Op1_uimm3=3 & CRn=4 & CRm=2 & Op2_uimm3=0 & nzcv { export nzcv; }
+CopReg: fpcr is Op0=3 & Op1_uimm3=3 & CRn=4 & CRm=4 & Op2_uimm3=0 & fpcr { export fpcr; }
+CopReg: fpsr is Op0=3 & Op1_uimm3=3 & CRn=4 & CRm=4 & Op2_uimm3=1 & fpsr { export fpsr; }
+CopReg: dspsr_el0 is Op0=3 & Op1_uimm3=3 & CRn=4 & CRm=5 & Op2_uimm3=0 & dspsr_el0 { export dspsr_el0; }
+CopReg: dlr_el0 is Op0=3 & Op1_uimm3=3 & CRn=4 & CRm=5 & Op2_uimm3=1 & dlr_el0 { export dlr_el0; }
+CopReg: spsr_el2 is Op0=3 & Op1_uimm3=4 & CRn=4 & CRm=0 & Op2_uimm3=0 & spsr_el2 { export spsr_el2; }
+CopReg: elr_el2 is Op0=3 & Op1_uimm3=4 & CRn=4 & CRm=0 & Op2_uimm3=1 & elr_el2 { export elr_el2; }
+CopReg: sp_el1 is Op0=3 & Op1_uimm3=4 & CRn=4 & CRm=1 & Op2_uimm3=0 & sp_el1 { export sp_el1; }
+CopReg: spsr_irq is Op0=3 & Op1_uimm3=4 & CRn=4 & CRm=3 & Op2_uimm3=0 & spsr_irq { export spsr_irq; }
+CopReg: spsr_abt is Op0=3 & Op1_uimm3=4 & CRn=4 & CRm=3 & Op2_uimm3=1 & spsr_abt { export spsr_abt; }
+CopReg: spsr_und is Op0=3 & Op1_uimm3=4 & CRn=4 & CRm=3 & Op2_uimm3=2 & spsr_und { export spsr_und; }
+CopReg: spsr_fiq is Op0=3 & Op1_uimm3=4 & CRn=4 & CRm=3 & Op2_uimm3=3 & spsr_fiq { export spsr_fiq; }
+CopReg: spsr_el3 is Op0=3 & Op1_uimm3=6 & CRn=4 & CRm=0 & Op2_uimm3=0 & spsr_el3 { export spsr_el3; }
+CopReg: elr_el3 is Op0=3 & Op1_uimm3=6 & CRn=4 & CRm=0 & Op2_uimm3=1 & elr_el3 { export elr_el3; }
+CopReg: sp_el2 is Op0=3 & Op1_uimm3=6 & CRn=4 & CRm=1 & Op2_uimm3=0 & sp_el2 { export sp_el2; }
+# CopReg: spsr_svc is Op0=3 & Op1_uimm3=0 & CRn=4 & CRm=0 & Op2_uimm3=0 & spsr_svc { export spsr_svc; }
+# CopReg: spsr_hyp is Op0=3 & Op1_uimm3=4 & CRn=4 & CRm=0 & Op2_uimm3=0 & spsr_hyp { export spsr_hyp; }
+
+CopReg: midr_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=0 & Op2_uimm3=0 & midr_el1 { export midr_el1; }
+CopReg: mpidr_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=0 & Op2_uimm3=5 & mpidr_el1 { export mpidr_el1; }
+CopReg: revidr_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=0 & Op2_uimm3=6 & revidr_el1 { export revidr_el1; }
+CopReg: id_dfr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=2 & id_dfr0_el1 { export id_dfr0_el1; }
+CopReg: id_pfr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=0 & id_pfr0_el1 { export id_pfr0_el1; }
+CopReg: id_pfr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=1 & id_pfr1_el1 { export id_pfr1_el1; }
+CopReg: id_afr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=3 & id_afr0_el1 { export id_afr0_el1; }
+CopReg: id_mmfr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=4 & id_mmfr0_el1 { export id_mmfr0_el1; }
+CopReg: id_mmfr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=5 & id_mmfr1_el1 { export id_mmfr1_el1; }
+CopReg: id_mmfr2_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=6 & id_mmfr2_el1 { export id_mmfr2_el1; }
+CopReg: id_mmfr3_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=7 & id_mmfr3_el1 { export id_mmfr3_el1; }
+CopReg: id_isar0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=0 & id_isar0_el1 { export id_isar0_el1; }
+CopReg: id_isar1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=1 & id_isar1_el1 { export id_isar1_el1; }
+CopReg: id_isar2_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=2 & id_isar2_el1 { export id_isar2_el1; }
+CopReg: id_isar3_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=3 & id_isar3_el1 { export id_isar3_el1; }
+CopReg: id_isar4_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=4 & id_isar4_el1 { export id_isar4_el1; }
+CopReg: id_isar5_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=5 & id_isar5_el1 { export id_isar5_el1; }
+CopReg: mvfr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=3 & Op2_uimm3=0 & mvfr0_el1 { export mvfr0_el1; }
+CopReg: mvfr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=3 & Op2_uimm3=1 & mvfr1_el1 { export mvfr1_el1; }
+CopReg: mvfr2_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=3 & Op2_uimm3=2 & mvfr2_el1 { export mvfr2_el1; }
+CopReg: ccsidr_el1 is Op0=3 & Op1_uimm3=1 & CRn=0 & CRm=0 & Op2_uimm3=0 & ccsidr_el1 { export ccsidr_el1; }
+CopReg: id_aa64pfr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=4 & Op2_uimm3=0 & id_aa64pfr0_el1 { export id_aa64pfr0_el1; }
+CopReg: id_aa64pfr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=4 & Op2_uimm3=1 & id_aa64pfr1_el1 { export id_aa64pfr1_el1; }
+CopReg: id_aa64dfr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=5 & Op2_uimm3=0 & id_aa64dfr0_el1 { export id_aa64dfr0_el1; }
+CopReg: id_aa64dfr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=5 & Op2_uimm3=1 & id_aa64dfr1_el1 { export id_aa64dfr1_el1; }
+CopReg: id_aa64isar0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=6 & Op2_uimm3=0 & id_aa64isar0_el1 { export id_aa64isar0_el1; }
+CopReg: id_aa64isar1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=6 & Op2_uimm3=1 & id_aa64isar1_el1 { export id_aa64isar1_el1; }
+CopReg: id_aa64mmfr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=7 & Op2_uimm3=0 & id_aa64mmfr0_el1 { export id_aa64mmfr0_el1; }
+CopReg: id_aa64mmfr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=7 & Op2_uimm3=1 & id_aa64mmfr1_el1 { export id_aa64mmfr1_el1; }
+CopReg: id_aa64afr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=5 & Op2_uimm3=4 & id_aa64afr0_el1 { export id_aa64afr0_el1; }
+CopReg: id_aa64afr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=5 & Op2_uimm3=5 & id_aa64afr1_el1 { export id_aa64afr1_el1; }
+CopReg: clidr_el1 is Op0=3 & Op1_uimm3=1 & CRn=0 & CRm=0 & Op2_uimm3=1 & clidr_el1 { export clidr_el1; }
+CopReg: aidr_el1 is Op0=3 & Op1_uimm3=1 & CRn=0 & CRm=0 & Op2_uimm3=7 & aidr_el1 { export aidr_el1; }
+CopReg: csselr_el1 is Op0=3 & Op1_uimm3=2 & CRn=0 & CRm=0 & Op2_uimm3=0 & csselr_el1 { export csselr_el1; }
+CopReg: ctr_el0 is Op0=3 & Op1_uimm3=3 & CRn=0 & CRm=0 & Op2_uimm3=1 & ctr_el0 { export ctr_el0; }
+CopReg: dczid_el0 is Op0=3 & Op1_uimm3=3 & CRn=0 & CRm=0 & Op2_uimm3=7 & dczid_el0 { export dczid_el0; }
+CopReg: vpidr_el2 is Op0=3 & Op1_uimm3=4 & CRn=0 & CRm=0 & Op2_uimm3=0 & vpidr_el2 { export vpidr_el2; }
+CopReg: vmpidr_el2 is Op0=3 & Op1_uimm3=4 & CRn=0 & CRm=0 & Op2_uimm3=5 & vmpidr_el2 { export vmpidr_el2; }
+CopReg: sctlr_el1 is Op0=3 & Op1_uimm3=0 & CRn=1 & CRm=0 & Op2_uimm3=0 & sctlr_el1 { export sctlr_el1; }
+CopReg: actlr_el1 is Op0=3 & Op1_uimm3=0 & CRn=1 & CRm=0 & Op2_uimm3=1 & actlr_el1 { export actlr_el1; }
+CopReg: cpacr_el1 is Op0=3 & Op1_uimm3=0 & CRn=1 & CRm=0 & Op2_uimm3=2 & cpacr_el1 { export cpacr_el1; }
+CopReg: sctlr_el2 is Op0=3 & Op1_uimm3=4 & CRn=1 & CRm=0 & Op2_uimm3=0 & sctlr_el2 { export sctlr_el2; }
+CopReg: actlr_el2 is Op0=3 & Op1_uimm3=4 & CRn=1 & CRm=0 & Op2_uimm3=1 & actlr_el2 { export actlr_el2; }
+CopReg: hcr_el2 is Op0=3 & Op1_uimm3=4 & CRn=1 & CRm=1 & Op2_uimm3=0 & hcr_el2 { export hcr_el2; }
+CopReg: mdcr_el2 is Op0=3 & Op1_uimm3=4 & CRn=1 & CRm=1 & Op2_uimm3=1 & mdcr_el2 { export mdcr_el2; }
+CopReg: cptr_el2 is Op0=3 & Op1_uimm3=4 & CRn=1 & CRm=1 & Op2_uimm3=2 & cptr_el2 { export cptr_el2; }
+CopReg: hstr_el2 is Op0=3 & Op1_uimm3=4 & CRn=1 & CRm=1 & Op2_uimm3=3 & hstr_el2 { export hstr_el2; }
+CopReg: hacr_el2 is Op0=3 & Op1_uimm3=4 & CRn=1 & CRm=1 & Op2_uimm3=7 & hacr_el2 { export hacr_el2; }
+CopReg: sctlr_el3 is Op0=3 & Op1_uimm3=6 & CRn=1 & CRm=0 & Op2_uimm3=0 & sctlr_el3 { export sctlr_el3; }
+CopReg: actlr_el3 is Op0=3 & Op1_uimm3=6 & CRn=1 & CRm=0 & Op2_uimm3=1 & actlr_el3 { export actlr_el3; }
+CopReg: scr_el3 is Op0=3 & Op1_uimm3=6 & CRn=1 & CRm=1 & Op2_uimm3=0 & scr_el3 { export scr_el3; }
+CopReg: cptr_el3 is Op0=3 & Op1_uimm3=6 & CRn=1 & CRm=1 & Op2_uimm3=2 & cptr_el3 { export cptr_el3; }
+CopReg: mdcr_el3 is Op0=3 & Op1_uimm3=6 & CRn=1 & CRm=3 & Op2_uimm3=1 & mdcr_el3 { export mdcr_el3; }
+CopReg: ttbr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=2 & CRm=0 & Op2_uimm3=0 & ttbr0_el1 { export ttbr0_el1; }
+CopReg: ttbr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=2 & CRm=0 & Op2_uimm3=1 & ttbr1_el1 { export ttbr1_el1; }
+CopReg: ttbr0_el2 is Op0=3 & Op1_uimm3=4 & CRn=2 & CRm=0 & Op2_uimm3=0 & ttbr0_el2 { export ttbr0_el2; }
+CopReg: ttbr0_el3 is Op0=3 & Op1_uimm3=6 & CRn=2 & CRm=0 & Op2_uimm3=0 & ttbr0_el3 { export ttbr0_el3; }
+CopReg: vttbr_el2 is Op0=3 & Op1_uimm3=4 & CRn=2 & CRm=1 & Op2_uimm3=0 & vttbr_el2 { export vttbr_el2; }
+CopReg: tcr_el1 is Op0=3 & Op1_uimm3=0 & CRn=2 & CRm=0 & Op2_uimm3=2 & tcr_el1 { export tcr_el1; }
+CopReg: tcr_el2 is Op0=3 & Op1_uimm3=4 & CRn=2 & CRm=0 & Op2_uimm3=2 & tcr_el2 { export tcr_el2; }
+CopReg: tcr_el3 is Op0=3 & Op1_uimm3=6 & CRn=2 & CRm=0 & Op2_uimm3=2 & tcr_el3 { export tcr_el3; }
+CopReg: vtcr_el2 is Op0=3 & Op1_uimm3=4 & CRn=2 & CRm=1 & Op2_uimm3=2 & vtcr_el2 { export vtcr_el2; }
+CopReg: afsr0_el1 is Op0=3 & Op1_uimm3=0 & CRn=5 & CRm=1 & Op2_uimm3=0 & afsr0_el1 { export afsr0_el1; }
+CopReg: afsr1_el1 is Op0=3 & Op1_uimm3=0 & CRn=5 & CRm=1 & Op2_uimm3=1 & afsr1_el1 { export afsr1_el1; }
+CopReg: afsr0_el2 is Op0=3 & Op1_uimm3=4 & CRn=5 & CRm=1 & Op2_uimm3=0 & afsr0_el2 { export afsr0_el2; }
+CopReg: afsr1_el2 is Op0=3 & Op1_uimm3=4 & CRn=5 & CRm=1 & Op2_uimm3=1 & afsr1_el2 { export afsr1_el2; }
+CopReg: afsr0_el3 is Op0=3 & Op1_uimm3=6 & CRn=5 & CRm=1 & Op2_uimm3=0 & afsr0_el3 { export afsr0_el3; }
+CopReg: afsr1_el3 is Op0=3 & Op1_uimm3=6 & CRn=5 & CRm=1 & Op2_uimm3=1 & afsr1_el3 { export afsr1_el3; }
+CopReg: esr_el1 is Op0=3 & Op1_uimm3=0 & CRn=5 & CRm=2 & Op2_uimm3=0 & esr_el1 { export esr_el1; }
+CopReg: esr_el2 is Op0=3 & Op1_uimm3=4 & CRn=5 & CRm=2 & Op2_uimm3=0 & esr_el2 { export esr_el2; }
+CopReg: esr_el3 is Op0=3 & Op1_uimm3=6 & CRn=5 & CRm=2 & Op2_uimm3=0 & esr_el3 { export esr_el3; }
+CopReg: fpexc32_el2 is Op0=3 & Op1_uimm3=4 & CRn=5 & CRm=3 & Op2_uimm3=0 & fpexc32_el2 { export fpexc32_el2; }
+CopReg: far_el1 is Op0=3 & Op1_uimm3=0 & CRn=6 & CRm=0 & Op2_uimm3=0 & far_el1 { export far_el1; }
+CopReg: far_el2 is Op0=3 & Op1_uimm3=4 & CRn=6 & CRm=0 & Op2_uimm3=0 & far_el2 { export far_el2; }
+CopReg: far_el3 is Op0=3 & Op1_uimm3=6 & CRn=6 & CRm=0 & Op2_uimm3=0 & far_el3 { export far_el3; }
+CopReg: hpfar_el2 is Op0=3 & Op1_uimm3=4 & CRn=6 & CRm=0 & Op2_uimm3=4 & hpfar_el2 { export hpfar_el2; }
+CopReg: par_el1 is Op0=3 & Op1_uimm3=0 & CRn=7 & CRm=4 & Op2_uimm3=0 & par_el1 { export par_el1; }
+CopReg: pmintenset_el1 is Op0=3 & Op1_uimm3=0 & CRn=9 & CRm=14 & Op2_uimm3=1 & pmintenset_el1 { export pmintenset_el1; }
+CopReg: pmintenclr_el1 is Op0=3 & Op1_uimm3=0 & CRn=9 & CRm=14 & Op2_uimm3=2 & pmintenclr_el1 { export pmintenclr_el1; }
+CopReg: pmcr_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=12 & Op2_uimm3=0 & pmcr_el0 { export pmcr_el0; }
+CopReg: pmcntenset_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=12 & Op2_uimm3=1 & pmcntenset_el0 { export pmcntenset_el0; }
+CopReg: pmcntenclr_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=12 & Op2_uimm3=2 & pmcntenclr_el0 { export pmcntenclr_el0; }
+CopReg: pmovsclr_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=12 & Op2_uimm3=3 & pmovsclr_el0 { export pmovsclr_el0; }
+CopReg: pmswinc_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=12 & Op2_uimm3=4 & pmswinc_el0 { export pmswinc_el0; }
+CopReg: pmselr_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=12 & Op2_uimm3=5 & pmselr_el0 { export pmselr_el0; }
+CopReg: pmceid0_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=12 & Op2_uimm3=6 & pmceid0_el0 { export pmceid0_el0; }
+CopReg: pmceid1_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=12 & Op2_uimm3=7 & pmceid1_el0 { export pmceid1_el0; }
+CopReg: pmccntr_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=13 & Op2_uimm3=0 & pmccntr_el0 { export pmccntr_el0; }
+CopReg: pmxevtyper_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=13 & Op2_uimm3=1 & pmxevtyper_el0 { export pmxevtyper_el0; }
+CopReg: pmxevcntr_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=13 & Op2_uimm3=2 & pmxevcntr_el0 { export pmxevcntr_el0; }
+CopReg: pmuserenr_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=14 & Op2_uimm3=0 & pmuserenr_el0 { export pmuserenr_el0; }
+CopReg: pmovsset_el0 is Op0=3 & Op1_uimm3=3 & CRn=9 & CRm=14 & Op2_uimm3=3 & pmovsset_el0 { export pmovsset_el0; }
+CopReg: pmevcntr0_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=8 & Op2_uimm3=0 & pmevcntr0_el0 { export pmevcntr0_el0; }
+CopReg: pmevcntr1_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=8 & Op2_uimm3=1 & pmevcntr1_el0 { export pmevcntr1_el0; }
+CopReg: pmevcntr2_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=8 & Op2_uimm3=2 & pmevcntr2_el0 { export pmevcntr2_el0; }
+CopReg: pmevcntr3_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=8 & Op2_uimm3=3 & pmevcntr3_el0 { export pmevcntr3_el0; }
+CopReg: pmevcntr4_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=8 & Op2_uimm3=4 & pmevcntr4_el0 { export pmevcntr4_el0; }
+CopReg: pmevcntr5_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=8 & Op2_uimm3=5 & pmevcntr5_el0 { export pmevcntr5_el0; }
+CopReg: pmevcntr6_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=8 & Op2_uimm3=6 & pmevcntr6_el0 { export pmevcntr6_el0; }
+CopReg: pmevcntr7_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=8 & Op2_uimm3=7 & pmevcntr7_el0 { export pmevcntr7_el0; }
+CopReg: pmevcntr8_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=9 & Op2_uimm3=0 & pmevcntr8_el0 { export pmevcntr8_el0; }
+CopReg: pmevcntr9_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=9 & Op2_uimm3=1 & pmevcntr9_el0 { export pmevcntr9_el0; }
+CopReg: pmevcntr10_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=9 & Op2_uimm3=2 & pmevcntr10_el0 { export pmevcntr10_el0; }
+CopReg: pmevcntr11_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=9 & Op2_uimm3=3 & pmevcntr11_el0 { export pmevcntr11_el0; }
+CopReg: pmevcntr12_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=9 & Op2_uimm3=4 & pmevcntr12_el0 { export pmevcntr12_el0; }
+CopReg: pmevcntr13_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=9 & Op2_uimm3=5 & pmevcntr13_el0 { export pmevcntr13_el0; }
+CopReg: pmevcntr14_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=9 & Op2_uimm3=6 & pmevcntr14_el0 { export pmevcntr14_el0; }
+CopReg: pmevcntr15_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=9 & Op2_uimm3=7 & pmevcntr15_el0 { export pmevcntr15_el0; }
+CopReg: pmevcntr16_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=10 & Op2_uimm3=0 & pmevcntr16_el0 { export pmevcntr16_el0; }
+CopReg: pmevcntr17_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=10 & Op2_uimm3=1 & pmevcntr17_el0 { export pmevcntr17_el0; }
+CopReg: pmevcntr18_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=10 & Op2_uimm3=2 & pmevcntr18_el0 { export pmevcntr18_el0; }
+CopReg: pmevcntr19_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=10 & Op2_uimm3=3 & pmevcntr19_el0 { export pmevcntr19_el0; }
+CopReg: pmevcntr20_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=10 & Op2_uimm3=4 & pmevcntr20_el0 { export pmevcntr20_el0; }
+CopReg: pmevcntr21_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=10 & Op2_uimm3=5 & pmevcntr21_el0 { export pmevcntr21_el0; }
+CopReg: pmevcntr22_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=10 & Op2_uimm3=6 & pmevcntr22_el0 { export pmevcntr22_el0; }
+CopReg: pmevcntr23_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=10 & Op2_uimm3=7 & pmevcntr23_el0 { export pmevcntr23_el0; }
+CopReg: pmevcntr24_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=11 & Op2_uimm3=0 & pmevcntr24_el0 { export pmevcntr24_el0; }
+CopReg: pmevcntr25_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=11 & Op2_uimm3=1 & pmevcntr25_el0 { export pmevcntr25_el0; }
+CopReg: pmevcntr26_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=11 & Op2_uimm3=2 & pmevcntr26_el0 { export pmevcntr26_el0; }
+CopReg: pmevcntr27_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=11 & Op2_uimm3=3 & pmevcntr27_el0 { export pmevcntr27_el0; }
+CopReg: pmevcntr28_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=11 & Op2_uimm3=4 & pmevcntr28_el0 { export pmevcntr28_el0; }
+CopReg: pmevcntr29_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=11 & Op2_uimm3=5 & pmevcntr29_el0 { export pmevcntr29_el0; }
+CopReg: pmevcntr30_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=11 & Op2_uimm3=6 & pmevcntr30_el0 { export pmevcntr30_el0; }
+CopReg: pmevtyper0_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=12 & Op2_uimm3=0 & pmevtyper0_el0 { export pmevtyper0_el0; }
+CopReg: pmevtyper1_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=12 & Op2_uimm3=1 & pmevtyper1_el0 { export pmevtyper1_el0; }
+CopReg: pmevtyper2_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=12 & Op2_uimm3=2 & pmevtyper2_el0 { export pmevtyper2_el0; }
+CopReg: pmevtyper3_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=12 & Op2_uimm3=3 & pmevtyper3_el0 { export pmevtyper3_el0; }
+CopReg: pmevtyper4_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=12 & Op2_uimm3=4 & pmevtyper4_el0 { export pmevtyper4_el0; }
+CopReg: pmevtyper5_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=12 & Op2_uimm3=5 & pmevtyper5_el0 { export pmevtyper5_el0; }
+CopReg: pmevtyper6_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=12 & Op2_uimm3=6 & pmevtyper6_el0 { export pmevtyper6_el0; }
+CopReg: pmevtyper7_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=12 & Op2_uimm3=7 & pmevtyper7_el0 { export pmevtyper7_el0; }
+CopReg: pmevtyper8_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=13 & Op2_uimm3=0 & pmevtyper8_el0 { export pmevtyper8_el0; }
+CopReg: pmevtyper9_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=13 & Op2_uimm3=1 & pmevtyper9_el0 { export pmevtyper9_el0; }
+CopReg: pmevtyper10_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=13 & Op2_uimm3=2 & pmevtyper10_el0 { export pmevtyper10_el0; }
+CopReg: pmevtyper11_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=13 & Op2_uimm3=3 & pmevtyper11_el0 { export pmevtyper11_el0; }
+CopReg: pmevtyper12_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=13 & Op2_uimm3=4 & pmevtyper12_el0 { export pmevtyper12_el0; }
+CopReg: pmevtyper13_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=13 & Op2_uimm3=5 & pmevtyper13_el0 { export pmevtyper13_el0; }
+CopReg: pmevtyper14_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=13 & Op2_uimm3=6 & pmevtyper14_el0 { export pmevtyper14_el0; }
+CopReg: pmevtyper15_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=13 & Op2_uimm3=7 & pmevtyper15_el0 { export pmevtyper15_el0; }
+CopReg: pmevtyper16_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=14 & Op2_uimm3=0 & pmevtyper16_el0 { export pmevtyper16_el0; }
+CopReg: pmevtyper17_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=14 & Op2_uimm3=1 & pmevtyper17_el0 { export pmevtyper17_el0; }
+CopReg: pmevtyper18_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=14 & Op2_uimm3=2 & pmevtyper18_el0 { export pmevtyper18_el0; }
+CopReg: pmevtyper19_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=14 & Op2_uimm3=3 & pmevtyper19_el0 { export pmevtyper19_el0; }
+CopReg: pmevtyper20_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=14 & Op2_uimm3=4 & pmevtyper20_el0 { export pmevtyper20_el0; }
+CopReg: pmevtyper21_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=14 & Op2_uimm3=5 & pmevtyper21_el0 { export pmevtyper21_el0; }
+CopReg: pmevtyper22_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=14 & Op2_uimm3=6 & pmevtyper22_el0 { export pmevtyper22_el0; }
+CopReg: pmevtyper23_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=14 & Op2_uimm3=7 & pmevtyper23_el0 { export pmevtyper23_el0; }
+CopReg: pmevtyper24_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=15 & Op2_uimm3=0 & pmevtyper24_el0 { export pmevtyper24_el0; }
+CopReg: pmevtyper25_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=15 & Op2_uimm3=1 & pmevtyper25_el0 { export pmevtyper25_el0; }
+CopReg: pmevtyper26_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=15 & Op2_uimm3=2 & pmevtyper26_el0 { export pmevtyper26_el0; }
+CopReg: pmevtyper27_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=15 & Op2_uimm3=3 & pmevtyper27_el0 { export pmevtyper27_el0; }
+CopReg: pmevtyper28_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=15 & Op2_uimm3=4 & pmevtyper28_el0 { export pmevtyper28_el0; }
+CopReg: pmevtyper29_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=15 & Op2_uimm3=5 & pmevtyper29_el0 { export pmevtyper29_el0; }
+CopReg: pmevtyper30_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=15 & Op2_uimm3=6 & pmevtyper30_el0 { export pmevtyper30_el0; }
+CopReg: pmccfiltr_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=15 & Op2_uimm3=7 & pmccfiltr_el0 { export pmccfiltr_el0; }
+CopReg: mair_el1 is Op0=3 & Op1_uimm3=0 & CRn=10 & CRm=2 & Op2_uimm3=0 & mair_el1 { export mair_el1; }
+CopReg: mair_el2 is Op0=3 & Op1_uimm3=4 & CRn=10 & CRm=2 & Op2_uimm3=0 & mair_el2 { export mair_el2; }
+CopReg: mair_el3 is Op0=3 & Op1_uimm3=6 & CRn=10 & CRm=2 & Op2_uimm3=0 & mair_el3 { export mair_el3; }
+CopReg: amair_el1 is Op0=3 & Op1_uimm3=0 & CRn=10 & CRm=3 & Op2_uimm3=0 & amair_el1 { export amair_el1; }
+CopReg: amair_el2 is Op0=3 & Op1_uimm3=4 & CRn=10 & CRm=3 & Op2_uimm3=0 & amair_el2 { export amair_el2; }
+CopReg: amair_el3 is Op0=3 & Op1_uimm3=6 & CRn=10 & CRm=3 & Op2_uimm3=0 & amair_el3 { export amair_el3; }
+CopReg: vbar_el1 is Op0=3 & Op1_uimm3=0 & CRn=12 & CRm=0 & Op2_uimm3=0 & vbar_el1 { export vbar_el1; }
+CopReg: vbar_el2 is Op0=3 & Op1_uimm3=4 & CRn=12 & CRm=0 & Op2_uimm3=0 & vbar_el2 { export vbar_el2; }
+CopReg: vbar_el3 is Op0=3 & Op1_uimm3=6 & CRn=12 & CRm=0 & Op2_uimm3=0 & vbar_el3 { export vbar_el3; }
+CopReg: rvbar_el1 is Op0=3 & Op1_uimm3=0 & CRn=12 & CRm=0 & Op2_uimm3=1 & rvbar_el1 { export rvbar_el1; }
+CopReg: rvbar_el2 is Op0=3 & Op1_uimm3=4 & CRn=12 & CRm=0 & Op2_uimm3=1 & rvbar_el2 { export rvbar_el2; }
+CopReg: rvbar_el3 is Op0=3 & Op1_uimm3=6 & CRn=12 & CRm=0 & Op2_uimm3=1 & rvbar_el3 { export rvbar_el3; }
+CopReg: rmr_el1 is Op0=3 & Op1_uimm3=0 & CRn=12 & CRm=0 & Op2_uimm3=2 & rmr_el1 { export rmr_el1; }
+CopReg: rmr_el2 is Op0=3 & Op1_uimm3=4 & CRn=12 & CRm=0 & Op2_uimm3=2 & rmr_el2 { export rmr_el2; }
+CopReg: rmr_el3 is Op0=3 & Op1_uimm3=6 & CRn=12 & CRm=0 & Op2_uimm3=2 & rmr_el3 { export rmr_el3; }
+CopReg: isr_el1 is Op0=3 & Op1_uimm3=0 & CRn=12 & CRm=1 & Op2_uimm3=0 & isr_el1 { export isr_el1; }
+CopReg: contextidr_el1 is Op0=3 & Op1_uimm3=0 & CRn=13 & CRm=0 & Op2_uimm3=1 & contextidr_el1 { export contextidr_el1; }
+CopReg: tpidr_el0 is Op0=3 & Op1_uimm3=3 & CRn=13 & CRm=0 & Op2_uimm3=2 & tpidr_el0 { export tpidr_el0; }
+CopReg: tpidrro_el0 is Op0=3 & Op1_uimm3=3 & CRn=13 & CRm=0 & Op2_uimm3=3 & tpidrro_el0 { export tpidrro_el0; }
+CopReg: tpidr_el1 is Op0=3 & Op1_uimm3=0 & CRn=13 & CRm=0 & Op2_uimm3=4 & tpidr_el1 { export tpidr_el1; }
+CopReg: tpidr_el2 is Op0=3 & Op1_uimm3=4 & CRn=13 & CRm=0 & Op2_uimm3=2 & tpidr_el2 { export tpidr_el2; }
+CopReg: tpidr_el3 is Op0=3 & Op1_uimm3=6 & CRn=13 & CRm=0 & Op2_uimm3=2 & tpidr_el3 { export tpidr_el3; }
+CopReg: teecr32_el1 is Op0=2 & Op1_uimm3=2 & CRn=0 & CRm=0 & Op2_uimm3=0 & teecr32_el1 { export teecr32_el1; }
+CopReg: cntfrq_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=0 & Op2_uimm3=0 & cntfrq_el0 { export cntfrq_el0; }
+CopReg: cntpct_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=0 & Op2_uimm3=1 & cntpct_el0 { export cntpct_el0; }
+CopReg: cntvct_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=0 & Op2_uimm3=2 & cntvct_el0 { export cntvct_el0; }
+CopReg: cntvoff_el2 is Op0=3 & Op1_uimm3=4 & CRn=14 & CRm=0 & Op2_uimm3=3 & cntvoff_el2 { export cntvoff_el2; }
+CopReg: cntkctl_el1 is Op0=3 & Op1_uimm3=0 & CRn=14 & CRm=1 & Op2_uimm3=0 & cntkctl_el1 { export cntkctl_el1; }
+CopReg: cnthctl_el2 is Op0=3 & Op1_uimm3=4 & CRn=14 & CRm=1 & Op2_uimm3=0 & cnthctl_el2 { export cnthctl_el2; }
+CopReg: cntp_tval_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=2 & Op2_uimm3=0 & cntp_tval_el0 { export cntp_tval_el0; }
+CopReg: cntp_ctl_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=2 & Op2_uimm3=1 & cntp_ctl_el0 { export cntp_ctl_el0; }
+CopReg: cntp_cval_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=2 & Op2_uimm3=2 & cntp_cval_el0 { export cntp_cval_el0; }
+CopReg: cntv_tval_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=3 & Op2_uimm3=0 & cntv_tval_el0 { export cntv_tval_el0; }
+CopReg: cntv_ctl_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=3 & Op2_uimm3=1 & cntv_ctl_el0 { export cntv_ctl_el0; }
+CopReg: cntv_cval_el0 is Op0=3 & Op1_uimm3=3 & CRn=14 & CRm=3 & Op2_uimm3=2 & cntv_cval_el0 { export cntv_cval_el0; }
+CopReg: cnthp_tval_el2 is Op0=3 & Op1_uimm3=4 & CRn=14 & CRm=2 & Op2_uimm3=0 & cnthp_tval_el2 { export cnthp_tval_el2; }
+CopReg: cnthp_ctl_el2 is Op0=3 & Op1_uimm3=4 & CRn=14 & CRm=2 & Op2_uimm3=1 & cnthp_ctl_el2 { export cnthp_ctl_el2; }
+CopReg: cnthp_cval_el2 is Op0=3 & Op1_uimm3=4 & CRn=14 & CRm=2 & Op2_uimm3=2 & cnthp_cval_el2 { export cnthp_cval_el2; }
+CopReg: cntps_tval_el1 is Op0=3 & Op1_uimm3=7 & CRn=14 & CRm=2 & Op2_uimm3=0 & cntps_tval_el1 { export cntps_tval_el1; }
+CopReg: cntps_ctl_el1 is Op0=3 & Op1_uimm3=7 & CRn=14 & CRm=2 & Op2_uimm3=1 & cntps_ctl_el1 { export cntps_ctl_el1; }
+CopReg: cntps_cval_el1 is Op0=3 & Op1_uimm3=7 & CRn=14 & CRm=2 & Op2_uimm3=2 & cntps_cval_el1 { export cntps_cval_el1; }
+CopReg: dacr32_el2 is Op0=3 & Op1_uimm3=4 & CRn=3 & CRm=0 & Op2_uimm3=0 & dacr32_el2 { export dacr32_el2; }
+CopReg: ifsr32_el2 is Op0=3 & Op1_uimm3=4 & CRn=5 & CRm=0 & Op2_uimm3=1 & ifsr32_el2 { export ifsr32_el2; }
+CopReg: teehbr32_el1 is Op0=2 & Op1_uimm3=2 & CRn=1 & CRm=0 & Op2_uimm3=0 & teehbr32_el1 { export teehbr32_el1; }
+CopReg: sder32_el3 is Op0=3 & Op1_uimm3=6 & CRn=1 & CRm=1 & Op2_uimm3=1 & sder32_el3 { export sder32_el3; }
+CopReg: osdtrrx_el1 is Op0=3 & Op1_uimm3=0 & CRn=0 & CRm=0 & Op2_uimm3=2 & osdtrrx_el1 { export osdtrrx_el1; }
+
+CopReg: mdccint_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=0 & mdccint_el1 { export mdccint_el1; }
+CopReg: mdscr_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=2 & mdscr_el1 { export mdscr_el1; }
+CopReg: osdtrtx_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=3 & Op2_uimm3=2 & osdtrtx_el1 { export osdtrtx_el1; }
+CopReg: oseccr_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=6 & Op2_uimm3=2 & oseccr_el1 { export oseccr_el1; }
+CopReg: dbgbvr0_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=0 & Op2_uimm3=4 & dbgbvr0_el1 { export dbgbvr0_el1; }
+CopReg: dbgbvr1_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=4 & dbgbvr1_el1 { export dbgbvr1_el1; }
+CopReg: dbgbvr2_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=4 & dbgbvr2_el1 { export dbgbvr2_el1; }
+CopReg: dbgbvr3_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=3 & Op2_uimm3=4 & dbgbvr3_el1 { export dbgbvr3_el1; }
+CopReg: dbgbvr4_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=4 & Op2_uimm3=4 & dbgbvr4_el1 { export dbgbvr4_el1; }
+CopReg: dbgbvr5_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=5 & Op2_uimm3=4 & dbgbvr5_el1 { export dbgbvr5_el1; }
+CopReg: dbgbvr6_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=6 & Op2_uimm3=4 & dbgbvr6_el1 { export dbgbvr6_el1; }
+CopReg: dbgbvr7_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=7 & Op2_uimm3=4 & dbgbvr7_el1 { export dbgbvr7_el1; }
+CopReg: dbgbvr8_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=8 & Op2_uimm3=4 & dbgbvr8_el1 { export dbgbvr8_el1; }
+CopReg: dbgbvr9_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=9 & Op2_uimm3=4 & dbgbvr9_el1 { export dbgbvr9_el1; }
+CopReg: dbgbvr10_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=10 & Op2_uimm3=4 & dbgbvr10_el1 { export dbgbvr10_el1; }
+CopReg: dbgbvr11_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=11 & Op2_uimm3=4 & dbgbvr11_el1 { export dbgbvr11_el1; }
+CopReg: dbgbvr12_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=12 & Op2_uimm3=4 & dbgbvr12_el1 { export dbgbvr12_el1; }
+CopReg: dbgbvr13_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=13 & Op2_uimm3=4 & dbgbvr13_el1 { export dbgbvr13_el1; }
+CopReg: dbgbvr14_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=14 & Op2_uimm3=4 & dbgbvr14_el1 { export dbgbvr14_el1; }
+CopReg: dbgbvr15_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=15 & Op2_uimm3=4 & dbgbvr15_el1 { export dbgbvr15_el1; }
+CopReg: dbgbcr0_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=0 & Op2_uimm3=5 & dbgbcr0_el1 { export dbgbcr0_el1; }
+CopReg: dbgbcr1_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=5 & dbgbcr1_el1 { export dbgbcr1_el1; }
+CopReg: dbgbcr2_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=5 & dbgbcr2_el1 { export dbgbcr2_el1; }
+CopReg: dbgbcr3_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=3 & Op2_uimm3=5 & dbgbcr3_el1 { export dbgbcr3_el1; }
+CopReg: dbgbcr4_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=4 & Op2_uimm3=5 & dbgbcr4_el1 { export dbgbcr4_el1; }
+CopReg: dbgbcr5_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=5 & Op2_uimm3=5 & dbgbcr5_el1 { export dbgbcr5_el1; }
+CopReg: dbgbcr6_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=6 & Op2_uimm3=5 & dbgbcr6_el1 { export dbgbcr6_el1; }
+CopReg: dbgbcr7_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=7 & Op2_uimm3=5 & dbgbcr7_el1 { export dbgbcr7_el1; }
+CopReg: dbgbcr8_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=8 & Op2_uimm3=5 & dbgbcr8_el1 { export dbgbcr8_el1; }
+CopReg: dbgbcr9_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=9 & Op2_uimm3=5 & dbgbcr9_el1 { export dbgbcr9_el1; }
+CopReg: dbgbcr10_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=10 & Op2_uimm3=5 & dbgbcr10_el1 { export dbgbcr10_el1; }
+CopReg: dbgbcr11_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=11 & Op2_uimm3=5 & dbgbcr11_el1 { export dbgbcr11_el1; }
+CopReg: dbgbcr12_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=12 & Op2_uimm3=5 & dbgbcr12_el1 { export dbgbcr12_el1; }
+CopReg: dbgbcr13_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=13 & Op2_uimm3=5 & dbgbcr13_el1 { export dbgbcr13_el1; }
+CopReg: dbgbcr14_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=14 & Op2_uimm3=5 & dbgbcr14_el1 { export dbgbcr14_el1; }
+CopReg: dbgbcr15_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=15 & Op2_uimm3=5 & dbgbcr15_el1 { export dbgbcr15_el1; }
+CopReg: dbgwvr0_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=0 & Op2_uimm3=6 & dbgwvr0_el1 { export dbgwvr0_el1; }
+CopReg: dbgwvr1_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=6 & dbgwvr1_el1 { export dbgwvr1_el1; }
+CopReg: dbgwvr2_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=6 & dbgwvr2_el1 { export dbgwvr2_el1; }
+CopReg: dbgwvr3_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=3 & Op2_uimm3=6 & dbgwvr3_el1 { export dbgwvr3_el1; }
+CopReg: dbgwvr4_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=4 & Op2_uimm3=6 & dbgwvr4_el1 { export dbgwvr4_el1; }
+CopReg: dbgwvr5_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=5 & Op2_uimm3=6 & dbgwvr5_el1 { export dbgwvr5_el1; }
+CopReg: dbgwvr6_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=6 & Op2_uimm3=6 & dbgwvr6_el1 { export dbgwvr6_el1; }
+CopReg: dbgwvr7_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=7 & Op2_uimm3=6 & dbgwvr7_el1 { export dbgwvr7_el1; }
+CopReg: dbgwvr8_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=8 & Op2_uimm3=6 & dbgwvr8_el1 { export dbgwvr8_el1; }
+CopReg: dbgwvr9_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=9 & Op2_uimm3=6 & dbgwvr9_el1 { export dbgwvr9_el1; }
+CopReg: dbgwvr10_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=10 & Op2_uimm3=6 & dbgwvr10_el1 { export dbgwvr10_el1; }
+CopReg: dbgwvr11_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=11 & Op2_uimm3=6 & dbgwvr11_el1 { export dbgwvr11_el1; }
+CopReg: dbgwvr12_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=12 & Op2_uimm3=6 & dbgwvr12_el1 { export dbgwvr12_el1; }
+CopReg: dbgwvr13_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=13 & Op2_uimm3=6 & dbgwvr13_el1 { export dbgwvr13_el1; }
+CopReg: dbgwvr14_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=14 & Op2_uimm3=6 & dbgwvr14_el1 { export dbgwvr14_el1; }
+CopReg: dbgwvr15_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=15 & Op2_uimm3=6 & dbgwvr15_el1 { export dbgwvr15_el1; }
+CopReg: dbgwcr0_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=0 & Op2_uimm3=7 & dbgwcr0_el1 { export dbgwcr0_el1; }
+CopReg: dbgwcr1_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=1 & Op2_uimm3=7 & dbgwcr1_el1 { export dbgwcr1_el1; }
+CopReg: dbgwcr2_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=2 & Op2_uimm3=7 & dbgwcr2_el1 { export dbgwcr2_el1; }
+CopReg: dbgwcr3_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=3 & Op2_uimm3=7 & dbgwcr3_el1 { export dbgwcr3_el1; }
+CopReg: dbgwcr4_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=4 & Op2_uimm3=7 & dbgwcr4_el1 { export dbgwcr4_el1; }
+CopReg: dbgwcr5_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=5 & Op2_uimm3=7 & dbgwcr5_el1 { export dbgwcr5_el1; }
+CopReg: dbgwcr6_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=6 & Op2_uimm3=7 & dbgwcr6_el1 { export dbgwcr6_el1; }
+CopReg: dbgwcr7_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=7 & Op2_uimm3=7 & dbgwcr7_el1 { export dbgwcr7_el1; }
+CopReg: dbgwcr8_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=8 & Op2_uimm3=7 & dbgwcr8_el1 { export dbgwcr8_el1; }
+CopReg: dbgwcr9_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=9 & Op2_uimm3=7 & dbgwcr9_el1 { export dbgwcr9_el1; }
+CopReg: dbgwcr10_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=10 & Op2_uimm3=7 & dbgwcr10_el1 { export dbgwcr10_el1; }
+CopReg: dbgwcr11_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=11 & Op2_uimm3=7 & dbgwcr11_el1 { export dbgwcr11_el1; }
+CopReg: dbgwcr12_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=12 & Op2_uimm3=7 & dbgwcr12_el1 { export dbgwcr12_el1; }
+CopReg: dbgwcr13_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=13 & Op2_uimm3=7 & dbgwcr13_el1 { export dbgwcr13_el1; }
+CopReg: dbgwcr14_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=14 & Op2_uimm3=7 & dbgwcr14_el1 { export dbgwcr14_el1; }
+CopReg: dbgwcr15_el1 is Op0=2 & Op1_uimm3=0 & CRn=0 & CRm=15 & Op2_uimm3=7 & dbgwcr15_el1 { export dbgwcr15_el1; }
+CopReg: mdrar_el1 is Op0=2 & Op1_uimm3=0 & CRn=1 & CRm=0 & Op2_uimm3=0 & mdrar_el1 { export mdrar_el1; }
+CopReg: oslar_el1 is Op0=2 & Op1_uimm3=0 & CRn=1 & CRm=0 & Op2_uimm3=4 & oslar_el1 { export oslar_el1; }
+CopReg: oslsr_el1 is Op0=2 & Op1_uimm3=0 & CRn=1 & CRm=1 & Op2_uimm3=4 & oslsr_el1 { export oslsr_el1; }
+CopReg: osdlr_el1 is Op0=2 & Op1_uimm3=0 & CRn=1 & CRm=3 & Op2_uimm3=4 & osdlr_el1 { export osdlr_el1; }
+CopReg: dbgprcr_el1 is Op0=2 & Op1_uimm3=0 & CRn=1 & CRm=4 & Op2_uimm3=4 & dbgprcr_el1 { export dbgprcr_el1; }
+CopReg: dbgclaimset_el1 is Op0=2 & Op1_uimm3=0 & CRn=7 & CRm=8 & Op2_uimm3=6 & dbgclaimset_el1 { export dbgclaimset_el1; }
+CopReg: dbgclaimclr_el1 is Op0=2 & Op1_uimm3=0 & CRn=7 & CRm=9 & Op2_uimm3=6 & dbgclaimclr_el1 { export dbgclaimclr_el1; }
+CopReg: dbgauthstatus_el1 is Op0=2 & Op1_uimm3=0 & CRn=7 & CRm=14 & Op2_uimm3=6 & dbgauthstatus_el1 { export dbgauthstatus_el1; }
+CopReg: mdccsr_el0 is Op0=2 & Op1_uimm3=3 & CRn=0 & CRm=1 & Op2_uimm3=0 & mdccsr_el0 { export mdccsr_el0; }
+CopReg: dbgdtr_el0 is Op0=2 & Op1_uimm3=3 & CRn=0 & CRm=4 & Op2_uimm3=0 & dbgdtr_el0 { export dbgdtr_el0; }
+CopReg: dbgvcr32_el2 is Op0=2 & Op1_uimm3=4 & CRn=0 & CRm=7 & Op2_uimm3=0 & dbgvcr32_el2 { export dbgvcr32_el2; }
+# The SysReg document implies that GMID_EL1 can only be read - the doc only provides pseudocode for read access.
+# However, the register is in this block (without a required value for 'l') because that might not be fully accurate.
+CopReg: gmid_el1 is Op0=3 & Op1_uimm3=1 & CRn=0 & CRm=0 & Op2_uimm3=4 & gmid_el1 { export gmid_el1; }
+CopReg: ssbs is Op0=3 & Op1_uimm3=3 & CRn=4 & CRm=2 & Op2_uimm3=6 & ssbs { export ssbs; }
+} # with : (l=0 | l=1) {
+
+CopReg: dbgdtrrx_el0 is l=0 & Op0=2 & Op1_uimm3=3 & CRn=0 & CRm=5 & Op2_uimm3=0 & dbgdtrrx_el0 { export dbgdtrrx_el0; }
+CopReg: dbgdtrtx_el0 is l=1 & Op0=2 & Op1_uimm3=3 & CRn=0 & CRm=5 & Op2_uimm3=0 & dbgdtrtx_el0 { export dbgdtrtx_el0; }
+
+CopReg: "sreg("^Op0^", "^Op1_uimm3^", c"^CRn^", c"^CRm^", "^Op2_uimm3^")" is l=1 & Op0 & Op1_uimm3 & CRn & CRm & Op2_uimm3 { tmp:8 = UnkSytemRegRead(Op0:1, Op1_uimm3:1, CRn:1, CRm:1, Op2_uimm3:1); export tmp; }
+CopReg: "sreg("^Op0^", "^Op1_uimm3^", c"^CRn^", c"^CRm^", "^Op2_uimm3^")" is l=0 & Op0 & Op1_uimm3 & CRn & CRm & Op2_uimm3 & Rt_GPR64 { tmp:8 = UnkSytemRegWrite(Op0:1, Op1_uimm3:1, CRn:1, CRm:1, Op2_uimm3:1, Rt_GPR64); export tmp; }
+
+PState_pstate_op: "DAIFSet" is Op1_uimm3=3 & Op2_uimm3=6 & CRm { daif = (CRm << 6) | daif; }
+PState_pstate_op: "DAIFClr" is Op1_uimm3=3 & Op2_uimm3=7 & CRm { tmp:8 = CRm; daif = (~(tmp << 6)) & daif; }
+PState_pstate_op: "PState.UAO" is Op1_uimm3=0 & Op2_uimm3=3 & CRm { tmp:8 = CRm; uao = tmp & 1; }
+PState_pstate_op: "PState.PAN" is Op1_uimm3=0 & Op2_uimm3=4 & CRm { tmp:8 = CRm; pan = tmp & 1; }
+PState_pstate_op: "PState.SP" is Op1_uimm3=0 & Op2_uimm3=5 & CRm { tmp:8 = CRm; spsel = tmp & 1; }
+PState_pstate_op: "PState.TCO" is Op1_uimm3=3 & Op2_uimm3=4 & CRm { tmp:8 = CRm; tco = tmp & 1; }
+PState_pstate_op: "PState.ALLINT" is Op1_uimm3=1 & Op2_uimm3=0 & b_0911=0 & CRm { tmp:8 = CRm; allint = tmp & 1; }
+PState_pstate_op: "PState.DIT" is Op1_uimm3=3 & Op2_uimm3=2 & CRm { tmp:8 = CRm; dit = tmp & 1; }
+#PState_pstate_op: "PState.SVCRSM" is Op1_uimm3=3 & Op2_uimm3=3 & b_0911=1 & b_08 { tmp:8 = b_08; svcrsm = tmp & 1; } # see SMSTART/SMSTOP
+#PState_pstate_op: "PState.SVCRZA" is Op1_uimm3=3 & Op2_uimm3=3 & b_0911=2 & b_08 { tmp:8 = b_08; svcrza = tmp & 1; } # see SMSTART/SMSTOP
+#PState_pstate_op: "PState.SVZRMZA" is Op1_uimm3=3 & Op2_uimm3=3 & b_0911=3 & b_08 { tmp:8 = b_08; svcrsmza = tmp & 1; } # see SMSTART/SMSTOP
+PState_pstate_op: "PState.SSBS" is Op1_uimm3=3 & Op2_uimm3=1 & CRm { tmp:8 = CRm; ssbs = tmp & 1; }
+
+
+
+# C6.2.228 MRS page C6-1683 line 99588 MATCH xd5300000/mask=xfff00000
+# C6.2.379 TSTART page C6-1979 line 116075 MATCH xd5233060/mask=xffffffe0
+# C6.2.380 TTEST page C6-1981 line 116175 MATCH xd5233160/mask=xffffffe0
+# CONSTRUCT xd5200000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst xd5200000/mask=xffe00000 --status noqemu
+
+:mrs Rt_GPR64, CopReg
+is b_2431=0xd5 & b_2223=0 & l=1 & CopReg & Rt_GPR64
+{
+ Rt_GPR64 = CopReg;
+}
+
+# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f
+# CONSTRUCT xd500401f/mask=xfff8f01f MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd500401f/mask=xfff8f01f --status nodest
+
+:msr PState_pstate_op, CRm_uimm4
+is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & PState_pstate_op & CRn=0x4 & CRm_uimm4 & Rt=0x1f
+{
+}
+
+# CONSTRUCT xd5000000/mask=xffe00000 DID NOT MATCH ANY DOCUMENTED OPCODE
+# AUNIT --inst xd5000000/mask=xffe00000 --status noqemu
+
+:msr CopReg, Rt_GPR64
+is b_2431=0xd5 & b_2223=0 & l=0 & CopReg & Rt_GPR64
+{
+ CopReg = Rt_GPR64;
+}
+
+# C6.2.231 MSUB page C6-1689 line 99963 MATCH x1b008000/mask=x7fe08000
+# C6.2.219 MNEG page C6-1666 line 98782 MATCH x1b00fc00/mask=x7fe0fc00
+# CONSTRUCT x1b008000/mask=xffe08000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x1b008000/mask=xffe08000 --status pass
+
+:msub Rd_GPR32, Rn_GPR32, Rm_GPR32, Ra_GPR32
+is sf=0 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=0 & Rm_GPR32 & op.dp3_o0=1 & Ra_GPR32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp_2:4 = Rn_GPR32 * Rm_GPR32;
+ tmp_1:4 = Ra_GPR32 - tmp_2;
+ Rd_GPR64 = zext(tmp_1);
+}
+
+# C6.2.231 MSUB page C6-1689 line 99963 MATCH x1b008000/mask=x7fe08000
+# C6.2.219 MNEG page C6-1666 line 98782 MATCH x1b00fc00/mask=x7fe0fc00
+# CONSTRUCT x9b008000/mask=xffe08000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x9b008000/mask=xffe08000 --status pass
+
+:msub Rd_GPR64, Rn_GPR64, Rm_GPR64, Ra_GPR64
+is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=0 & Rm_GPR64 & op.dp3_o0=1 & Ra_GPR64 & Rn_GPR64 & Rd_GPR64
+{
+ tmp_2:8 = Rn_GPR64 * Rm_GPR64;
+ tmp_1:8 = Ra_GPR64 - tmp_2;
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.232 MUL page C6-1691 line 100073 MATCH x1b007c00/mask=x7fe0fc00
+# C6.2.218 MADD page C6-1664 line 98671 MATCH x1b000000/mask=x7fe08000
+# CONSTRUCT x1b007c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x1b007c00/mask=xffe0fc00 --status pass
+
+:mul Rd_GPR32, Rn_GPR32, Rm_GPR32
+is sf=0 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=0 & Rm_GPR32 & op.dp3_o0=0 & Ra=0x1f & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp_2:4 = Rn_GPR32 * Rm_GPR32;
+ Rd_GPR64 = zext(tmp_2);
+}
+
+# C6.2.232 MUL page C6-1691 line 100073 MATCH x1b007c00/mask=x7fe0fc00
+# C6.2.218 MADD page C6-1664 line 98671 MATCH x1b000000/mask=x7fe08000
+# CONSTRUCT x9b007c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x9b007c00/mask=xffe0fc00 --status pass
+
+:mul Rd_GPR64, Rn_GPR64, Rm_GPR64
+is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=0 & Rm_GPR64 & op.dp3_o0=0 & Ra=0x1f & Rn_GPR64 & Rd_GPR64
+{
+ tmp_2:8 = Rn_GPR64 * Rm_GPR64;
+ Rd_GPR64 = tmp_2;
+}
+
+# C6.2.233 MVN page C6-1692 line 100146 MATCH x2a2003e0/mask=x7f2003e0
+# C6.2.239 ORN (shifted register) page C6-1703 line 100663 MATCH x2a200000/mask=x7f200000
+# CONSTRUCT x2a2003e0/mask=xff2003e0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x2a2003e0/mask=xff2003e0 --status pass
+
+:mvn Rd_GPR32, RegShift32Log
+is sf=0 & opc=1 & b_2428=0xa & N=1 & RegShift32Log & Rn=0x1f & Rd_GPR32 & Rd_GPR64
+{
+ tmp_1:4 = ~RegShift32Log;
+ Rd_GPR64 = zext(tmp_1);
+}
+
+# C6.2.233 MVN page C6-1692 line 100146 MATCH x2a2003e0/mask=x7f2003e0
+# C6.2.239 ORN (shifted register) page C6-1703 line 100663 MATCH x2a200000/mask=x7f200000
+# CONSTRUCT xaa2003e0/mask=xff2003e0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xaa2003e0/mask=xff2003e0 --status pass
+
+:mvn Rd_GPR64, RegShift64Log
+is sf=1 & opc=1 & b_2428=0xa & N=1 & Rm_GPR64 & RegShift64Log & Rn=0x1f & Rd_GPR64
+{
+ tmp_1:8 = ~RegShift64Log;
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.234 NEG (shifted register) page C6-1694 line 100243 MATCH x4b0003e0/mask=x7f2003e0
+# C6.2.358 SUB (shifted register) page C6-1945 line 114221 MATCH x4b000000/mask=x7f200000
+# CONSTRUCT x4b0003e0/mask=xff2003e0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x4b0003e0/mask=xff2003e0 --status pass
+
+:neg Rd_GPR32, RegShift32
+is sf=0 & op=1 & s=0 & b_2428=0xb & b_2121=0 & RegShift32 & Rn=0x1f & Rd_GPR32 & Rd_GPR64
+{
+ tmp_2:4 = RegShift32;
+ tmp_1:4 = - tmp_2;
+ Rd_GPR64 = zext(tmp_1);
+}
+
+# C6.2.234 NEG (shifted register) page C6-1694 line 100243 MATCH x4b0003e0/mask=x7f2003e0
+# C6.2.358 SUB (shifted register) page C6-1945 line 114221 MATCH x4b000000/mask=x7f200000
+# CONSTRUCT xcb0003e0/mask=xff2003e0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xcb0003e0/mask=xff2003e0 --status pass
+
+:neg Rd_GPR64, RegShift64
+is sf=1 & op=1 & s=0 & b_2428=0xb & b_2121=0 & RegShift64 & Rn=0x1f & Rd_GPR64
+{
+ tmp_2:8 = RegShift64;
+ tmp_1:8 = - tmp_2;
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.235 NEGS page C6-1696 line 100340 MATCH x6b0003e0/mask=x7f2003e0
+# C6.2.64 CMP (shifted register) page C6-1256 line 73623 MATCH x6b00001f/mask=x7f20001f
+# C6.2.364 SUBS (shifted register) page C6-1955 line 114807 MATCH x6b000000/mask=x7f200000
+# CONSTRUCT x6b0003e0/mask=xff2003e0 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst x6b0003e0/mask=xff2003e0 --status pass --comment "flags"
+
+:negs Rd_GPR32, RegShift32
+is sf=0 & op=1 & s=1 & b_2428=0xb & b_2121=0 & RegShift32 & Rn=0x1f & Rd_GPR32 & Rd & Rd_GPR64
+{
+ tmp_2:4 = RegShift32;
+ subflags0(tmp_2);
+ tmp_1:4 = 0:4 - tmp_2;
+ resultflags(tmp_1);
+ Rd_GPR64 = zext(tmp_1);
+ affectflags();
+}
+
+# C6.2.235 NEGS page C6-1696 line 100340 MATCH x6b0003e0/mask=x7f2003e0
+# C6.2.64 CMP (shifted register) page C6-1256 line 73623 MATCH x6b00001f/mask=x7f20001f
+# C6.2.364 SUBS (shifted register) page C6-1955 line 114807 MATCH x6b000000/mask=x7f200000
+# CONSTRUCT xeb0003e0/mask=xff2003e0 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst xeb0003e0/mask=xff2003e0 --status pass --comment "flags"
+
+:negs Rd_GPR64, RegShift64
+is sf=1 & op=1 & s=1 & b_2428=0xb & b_2121=0 & RegShift64 & Rn=0x1f & Rd_GPR64 & Rd
+{
+ tmp_2:8 = RegShift64;
+ subflags0(tmp_2);
+ tmp_1:8 = 0:8 - tmp_2;
+ resultflags(tmp_1);
+ Rd_GPR64 = tmp_1;
+ affectflags();
+}
+
+# C6.2.236 NGC page C6-1698 line 100437 MATCH x5a0003e0/mask=x7fe0ffe0
+# C6.2.265 SBC page C6-1747 line 102973 MATCH x5a000000/mask=x7fe0fc00
+# CONSTRUCT x5a0003e0/mask=xffe0ffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x5a0003e0/mask=xffe0ffe0 --status pass --comment "flags"
+
+:ngc Rd_GPR32, Rm_GPR32
+is sf=0 & op=1 & s=0 & b_2428=0x1a & b_2123=0 & Rm_GPR32 & opcode2=0x0 & Rn=0x1f & Rd_GPR32 & Rd_GPR64
+{
+ tmp:4 = Rm_GPR32 + zext(!CY);
+ Rd_GPR64 = zext(-tmp);
+}
+
+# C6.2.236 NGC page C6-1698 line 100437 MATCH x5a0003e0/mask=x7fe0ffe0
+# C6.2.265 SBC page C6-1747 line 102973 MATCH x5a000000/mask=x7fe0fc00
+# CONSTRUCT xda0003e0/mask=xffe0ffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xda0003e0/mask=xffe0ffe0 --status pass --comment "flags"
+
+:ngc Rd_GPR64, Rm_GPR64
+is sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=0 & Rm_GPR64 & opcode2=0x0 & Rn=0x1f & Rd_GPR64
+{
+ tmp:8 = Rm_GPR64 + zext(!CY);
+ Rd_GPR64 = -tmp;
+}
+
+# C6.2.237 NGCS page C6-1700 line 100524 MATCH x7a0003e0/mask=x7fe0ffe0
+# C6.2.266 SBCS page C6-1749 line 103074 MATCH x7a000000/mask=x7fe0fc00
+# CONSTRUCT x7a0003e0/mask=xffe0ffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x7a0003e0/mask=xffe0ffe0 --status pass --comment "flags"
+
+:ngcs Rd_GPR32, Rm_GPR32
+is sf=0 & op=1 & s=1 & b_2428=0x1a & b_2123=0 & Rn=0x1f & opcode2=0x0 & Rm_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp:4 = Rm_GPR32 + zext(!CY);
+ add_with_carry_flags(0,~tmp);
+ Rd_GPR64 = zext(-tmp);
+ resultflags(Rd_GPR32);
+ affectflags();
+}
+
+# C6.2.237 NGCS page C6-1700 line 100524 MATCH x7a0003e0/mask=x7fe0ffe0
+# C6.2.266 SBCS page C6-1749 line 103074 MATCH x7a000000/mask=x7fe0fc00
+# CONSTRUCT xfa0003e0/mask=xffe0ffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xfa0003e0/mask=xffe0ffe0 --status pass --comment "flags"
+
+:ngcs Rd_GPR64, Rm_GPR64
+is sf=1 & op=1 & s=1 & b_2428=0x1a & b_2123=0 & Rn=0x1f & opcode2=0x0 & Rm_GPR64 & Rd_GPR64
+{
+ tmp:8 = Rm_GPR64 + zext(!CY);
+ add_with_carry_flags(0,~tmp);
+ Rd_GPR64 = -tmp;
+ resultflags(Rd_GPR64);
+ affectflags();
+}
+
+# C6.2.238 NOP page C6-1702 line 100611 MATCH xd503201f/mask=xffffffff
+# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f
+# CONSTRUCT xd503201f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd503201f/mask=xffffffff --status nodest
+
+:nop
+is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low=0 & Rt=0x1f
+{
+}
+
+# C6.2.239 ORN (shifted register) page C6-1703 line 100663 MATCH x2a200000/mask=x7f200000
+# C6.2.233 MVN page C6-1692 line 100146 MATCH x2a2003e0/mask=x7f2003e0
+# CONSTRUCT x2a200000/mask=xff200000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x2a200000/mask=xff200000 --status pass
+
+:orn Rd_GPR32, Rn_GPR32, RegShift32Log
+is sf=0 & opc=1 & b_2428=0xa & N=1 & RegShift32Log & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp_3:4 = RegShift32Log;
+ tmp_2:4 = tmp_3 ^ -1:4;
+ tmp_1:4 = Rn_GPR32 | tmp_2;
+ Rd_GPR64 = zext(tmp_1);
+}
+
+# C6.2.239 ORN (shifted register) page C6-1703 line 100663 MATCH x2a200000/mask=x7f200000
+# C6.2.233 MVN page C6-1692 line 100146 MATCH x2a2003e0/mask=x7f2003e0
+# CONSTRUCT xaa200000/mask=xff200000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xaa200000/mask=xff200000 --status pass
+
+:orn Rd_GPR64, Rn_GPR64, RegShift64Log
+is sf=1 & opc=1 & b_2428=0xa & N=1 & RegShift64Log & Rn_GPR64 & Rd_GPR64
+{
+ tmp_3:8= RegShift64Log;
+ tmp_2:8 = tmp_3 ^ -1:8;
+ tmp_1:8 = Rn_GPR64 | tmp_2;
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.240 ORR (immediate) page C6-1705 line 100779 MATCH x32000000/mask=x7f800000
+# C6.2.223 MOV (bitmask immediate) page C6-1673 line 99125 MATCH x320003e0/mask=x7f8003e0
+# CONSTRUCT x32000000/mask=xff800000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x32000000/mask=xff800000 --status pass
+
+:orr Rd_GPR32wsp, Rn_GPR32, DecodeWMask32
+is sf=0 & opc=1 & b_2428=0x12 & b_2323=0 & DecodeWMask32 & Rn_GPR32 & Rd_GPR32wsp & Rd_GPR64xsp
+{
+ tmp_1:4 = Rn_GPR32 | DecodeWMask32;
+ Rd_GPR64xsp = zext(tmp_1);
+}
+
+# C6.2.240 ORR (immediate) page C6-1705 line 100779 MATCH x32000000/mask=x7f800000
+# C6.2.223 MOV (bitmask immediate) page C6-1673 line 99125 MATCH x320003e0/mask=x7f8003e0
+# CONSTRUCT xb2000000/mask=xff800000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xb2000000/mask=xff800000 --status pass
+
+:orr Rd_GPR64xsp, Rn_GPR64, DecodeWMask64
+is sf=1 & opc=1 & b_2428=0x12 & b_2323=0 & DecodeWMask64 & Rn_GPR64 & Rd_GPR64xsp
+{
+ tmp_1:8 = Rn_GPR64 | DecodeWMask64;
+ Rd_GPR64xsp = tmp_1;
+}
+
+# C6.2.241 ORR (shifted register) page C6-1707 line 100882 MATCH x2a000000/mask=x7f200000
+# C6.2.224 MOV (register) page C6-1675 line 99214 MATCH x2a0003e0/mask=x7fe0ffe0
+# CONSTRUCT x2a000000/mask=xff200000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x2a000000/mask=xff200000 --status pass
+
+:orr Rd_GPR32, Rn_GPR32, RegShift32Log
+is b_31=0 & b_2430=0b0101010 & b_21=0 & RegShift32Log & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp_2:4 = RegShift32Log;
+ tmp_1:4 = Rn_GPR32 | tmp_2;
+ Rd_GPR64 = zext(tmp_1);
+}
+
+# C6.2.241 ORR (shifted register) page C6-1707 line 100882 MATCH x2a000000/mask=x7f200000
+# C6.2.224 MOV (register) page C6-1675 line 99214 MATCH x2a0003e0/mask=x7fe0ffe0
+# CONSTRUCT xaa000000/mask=xff200000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xaa000000/mask=xff200000 --status pass
+
+:orr Rd_GPR64, Rn_GPR64, RegShift64Log
+is b_31=1 & b_2430=0b0101010 & b_21=0 & RegShift64Log & Rn_GPR64 & Rd_GPR64
+{
+ tmp_2:8 = RegShift64Log;
+ tmp_1:8 = Rn_GPR64 | tmp_2;
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.242 PACDA, PACDZA page C6-1709 line 100996 MATCH xdac10800/mask=xffffdc00
+# CONSTRUCT xdac10800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xdac10800/mask=xfffffc00 --status noqemu
+# z == 0 pacda variant
+
+:pacda Rd_GPR64, Rn_GPR64xsp
+is pacda__PACpart & b_1431=0b110110101100000100 & b_1012=0b010 & b_13=0 & Rn_GPR64xsp & Rd_GPR64
+{
+ build pacda__PACpart;
+}
+
+# C6.2.242 PACDA, PACDZA page C6-1709 line 100996 MATCH xdac10800/mask=xffffdc00
+# CONSTRUCT xdac12be0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xdac12be0/mask=xffffffe0 --status noqemu
+# z == 1 pacdza variant
+
+:pacdza Rd_GPR64
+is pacdza__PACpart & b_1431=0b110110101100000100 & b_1012=0b010 & b_13=1 & b_0509=0b11111 & Rd_GPR64
+{
+ build pacdza__PACpart;
+}
+
+# C6.2.243 PACDB, PACDZB page C6-1710 line 101067 MATCH xdac10c00/mask=xffffdc00
+# CONSTRUCT xdac10c00/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xdac10c00/mask=xfffffc00 --status noqemu
+# z == 0 pacdb variant
+
+:pacdb Rd_GPR64, Rn_GPR64xsp
+is pacdb__PACpart & b_1431=0b110110101100000100 & b_1012=0b011 & b_13=0 & Rn_GPR64xsp & Rd_GPR64
+{
+ build pacdb__PACpart;
+}
+
+# C6.2.243 PACDB, PACDZB page C6-1710 line 101067 MATCH xdac10c00/mask=xffffdc00
+# CONSTRUCT xdac12fe0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xdac12fe0/mask=xffffffe0 --status noqemu
+# z == 1 pacdzb variant
+
+:pacdzb Rd_GPR64
+is pacdzb__PACpart & b_1431=0b110110101100000100 & b_1012=0b011 & b_13=1 & b_0509=0b11111 & Rd_GPR64
+{
+ build pacdzb__PACpart;
+}
+
+# C6.2.244 PACGA page C6-1711 line 101138 MATCH x9ac03000/mask=xffe0fc00
+# CONSTRUCT x9ac03000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x9ac03000/mask=xffe0fc00 --status noqemu
+
+:pacga Rd_GPR64, Rn_GPR64, Rm_GPR64xsp
+is b_2131=0b10011010110 & b_1015=0b001100 & Rm_GPR64xsp & Rn_GPR64 & Rd_GPR64
+{
+ # This operation, unlike all other PAC operations, does not put its output in
+ # the same register as its first input. This means that putting a "noclobber"
+ # variant on this operation would violate the definition of PACGA.
+ Rd_GPR64 = pacga(Rn_GPR64, Rm_GPR64xsp);
+}
+
+# C6.2.245 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA page C6-1712 line 101196 MATCH xdac10000/mask=xffffdc00
+# CONSTRUCT xdac10000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xdac10000/mask=xfffffc00 --status noqemu
+# Z == 0 PACIA variant
+
+:pacia Rd_GPR64, Rn_GPR64xsp
+is pacia__PACpart & b_1431=0b110110101100000100 & b_1012=0b000 & b_13=0 & Rn_GPR64xsp & Rd_GPR64
+{
+ build pacia__PACpart;
+}
+
+# C6.2.245 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA page C6-1712 line 101196 MATCH xdac10000/mask=xffffdc00
+# CONSTRUCT xdac123e0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xdac123e0/mask=xffffffe0 --status noqemu
+# Z == 1 && Rn == 11111 PACIZA variant
+
+:paciza Rd_GPR64
+is paciza__PACpart & b_1431=0b110110101100000100 & b_1012=0b000 & b_13=1 & b_0509=0b11111 & Rd_GPR64
+{
+ build paciza__PACpart;
+}
+
+# C6.2.245 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA page C6-1712 line 101196 MATCH xd503211f/mask=xfffffddf
+# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f
+# CONSTRUCT xd503211f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd503211f/mask=xffffffff --status nodest
+# CRm == 0001 && op2 == 000 PICIA1716 variant
+
+:pacia1716
+is pacia1716__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0001 & b_0507=0b000 & b_0004=0b11111
+{
+ build pacia1716__PACpart;
+}
+
+# C6.2.245 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA page C6-1712 line 101196 MATCH xd503211f/mask=xfffffddf
+# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f
+# CONSTRUCT xd503233f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd503233f/mask=xffffffff --status nodest
+# CRm == 0011 && op2 == 001 PACIASP variant
+
+:paciasp
+is paciasp__PACpart & PACIXSP_BTITARGETS & b_1231=0b11010101000000110010 & b_0811=0b0011 & b_0507=0b001 & b_0004=0b11111
+{
+ build paciasp__PACpart;
+}
+
+# C6.2.245 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA page C6-1712 line 101196 MATCH xd503211f/mask=xfffffddf
+# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f
+# CONSTRUCT xd503231f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd503231f/mask=xffffffff --status nodest
+# CRm == 0011 && op2 == 000 PACIAZ variant
+
+:paciaz
+is paciaz__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0011 & b_0507=0b000 & b_0004=0b11111
+{
+ build paciaz__PACpart;
+}
+
+# C6.2.246 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB page C6-1715 line 101358 MATCH xdac10400/mask=xffffdc00
+# CONSTRUCT xdac10400/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xdac10400/mask=xfffffc00 --status noqemu
+# Z == 0 PACIB variant
+
+:pacib Rd_GPR64, Rn_GPR64xsp
+is pacib__PACpart & b_1431=0b110110101100000100 & b_1012=0b001 & b_13=0 & Rn_GPR64xsp & Rd_GPR64
+{
+ build pacib__PACpart;
+}
+
+# C6.2.246 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB page C6-1715 line 101358 MATCH xdac10400/mask=xffffdc00
+# CONSTRUCT xdac127e0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xdac127e0/mask=xffffffe0 --status noqemu
+# Z == 1 && Rn = 11111 PACIZB variant
+
+:pacizb Rd_GPR64
+is pacizb__PACpart & b_1431=0b110110101100000100 & b_1012=0b001 & b_13=1 & b_0509=0b11111 & Rd_GPR64
+{
+ build pacizb__PACpart;
+}
+
+# C6.2.246 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB page C6-1715 line 101358 MATCH xd503215f/mask=xfffffddf
+# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f
+# CONSTRUCT xd503215f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd503215f/mask=xffffffff --status nodest
+# CRm == 0001 && op2 == 010 PACIB1716 variant
+
+:pacib1716
+is pacib1716__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0001 & b_0507=0b010 & b_0004=0b11111
+{
+ build pacib1716__PACpart;
+}
+
+# C6.2.246 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB page C6-1715 line 101358 MATCH xd503215f/mask=xfffffddf
+# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f
+# CONSTRUCT xd503237f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd503237f/mask=xffffffff --status nodest
+# CRm == 0011 && op2 == 011 PACIBSP variant
+
+:pacibsp
+is pacibsp__PACpart & PACIXSP_BTITARGETS & b_1231=0b11010101000000110010 & b_0811=0b0011 & b_0507=0b011 & b_0004=0b11111
+{
+ build pacibsp__PACpart;
+}
+
+# C6.2.246 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB page C6-1715 line 101358 MATCH xd503215f/mask=xfffffddf
+# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f
+# CONSTRUCT xd503235f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd503235f/mask=xffffffff --status nodest
+# CRm == 0011 && op2 == 010 PACIBZ variant
+
+:pacibz
+is pacibz__PACpart & b_1231=0b11010101000000110010 & b_0811=0b0011 & b_0507=0b010 & b_0004=0b11111
+{
+ build pacibz__PACpart;
+}
+
+# C6.2.247 PRFM (immediate) page C6-1718 line 101520 MATCH xf9800000/mask=xffc00000
+# CONSTRUCT xf9800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xf9800000/mask=xffc00000 --status nomem
+
+:prfm aa_prefetch, addrIndexed
+is size.ldstr=3 & b_2729=7 & v=0 & b_2425=1 & b_2223=2 & addrIndexed & b_0304 & b_0102 & b_00 & aa_prefetch
+{
+ addr:8 = addrIndexed;
+ hint:1 = b_0304;
+ target:1 = b_0102;
+ stream:1 = b_00;
+ Hint_Prefetch(addr, hint, target, stream);
+}
+
+# C6.2.248 PRFM (literal) page C6-1720 line 101616 MATCH xd8000000/mask=xff000000
+# CONSTRUCT xd8000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd8000000/mask=xff000000 --status nodest --comment "qemuerr(illegal addresses cause qemu exit)"
+
+:prfm aa_prefetch, Addr19
+is size.ldstr=3 & b_2729=3 & v=0 & b_2425=0 & Addr19 & b_0304 & b_0102 & b_00 & aa_prefetch
+{
+ addr:8 = &Addr19;
+ hint:1 = b_0304;
+ target:1 = b_0102;
+ stream:1 = b_00;
+ Hint_Prefetch(addr, hint, target, stream);
+}
+
+# C6.2.249 PRFM (register) page C6-1722 line 101700 MATCH xf8a04800/mask=xffe04c00
+# CONSTRUCT xf8a00800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xf8a00800/mask=xffe00c00 --status nomem
+
+:prfm aa_prefetch, addrIndexed
+is size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=1 & addrIndexed & b_1011=2 & b_0304 & b_0102 & b_00 & aa_prefetch
+{
+ addr:8 = addrIndexed;
+ hint:1 = b_0304;
+ target:1 = b_0102;
+ stream:1 = b_00;
+ Hint_Prefetch(addr, hint, target, stream);
+}
+
+# C6.2.250 PRFUM page C6-1724 line 101815 MATCH xf8800000/mask=xffe00c00
+# CONSTRUCT xf8800000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xf8800000/mask=xfffffc00 --status nomem
+
+:prfum aa_prefetch, addr_SIMM9
+is size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=0 & addr_SIMM9 & simm9=0 & b_1011=0 & b_0304 & b_0102 & b_00 & aa_prefetch
+{
+ addr:8 = addr_SIMM9;
+ hint:1 = b_0304;
+ target:1 = b_0102;
+ stream:1 = b_00;
+ Hint_Prefetch(addr, hint, target, stream);
+}
+
+# C6.2.250 PRFUM page C6-1724 line 101815 MATCH xf8800000/mask=xffe00c00
+# CONSTRUCT xf8800000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xf8800000/mask=xffe00c00 --status nomem
+
+:prfum aa_prefetch, addr_SIMM9
+is size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_2223=2 & b_2121=0 & addr_SIMM9 & b_1011=0 & b_0304 & b_0102 & b_00 & aa_prefetch
+{
+ addr:8 = addr_SIMM9;
+ hint:1 = b_0304;
+ target:1 = b_0102;
+ stream:1 = b_00;
+ Hint_Prefetch(addr, hint, target, stream);
+}
+
+# C6.2.253 RBIT page C6-1728 line 102006 MATCH x5ac00000/mask=x7ffffc00
+# CONSTRUCT x5ac00000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x5ac00000/mask=xfffffc00 --status pass
+
+:rbit Rd_GPR32, Rn_GPR32
+is sf=0 & b_3030=1 & S=0 & b_2428=0x1a & b_2123=6 & dp1.opcode2=0x0 & b_1015=0x0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ # The algorithm swaps 1, 2, 4, 8 bits, ect
+ local tmp:4 = Rn_GPR32;
+ tmp = (((tmp & 0xaaaaaaaa) >> 1) | ((tmp & 0x55555555) << 1));
+ tmp = (((tmp & 0xcccccccc) >> 2) | ((tmp & 0x33333333) << 2));
+ tmp = (((tmp & 0xf0f0f0f0) >> 4) | ((tmp & 0x0f0f0f0f) << 4));
+ tmp = (((tmp & 0xff00ff00) >> 8) | ((tmp & 0x00ff00ff) << 8));
+ tmp = ((tmp >> 16) | (tmp << 16));
+ Rd_GPR64 = zext(tmp);
+}
+
+# C6.2.253 RBIT page C6-1728 line 102006 MATCH x5ac00000/mask=x7ffffc00
+# CONSTRUCT xdac00000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xdac00000/mask=xfffffc00 --status pass
+
+:rbit Rd_GPR64, Rn_GPR64
+is sf=1 & b_3030=1 & S=0 & b_2428=0x1a & b_2123=6 & dp1.opcode2=0x0 & b_1015=0x0 & Rn_GPR64 & Rd_GPR64
+{
+ # The algorithm swaps 1, 2, 4, 8 bits, ect
+ local tmp:8 = Rn_GPR64;
+ tmp = (((tmp & 0xaaaaaaaaaaaaaaaa) >> 1) | ((tmp & 0x5555555555555555) << 1));
+ tmp = (((tmp & 0xcccccccccccccccc) >> 2) | ((tmp & 0x3333333333333333) << 2));
+ tmp = (((tmp & 0xf0f0f0f0f0f0f0f0) >> 4) | ((tmp & 0x0f0f0f0f0f0f0f0f) << 4));
+ tmp = (((tmp & 0xff00ff00ff00ff00) >> 8) | ((tmp & 0x00ff00ff00ff00ff) << 8));
+ tmp = (((tmp & 0xffff0000ffff0000) >> 16) | ((tmp & 0x0000ffff0000ffff) << 16));
+ Rd_GPR64 = ((tmp >> 32) | (tmp << 32));
+}
+
+# C6.2.254 RET page C6-1730 line 102090 MATCH xd65f0000/mask=xfffffc1f
+# CONSTRUCT xd65f0000/mask=xfffffc1f MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd65f0000/mask=xfffffc1f --status nodest
+
+:ret Rn_GPR64
+is b_2531=0x6b & b_2324=0 & b_2122=2 & b_1620=0x1f & b_1015=0 & Rn_GPR64 & b_0004=0
+{
+ pc = Rn_GPR64;
+ return [pc];
+}
+
+# C6.2.254 RET page C6-1730 line 102090 MATCH xd65f0000/mask=xfffffc1f
+# CONSTRUCT xd65f03c0/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd65f03c0/mask=xffffffff --status nodest
+
+:ret
+is b_2531=0x6b & b_2324=0 & b_2122=2 & b_1620=0x1f & b_1015=0 & aa_Xn=30 & b_0004=0
+{
+ pc = x30;
+ return [pc];
+}
+
+# C6.2.255 RETAA, RETAB page C6-1731 line 102135 MATCH xd65f0bff/mask=xfffffbff
+# CONSTRUCT xd65f0bff/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd65f0bff/mask=xffffffff --status nodest
+# M == 0 RETAA variant
+
+:retaa
+is retaa__PACpart & b_1131=0b110101100101111100001 & b_0009=0b1111111111 & b_10=0
+{
+ build retaa__PACpart;
+ pc = x30;
+ return [pc];
+}
+
+# C6.2.255 RETAA, RETAB page C6-1731 line 102135 MATCH xd65f0bff/mask=xfffffbff
+# CONSTRUCT xd65f0fff/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd65f0fff/mask=xffffffff --status nodest
+# M == 1 RETAB variant
+
+:retab
+is retab__PACpart & b_1131=0b110101100101111100001 & b_0009=0b1111111111 & b_10=1
+{
+ build retab__PACpart;
+ pc = x30;
+ return [pc];
+}
+
+# C6.2.256 REV page C6-1732 line 102201 MATCH x5ac00800/mask=x7ffff800
+# CONSTRUCT x5ac00800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x5ac00800/mask=xfffffc00 --status pass
+# sf == 0 && opc == 10 32-bit variant (3210 -> 0123)
+
+:rev Rd_GPR32, Rn_GPR32
+is b_1230=0b1011010110000000000 & b_31=0 & b_1011=0b10 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ local tmp:4 = Rn_GPR32;
+ tmp = (((tmp & 0xff00ff00) >> 8) | ((tmp & 0x00ff00ff) << 8));
+ tmp = ((tmp >> 16) | (tmp << 16));
+ Rd_GPR64 = zext(tmp);
+}
+
+# C6.2.256 REV page C6-1732 line 102201 MATCH x5ac00800/mask=x7ffff800
+# C6.2.259 REV64 page C6-1738 line 102502 MATCH xdac00c00/mask=xfffffc00
+# CONSTRUCT xdac00c00/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xdac00c00/mask=xfffffc00 --status pass
+# sf == 1 && opc == 11 64-bit variant (76543210 -> 01234567)
+# NB equivalent to REV64, which is never the preferred disassembly
+
+:rev Rd_GPR64, Rn_GPR64
+is b_1230=0b1011010110000000000 & b_31=1 & b_1011=0b11 & Rn_GPR64 & Rd_GPR64
+{
+ local tmp:8 = Rn_GPR64;
+ tmp = (((tmp & 0xff00ff00ff00ff00) >> 8) | ((tmp & 0x00ff00ff00ff00ff) << 8));
+ tmp = (((tmp & 0xffff0000ffff0000) >> 16) | ((tmp & 0x0000ffff0000ffff) << 16));
+ Rd_GPR64 = ((tmp >> 32) | (tmp << 32));
+}
+
+# C6.2.257 REV16 page C6-1734 line 102308 MATCH x5ac00400/mask=x7ffffc00
+# CONSTRUCT x5ac00400/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x5ac00400/mask=xfffffc00 --status pass
+# sf == 0 (and opc == 01) 32-bit variant (3210 -> 2301)
+
+:rev16 Rd_GPR32, Rn_GPR32
+is b_1230=0b1011010110000000000 & b_31=0 & b_1011=0b01 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ local tmp:4 = Rn_GPR32;
+ tmp = (((tmp & 0xff00ff00) >> 8) | ((tmp & 0x00ff00ff) << 8));
+ Rd_GPR64 = zext(tmp);
+}
+
+# C6.2.257 REV16 page C6-1734 line 102308 MATCH x5ac00400/mask=x7ffffc00
+# CONSTRUCT xdac00400/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xdac00400/mask=xfffffc00 --status pass
+# sf == 1 (and opc=01) 64-bit variant (76543210 -> 67452301)
+
+:rev16 Rd_GPR64, Rn_GPR64
+is b_1230=0b1011010110000000000 & b_31=1 & b_1011=0b01 & Rn_GPR64 & Rd_GPR64
+{
+ local tmp:8 = Rn_GPR64;
+ Rd_GPR64 = (((tmp & 0xff00ff00ff00ff00) >> 8) | ((tmp & 0x00ff00ff00ff00ff) << 8));
+}
+
+# C6.2.258 REV32 page C6-1736 line 102412 MATCH xdac00800/mask=xfffffc00
+# C6.2.256 REV page C6-1732 line 102201 MATCH x5ac00800/mask=x7ffff800
+# CONSTRUCT xdac00800/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xdac00800/mask=xfffffc00 --status pass
+# sf == 1 (and opc == 10) 64-bit variant (76543210 -> 45670123)
+
+:rev32 Rd_GPR64, Rn_GPR64
+is b_1230=0b1011010110000000000 & b_31=1 & b_1011=0b10 & Rn_GPR64 & Rd_GPR64
+{
+ local tmp:8 = Rn_GPR64;
+ tmp = (((tmp & 0xff00ff00ff00ff00) >> 8) | ((tmp & 0x00ff00ff00ff00ff) << 8));
+ Rd_GPR64 = (((tmp & 0xffff0000ffff0000) >> 16) | ((tmp & 0x0000ffff0000ffff) << 16));
+}
+
+# C6.2.260 RMIF page C6-1739 line 102566 MATCH xba000400/mask=xffe07c10
+# CONSTRUCT xba000400/mask=xffe07c10 MATCHED 1 DOCUMENTED OPCODES
+
+:rmif Rn_GPR64, UImm6, NZCVImm_uimm4
+is b_2131=0b10111010000 & b_1014=0b00001 & b_04=0b0 & Rn_GPR64 & UImm6 & NZCVImm_uimm4
+{
+ tmp:8 = Rn_GPR64 >> UImm6;
+ condMask:1 = NZCVImm_uimm4;
+ set_NZCV(tmp,condMask);
+}
+
+# C6.2.261 ROR (immediate) page C6-1740 line 102633 MATCH x13800000/mask=x7fa00000
+# C6.2.124 EXTR page C6-1477 line 87864 MATCH x13800000/mask=x7fa00000
+# CONSTRUCT x13800000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x13800000/mask=xffe00000 --status pass
+
+:ror Rd_GPR32, Rn_GPR32, LSB_bitfield32_imm
+is sf=0 & b_2930=0 & b_2428=0x13 & b_2323=1 & n=0 & b_21=0 & Rn=Rm & Rm_GPR32 & LSB_bitfield32_imm & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ result:4 = (Rn_GPR32 >> LSB_bitfield32_imm) | (Rn_GPR32 << (32 - LSB_bitfield32_imm));
+ Rd_GPR64 = zext(result);
+}
+
+# C6.2.261 ROR (immediate) page C6-1740 line 102633 MATCH x13800000/mask=x7fa00000
+# C6.2.124 EXTR page C6-1477 line 87864 MATCH x13800000/mask=x7fa00000
+# CONSTRUCT x93c00000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x93c00000/mask=xffe00000 --status pass
+
+:ror Rd_GPR64, Rn_GPR64, LSB_bitfield64_imm
+is sf=1 & b_2930=0 & b_2428=0x13 & b_2323=1 & n=1 & b_21=0 & Rn=Rm & Rm_GPR64 & LSB_bitfield64_imm & Rn_GPR64 & Rd_GPR64
+{
+ result:8 = (Rn_GPR64 >> LSB_bitfield64_imm) | (Rn_GPR64 << (64 - LSB_bitfield64_imm));
+ Rd_GPR64 = result;
+}
+
+# C6.2.262 ROR (register) page C6-1742 line 102726 MATCH x1ac02c00/mask=x7fe0fc00
+# C6.2.263 RORV page C6-1744 line 102821 MATCH x1ac02c00/mask=x7fe0fc00
+# CONSTRUCT x1ac02c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x1ac02c00/mask=xffe0fc00 --status pass
+
+:ror Rd_GPR32, Rn_GPR32, Rm_GPR32
+is sf=0 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR32 & b_1015=0xb & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ rval:4 = Rm_GPR32 & 0x1f;
+ tmp_1:4 = ( Rn_GPR32 >> rval) | ( Rn_GPR32 << ( 32 - rval ) );
+ Rd_GPR64 = zext(tmp_1);
+}
+
+# C6.2.262 ROR (register) page C6-1742 line 102726 MATCH x1ac02c00/mask=x7fe0fc00
+# C6.2.263 RORV page C6-1744 line 102821 MATCH x1ac02c00/mask=x7fe0fc00
+# CONSTRUCT x9ac02c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x9ac02c00/mask=xffe0fc00 --status pass
+
+:ror Rd_GPR64, Rn_GPR64, Rm_GPR64
+is sf=1 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR64 & b_1015=0xb & Rn_GPR64 & Rd_GPR64
+{
+ rval:8 = Rm_GPR64 & 0x3f;
+ tmp_1:8 = ( Rn_GPR64 >> rval ) | ( Rn_GPR64 << ( 64 - rval ) );
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.264 SB page C6-1746 line 102913 MATCH xd50330ff/mask=xfffff0ff
+# CONSTRUCT xd50330ff/mask=xfffff0ff MATCHED 1 DOCUMENTED OPCODES
+
+:sb
+is b_1231=0xd5033 & b_0007=0xff
+{
+ SpeculationBarrier();
+}
+
+# C6.2.265 SBC page C6-1747 line 102973 MATCH x5a000000/mask=x7fe0fc00
+# C6.2.236 NGC page C6-1698 line 100437 MATCH x5a0003e0/mask=x7fe0ffe0
+# CONSTRUCT x5a000000/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x5a000000/mask=xffe0fc00 --status pass --comment "flags"
+
+:sbc Rd_GPR32, Rn_GPR32, Rm_GPR32
+is sf=0 & op=1 & s=0 & b_2428=0x1a & b_2123=0 & Rm_GPR32 & opcode2=0x0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp:4 = Rm_GPR32 + zext(!CY);
+ Rd_GPR64 = zext(Rn_GPR32 - tmp);
+}
+
+# C6.2.265 SBC page C6-1747 line 102973 MATCH x5a000000/mask=x7fe0fc00
+# C6.2.236 NGC page C6-1698 line 100437 MATCH x5a0003e0/mask=x7fe0ffe0
+# CONSTRUCT xda000000/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xda000000/mask=xffe0fc00 --status pass --comment "flags"
+
+:sbc Rd_GPR64, Rn_GPR64, Rm_GPR64
+is sf=1 & op=1 & s=0 & b_2428=0x1a & b_2123=0 & Rm_GPR64 & opcode2=0x0 & Rn_GPR64 & Rd_GPR64
+{
+ tmp:8 = Rm_GPR64 + zext(!CY);
+ Rd_GPR64 = Rn_GPR64 - tmp;
+}
+
+# C6.2.266 SBCS page C6-1749 line 103074 MATCH x7a000000/mask=x7fe0fc00
+# C6.2.237 NGCS page C6-1700 line 100524 MATCH x7a0003e0/mask=x7fe0ffe0
+# CONSTRUCT x7a000000/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x7a000000/mask=xffe0fc00 --status pass --comment "flags"
+
+:sbcs Rd_GPR32, Rn_GPR32, Rm_GPR32
+is sf=0 & op=1 & s=1 & b_2428=0x1a & b_2123=0 & Rm_GPR32 & opcode2=0x0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp:4 = Rm_GPR32 + zext(!CY);
+ add_with_carry_flags(Rn_GPR32, ~Rm_GPR32);
+ Rd_GPR64 = zext(Rn_GPR32 - tmp);
+ resultflags(Rd_GPR32);
+ affectflags();
+}
+
+# C6.2.266 SBCS page C6-1749 line 103074 MATCH x7a000000/mask=x7fe0fc00
+# C6.2.237 NGCS page C6-1700 line 100524 MATCH x7a0003e0/mask=x7fe0ffe0
+# CONSTRUCT xfa000000/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xfa000000/mask=xffe0fc00 --status pass --comment "flags"
+
+:sbcs Rd_GPR64, Rn_GPR64, Rm_GPR64
+is sf=1 & op=1 & s=1 & b_2428=0x1a & b_2123=0 & Rm_GPR64 & opcode2=0x0 & Rn_GPR64 & Rd_GPR64
+{
+ tmp:8 = Rm_GPR64 + zext(!CY);
+ add_with_carry_flags(Rn_GPR64, ~Rm_GPR64);
+ Rd_GPR64 = Rn_GPR64 - tmp;
+ resultflags(Rd_GPR64);
+ affectflags();
+}
+
+# C6.2.209 SBFIZ page C6-856 line 49751 KEEPWITH
+
+sbfiz_lsb: "#"^imm is ImmR [ imm = 32 - ImmR; ] { export *[const]:4 imm; }
+sbfiz_width: "#"^imm is ImmS [ imm = ImmS + 1; ] { export *[const]:4 imm; }
+sbfiz_lsb64: "#"^imm is ImmR [ imm = 64 - ImmR; ] { export *[const]:4 imm; }
+
+# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000
+# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00
+# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000
+# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000
+# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00
+# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00
+# CONSTRUCT x13000002/mask=xffe08006 MATCHED 6 DOCUMENTED OPCODES
+# AUNIT --inst x13000002/mask=xffe08006 --status pass
+# Special alias case of sbfm for when ImmS < ImmR-1
+# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue();
+
+:sbfiz Rd_GPR32, Rn_GPR32, sbfiz_lsb, sbfiz_width
+is sbfiz_lsb & sbfiz_width & ImmS_LT_ImmR=1 & ImmS_EQ_ImmR=0 & sf=0 & opc=0 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & ImmSConst32 & DecodeWMask32 & DecodeTMask32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ local wmask:4 = DecodeWMask32;
+ local tmask:4 = DecodeTMask32;
+ local src:4 = Rn_GPR32;
+ local bot:4 = ((src>>ImmRConst32)|(src<<(32-ImmRConst32))) & wmask;
+ local top:4 = (((src>>ImmSConst32)&0x1)*(-1))&0xffffffff;
+ Rd_GPR64 = zext((top & ~(tmask)) | (bot & tmask));
+}
+
+# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000
+# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00
+# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000
+# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000
+# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00
+# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00
+# C6.2.371 SXTW page C6-1968 line 115498 MATCH x93407c00/mask=xfffffc00
+# CONSTRUCT x93400002/mask=xffc00006 MATCHED 7 DOCUMENTED OPCODES
+# AUNIT --inst x93400002/mask=xffc00006 --status pass
+# Special alias case of sbfm for when ImmS < ImmR-1
+
+:sbfiz Rd_GPR64, Rn_GPR64, sbfiz_lsb64, sbfiz_width
+is sbfiz_lsb64 & sbfiz_width & ImmS_LT_ImmR=1 & ImmS_EQ_ImmR=0 & sf=1 & opc=0 & b_2428=0x13 & b_2323=0 & n=1 & ImmRConst64 & ImmSConst64 & DecodeWMask64 & DecodeTMask64 & Rn_GPR64 & Rd_GPR64
+{
+ local wmask:8 = DecodeWMask64;
+ local tmask:8 = DecodeTMask64;
+ local src:8 = Rn_GPR64;
+ local bot:8 = ((src>>ImmRConst64)|(src<<(64-ImmRConst64))) & wmask;
+ local top:8 = ((src>>ImmSConst64)&0x1)*(-1);
+ Rd_GPR64 = (top & ~(tmask)) | (bot & tmask);
+}
+
+# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000
+# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00
+# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000
+# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000
+# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00
+# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00
+# CONSTRUCT x13000000/mask=xffe08000 MATCHED 6 DOCUMENTED OPCODES
+# AUNIT --inst x13000000/mask=xffe08000 --status pass
+# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue();
+
+:sbfm Rd_GPR32, Rn_GPR32, ImmRConst32, ImmSConst32
+is sf=0 & opc=0 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & ImmSConst32 & DecodeWMask32 & DecodeTMask32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ local wmask:4 = DecodeWMask32;
+ local tmask:4 = DecodeTMask32;
+ local src:4 = Rn_GPR32;
+ local bot:4 = ((src>>ImmRConst32)|(src<<(32-ImmRConst32))) & wmask;
+ local top:4 = (((src>>ImmSConst32)&0x1)*(-1))&0xffffffff;
+ Rd_GPR64 = zext((top & ~(tmask)) | (bot & tmask));
+}
+
+# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000
+# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00
+# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000
+# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000
+# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00
+# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00
+# C6.2.371 SXTW page C6-1968 line 115498 MATCH x93407c00/mask=xfffffc00
+# CONSTRUCT x93400000/mask=xffc00000 MATCHED 7 DOCUMENTED OPCODES
+# AUNIT --inst x93400000/mask=xffc00000 --status pass
+
+:sbfm Rd_GPR64, Rn_GPR64, ImmRConst64, ImmSConst64
+is sf=1 & opc=0 & b_2428=0x13 & b_2323=0 & n=1 & ImmRConst64 & ImmSConst64 & DecodeWMask64 & DecodeTMask64 & Rn_GPR64 & Rd_GPR64
+{
+ local wmask:8 = DecodeWMask64;
+ local tmask:8 = DecodeTMask64;
+ local src:8 = Rn_GPR64;
+ local bot:8 = ((src>>ImmRConst64)|(src<<(64-ImmRConst64))) & wmask;
+ local top:8 = ((src>>ImmSConst64)&0x1)*(-1);
+ Rd_GPR64 = (top & ~(tmask)) | (bot & tmask);
+}
+
+# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000
+# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00
+# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000
+# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000
+# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00
+# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00
+# CONSTRUCT x13000004/mask=xffe08006 MATCHED 6 DOCUMENTED OPCODES
+# AUNIT --inst x13000004/mask=xffe08006 --status pass
+# Special cases when just getting the 0 bit
+# >> Not sure about the above old comment one, this is actually for getting one bit from Rn
+# SBFX alias of SMFM is used when ImmS >= ImmR
+# We split the '>=' into two separate cases
+# Here ImmS = ImmR (for 32-bit)
+# Alias for sbfm as determined by BFXPreferred()
+# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue();
+
+:sbfx Rd_GPR32, Rn_GPR32, ImmRConst32, BFextractWidth32
+is ImmS_LT_ImmR=0 & ImmS_EQ_ImmR=1 & sf=0 & opc=0 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & BFextractWidth32 & ImmSConst32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp:4 = ((Rn_GPR32 >> ImmSConst32) & 0x1) * 0xffffffff;
+ Rd_GPR64 = zext(tmp);
+}
+
+# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000
+# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00
+# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000
+# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000
+# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00
+# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00
+# C6.2.371 SXTW page C6-1968 line 115498 MATCH x93407c00/mask=xfffffc00
+# CONSTRUCT x93400004/mask=xffc00006 MATCHED 7 DOCUMENTED OPCODES
+# AUNIT --inst x93400004/mask=xffc00006 --status pass
+# Now, the case where ImmS = ImmR (for 64-bit)
+
+:sbfx Rd_GPR64, Rn_GPR64, ImmRConst64, BFextractWidth64
+is ImmS_LT_ImmR=0 & ImmS_EQ_ImmR=1 & sf=1 & opc=0 & b_2428=0x13 & b_2323=0 & n=1 & BFextractWidth64 & ImmRConst64 & ImmSConst64 & Rn_GPR64 & Rd_GPR64
+{
+ tmp:8 = ((Rn_GPR64 >> ImmSConst64) & 0x1) * 0xffffffffffffffff;
+ Rd_GPR64 = tmp;
+}
+
+# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000
+# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00
+# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000
+# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000
+# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00
+# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00
+# CONSTRUCT x13000000/mask=xffe08006 MATCHED 6 DOCUMENTED OPCODES
+# AUNIT --inst x13000000/mask=xffe08006 --status pass
+# Now, the case where ImmS > ImmR (for 32-bit)
+# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue();
+
+:sbfx Rd_GPR32, Rn_GPR32, ImmRConst32, BFextractWidth32
+is ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=0 & sf=0 & opc=0 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & BFextractWidth32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ src:4 = Rn_GPR32;
+ tmp:4 = src << (31 - (ImmRConst32 + BFextractWidth32 - 1));
+ tmp = tmp s>> (32 - BFextractWidth32);
+ Rd_GPR64 = zext(tmp);
+}
+
+# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000
+# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00
+# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000
+# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000
+# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00
+# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00
+# C6.2.371 SXTW page C6-1968 line 115498 MATCH x93407c00/mask=xfffffc00
+# CONSTRUCT x93400000/mask=xffc00000 MATCHED 7 DOCUMENTED OPCODES
+# AUNIT --inst x93400000/mask=xffc00000 --status pass
+# Finally, the case where ImmS > ImmR (for 64-bit)
+
+:sbfx Rd_GPR64, Rn_GPR64, ImmRConst64, BFextractWidth64
+is sf=1 & opc=0 & b_2428=0x13 & b_2323=0 & n=1 & ImmRConst64 & BFextractWidth64 & (ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=0) & Rn_GPR64 & Rd_GPR64
+{
+ src:8 = Rn_GPR64;
+ tmp:8 = src << (63 - (ImmRConst64 + BFextractWidth64 - 1));
+ tmp = tmp s>> (64 - BFextractWidth64);
+ Rd_GPR64 = tmp;
+}
+
+# C6.2.270 SDIV page C6-1758 line 103515 MATCH x1ac00c00/mask=x7fe0fc00
+# CONSTRUCT x1ac00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x1ac00c00/mask=xffe0fc00 --status pass
+
+:sdiv Rd_GPR32, Rn_GPR32, Rm_GPR32
+is sf=0 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR32 & b_1015=0x3 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ local tmp_1:4 = 0;
+ if (Rm_GPR32 == 0) goto ;
+ tmp_1 = Rn_GPR32 s/ Rm_GPR32;
+
+ Rd_GPR64 = zext(tmp_1);
+}
+
+# C6.2.270 SDIV page C6-1758 line 103515 MATCH x1ac00c00/mask=x7fe0fc00
+# CONSTRUCT x9ac00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x9ac00c00/mask=xffe0fc00 --status pass
+
+:sdiv Rd_GPR64, Rn_GPR64, Rm_GPR64
+is sf=1 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR64 & b_1015=0x3 & Rn_GPR64 & Rd_GPR64
+{
+ local tmp_1:8 = 0;
+ if (Rm_GPR64 == 0) goto ;
+ tmp_1 = Rn_GPR64 s/ Rm_GPR64;
+
+ Rd_GPR64 = tmp_1;
+}
+
+
+# C6.2.271 SETF8, SETF16 page C6-1759 line 103584 MATCH x3a00080d/mask=xffffbc1f
+# CONSTRUCT x3a00080d/mask=xfffffc1f MATCHED 1 DOCUMENTED OPCODES
+
+:setf8 aa_Wn
+is b_1531=0b00111010000000000 & b_14=0 & b_1013=0b0010 & b_0004=0b01101 & aa_Wn
+{
+ NG = ((aa_Wn:1 >> 7) & 1) == 1;
+ ZR = (aa_Wn:1 == 0);
+ OV = (((aa_Wn >> 7) & 1) ^ ((aa_Wn >>8) & 1)) == 1;
+}
+
+
+# C6.2.271 SETF8, SETF16 page C6-1759 line 103584 MATCH x3a00080d/mask=xffffbc1f
+# CONSTRUCT x3a00480d/mask=xfffffc1f MATCHED 1 DOCUMENTED OPCODES
+
+:setf16 aa_Wn
+is b_1531=0b00111010000000000 & b_14=1 & b_1013=0b0010 & b_0004=0b01101 & aa_Wn
+{
+ NG = ((aa_Wn:2 >> 15) & 1) == 1;
+ ZR = (aa_Wn:2 == 0);
+ OV = (((aa_Wn >> 15) & 1) ^ ((aa_Wn >>16) & 1)) == 1;
+}
+
+
+
+
+# C6.2.276 SETP, SETM, SETE page C6-1780 line 105072 MATCH x19c00400/mask=x3fe03c00
+# C6.2.272 SETGP, SETGM, SETGE page C6-1760 line 103652 MATCH x1dc00400/mask=x3fe03c00
+# CONSTRUCT x1dc00400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES
+
+setPhase:"p" is b_1415=0 {export 0:1;}
+setPhase:"m" is b_1415=1 {export 1:1;}
+setPhase:"e" is b_1415=2 {export 2:1;}
+
+setType: "" is b_1013=0x1 {export 1:1; }
+setType: "n" is b_1013=0x9 {export 9:1; }
+setType: "t" is b_1013=0x5 {export 5:1; }
+setType: "tn" is b_1013=0xd {export 13:1; }
+
+define pcodeop memorySetTag;
+:setg^setPhase^setType [Rd_GPR64]!, Rn_GPR64!, Rs_GPR64
+is size.ldstr & b_2129=0xee & Rs_GPR64 & b_1415 <3 & setPhase & setType & Rn_GPR64 & Rd_GPR64 {
+ memorySetTag(Rd_GPR64, Rn_GPR64, Rs_GPR64, setPhase, setType);
+}
+
+
+# C6.2.276 SETP, SETM, SETE page C6-1780 line 105072 MATCH x19c00400/mask=x3fe03c00
+# CONSTRUCT x19c00400/mask=x3fe03c00 MATCHED 5 DOCUMENTED OPCODES
+define pcodeop memorySet;
+:setp^setPhase^setType [Rd_GPR64]!, Rn_GPR64!, Rs_GPR64
+is size.ldstr & b_2129=0xce & Rs_GPR64 & b_1415 <3 & setPhase & setType & Rn_GPR64 & Rd_GPR64 {
+ memorySet(Rd_GPR64, Rn_GPR64, Rs_GPR64, setPhase, setType);
+}
+
+
+# C6.2.280 SEV page C6-1796 line 106224 MATCH xd503209f/mask=xffffffff
+# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f
+# CONSTRUCT xd503209f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd503209f/mask=xffffffff --status nodest
+
+:sev
+is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low=4 & Rt=0x1f
+{
+ SendEvent();
+}
+
+# C6.2.281 SEVL page C6-1797 line 106259 MATCH xd50320bf/mask=xffffffff
+# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f
+# CONSTRUCT xd50320bf/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50320bf/mask=xffffffff --status nodest
+
+:sevl
+is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low=5 & Rt=0x1f
+{
+ SendEventLocally();
+}
+
+# C6.2.282 SMADDL page C6-1798 line 106294 MATCH x9b200000/mask=xffe08000
+# CONSTRUCT x9b200000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x9b200000/mask=xffe08000 --status pass
+
+:smaddl Rd_GPR64, Rn_GPR32, Rm_GPR32, Ra_GPR64
+is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=1 & Rm_GPR32 & op.dp3_o0=0 & Ra_GPR64 & Rn_GPR32 & Rd_GPR64
+{
+ tmp_3:8 = sext(Rn_GPR32);
+ tmp_4:8 = sext(Rm_GPR32);
+ tmp_2:8 = tmp_3 * tmp_4;
+ tmp_1:8 = Ra_GPR64 + tmp_2;
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.283 SMC page C6-1800 line 106384 MATCH xd4000003/mask=xffe0001f
+# CONSTRUCT xd4000003/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd4000003/mask=xffe0001f --status nodest
+
+:smc imm16
+is b_2431=0xd4 & excCode=0 & imm16 & excCode2=0 & ll=3
+{
+ CallSecureMonitor(imm16:2);
+}
+
+# C6.2.284 SMNEGL page C6-1801 line 106433 MATCH x9b20fc00/mask=xffe0fc00
+# C6.2.287 SMSUBL page C6-1806 line 106711 MATCH x9b208000/mask=xffe08000
+# CONSTRUCT x9b20fc00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x9b20fc00/mask=xffe0fc00 --status pass
+
+:smnegl Rd_GPR64, Rn_GPR32, Rm_GPR32
+is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=1 & Rm_GPR32 & op.dp3_o0=1 & Ra=0x1f & Rn_GPR32 & Rd_GPR64
+{
+ tmp_3:8 = sext(Rn_GPR32);
+ tmp_4:8 = sext(Rm_GPR32);
+ tmp_2:8 = tmp_3 * tmp_4;
+ subflags0(tmp_2);
+ tmp_1:8 = -tmp_2;
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.287 SMSUBL page C6-1806 line 106711 MATCH x9b208000/mask=xffe08000
+# CONSTRUCT x9b208000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x9b208000/mask=xffe08000 --status pass
+
+:smsubl Rd_GPR64, Rn_GPR32, Rm_GPR32, Ra_GPR64
+is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=1 & Rm_GPR32 & op.dp3_o0=1 & Ra_GPR64 & Rn_GPR32 & Rd_GPR64
+{
+ tmp_3:8 = sext(Rn_GPR32);
+ tmp_4:8 = sext(Rm_GPR32);
+ tmp_2:8 = tmp_3 * tmp_4;
+ tmp_1:8 = Ra_GPR64 - tmp_2;
+ Rd_GPR64 = tmp_1;
+}
+
+
+# C6.2.285 SMSTART page C6-1802 line 106497 MATCH xd503417f/mask=xfffff9ff
+# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f
+# CONSTRUCT xd503417f/mask=xfffff9ff MATCHED 2 DOCUMENTED OPCODES
+# xd503417f/mask=xfffff9ff NOT MATCHED BY ANY CONSTRUCTOR
+# b_0031=110101010000001101000..101111111
+
+define pcodeop sveStreamingModeStart;
+define pcodeop sveStreamingModeStop;
+
+SVAmodeOp: "SM" is b_0911=0x1 & b_08 { svcr[0,1] = b_08; }
+SVAmodeOp: "ZA" is b_0911=0x2 & b_08 { svcr[1,1] = b_08; }
+SVAmodeOp: "" is b_0911=0x3 & b_08 { svcr[0,1] = b_08; svcr[1,1] = b_08; }
+
+:smstart "{"^SVAmodeOp^"}"
+is b_1131=0x1aa068 & SVAmodeOp & b_08=1 & b_0507=0x3 & op4=0x1f {
+ build SVAmodeOp;
+ sveStreamingModeStart();
+}
+
+
+# C6.2.286 SMSTOP page C6-1804 line 106604 MATCH xd503407f/mask=xfffff9ff
+# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f
+# CONSTRUCT xd503407f/mask=xfffff9ff MATCHED 2 DOCUMENTED OPCODES
+# xd503407f/mask=xfffff9ff NOT MATCHED BY ANY CONSTRUCTOR
+# b_0031=110101010000001101000..001111111
+
+:smstop "{"^SVAmodeOp^"}"
+is b_1131=0x1aa068 & SVAmodeOp & b_08=0 & b_0507=0x3 & op4=0x1f {
+ sveStreamingModeStop();
+}
+
+
+# C6.2.288 SMULH page C6-1808 line 106800 MATCH x9b400000/mask=xffe08000
+# CONSTRUCT x9b400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x9b400000/mask=xffe08000 --status pass
+# To enforce SHOULD BE ONE fields add: b_1014=0b11111
+
+:smulh Rd_GPR64, Rn_GPR64, Rm_GPR64
+is sf=1 & op.dp3=0 & b_2428=0x1b & op.dp3_op31=2 & Rm_GPR64 & op.dp3_o0=0 & Ra & Rn_GPR64 & Rd_GPR64
+{
+ local tmpq:16 = sext(Rn_GPR64) * sext(Rm_GPR64);
+ Rd_GPR64 = tmpq(8);
+}
+
+# C6.2.289 SMULL page C6-1809 line 106867 MATCH x9b207c00/mask=xffe0fc00
+# C6.2.282 SMADDL page C6-1798 line 106294 MATCH x9b200000/mask=xffe08000
+# CONSTRUCT x9b207c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x9b207c00/mask=xffe0fc00 --status pass
+
+:smull Rd_GPR64, Rn_GPR32, Rm_GPR32
+is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=1 & Rm_GPR32 & op.dp3_o0=0 & Ra=0x1f & Rn_GPR32 & Rd_GPR64
+{
+ tmp_3:8 = sext(Rn_GPR32);
+ tmp_4:8 = sext(Rm_GPR32);
+ tmp_2:8 = tmp_3 * tmp_4;
+ tmp_1:8 = tmp_2;
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.295 STADDB, STADDLB page C6-1818 line 107383 MATCH x3820001f/mask=xffa0fc1f
+# C6.2.298 STCLRB, STCLRLB page C6-1824 line 107670 MATCH x3820101f/mask=xffa0fc1f
+# C6.2.301 STEORB, STEORLB page C6-1830 line 107956 MATCH x3820201f/mask=xffa0fc1f
+# C6.2.328 STSETB, STSETLB page C6-1886 line 111044 MATCH x3820301f/mask=xffa0fc1f
+# C6.2.331 STSMAXB, STSMAXLB page C6-1892 line 111330 MATCH x3820401f/mask=xffa0fc1f
+# C6.2.334 STSMINB, STSMINLB page C6-1898 line 111623 MATCH x3820501f/mask=xffa0fc1f
+# C6.2.340 STUMAXB, STUMAXLB page C6-1910 line 112231 MATCH x3820601f/mask=xffa0fc1f
+# C6.2.343 STUMINB, STUMINLB page C6-1916 line 112525 MATCH x3820701f/mask=xffa0fc1f
+# C6.2.133 LDADDB, LDADDAB, LDADDALB, LDADDLB page C6-1489 line 88545 MATCH x38200000/mask=xff20fc00
+# C6.2.152 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB page C6-1524 line 90495 MATCH x38201000/mask=xff20fc00
+# C6.2.155 LDEORB, LDEORAB, LDEORALB, LDEORLB page C6-1531 line 90916 MATCH x38202000/mask=xff20fc00
+# C6.2.181 LDSETB, LDSETAB, LDSETALB, LDSETLB page C6-1590 line 94403 MATCH x38203000/mask=xff20fc00
+# C6.2.184 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB page C6-1597 line 94824 MATCH x38204000/mask=xff20fc00
+# C6.2.187 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB page C6-1604 line 95245 MATCH x38205000/mask=xff20fc00
+# C6.2.196 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB page C6-1623 line 96362 MATCH x38206000/mask=xff20fc00
+# C6.2.199 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB page C6-1630 line 96783 MATCH x38207000/mask=xff20fc00
+# CONSTRUCT x3820001f/mask=xffa08c1f MATCHED 16 DOCUMENTED OPCODES
+# AUNIT --inst x3820001f/mask=xffa08c1f --status nomem
+
+# size=0b00 (3031)
+
+:st^ls_opc1^ls_lor^"b" aa_Ws, [Rn_GPR64xsp]
+is b_3031=0b00 & b_2429=0b111000 & b_23=0 & b_21=1 & b_1515=0 & b_1011=0b00 & b_0004=0b11111 & ls_opc1 & ls_lor & aa_Ws & Rn_GPR64xsp
+{ build ls_opc1; build ls_lor; }
+
+# C6.2.296 STADDH, STADDLH page C6-1820 line 107469 MATCH x7820001f/mask=xffa0fc1f
+# C6.2.299 STCLRH, STCLRLH page C6-1826 line 107756 MATCH x7820101f/mask=xffa0fc1f
+# C6.2.302 STEORH, STEORLH page C6-1832 line 108042 MATCH x7820201f/mask=xffa0fc1f
+# C6.2.329 STSETH, STSETLH page C6-1888 line 111130 MATCH x7820301f/mask=xffa0fc1f
+# C6.2.332 STSMAXH, STSMAXLH page C6-1894 line 111419 MATCH x7820401f/mask=xffa0fc1f
+# C6.2.335 STSMINH, STSMINLH page C6-1900 line 111712 MATCH x7820501f/mask=xffa0fc1f
+# C6.2.341 STUMAXH, STUMAXLH page C6-1912 line 112320 MATCH x7820601f/mask=xffa0fc1f
+# C6.2.344 STUMINH, STUMINLH page C6-1918 line 112614 MATCH x7820701f/mask=xffa0fc1f
+# C6.2.134 LDADDH, LDADDAH, LDADDALH, LDADDLH page C6-1491 line 88670 MATCH x78200000/mask=xff20fc00
+# C6.2.153 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH page C6-1526 line 90621 MATCH x78201000/mask=xff20fc00
+# C6.2.156 LDEORH, LDEORAH, LDEORALH, LDEORLH page C6-1533 line 91042 MATCH x78202000/mask=xff20fc00
+# C6.2.182 LDSETH, LDSETAH, LDSETALH, LDSETLH page C6-1592 line 94529 MATCH x78203000/mask=xff20fc00
+# C6.2.185 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH page C6-1599 line 94950 MATCH x78204000/mask=xff20fc00
+# C6.2.188 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH page C6-1606 line 95371 MATCH x78205000/mask=xff20fc00
+# C6.2.197 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH page C6-1625 line 96488 MATCH x78206000/mask=xff20fc00
+# C6.2.200 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH page C6-1632 line 96909 MATCH x78207000/mask=xff20fc00
+# CONSTRUCT x7820001f/mask=xffa08c1f MATCHED 16 DOCUMENTED OPCODES
+# AUNIT --inst x7820001f/mask=xffa08c1f --status nomem
+
+# size=0b01 (3031)
+
+:st^ls_opc2^ls_lor^"h" aa_Ws, [Rn_GPR64xsp]
+is b_3031=0b01 & b_2429=0b111000 & b_23=0 & b_21=1 & b_1515=0 & b_1011=0b00 & b_0004=0b11111 & ls_opc2 & ls_lor & aa_Ws & Rn_GPR64xsp
+{ build ls_opc2; build ls_lor; }
+
+# C6.2.297 STADD, STADDL page C6-1822 line 107555 MATCH xb820001f/mask=xbfa0fc1f
+# C6.2.300 STCLR, STCLRL page C6-1828 line 107842 MATCH xb820101f/mask=xbfa0fc1f
+# C6.2.303 STEOR, STEORL page C6-1834 line 108128 MATCH xb820201f/mask=xbfa0fc1f
+# C6.2.330 STSET, STSETL page C6-1890 line 111216 MATCH xb820301f/mask=xbfa0fc1f
+# C6.2.333 STSMAX, STSMAXL page C6-1896 line 111508 MATCH xb820401f/mask=xbfa0fc1f
+# C6.2.336 STSMIN, STSMINL page C6-1902 line 111801 MATCH xb820501f/mask=xbfa0fc1f
+# C6.2.342 STUMAX, STUMAXL page C6-1914 line 112409 MATCH xb820601f/mask=xbfa0fc1f
+# C6.2.345 STUMIN, STUMINL page C6-1920 line 112703 MATCH xb820701f/mask=xbfa0fc1f
+# C6.2.135 LDADD, LDADDA, LDADDAL, LDADDL page C6-1493 line 88796 MATCH xb8200000/mask=xbf20fc00
+# C6.2.154 LDCLR, LDCLRA, LDCLRAL, LDCLRL page C6-1528 line 90747 MATCH xb8201000/mask=xbf20fc00
+# C6.2.157 LDEOR, LDEORA, LDEORAL, LDEORL page C6-1535 line 91168 MATCH xb8202000/mask=xbf20fc00
+# C6.2.183 LDSET, LDSETA, LDSETAL, LDSETL page C6-1594 line 94655 MATCH xb8203000/mask=xbf20fc00
+# C6.2.186 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL page C6-1601 line 95076 MATCH xb8204000/mask=xbf20fc00
+# C6.2.189 LDSMIN, LDSMINA, LDSMINAL, LDSMINL page C6-1608 line 95497 MATCH xb8205000/mask=xbf20fc00
+# C6.2.198 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL page C6-1627 line 96614 MATCH xb8206000/mask=xbf20fc00
+# C6.2.201 LDUMIN, LDUMINA, LDUMINAL, LDUMINL page C6-1634 line 97035 MATCH xb8207000/mask=xbf20fc00
+# CONSTRUCT xb820001f/mask=xffa08c1f MATCHED 16 DOCUMENTED OPCODES
+# AUNIT --inst xb820001f/mask=xffa08c1f --status nomem
+
+# size=0b10 (3031)
+
+:st^ls_opc4^ls_lor aa_Ws, [Rn_GPR64xsp]
+is b_3031=0b10 & b_2429=0b111000 & b_23=0 & b_21=1 & b_1515=0 & b_1011=0b00 & b_0004=0b11111 & ls_opc4 & ls_lor & aa_Ws & Rn_GPR64xsp
+{ build ls_opc4; build ls_lor; }
+
+# C6.2.297 STADD, STADDL page C6-1822 line 107555 MATCH xb820001f/mask=xbfa0fc1f
+# C6.2.300 STCLR, STCLRL page C6-1828 line 107842 MATCH xb820101f/mask=xbfa0fc1f
+# C6.2.303 STEOR, STEORL page C6-1834 line 108128 MATCH xb820201f/mask=xbfa0fc1f
+# C6.2.330 STSET, STSETL page C6-1890 line 111216 MATCH xb820301f/mask=xbfa0fc1f
+# C6.2.333 STSMAX, STSMAXL page C6-1896 line 111508 MATCH xb820401f/mask=xbfa0fc1f
+# C6.2.336 STSMIN, STSMINL page C6-1902 line 111801 MATCH xb820501f/mask=xbfa0fc1f
+# C6.2.342 STUMAX, STUMAXL page C6-1914 line 112409 MATCH xb820601f/mask=xbfa0fc1f
+# C6.2.345 STUMIN, STUMINL page C6-1920 line 112703 MATCH xb820701f/mask=xbfa0fc1f
+# C6.2.135 LDADD, LDADDA, LDADDAL, LDADDL page C6-1493 line 88796 MATCH xb8200000/mask=xbf20fc00
+# C6.2.154 LDCLR, LDCLRA, LDCLRAL, LDCLRL page C6-1528 line 90747 MATCH xb8201000/mask=xbf20fc00
+# C6.2.157 LDEOR, LDEORA, LDEORAL, LDEORL page C6-1535 line 91168 MATCH xb8202000/mask=xbf20fc00
+# C6.2.183 LDSET, LDSETA, LDSETAL, LDSETL page C6-1594 line 94655 MATCH xb8203000/mask=xbf20fc00
+# C6.2.186 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL page C6-1601 line 95076 MATCH xb8204000/mask=xbf20fc00
+# C6.2.189 LDSMIN, LDSMINA, LDSMINAL, LDSMINL page C6-1608 line 95497 MATCH xb8205000/mask=xbf20fc00
+# C6.2.198 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL page C6-1627 line 96614 MATCH xb8206000/mask=xbf20fc00
+# C6.2.201 LDUMIN, LDUMINA, LDUMINAL, LDUMINL page C6-1634 line 97035 MATCH xb8207000/mask=xbf20fc00
+# CONSTRUCT xf820001f/mask=xffa08c1f MATCHED 16 DOCUMENTED OPCODES
+# AUNIT --inst xf820001f/mask=xffa08c1f --status nomem
+# size=0b11 (3031)
+
+:st^ls_opc8^ls_lor aa_Xs, [Rn_GPR64xsp]
+is b_3031=0b11 & b_2429=0b111000 & b_23=0 & b_21=1 & b_1515=0 & b_1011=0b00 & b_0004=0b11111 & ls_opc8 & ls_lor & aa_Xs & Rn_GPR64xsp
+{ build ls_opc8; build ls_lor; }
+
+# C6.2.307 STLLRB page C6-1842 line 108609 MATCH x08800000/mask=xffe08000
+# CONSTRUCT x08800000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x08800000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111
+# size=0b00 (3031)
+
+:stllrb aa_Wt, [Rn_GPR64xsp]
+is b_3031=0b00 & b_2329=0b0010001 & b_22=0 & b_21=0 & b_15=0 & aa_Wt & Rn_GPR64xsp
+{ *:1 Rn_GPR64xsp = aa_Wt:1; LORelease(); }
+
+# C6.2.308 STLLRH page C6-1843 line 108673 MATCH x48800000/mask=xffe08000
+# CONSTRUCT x48800000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x48800000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111
+# size=0b01 (3031)
+
+:stllrh aa_Wt, [Rn_GPR64xsp]
+is b_3031=0b01 & b_2329=0b0010001 & b_22=0 & b_21=0 & b_15=0 & aa_Wt & Rn_GPR64xsp
+{ *:2 Rn_GPR64xsp = aa_Wt:2; LORelease(); }
+
+# C6.2.309 STLLR page C6-1844 line 108737 MATCH x88800000/mask=xbfe08000
+# CONSTRUCT x88800000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x88800000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111
+# size=0b10 (3031)
+
+:stllr aa_Wt, [Rn_GPR64xsp]
+is b_3031=0b10 & b_2329=0b0010001 & b_22=0 & b_21=0 & b_15=0 & aa_Wt & Rn_GPR64xsp
+{ *:4 Rn_GPR64xsp = aa_Wt; LORelease(); }
+
+# C6.2.309 STLLR page C6-1844 line 108737 MATCH x88800000/mask=xbfe08000
+# CONSTRUCT xc8800000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xc8800000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111
+# size=0b11 (3031)
+
+:stllr aa_Xt, [Rn_GPR64xsp]
+is b_3031=0b11 & b_2329=0b0010001 & b_22=0 & b_21=0 & b_15=0 & aa_Xt & Rn_GPR64xsp
+{ *:8 Rn_GPR64xsp = aa_Xt; LORelease(); }
+
+# C6.2.310 STLR page C6-1846 line 108821 MATCH x88808000/mask=xbfe08000
+# CONSTRUCT xc8808000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xc8808000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111
+
+:stlr Rt_GPR64, addrReg
+is size.ldstr=3 & b_2429=0x8 & b_23=1 & L=0 & b_21=0 & b_15=1 & addrReg & Rt_GPR64
+{
+ *addrReg = Rt_GPR64;
+}
+
+# C6.2.310 STLR page C6-1846 line 108821 MATCH x88808000/mask=xbfe08000
+# CONSTRUCT x88808000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x88808000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111
+
+:stlr Rt_GPR32, addrReg
+is size.ldstr=2 & b_2429=0x8 & b_23=1 & L=0 & b_21=0 & b_15=1 & addrReg & Rt_GPR32
+{
+ *addrReg = Rt_GPR32;
+}
+
+# C6.2.311 STLRB page C6-1848 line 108904 MATCH x08808000/mask=xffe08000
+# CONSTRUCT x08808000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x08808000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111
+
+:stlrb Rt_GPR32, addrReg
+is size.ldstr=0 & b_2429=0x8 & b_23=1 & L=0 & b_21=0 & b_15=1 & addrReg & Rt_GPR32
+{
+ *addrReg = Rt_GPR32;
+}
+
+# C6.2.312 STLRH page C6-1849 line 108967 MATCH x48808000/mask=xffe08000
+# CONSTRUCT x48808000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x48808000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1620=0b11111 & b_1014=0b11111
+
+:stlrh Rt_GPR32, addrReg
+is size.ldstr=1 & b_2429=0x8 & b_23=1 & L=0 & b_21=0 & b_15=1 & addrReg & Rt_GPR32
+{
+ *addrReg = Rt_GPR32;
+}
+
+# C6.2.313 STLUR page C6-1850 line 109030 MATCH x99000000/mask=xbfe00c00
+# CONSTRUCT x99000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+
+:stlur aa_Wt, addr_SIMM9
+is b_3031=0b10 & b_2129=0b011001000 & b_1011=0b00 & addr_SIMM9 & aa_Wt
+{
+ *addr_SIMM9 = aa_Wt;
+}
+
+# C6.2.313 STLUR page C6-1850 line 109030 MATCH x99000000/mask=xbfe00c00
+# CONSTRUCT xd9000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+
+:stlur aa_Xt, addr_SIMM9
+is b_3031=0b11 & b_2129=0b011001000 & b_1011=0b00 & addr_SIMM9 & aa_Xt
+{
+ *addr_SIMM9 = aa_Xt;
+}
+
+# C6.2.314 STLURB page C6-1852 line 109129 MATCH x19000000/mask=xffe00c00
+# CONSTRUCT x19000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# x19000000/mask=xffe00c00 NOT MATCHED BY ANY CONSTRUCTOR
+
+:stlurb aa_Wt, addr_SIMM9
+is b_2131=0b00011001000 & b_1011=0b00 & addr_SIMM9 & aa_Wt
+{
+ *addr_SIMM9 = aa_Wt:1;
+}
+
+# C6.2.315 STLURH page C6-1854 line 109217 MATCH x59000000/mask=xffe00c00
+# CONSTRUCT x59000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# x59000000/mask=xffe00c00 NOT MATCHED BY ANY CONSTRUCTOR
+
+:stlurh aa_Wt, addr_SIMM9
+is b_2131=0b01011001000 & b_1011=0b00 & addr_SIMM9 & aa_Wt
+{
+ *addr_SIMM9 = aa_Wt:2;
+}
+
+# C6.2.316 STLXP page C6-1856 line 109305 MATCH x88208000/mask=xbfe08000
+# CONSTRUCT xc8208000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xc8208000/mask=xffe08000 --status nomem
+
+:stlxp Rs_GPR32, Rt_GPR64, Rt2_GPR64, addrReg
+is size.ldstr=3 & b_2429=0x8 & b_23=0 & L=0 & b_21=1 & Rs_GPR32 & b_15=1 & Rt2_GPR64 & addrReg & Rt_GPR64 & Rs_GPR64
+{
+ status:1 = 1;
+ rsize:1 = 16;
+ check:1 = ExclusiveMonitorPass(addrReg, rsize);
+ if (!check) goto ;
+ *addrReg = Rt_GPR64;
+ *(addrReg + 4) = Rt2_GPR64;
+ status = ExclusiveMonitorsStatus();
+
+ Rs_GPR64 = zext(status);
+}
+
+# C6.2.316 STLXP page C6-1856 line 109305 MATCH x88208000/mask=xbfe08000
+# CONSTRUCT x88208000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x88208000/mask=xffe08000 --status nomem
+
+:stlxp Rs_GPR32, Rt_GPR32, Rt2_GPR32, addrReg
+is size.ldstr=2 & b_2429=0x8 & b_23=0 & L=0 & b_21=1 & Rs_GPR32 & b_15=1 & Rt2_GPR32 & addrReg & Rt_GPR32 & Rs_GPR64
+{
+ status:1 = 1;
+ rsize:1 = 16;
+ check:1 = ExclusiveMonitorPass(addrReg, rsize);
+ if (!check) goto ;
+ *addrReg = Rt_GPR32;
+ *(addrReg + 4) = Rt2_GPR32;
+ status = ExclusiveMonitorsStatus();
+
+ Rs_GPR64 = zext(status);
+}
+
+# C6.2.317 STLXR page C6-1859 line 109472 MATCH x88008000/mask=xbfe08000
+# CONSTRUCT xc8008000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xc8008000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1014=0b11111
+
+:stlxr Rs_GPR32, Rt_GPR64, addrReg
+is size.ldstr=3 & b_2429=0x8 & b_23=0 & L=0 & b_21=0 & Rs_GPR32 & b_15=1 & addrReg & Rt_GPR64 & Rs_GPR64
+{
+ status:1 = 1;
+ rsize:1 = 16;
+ check:1 = ExclusiveMonitorPass(addrReg, rsize);
+ if (!check) goto ;
+ *addrReg = Rt_GPR64;
+ status = ExclusiveMonitorsStatus();
+
+ Rs_GPR64 = zext(status);
+}
+
+# C6.2.317 STLXR page C6-1859 line 109472 MATCH x88008000/mask=xbfe08000
+# CONSTRUCT x88008000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x88008000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1014=0b11111
+
+:stlxr Rs_GPR32, Rt_GPR32, addrReg
+is size.ldstr=2 & b_2429=0x8 & b_23=0 & L=0 & b_21=0 & Rs_GPR32 & b_15=1 & addrReg & Rt_GPR32 & Rs_GPR64
+{
+ status:1 = 1;
+ rsize:1 = 16;
+ check:1 = ExclusiveMonitorPass(addrReg, rsize);
+ if (!check) goto ;
+ *addrReg = Rt_GPR32;
+ status = ExclusiveMonitorsStatus();
+
+ Rs_GPR64 = zext(status);
+}
+
+# C6.2.318 STLXRB page C6-1862 line 109627 MATCH x08008000/mask=xffe08000
+# CONSTRUCT x08008000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x08008000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1014=0b11111
+
+:stlxrb Rs_GPR32, Rt_GPR32, addrReg
+is size.ldstr=0 & b_2429=0x8 & b_23=0 & L=0 & b_21=0 & Rs_GPR32 & b_15=1 & addrReg & Rt_GPR32 & Rs_GPR64
+{
+ status:1 = 1;
+ rsize:1 = 16;
+ check:1 = ExclusiveMonitorPass(addrReg, rsize);
+ if (!check) goto ;
+ local tmp:4 = Rt_GPR32;
+ *addrReg = tmp:1;
+ status = ExclusiveMonitorsStatus();
+
+ Rs_GPR64 = zext(status);
+}
+
+# C6.2.319 STLXRH page C6-1864 line 109754 MATCH x48008000/mask=xffe08000
+# CONSTRUCT x48008000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x48008000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1014=0b11111
+
+:stlxrh Rs_GPR32, Rt_GPR32, addrReg
+is size.ldstr=1 & b_2429=0x8 & b_23=0 & L=0 & b_21=0 & Rs_GPR32 & b_15=1 & addrReg & Rt_GPR32 & Rs_GPR64
+{
+ status:1 = 1;
+ rsize:1 = 16;
+ check:1 = ExclusiveMonitorPass(addrReg, rsize);
+ if (!check) goto ;
+ local tmp:4 = Rt_GPR32;
+ *addrReg = tmp:2;
+ status = ExclusiveMonitorsStatus();
+
+ Rs_GPR64 = zext(status);
+}
+
+# C6.2.320 STNP page C6-1866 line 109888 MATCH x28000000/mask=x7fc00000
+# CONSTRUCT x28000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x28000000/mask=xffc00000 --status nomem
+
+:stnp Rt_GPR32, Rt2_GPR32, addrPairIndexed
+is b_3031=0b00 & b_2229=0b10100000 & Rt2_GPR32 & addrPairIndexed & Rt_GPR32
+{
+ data1:4 = Rt_GPR32;
+ data2:4 = Rt2_GPR32;
+ build addrPairIndexed;
+ *addrPairIndexed = data1;
+ *(addrPairIndexed + 4) = data2;
+}
+
+# C6.2.320 STNP page C6-1866 line 109888 MATCH x28000000/mask=x7fc00000
+# CONSTRUCT xa8000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xa8000000/mask=xffc00000 --status nomem
+
+:stnp Rt_GPR64, Rt2_GPR64, addrPairIndexed
+is b_3031=0b10 & b_2229=0b10100000 & Rt2_GPR64 & addrPairIndexed & Rt_GPR64
+{
+ data1:8 = Rt_GPR64;
+ data2:8 = Rt2_GPR64;
+ build addrPairIndexed;
+ *addrPairIndexed = data1;
+ *(addrPairIndexed + 8) = data2;
+}
+
+# C6.2.321 STP page C6-1868 line 109996 MATCH x28800000/mask=x7fc00000
+# C6.2.321 STP page C6-1868 line 109996 MATCH x29800000/mask=x7fc00000
+# C6.2.321 STP page C6-1868 line 109996 MATCH x29000000/mask=x7fc00000
+# C6.2.320 STNP page C6-1866 line 109888 MATCH x28000000/mask=x7fc00000
+# CONSTRUCT x28000000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst x28000000/mask=xfe400000 --status nomem
+
+:stp Rt_GPR32, Rt2_GPR32, addrPairIndexed
+is b_3031=0b00 & b_2529=0b10100 & b_22=0b0 & Rt2_GPR32 & addrPairIndexed & Rt_GPR32
+{
+ data1:4 = Rt_GPR32;
+ data2:4 = Rt2_GPR32;
+ build addrPairIndexed;
+ *addrPairIndexed = data1;
+ *(addrPairIndexed + 4) = data2;
+}
+
+# C6.2.321 STP page C6-1868 line 109996 MATCH x28800000/mask=x7fc00000
+# C6.2.321 STP page C6-1868 line 109996 MATCH x29800000/mask=x7fc00000
+# C6.2.321 STP page C6-1868 line 109996 MATCH x29000000/mask=x7fc00000
+# C6.2.320 STNP page C6-1866 line 109888 MATCH x28000000/mask=x7fc00000
+# CONSTRUCT xa8000000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst xa8000000/mask=xfe400000 --status nomem
+
+:stp Rt_GPR64, Rt2_GPR64, addrPairIndexed
+is b_3031=0b10 & b_2529=0b10100 & b_22=0b0 & Rt2_GPR64 & addrPairIndexed & Rt_GPR64
+{
+ data1:8 = Rt_GPR64;
+ data2:8 = Rt2_GPR64;
+ build addrPairIndexed;
+ *addrPairIndexed = data1;
+ *(addrPairIndexed + 8) = data2;
+}
+
+# C6.2.322 STR (immediate) page C6-1871 line 110209 MATCH xb9000000/mask=xbfc00000
+# CONSTRUCT xb9000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xb9000000/mask=xffc00000 --status nomem
+
+:str Rt_GPR32, addrUIMM
+is size.ldstr=2 & b_2729=7 & v=0 & b_2425=1 & b_23=0 & b_2222=0 & addrUIMM & Rn_GPR64xsp & Rt_GPR32
+{
+ *addrUIMM = Rt_GPR32;
+}
+
+# C6.2.322 STR (immediate) page C6-1871 line 110209 MATCH xb8000400/mask=xbfe00c00
+# C6.2.322 STR (immediate) page C6-1871 line 110209 MATCH xb8000c00/mask=xbfe00c00
+# C6.2.337 STTR page C6-1904 line 111916 MATCH xb8000800/mask=xbfe00c00
+# C6.2.346 STUR page C6-1922 line 112818 MATCH xb8000000/mask=xbfe00c00
+# CONSTRUCT xb8000000/mask=xffe00000 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst xb8000000/mask=xffe00000 --status nomem
+
+:st^UnscPriv^"r" Rt_GPR32, addrIndexed
+is size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR32
+{
+ data1:4 = Rt_GPR32;
+ build addrIndexed;
+ *addrIndexed = data1;
+}
+
+# C6.2.322 STR (immediate) page C6-1871 line 110209 MATCH xb8000400/mask=xbfe00c00
+# C6.2.322 STR (immediate) page C6-1871 line 110209 MATCH xb8000c00/mask=xbfe00c00
+# CONSTRUCT xb8000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xb8000400/mask=xffe00400 --status nomem
+
+:str Rt_GPR32, addrIndexed
+is size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR32
+{
+ data1:4 = Rt_GPR32;
+ build addrIndexed;
+ *addrIndexed = data1;
+}
+
+# C6.2.322 STR (immediate) page C6-1871 line 110209 MATCH xb9000000/mask=xbfc00000
+# CONSTRUCT xf9000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xf9000000/mask=xffc00000 --status nomem
+
+:str Rt_GPR64, addrUIMM
+is size.ldstr=3 & b_2729=7 & v=0 & b_2425=1 & b_23=0 & b_2222=0 & addrUIMM & Rn_GPR64xsp & Rt_GPR64
+{
+ *addrUIMM = Rt_GPR64;
+}
+
+# C6.2.322 STR (immediate) page C6-1871 line 110209 MATCH xb8000400/mask=xbfe00c00
+# C6.2.322 STR (immediate) page C6-1871 line 110209 MATCH xb8000c00/mask=xbfe00c00
+# CONSTRUCT xf8000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xf8000400/mask=xffe00400 --status nomem
+
+:str Rt_GPR64, addrIndexed
+is size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR64
+{
+ data1:8 = Rt_GPR64;
+ build addrIndexed;
+ *addrIndexed = data1;
+}
+
+# C6.2.323 STR (register) page C6-1874 line 110394 MATCH xb8200800/mask=xbfe00c00
+# CONSTRUCT xb8200800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xb8200800/mask=xffe00c00 --status nomem
+
+:str Rt_GPR32, addrIndexed
+is size.ldstr=2 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR32
+{
+ data1:4 = Rt_GPR32;
+ build addrIndexed;
+ *addrIndexed = data1;
+}
+
+# C6.2.323 STR (register) page C6-1874 line 110394 MATCH xb8200800/mask=xbfe00c00
+# CONSTRUCT xf8200800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xf8200800/mask=xffe00c00 --status nomem
+
+:str Rt_GPR64, addrIndexed
+is size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR64
+{
+ data1:8 = Rt_GPR64;
+ build addrIndexed;
+ *addrIndexed = data1;
+}
+
+# C6.2.324 STRB (immediate) page C6-1876 line 110516 MATCH x39000000/mask=xffc00000
+# CONSTRUCT x39000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x39000000/mask=xffc00000 --status nomem
+
+:strb Rt_GPR32, addrIndexed
+is size.ldstr=0 & b_2729=7 & v=0 & b_2425=1 & b_23=0 & b_2222=0 & addrIndexed & Rt_GPR32
+{
+ tmp:4 = Rt_GPR32;
+ build addrIndexed;
+ *addrIndexed = tmp:1;
+}
+
+# C6.2.324 STRB (immediate) page C6-1876 line 110516 MATCH x38000400/mask=xffe00c00
+# C6.2.324 STRB (immediate) page C6-1876 line 110516 MATCH x38000c00/mask=xffe00c00
+# CONSTRUCT x38000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x38000400/mask=xffe00400 --status nomem
+
+:strb Rt_GPR32, addrIndexed
+is size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR32
+{
+ tmp:4 = Rt_GPR32;
+ build addrIndexed;
+ *addrIndexed = tmp:1;
+}
+
+# C6.2.325 STRB (register) page C6-1879 line 110678 MATCH x38200800/mask=xffe00c00
+# CONSTRUCT x38200800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x38200800/mask=xffe00c00 --status nomem
+
+:strb Rt_GPR32, addrIndexed
+is size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR32
+{
+ tmp:4 = Rt_GPR32;
+ build addrIndexed;
+ *addrIndexed = tmp:1;
+}
+
+# C6.2.326 STRH (immediate) page C6-1881 line 110781 MATCH x79000000/mask=xffc00000
+# CONSTRUCT x79000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x79000000/mask=xffc00000 --status nomem
+
+:strh Rt_GPR32, addrUIMM
+is size.ldstr=1 & b_2729=7 & v=0 & b_2425=1 & b_23=0 & b_2222=0 & addrUIMM & Rn_GPR64xsp & Rt_GPR32
+{
+ tmp:4 = Rt_GPR32;
+ *addrUIMM = tmp:2;
+}
+
+# C6.2.326 STRH (immediate) page C6-1881 line 110781 MATCH x78000400/mask=xffe00c00
+# C6.2.326 STRH (immediate) page C6-1881 line 110781 MATCH x78000c00/mask=xffe00c00
+# CONSTRUCT x78000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x78000400/mask=xffe00400 --status nomem
+
+:strh Rt_GPR32, addrIndexed
+is size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & b_1010=1 & addrIndexed & Rt_GPR32
+{
+ tmp:4 = Rt_GPR32;
+ build addrIndexed;
+ *addrIndexed = tmp:2;
+}
+
+# C6.2.327 STRH (register) page C6-1884 line 110943 MATCH x78200800/mask=xffe00c00
+# CONSTRUCT x78200800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x78200800/mask=xffe00c00 --status nomem
+
+:strh Rt_GPR32, addrIndexed
+is size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=1 & b_1011=2 & addrIndexed & Rt_GPR32
+{
+ tmp:4 = Rt_GPR32;
+ build addrIndexed;
+ *addrIndexed = tmp:2;
+}
+
+# C6.2.337 STTR page C6-1904 line 111916 MATCH xb8000800/mask=xbfe00c00
+# CONSTRUCT xf8000800/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xf8000800/mask=xffe00c00 --status nomem
+
+:st^UnscPriv^"r" Rt_GPR64, addrIndexed
+is size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_2223=0 & b_2121=0 & b_1011=2 & UnscPriv & addrIndexed & Rt_GPR64
+{
+ data1:8 = Rt_GPR64;
+ build addrIndexed;
+ *addrIndexed = data1;
+}
+
+# C6.2.338 STTRB page C6-1906 line 112029 MATCH x38000800/mask=xffe00c00
+# C6.2.347 STURB page C6-1924 line 112913 MATCH x38000000/mask=xffe00c00
+# CONSTRUCT x38000000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x38000000/mask=xffe00000 --status nomem
+
+:st^UnscPriv^"rb" Rt_GPR32, addrIndexed
+is size.ldstr=0 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR32
+{
+ local tmp:4 = Rt_GPR32;
+ build addrIndexed;
+ *addrIndexed = tmp:1;
+}
+
+# C6.2.339 STTRH page C6-1908 line 112130 MATCH x78000800/mask=xffe00c00
+# C6.2.348 STURH page C6-1925 line 112984 MATCH x78000000/mask=xffe00c00
+# CONSTRUCT x78000000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x78000000/mask=xffe00000 --status nomem
+
+:st^UnscPriv^"rh" Rt_GPR32, addrIndexed
+is size.ldstr=1 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & UnscPriv & addrIndexed & Rt_GPR32
+{
+ local tmp:4 = Rt_GPR32;
+ build addrIndexed;
+ *addrIndexed = tmp:2;
+}
+
+# C6.2.346 STUR page C6-1922 line 112818 MATCH xb8000000/mask=xbfe00c00
+# CONSTRUCT xf8000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xf8000000/mask=xffe00c00 --status nomem
+
+:st^UnscPriv^"r" Rt_GPR64, addrIndexed
+is size.ldstr=3 & b_2729=7 & v=0 & b_2425=0 & b_23=0 & b_2122=0 & b_1011=0 & UnscPriv & addrIndexed & Rt_GPR64
+{
+ data1:8 = Rt_GPR64;
+ build addrIndexed;
+ *addrIndexed = data1;
+}
+
+# C6.2.349 STXP page C6-1926 line 113055 MATCH x88200000/mask=xbfe08000
+# CONSTRUCT xc8200000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xc8200000/mask=xffe08000 --status nomem
+
+:stxp Rs_GPR32, Rt_GPR64, Rt2_GPR64, addrReg
+is size.ldstr=3 & b_2429=0x8 & b_23=0 & L=0 & b_21=1 & Rs_GPR32 & b_15=0 & Rt2_GPR64 & addrReg & Rt_GPR64 & Rs_GPR64
+{
+ status:1 = 1;
+ rsize:1 = 16;
+ check:1 = ExclusiveMonitorPass(addrReg, rsize);
+ if (!check) goto ;
+ *addrReg = Rt_GPR64;
+ *(addrReg + 8) = Rt2_GPR64;
+ status = ExclusiveMonitorsStatus();
+
+ Rs_GPR64 = zext(status);
+}
+
+# C6.2.349 STXP page C6-1926 line 113055 MATCH x88200000/mask=xbfe08000
+# CONSTRUCT x88200000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x88200000/mask=xffe08000 --status nomem
+
+:stxp Rs_GPR32, Rt_GPR32, Rt2_GPR32, addrReg
+is size.ldstr=2 & b_2429=0x8 & b_23=0 & L=0 & b_21=1 & Rs_GPR32 & b_15=0 & Rt2_GPR32 & addrReg & Rt_GPR32 & Rs_GPR64
+{
+ status:1 = 1;
+ rsize:1 = 16;
+ check:1 = ExclusiveMonitorPass(addrReg, rsize);
+ if (!check) goto ;
+ *addrReg = Rt_GPR32;
+ *(addrReg + 4) = Rt2_GPR32;
+ status = ExclusiveMonitorsStatus();
+
+ Rs_GPR64 = zext(status);
+}
+
+# C6.2.350 STXR page C6-1929 line 113222 MATCH x88000000/mask=xbfe08000
+# CONSTRUCT xc8000000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xc8000000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1014=0b11111
+
+:stxr Rs_GPR32, Rt_GPR64, addrReg
+is size.ldstr=3 & b_2429=0x8 & b_23=0 & L=0 & b_21=0 & Rs_GPR32 & b_15=0 & addrReg & Rt_GPR64 & Rs_GPR64
+{
+ status:1 = 1;
+ rsize:1 = 16;
+ check:1 = ExclusiveMonitorPass(addrReg, rsize);
+ if (!check) goto ;
+ *addrReg = Rt_GPR64;
+ status = ExclusiveMonitorsStatus();
+
+ Rs_GPR64 = zext(status);
+}
+
+# C6.2.350 STXR page C6-1929 line 113222 MATCH x88000000/mask=xbfe08000
+# CONSTRUCT x88000000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x88000000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1014=0b11111
+
+:stxr Rs_GPR32, Rt_GPR32, addrReg
+is size.ldstr=2 & b_2429=0x8 & b_23=0 & L=0 & b_21=0 & Rs_GPR32 & b_15=0 & addrReg & Rt_GPR32 & Rs_GPR64
+{
+ status:1 = 1;
+ rsize:1 = 16;
+ check:1 = ExclusiveMonitorPass(addrReg, rsize);
+ if (!check) goto ;
+ *addrReg = Rt_GPR32;
+ status = ExclusiveMonitorsStatus();
+
+ Rs_GPR64 = zext(status);
+}
+
+# C6.2.351 STXRB page C6-1931 line 113368 MATCH x08000000/mask=xffe08000
+# CONSTRUCT x08000000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x08000000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1014=0b11111
+
+:stxrb Rs_GPR32, Rt_GPR32, addrReg
+is size.ldstr=0 & b_2429=0x8 & b_23=0 & L=0 & b_21=0 & Rs_GPR32 & b_15=0 & addrReg & Rt_GPR32 & Rs_GPR64
+{
+ status:1 = 1;
+ rsize:1 = 16;
+ check:1 = ExclusiveMonitorPass(addrReg, rsize);
+ if (!check) goto ;
+ local tmp:4 = Rt_GPR32;
+ *addrReg = tmp:1;
+ status = ExclusiveMonitorsStatus();
+
+ Rs_GPR64 = zext(status);
+}
+
+# C6.2.352 STXRH page C6-1933 line 113496 MATCH x48000000/mask=xffe08000
+# CONSTRUCT x48000000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x48000000/mask=xffe08000 --status nomem
+# To enforce SHOULD BE ONE fields add: b_1014=0b11111
+
+:stxrh Rs_GPR32, Rt_GPR32, addrReg
+is size.ldstr=1 & b_2429=0x8 & b_23=0 & L=0 & b_21=0 & Rs_GPR32 & b_15=0 & addrReg & Rt_GPR32 & Rs_GPR64
+{
+ status:1 = 1;
+ rsize:1 = 16;
+ check:1 = ExclusiveMonitorPass(addrReg, rsize);
+ if (!check) goto ;
+ local tmp:4 = Rt_GPR32;
+ *addrReg = tmp:2;
+ status = ExclusiveMonitorsStatus();
+
+ Rs_GPR64 = zext(status);
+}
+
+# C6.2.356 SUB (extended register) page C6-1940 line 113972 MATCH x4b200000/mask=x7fe00000
+# CONSTRUCT x4b200000/mask=xffe00000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x4b200000/mask=xffe00000 --status pass
+
+:sub Rd_GPR32wsp, Rn_GPR32wsp, ExtendRegShift32
+is sf=0 & op=1 & S=0 & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift32 & Rn_GPR32wsp & Rd_GPR32wsp & Rd_GPR64xsp
+{
+ tmp_2:4 = ExtendRegShift32;
+ tmp_1:4 = Rn_GPR32wsp - tmp_2;
+ Rd_GPR64xsp = zext(tmp_1);
+}
+
+# C6.2.356 SUB (extended register) page C6-1940 line 113972 MATCH x4b200000/mask=x7fe00000
+# CONSTRUCT xcb200000/mask=xffe00000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xcb200000/mask=xffe00000 --status pass
+
+:sub Rd_GPR64xsp, Rn_GPR64xsp, ExtendRegShift64
+is sf=1 & op=1 & S=0 & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift64 & Rn_GPR64xsp & Rd_GPR64xsp
+{
+ tmp_2:8 = ExtendRegShift64;
+ tmp_1:8 = Rn_GPR64xsp - tmp_2;
+ Rd_GPR64xsp = tmp_1;
+}
+
+# C6.2.357 SUB (immediate) page C6-1943 line 114120 MATCH x51000000/mask=x7f800000
+# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000
+# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f
+# CONSTRUCT x51000000/mask=xdf000000 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst x51000000/mask=xdf000000 --status pass --comment "flags"
+
+:sub^SBIT_CZNO Rd_GPR32xsp, Rn_GPR32xsp, ImmShift32
+is sf=0 & b_30=1 & S & SBIT_CZNO & b_2428=0x11 & ImmShift32 & Rn_GPR32xsp & Rd_GPR32xsp & Rd_GPR64xsp
+{
+ subflags(Rn_GPR32xsp, ImmShift32);
+ tmp:4 = Rn_GPR32xsp - ImmShift32;
+ resultflags(tmp);
+ build SBIT_CZNO;
+ Rd_GPR64xsp = zext(tmp);
+}
+
+# C6.2.357 SUB (immediate) page C6-1943 line 114120 MATCH x51000000/mask=x7f800000
+# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000
+# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f
+# CONSTRUCT xd1000000/mask=xdf000000 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst xd1000000/mask=xdf000000 --status pass --comment "flags"
+
+:sub^SBIT_CZNO Rd_GPR64xsp, Rn_GPR64xsp, ImmShift64
+is sf=1 & b_30=1 & S & SBIT_CZNO & b_2428=0x11 & ImmShift64 & Rn_GPR64xsp & Rd_GPR64xsp
+{
+ subflags(Rn_GPR64xsp, ImmShift64);
+ Rd_GPR64xsp = Rn_GPR64xsp - ImmShift64;
+ resultflags(Rd_GPR64xsp);
+ build SBIT_CZNO;
+}
+
+# C6.2.357 SUB (immediate) page C6-1943 line 114120 MATCH x51000000/mask=x7f800000
+# CONSTRUCT x51000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x51000000/mask=xffc00000 --status pass
+
+:sub Rd_GPR32wsp, Rn_GPR32wsp, Imm12_addsubimm_operand_i32_negimm_lsl0
+is sf=0 & op=1 & S=0 & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i32_negimm_lsl0 & Rn_GPR32wsp & Rd_GPR32wsp & Rd_GPR64xsp
+{
+ tmp_2:4 = Imm12_addsubimm_operand_i32_negimm_lsl0;
+ tmp_1:4 = Rn_GPR32wsp - tmp_2;
+ Rd_GPR64xsp = zext(tmp_1);
+}
+
+# C6.2.357 SUB (immediate) page C6-1943 line 114120 MATCH x51000000/mask=x7f800000
+# CONSTRUCT x51400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x51400000/mask=xffc00000 --status pass
+
+:sub Rd_GPR32wsp, Rn_GPR32wsp, Imm12_addsubimm_operand_i32_negimm_lsl12
+is sf=0 & op=1 & S=0 & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i32_negimm_lsl12 & Rn_GPR32wsp & Rd_GPR32wsp & Rd_GPR64xsp
+{
+ tmp_2:4 = Imm12_addsubimm_operand_i32_negimm_lsl12;
+ tmp_1:4 = Rn_GPR32wsp - tmp_2;
+ Rd_GPR64xsp = zext(tmp_1);
+}
+
+# C6.2.357 SUB (immediate) page C6-1943 line 114120 MATCH x51000000/mask=x7f800000
+# CONSTRUCT xd1000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd1000000/mask=xffc00000 --status pass
+
+:sub Rd_GPR64xsp, Rn_GPR64xsp, Imm12_addsubimm_operand_i64_negimm_lsl0
+is sf=1 & op=1 & S=0 & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i64_negimm_lsl0 & Rn_GPR64xsp & Rd_GPR64xsp
+{
+ tmp_2:8 = Imm12_addsubimm_operand_i64_negimm_lsl0;
+ tmp_1:8 = Rn_GPR64xsp - tmp_2;
+ Rd_GPR64xsp = tmp_1;
+}
+
+# C6.2.357 SUB (immediate) page C6-1943 line 114120 MATCH x51000000/mask=x7f800000
+# CONSTRUCT xd1400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd1400000/mask=xffc00000 --status pass
+
+:sub Rd_GPR64xsp, Rn_GPR64xsp, Imm12_addsubimm_operand_i64_negimm_lsl12
+is sf=1 & op=1 & S=0 & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i64_negimm_lsl12 & Rn_GPR64xsp & Rd_GPR64xsp
+{
+ tmp_2:8 = Imm12_addsubimm_operand_i64_negimm_lsl12;
+ tmp_1:8 = Rn_GPR64xsp - tmp_2;
+ Rd_GPR64xsp = tmp_1;
+}
+
+# C6.2.358 SUB (shifted register) page C6-1945 line 114221 MATCH x4b000000/mask=x7f200000
+# C6.2.234 NEG (shifted register) page C6-1694 line 100243 MATCH x4b0003e0/mask=x7f2003e0
+# CONSTRUCT x4b000000/mask=xff200000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x4b000000/mask=xff200000 --status pass
+
+:sub Rd_GPR32, Rn_GPR32, RegShift32
+is sf=0 & op=1 & s=0 & b_2428=0xb & b_2121=0 & RegShift32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp_2:4 = RegShift32;
+ tmp_1:4 = Rn_GPR32 - tmp_2;
+ Rd_GPR64 = zext(tmp_1);
+}
+
+# C6.2.358 SUB (shifted register) page C6-1945 line 114221 MATCH x4b000000/mask=x7f200000
+# C6.2.234 NEG (shifted register) page C6-1694 line 100243 MATCH x4b0003e0/mask=x7f2003e0
+# CONSTRUCT xcb000000/mask=xff200000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xcb000000/mask=xff200000 --status pass
+
+:sub Rd_GPR64, Rn_GPR64, RegShift64
+is sf=1 & op=1 & s=0 & b_2428=0xb & b_2121=0 & RegShift64 & Rn_GPR64 & Rd_GPR64
+{
+ tmp_2:8 = RegShift64;
+ tmp_1:8 = Rn_GPR64 - tmp_2;
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.362 SUBS (extended register) page C6-1950 line 114543 MATCH x6b200000/mask=x7fe00000
+# C6.2.62 CMP (extended register) page C6-1252 line 73406 MATCH x6b20001f/mask=x7fe0001f
+# CONSTRUCT x6b200000/mask=xffe00000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x6b200000/mask=xffe00000 --status pass --comment "flags"
+
+:subs Rd_GPR32, Rn_GPR32wsp, ExtendRegShift32
+is sf=0 & op=1 & S=1 & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift32 & Rn_GPR32wsp & Rd_GPR32 & Rd_GPR64
+{
+ tmp_2:4 = ExtendRegShift32;
+ subflags(Rn_GPR32wsp, tmp_2);
+ tmp_1:4 = Rn_GPR32wsp - tmp_2;
+ resultflags(tmp_1);
+ Rd_GPR64 = zext(tmp_1);
+ affectflags();
+}
+
+# C6.2.362 SUBS (extended register) page C6-1950 line 114543 MATCH x6b200000/mask=x7fe00000
+# C6.2.364 SUBS (shifted register) page C6-1955 line 114807 MATCH x6b000000/mask=x7f200000
+# C6.2.62 CMP (extended register) page C6-1252 line 73406 MATCH x6b20001f/mask=x7fe0001f
+# C6.2.64 CMP (shifted register) page C6-1256 line 73623 MATCH x6b00001f/mask=x7f20001f
+# C6.2.235 NEGS page C6-1696 line 100340 MATCH x6b0003e0/mask=x7f2003e0
+# CONSTRUCT xeb000000/mask=xffc00000 MATCHED 5 DOCUMENTED OPCODES
+# AUNIT --inst xeb000000/mask=xffc00000 --status pass --comment "flags"
+
+:subs Rd_GPR64, Rn_GPR64xsp, ExtendRegShift64
+is sf=1 & op=1 & S=1 & b_2428=0xb & opt=0 & b_2121=1 & ExtendRegShift64 & Rn_GPR64xsp & Rd_GPR64
+{
+ tmp_2:8 = ExtendRegShift64;
+ subflags(Rn_GPR64xsp, tmp_2);
+ tmp_1:8 = Rn_GPR64xsp - tmp_2;
+ resultflags(tmp_1);
+ Rd_GPR64 = tmp_1;
+ affectflags();
+}
+
+# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000
+# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f
+# CONSTRUCT x71000000/mask=xffc00000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x71000000/mask=xffc00000 --status pass --comment "flags"
+
+:subs Rd_GPR32, Rn_GPR32wsp, Imm12_addsubimm_operand_i32_negimm_lsl0
+is sf=0 & op=1 & S=1 & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i32_negimm_lsl0 & Rn_GPR32wsp & Rd_GPR32 & Rd_GPR64
+{
+ tmp_2:4 = Imm12_addsubimm_operand_i32_negimm_lsl0;
+ subflags(Rn_GPR32wsp, tmp_2);
+ tmp_1:4 = Rn_GPR32wsp - tmp_2;
+ resultflags(tmp_1);
+ Rd_GPR64 = zext(tmp_1);
+ affectflags();
+}
+
+# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000
+# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f
+# CONSTRUCT x71400000/mask=xffc00000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x71400000/mask=xffc00000 --status pass --comment "flags"
+
+:subs Rd_GPR32, Rn_GPR32wsp, Imm12_addsubimm_operand_i32_negimm_lsl12
+is sf=0 & op=1 & S=1 & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i32_negimm_lsl12 & Rn_GPR32wsp & Rd_GPR32 & Rd_GPR64
+{
+ tmp_2:4 = Imm12_addsubimm_operand_i32_negimm_lsl12;
+ subflags(Rn_GPR32wsp, tmp_2);
+ tmp_1:4 = Rn_GPR32wsp - tmp_2;
+ resultflags(tmp_1);
+ Rd_GPR64 = zext(tmp_1);
+ affectflags();
+}
+
+# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000
+# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f
+# CONSTRUCT xf1000000/mask=xffc00000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xf1000000/mask=xffc00000 --status pass --comment "flags"
+
+:subs Rd_GPR64, Rn_GPR64xsp, Imm12_addsubimm_operand_i64_negimm_lsl0
+is sf=1 & op=1 & S=1 & b_2428=0x11 & shift=0 & Imm12_addsubimm_operand_i64_negimm_lsl0 & Rn_GPR64xsp & Rd_GPR64
+{
+ tmp_2:8 = Imm12_addsubimm_operand_i64_negimm_lsl0;
+ subflags(Rn_GPR64xsp, tmp_2);
+ tmp_1:8 = Rn_GPR64xsp - tmp_2;
+ resultflags(tmp_1);
+ Rd_GPR64 = tmp_1;
+ affectflags();
+}
+
+# C6.2.363 SUBS (immediate) page C6-1953 line 114699 MATCH x71000000/mask=x7f800000
+# C6.2.63 CMP (immediate) page C6-1254 line 73533 MATCH x7100001f/mask=x7f80001f
+# CONSTRUCT xf1400000/mask=xffc00000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xf1400000/mask=xffc00000 --status pass --comment "flags"
+
+:subs Rd_GPR64, Rn_GPR64xsp, Imm12_addsubimm_operand_i64_negimm_lsl12
+is sf=1 & op=1 & S=1 & b_2428=0x11 & shift=1 & Imm12_addsubimm_operand_i64_negimm_lsl12 & Rn_GPR64xsp & Rd_GPR64
+{
+ tmp_2:8 = Imm12_addsubimm_operand_i64_negimm_lsl12;
+ subflags(Rn_GPR64xsp, tmp_2);
+ tmp_1:8 = Rn_GPR64xsp - tmp_2;
+ resultflags(tmp_1);
+ Rd_GPR64 = tmp_1;
+ affectflags();
+}
+
+# C6.2.364 SUBS (shifted register) page C6-1955 line 114807 MATCH x6b000000/mask=x7f200000
+# C6.2.64 CMP (shifted register) page C6-1256 line 73623 MATCH x6b00001f/mask=x7f20001f
+# C6.2.235 NEGS page C6-1696 line 100340 MATCH x6b0003e0/mask=x7f2003e0
+# CONSTRUCT x6b000000/mask=xff200000 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst x6b000000/mask=xff200000 --status pass
+
+:subs Rd_GPR32, Rn_GPR32, RegShift32
+is sf=0 & op=1 & s=1 & b_2428=0xb & b_2121=0 & RegShift32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp_2:4 = RegShift32;
+ subflags(Rn_GPR32, tmp_2);
+ tmp_1:4 = Rn_GPR32 - tmp_2;
+ resultflags(tmp_1);
+ Rd_GPR64 = zext(tmp_1);
+ affectflags();
+}
+
+# C6.2.364 SUBS (shifted register) page C6-1955 line 114807 MATCH x6b000000/mask=x7f200000
+# C6.2.64 CMP (shifted register) page C6-1256 line 73623 MATCH x6b00001f/mask=x7f20001f
+# C6.2.235 NEGS page C6-1696 line 100340 MATCH x6b0003e0/mask=x7f2003e0
+# CONSTRUCT xeb000000/mask=xff200000 MATCHED 3 DOCUMENTED OPCODES
+# AUNIT --inst xeb000000/mask=xff200000 --status pass
+
+:subs Rd_GPR64, Rn_GPR64, RegShift64
+is sf=1 & op=1 & s=1 & b_2428=0xb & b_2121=0 & RegShift64 & Rn_GPR64 & Rd_GPR64 & Rd
+{
+ tmp_2:8 = RegShift64;
+ subflags(Rn_GPR64, tmp_2);
+ tmp_1:8 = Rn_GPR64 - tmp_2;
+ resultflags(tmp_1);
+ Rd_GPR64 = tmp_1;
+ affectflags();
+}
+
+# C6.2.365 SVC page C6-1957 line 114930 MATCH xd4000001/mask=xffe0001f
+# CONSTRUCT xd4000001/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd4000001/mask=xffe0001f --status nodest
+
+:svc imm16
+is b_2431=0xd4 & excCode=0 & imm16 & excCode2=0 & ll=1
+{
+ CallSupervisor(imm16:2);
+}
+
+# C6.2.366 SWPB, SWPAB, SWPALB, SWPLB page C6-1958 line 114973 MATCH x38208000/mask=xff20fc00
+# CONSTRUCT x38208000/mask=xff20fc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x38208000/mask=xff20fc00 --status nomem
+
+# size=0b00 (3031)
+
+:swp^ls_lor^"b" aa_Ws, aa_Wt, [Rn_GPR64xsp]
+is b_3031=0b00 & b_2429=0b111000 & b_21=1 & b_1215=0b1000 & b_1011=0b00 & ls_loa & ls_lor & aa_Wt & ls_data1 & ls_mem1 & aa_Ws & Rn_GPR64xsp
+{ build ls_loa; build ls_data1; ls_opc_swp(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem1; aa_Wt = tmp_ldWn; build ls_lor; }
+
+# C6.2.367 SWPH, SWPAH, SWPALH, SWPLH page C6-1960 line 115079 MATCH x78208000/mask=xff20fc00
+# CONSTRUCT x78208000/mask=xff20fc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x78208000/mask=xff20fc00 --status nomem
+
+# size=0b01 (3031)
+
+:swp^ls_lor^"h" aa_Ws, aa_Wt, [Rn_GPR64xsp]
+is b_3031=0b01 & b_2429=0b111000 & b_21=1 & b_1215=0b1000 & b_1011=0b00 & ls_loa & ls_lor & aa_Wt & ls_data2 & ls_mem2 & aa_Ws & Rn_GPR64xsp
+{ build ls_loa; build ls_data2; ls_opc_swp(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem2; aa_Wt = tmp_ldWn; build ls_lor; }
+
+# C6.2.368 SWP, SWPA, SWPAL, SWPL page C6-1962 line 115186 MATCH xb8208000/mask=xbf20fc00
+# CONSTRUCT xb8208000/mask=xff20fc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xb8208000/mask=xff20fc00 --status nomem
+
+# size=0b10 (3031)
+
+:swp^ls_lor aa_Ws, aa_Wt, [Rn_GPR64xsp]
+is b_3031=0b10 & b_2429=0b111000 & b_21=1 & b_1215=0b1000 & b_1011=0b00 & ls_loa & ls_lor & aa_Wt & ls_data4 & ls_mem4 & aa_Ws & Rn_GPR64xsp
+{ build ls_loa; build ls_data4; ls_opc_swp(tmp_ldWn, aa_Ws, tmp_stWn); build ls_mem4; aa_Wt = tmp_ldWn; build ls_lor; }
+
+# C6.2.368 SWP, SWPA, SWPAL, SWPL page C6-1962 line 115186 MATCH xb8208000/mask=xbf20fc00
+# CONSTRUCT xf8208000/mask=xff20fc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xf8208000/mask=xff20fc00 --status nomem
+
+# size=0b11 (3031)
+
+:swp^ls_lor aa_Xs, aa_Xt, [Rn_GPR64xsp]
+is b_3031=0b11 & b_2429=0b111000 & b_21=1 & b_1215=0b1000 & b_1011=0b00 & ls_loa & ls_lor & aa_Xt & ls_data8 & ls_mem8 & aa_Xs & Rn_GPR64xsp
+{ build ls_loa; build ls_data8; ls_opc_swp(tmp_ldXn, aa_Xs, tmp_stXn); build ls_mem8; aa_Xt = tmp_ldXn; build ls_lor; }
+
+# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00
+# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000
+# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000
+# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000
+# CONSTRUCT x93401c00/mask=xfffffc06 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst x93401c00/mask=xfffffc06 --status pass
+
+# Special case of sbfm where imms='000111' and immr='000000'
+
+:sxtb Rd_GPR64, Rn_GPR32
+is ImmR=0x0 & ImmS=0x7 & ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=0 & sf=1 & opc=0 & b_2428=0x13 & b_2323=0 & n=1 & Rn_GPR32 & Rd_GPR64
+{
+ tmp:4 = Rn_GPR32;
+ tmp_byte:1 = tmp:1;
+ result:8 = sext(tmp_byte);
+ Rd_GPR64 = result;
+}
+
+# C6.2.369 SXTB page C6-1964 line 115324 MATCH x13001c00/mask=x7fbffc00
+# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000
+# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000
+# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000
+# CONSTRUCT x13001c00/mask=xfffffc06 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst x13001c00/mask=xfffffc06 --status pass
+
+# Special case of sbfm when ImmS=7 and ImmR=0. Note that this implies ImmS > ImmR-1
+# Otherwise, this might appear to conflict with sbfiz
+
+:sxtb Rd_GPR32, Rn_GPR32
+is ImmR=0x0 & ImmS=0x7 & ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=0 & sf=0 & opc=0 & b_2428=0x13 & b_2323=0 & n=0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp:4 = Rn_GPR32;
+ tmp_byte:1 = tmp:1;
+ result:4 = sext(tmp_byte);
+ Rd_GPR64 = zext(result);
+}
+
+# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00
+# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000
+# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000
+# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000
+# CONSTRUCT x93403c00/mask=xfffffc06 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst x93403c00/mask=xfffffc06 --status pass
+
+# Special case of sbfm where imms='001111' and immr='000000'
+
+:sxth Rd_GPR64, Rn_GPR32
+is ImmR=0x0 & ImmS=0xf & ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=0 & sf=1 & opc=0 & b_2428=0x13 & b_2323=0 & n=1 & Rn_GPR32 & Rd_GPR64
+{
+ tmp:4 = Rn_GPR32;
+ tmp_1:2 = tmp:2;
+ tmp_2:8 = sext(tmp_1);
+ Rd_GPR64 = tmp_2;
+}
+
+# C6.2.370 SXTH page C6-1966 line 115411 MATCH x13003c00/mask=x7fbffc00
+# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000
+# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000
+# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000
+# CONSTRUCT x13003c00/mask=xfffffc06 MATCHED 4 DOCUMENTED OPCODES
+# AUNIT --inst x13003c00/mask=xfffffc06 --status pass
+
+# Special case of sbfm where imms='001111' and immr='000000'
+
+:sxth Rd_GPR32, Rn_GPR32
+is ImmR=0x0 & ImmS=0xf & ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=0 & sf=0 & opc=0 & b_2428=0x13 & b_2323=0 & n=0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp:4 = Rn_GPR32;
+ tmp_1:2 = tmp:2;
+ tmp_2:4 = sext(tmp_1);
+ Rd_GPR64 = zext(tmp_2);
+}
+
+# C6.2.371 SXTW page C6-1968 line 115498 MATCH x93407c00/mask=xfffffc00
+# C6.2.17 ASR (immediate) page C6-1175 line 69498 MATCH x13007c00/mask=x7f807c00
+# C6.2.267 SBFIZ page C6-1751 line 103178 MATCH x13000000/mask=x7f800000
+# C6.2.268 SBFM page C6-1753 line 103272 MATCH x13000000/mask=x7f800000
+# C6.2.269 SBFX page C6-1756 line 103421 MATCH x13000000/mask=x7f800000
+# CONSTRUCT x93407c00/mask=xfffffc06 MATCHED 5 DOCUMENTED OPCODES
+# AUNIT --inst x93407c00/mask=xfffffc06 --status pass
+
+# Special case of sbfm where imms='011111' and immr='000000'
+
+:sxtw Rd_GPR64, Rn_GPR32
+is ImmR=0x0 & ImmS=0x1f & ImmS_EQ_ImmR=0 & ImmS_LT_ImmR=0 & sf=1 & opc=0 & b_2428=0x13 & b_2323=0 & n=1 & Rn_GPR32 & Rd_GPR64
+{
+ tmp:4 = Rn_GPR32;
+ Rd_GPR64 = sext(tmp);
+}
+
+# C6.2.286 SYS page C6-979 line 56782 KEEPWITH
+
+SysArgs: Op1_uimm3, CRn_CRx, CRm_CRx, Op2_uimm3, Rt_GPR64 is Op1_uimm3 & CRn_CRx & CRm_CRx & Op2_uimm3 & aa_Xt & Rt_GPR64 { export Rt_GPR64; }
+SysArgs: Op1_uimm3, CRn_CRx, CRm_CRx, Op2_uimm3 is Op1_uimm3 & CRn_CRx & CRm_CRx & Op2_uimm3 & aa_Xt=31 & Rt_GPR64 { export 0:8; }
+
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# C6.2.19 AT page C6-1179 line 69679 MATCH xd5087800/mask=xfff8fe00
+# C6.2.39 BRB page C6-1212 line 71361 MATCH xd5097200/mask=xffffff00
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# CONSTRUCT xd5080000/mask=xfff80000 MATCHED 6 DOCUMENTED OPCODES
+# AUNIT --inst xd5080000/mask=xfff80000 --status nodest
+
+:sys SysArgs
+is b_1931=0b1101010100001 & Op1_uimm3 & CRn_CRx & CRm_CRx & Op2_uimm3 & SysArgs
+{
+ tmp1:4 = Op1_uimm3;
+ tmp2:4 = CRn_CRx;
+ tmp3:4 = CRm_CRx;
+ tmp4:4 = Op2_uimm3;
+ SysOp_W(tmp1, tmp2, tmp3, tmp4, SysArgs);
+}
+
+# C6.2.373 SYSL page C6-1971 line 115652 MATCH xd5280000/mask=xfff80000
+# CONSTRUCT xd5280000/mask=xfff80000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd5280000/mask=xfff80000 --status nodest
+
+:sysl Rt_GPR64, Op1_uimm3, CRn_CRx, CRm_CRx, Op2_uimm3
+is b_2431=0xd5 & b_2223=0 & l=1 & Op0=1 & Op1_uimm3 & CRn_CRx & CRm_CRx & Op2_uimm3 & aa_Xt & Rt_GPR64
+{
+ tmp1:4 = Op1_uimm3;
+ tmp2:4 = CRn_CRx;
+ tmp3:4 = CRm_CRx;
+ tmp4:4 = Op2_uimm3;
+ Rt_GPR64 = SysOp_R(tmp1, tmp2, tmp3, tmp4);
+}
+
+# C6.2.373 SYSL page C6-1971 line 115652 MATCH xd5280000/mask=xfff80000
+# CONSTRUCT xd528001f/mask=xfff8001f MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xd528001f/mask=xfff8001f --status nodest
+
+:sysl Op1_uimm3, CRn_CRx, CRm_CRx, Op2_uimm3
+is b_2431=0xd5 & b_2223=0 & l=1 & Op0=1 & Op1_uimm3 & CRn_CRx & CRm_CRx & Op2_uimm3 & aa_Xt=31 & Rt_GPR64
+{
+ tmp1:4 = Op1_uimm3;
+ tmp2:4 = CRn_CRx;
+ tmp3:4 = CRm_CRx;
+ tmp4:4 = Op2_uimm3;
+ SysOp_R(tmp1, tmp2, tmp3, tmp4);
+}
+
+# C6.2.374 TBNZ page C6-1972 line 115708 MATCH x37000000/mask=x7f000000
+# C6.2.375 TBZ page C6-1973 line 115766 MATCH x36000000/mask=x7f000000
+# CONSTRUCT xb6000000/mask=xfe000000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xb6000000/mask=xfe000000 --status nodest
+
+:tb^ZeroOp Rd_GPR64, BitPos, Addr14
+is sf=1 & b_2530=0x1b & BitPos & ZeroOp & Addr14 & Rd_GPR64
+{
+ tmp:1 = BitPos;
+ if (tmp == ZeroOp) goto Addr14;
+}
+
+# C6.2.374 TBNZ page C6-1972 line 115708 MATCH x37000000/mask=x7f000000
+# C6.2.375 TBZ page C6-1973 line 115766 MATCH x36000000/mask=x7f000000
+# CONSTRUCT x36000000/mask=xfe000000 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x36000000/mask=xfe000000 --status nodest
+
+:tb^ZeroOp Rd_GPR32, BitPos, Addr14
+is sf=0 & b_2530=0x1b & BitPos & ZeroOp & Addr14 & Rd_GPR32
+{
+ tmp:1 = BitPos;
+ if (tmp == ZeroOp) goto Addr14;
+}
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50c8020/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50c8020/mask=xffffffe0 --status nodest
+
+:tlbi "IPAS2E1IS", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0000 & b_0507=0b001 & Rt_GPR64
+{ TLBI_IPAS2E1IS(Rt_GPR64); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50c80a0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50c80a0/mask=xffffffe0 --status nodest
+
+:tlbi "IPAS2LE1IS", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0000 & b_0507=0b101 & Rt_GPR64
+{ TLBI_IPAS2LE1IS(Rt_GPR64); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5088300/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd5088300/mask=xffffffe0 --status nodest
+
+:tlbi "VMALLE1IS"
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b000
+{ TLBI_VMALLE1IS(); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50c8300/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50c8300/mask=xffffffe0 --status nodest
+
+:tlbi "ALLE2IS"
+is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b000
+{ TLBI_ALLE2IS(); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50e8300/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50e8300/mask=xffffffe0 --status nodest
+
+:tlbi "ALLE3IS"
+is b_1931=0b1101010100001 & b_1618=0b110 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b000
+{ TLBI_ALLE3IS(); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5088320/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd5088320/mask=xffffffe0 --status nodest
+
+:tlbi "VAE1IS", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b001 & Rt_GPR64
+{ TLBI_VAE1IS(Rt_GPR64); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50c8320/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50c8320/mask=xffffffe0 --status nodest
+
+:tlbi "VAE2IS", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b001 & Rt_GPR64
+{ TLBI_VAE2IS(Rt_GPR64); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50e8320/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50e8320/mask=xffffffe0 --status nodest
+
+:tlbi "VAE3IS", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b110 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b001 & Rt_GPR64
+{ TLBI_VAE3IS(Rt_GPR64); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5088340/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd5088340/mask=xffffffe0 --status nodest
+
+:tlbi "ASIDE1IS", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b010 & Rt_GPR64
+{ TLBI_ASIDE1IS(Rt_GPR64); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5088360/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd5088360/mask=xffffffe0 --status nodest
+
+:tlbi "VAAE1IS", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b011 & Rt_GPR64
+{ TLBI_VAAE1IS(Rt_GPR64); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50c8380/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50c8380/mask=xffffffe0 --status nodest
+
+:tlbi "ALLE1IS"
+is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b100
+{ TLBI_ALLE1IS(); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50883a0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50883a0/mask=xffffffe0 --status nodest
+
+:tlbi "VALE1IS", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b101 & Rt_GPR64
+{ TLBI_VALE1IS(Rt_GPR64); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50c83a0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50c83a0/mask=xffffffe0 --status nodest
+
+:tlbi "VALE2IS", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b101 & Rt_GPR64
+{ TLBI_VALE2IS(Rt_GPR64); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50e83a0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50e83a0/mask=xffffffe0 --status nodest
+
+:tlbi "VALE3IS", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b110 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b101 & Rt_GPR64
+{ TLBI_VALE3IS(Rt_GPR64); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50c83c0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50c83c0/mask=xffffffe0 --status nodest
+
+:tlbi "VMALLS12E1IS"
+is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b110
+{ TLBI_VMALLS12E1IS(); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50883e0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50883e0/mask=xffffffe0 --status nodest
+
+:tlbi "VAALE1IS", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0011 & b_0507=0b111 & Rt_GPR64
+{ TLBI_VAALE1IS(Rt_GPR64); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50c8420/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50c8420/mask=xffffffe0 --status nodest
+
+:tlbi "IPAS2E1", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0100 & b_0507=0b001 & Rt_GPR64
+{ TLBI_IPAS2E1(Rt_GPR64); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50c84a0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50c84a0/mask=xffffffe0 --status nodest
+
+:tlbi "IPAS2LE1", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0100 & b_0507=0b101 & Rt_GPR64
+{ TLBI_IPAS2LE1(Rt_GPR64); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5088700/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd5088700/mask=xffffffe0 --status nodest
+
+:tlbi "VMALLE1"
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b000
+{ TLBI_VMALLE1(); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50c8700/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50c8700/mask=xffffffe0 --status nodest
+
+:tlbi "ALLE2"
+is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b000
+{ TLBI_ALLE2(); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50e8700/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50e8700/mask=xffffffe0 --status nodest
+
+:tlbi "ALLE3"
+is b_1931=0b1101010100001 & b_1618=0b110 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b000
+{ TLBI_ALLE3(); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5088720/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd5088720/mask=xffffffe0 --status nodest
+
+:tlbi "VAE1", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b001 & Rt_GPR64
+{ TLBI_VAE1(Rt_GPR64); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50c8720/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50c8720/mask=xffffffe0 --status nodest
+
+:tlbi "VAE2", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b001 & Rt_GPR64
+{ TLBI_VAE2(Rt_GPR64); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50e8720/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50e8720/mask=xffffffe0 --status nodest
+
+:tlbi "VAE3", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b110 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b001 & Rt_GPR64
+{ TLBI_VAE3(Rt_GPR64); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5088740/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd5088740/mask=xffffffe0 --status nodest
+
+:tlbi "ASIDE1", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b010 & Rt_GPR64
+{ TLBI_ASIDE1(Rt_GPR64); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5088760/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd5088760/mask=xffffffe0 --status nodest
+
+:tlbi "VAAE1", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b011 & Rt_GPR64
+{ TLBI_VAAE1(Rt_GPR64); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50c8780/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50c8780/mask=xffffffe0 --status nodest
+
+:tlbi "ALLE1"
+is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b100
+{ TLBI_ALLE1(); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50887a0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50887a0/mask=xffffffe0 --status nodest
+
+:tlbi "VALE1", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b101 & Rt_GPR64
+{ TLBI_VALE1(Rt_GPR64); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50c87a0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50c87a0/mask=xffffffe0 --status nodest
+
+:tlbi "VALE2", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b101 & Rt_GPR64
+{ TLBI_VALE2(Rt_GPR64); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50e87a0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50e87a0/mask=xffffffe0 --status nodest
+
+:tlbi "VALE3", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b110 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b101 & Rt_GPR64
+{ TLBI_VALE3(Rt_GPR64); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50c87c0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50c87c0/mask=xffffffe0 --status nodest
+
+:tlbi "VMALLS12E1"
+is b_1931=0b1101010100001 & b_1618=0b100 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b110
+{ TLBI_VMALLS12E1(); }
+
+# C6.2.378 TLBI page C6-1976 line 115920 MATCH xd5088000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50887e0/mask=xffffffe0 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50887e0/mask=xffffffe0 --status nodest
+
+:tlbi "VAALE1", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b1000 & b_0811=0b0111 & b_0507=0b111 & Rt_GPR64
+{ TLBI_VAALE1(Rt_GPR64); }
+
+# C6.2.382 TST (immediate) page C6-1983 line 116255 MATCH x7200001f/mask=x7f80001f
+# C6.2.14 ANDS (immediate) page C6-1169 line 69185 MATCH x72000000/mask=x7f800000
+# CONSTRUCT x7200001f/mask=xff80001f MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x7200001f/mask=xff80001f --status pass --comment "flags"
+
+:tst Rn_GPR32, DecodeWMask32
+is sf=0 & opc=3 & b_2428=0x12 & b_2323=0 & DecodeWMask32 & Rn_GPR32 & Rd=0x1f
+{
+ tmp_2:4 = DecodeWMask32;
+ tmp_1:4 = Rn_GPR32 & tmp_2;
+ resultflags(tmp_1);
+ affectLflags();
+}
+
+# C6.2.382 TST (immediate) page C6-1983 line 116255 MATCH x7200001f/mask=x7f80001f
+# C6.2.14 ANDS (immediate) page C6-1169 line 69185 MATCH x72000000/mask=x7f800000
+# CONSTRUCT xf200001f/mask=xff80001f MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xf200001f/mask=xff80001f --status pass --comment "flags"
+
+:tst Rn_GPR64, DecodeWMask64
+is sf=1 & opc=3 & b_2428=0x12 & b_2323=0 & DecodeWMask64 & Rn_GPR64 & Rd=0x1f
+{
+ tmp_2:8 = DecodeWMask64;
+ tmp_1:8 = Rn_GPR64 & tmp_2;
+ resultflags(tmp_1);
+ affectLflags();
+}
+
+# C6.2.383 TST (shifted register) page C6-1984 line 116319 MATCH x6a00001f/mask=x7f20001f
+# C6.2.15 ANDS (shifted register) page C6-1171 line 69286 MATCH x6a000000/mask=x7f200000
+# CONSTRUCT x6a00001f/mask=xff20001f MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x6a00001f/mask=xff20001f --status pass --comment "flags"
+
+:tst Rn_GPR32, RegShift32Log
+is sf=0 & opc=3 & b_2428=0xa & N=0 & RegShift32Log & Rn_GPR32 & Rd=0x1f
+{
+ tmp_2:4 = RegShift32Log;
+ tmp_1:4 = Rn_GPR32 & tmp_2;
+ resultflags(tmp_1);
+ affectLflags();
+}
+
+# C6.2.383 TST (shifted register) page C6-1984 line 116319 MATCH x6a00001f/mask=x7f20001f
+# C6.2.15 ANDS (shifted register) page C6-1171 line 69286 MATCH x6a000000/mask=x7f200000
+# CONSTRUCT xea00001f/mask=xff20001f MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xea00001f/mask=xff20001f --status pass --comment "flags"
+
+:tst Rn_GPR64, RegShift64Log
+is sf=1 & opc=3 & b_2428=0xa & N=0 & RegShift64Log & Rn_GPR64 & Rd=0x1f
+{
+ tmp_2:8 = RegShift64Log;
+ tmp_1:8 = Rn_GPR64 & tmp_2;
+ resultflags(tmp_1);
+ affectLflags();
+}
+
+# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000
+# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000
+# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00
+# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000
+# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000
+# C6.2.394 UXTB page C6-2002 line 117228 MATCH x53001c00/mask=xfffffc00
+# C6.2.395 UXTH page C6-2003 line 117288 MATCH x53003c00/mask=xfffffc00
+# CONSTRUCT x53000008/mask=xffe0800c MATCHED 7 DOCUMENTED OPCODES
+# AUNIT --inst x53000008/mask=xffe0800c --status pass
+# Special case of ubfm where UInt(imms) < UInt(immr).
+# Note because LSL is preferred where imms + 1 == immr, we use ImmS_LT_ImmR_minus_1
+# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue();
+
+:ubfiz Rd_GPR32, Rn_GPR32, ubfiz_lsb, ubfiz_width
+is ImmS_LT_ImmR_minus_1=1 & ImmS_EQ_ImmR=0 & sf=0 & opc=2 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & ubfiz_lsb & ubfiz_width & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 & DecodeWMask32 & DecodeTMask32
+{
+ local wmask:4 = DecodeWMask32;
+ local tmask:4 = DecodeTMask32;
+ local src:4 = Rn_GPR32;
+ local bot:4 = ((src>>ImmRConst32)|(src<<(32-ImmRConst32))) & wmask;
+ Rd_GPR64 = zext(bot & tmask);
+}
+
+# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000
+# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000
+# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00
+# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000
+# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000
+# CONSTRUCT xd340000a/mask=xffc0000a MATCHED 5 DOCUMENTED OPCODES
+# AUNIT --inst xd340000a/mask=xffc0000a --status pass
+# Special case of ubfm where UInt(imms) < UInt(immr).
+# Note because LSL is preferred where imms + 1 == immr, we use ImmS_LT_ImmR_minus_1
+
+:ubfiz Rd_GPR64, Rn_GPR64, ubfiz_lsb64, ubfiz_width
+is ImmS_LT_ImmR_minus_1=1 & ImmS_LT_ImmR=1 & sf=1 & opc=2 & b_2428=0x13 & b_2323=0 & n=1 & ImmR_bitfield64_imm & ImmS_bitfield64_imm & ImmRConst64 & ubfiz_lsb64 & ubfiz_width & Rn_GPR64 & Rd_GPR64 & DecodeWMask64 & DecodeTMask64
+{
+ local wmask:8 = DecodeWMask64;
+ local tmask:8 = DecodeTMask64;
+ local src:8 = Rn_GPR64;
+ local bot:8 = ((src>>ImmRConst64)|(src<<(64-ImmRConst64))) & wmask;
+ Rd_GPR64 = bot & tmask;
+}
+
+# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000
+# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000
+# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00
+# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000
+# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000
+# C6.2.394 UXTB page C6-2002 line 117228 MATCH x53001c00/mask=xfffffc00
+# C6.2.395 UXTH page C6-2003 line 117288 MATCH x53003c00/mask=xfffffc00
+# CONSTRUCT x53000000/mask=xffe08000 MATCHED 7 DOCUMENTED OPCODES
+# AUNIT --inst x53000000/mask=xffe08000 --status pass
+# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue();
+
+:ubfm Rd_GPR32, Rn_GPR32, ImmRConst32, ImmSConst32
+is sf=0 & opc=2 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & ImmRConst32 & ImmSConst32 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 & DecodeWMask32 & DecodeTMask32
+{
+ local wmask:4 = DecodeWMask32;
+ local tmask:4 = DecodeTMask32;
+ local src:4 = Rn_GPR32;
+ local bot:4 = ((src>>ImmRConst32)|(src<<(32-ImmRConst32))) & wmask;
+ Rd_GPR64 = zext(bot & tmask);
+}
+
+# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000
+# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000
+# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00
+# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000
+# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000
+# CONSTRUCT xd3400000/mask=xffc00000 MATCHED 5 DOCUMENTED OPCODES
+# AUNIT --inst xd3400000/mask=xffc00000 --status pass
+
+:ubfm Rd_GPR64, Rn_GPR64, ImmRConst64, ImmSConst64
+is sf=1 & opc=2 & b_2428=0x13 & b_2323=0 & n=1 & ImmR_bitfield64_imm & ImmS_bitfield64_imm & ImmRConst64 & ImmSConst64 & Rn_GPR64 & Rd_GPR64 & DecodeWMask64 & DecodeTMask64
+{
+ local wmask:8 = DecodeWMask64;
+ local tmask:8 = DecodeTMask64;
+ local src:8 = Rn_GPR64;
+ local bot:8 = ((src>>ImmRConst64)|(src<<(64-ImmRConst64))) & wmask;
+ Rd_GPR64 = bot & tmask;
+}
+
+# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000
+# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000
+# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00
+# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000
+# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000
+# C6.2.394 UXTB page C6-2002 line 117228 MATCH x53001c00/mask=xfffffc00
+# C6.2.395 UXTH page C6-2003 line 117288 MATCH x53003c00/mask=xfffffc00
+# CONSTRUCT x53000010/mask=xffe0801a MATCHED 7 DOCUMENTED OPCODES
+# AUNIT --inst x53000010/mask=xffe0801a --status pass
+# Special case of ubfm as determined by BFXPreferred()
+# if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue();
+
+:ubfx Rd_GPR32, Rn_GPR32, ImmRConst32, ubfx_width
+is ImmS_ne_1f=1 & ImmS_LT_ImmR=0 & ImmS_LT_ImmR_minus_1=0 & ImmRConst32 & ubfx_width & sf=0 & opc=2 & b_2428=0x13 & b_2323=0 & n=0 & b_21=0 & b_15=0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64 & DecodeWMask32 & DecodeTMask32
+{
+ local wmask:4 = DecodeWMask32;
+ local tmask:4 = DecodeTMask32;
+ local src:4 = Rn_GPR32;
+ local bot:4 = ((src>>ImmRConst32)|(src<<(32-ImmRConst32))) & wmask;
+ Rd_GPR64 = zext(bot & tmask);
+}
+
+# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000
+# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000
+# C6.2.216 LSR (immediate) page C6-1660 line 98490 MATCH x53007c00/mask=x7f807c00
+# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000
+# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000
+# CONSTRUCT xd3400020/mask=xffc0002a MATCHED 5 DOCUMENTED OPCODES
+# AUNIT --inst xd3400020/mask=xffc0002a --status pass
+
+# Special case of ubfm as determined by BFXPreferred()
+
+:ubfx Rd_GPR64, Rn_GPR64, ImmRConst64, ubfx_width
+is ImmS_ne_3f=1 & ImmS_LT_ImmR=0 & ImmS_LT_ImmR_minus_1=0 & ImmRConst64 & ubfx_width & sf=1 & opc=2 & b_2428=0x13 & b_2323=0 & n=1 & ImmR_bitfield64_imm & ImmS_bitfield64_imm & Rn_GPR64 & Rd_GPR64 & DecodeWMask64 & DecodeTMask64
+{
+ local wmask:8 = DecodeWMask64;
+ local tmask:8 = DecodeTMask64;
+ local src:8 = Rn_GPR64;
+ local bot:8 = ((src>>ImmRConst64)|(src<<(64-ImmRConst64))) & wmask;
+ Rd_GPR64 = bot & tmask;
+}
+
+# C6.2.388 UDIV page C6-1994 line 116786 MATCH x1ac00800/mask=x7fe0fc00
+# CONSTRUCT x1ac00800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x1ac00800/mask=xffe0fc00 --status pass
+
+:udiv Rd_GPR32, Rn_GPR32, Rm_GPR32
+is sf=0 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR32 & b_1015=0x2 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ local tmp_1:4 = 0;
+ if (Rm_GPR32 == 0) goto ;
+ tmp_1 = Rn_GPR32 / Rm_GPR32;
+
+ Rd_GPR64 = zext(tmp_1);
+}
+
+# C6.2.388 UDIV page C6-1994 line 116786 MATCH x1ac00800/mask=x7fe0fc00
+# CONSTRUCT x9ac00800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x9ac00800/mask=xffe0fc00 --status pass
+
+:udiv Rd_GPR64, Rn_GPR64, Rm_GPR64
+is sf=1 & b_3030=0 & S=0 & b_2428=0x1a & b_2123=6 & Rm_GPR64 & b_1015=0x2 & Rn_GPR64 & Rd_GPR64
+{
+ local tmp_1:8 = 0;
+ if (Rm_GPR64 == 0) goto ;
+ tmp_1 = Rn_GPR64 / Rm_GPR64;
+
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.389 UMADDL page C6-1995 line 116855 MATCH x9ba00000/mask=xffe08000
+# CONSTRUCT x9ba00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x9ba00000/mask=xffe08000 --status pass
+
+:umaddl Rd_GPR64, Rn_GPR32, Rm_GPR32, Ra_GPR64
+is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=5 & Rm_GPR32 & op.dp3_o0=0 & Ra_GPR64 & Rn_GPR32 & Rd_GPR64
+{
+ tmp_3:8 = zext(Rn_GPR32);
+ tmp_4:8 = zext(Rm_GPR32);
+ tmp_2:8 = tmp_3 * tmp_4;
+ tmp_1:8 = Ra_GPR64 + tmp_2;
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.390 UMNEGL page C6-1997 line 116945 MATCH x9ba0fc00/mask=xffe0fc00
+# C6.2.391 UMSUBL page C6-1998 line 117009 MATCH x9ba08000/mask=xffe08000
+# CONSTRUCT x9ba0fc00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x9ba0fc00/mask=xffe0fc00 --status pass
+
+:umnegl Rd_GPR64, Rn_GPR32, Rm_GPR32
+is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=5 & Rm_GPR32 & op.dp3_o0=1 & Ra=0x1f & Rn_GPR32 & Rd_GPR64
+{
+ tmp_3:8 = zext(Rn_GPR32);
+ tmp_4:8 = zext(Rm_GPR32);
+ tmp_2:8 = tmp_3 * tmp_4;
+ tmp_1:8 = - tmp_2;
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.391 UMSUBL page C6-1998 line 117009 MATCH x9ba08000/mask=xffe08000
+# CONSTRUCT x9ba08000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x9ba08000/mask=xffe08000 --status pass
+
+:umsubl Rd_GPR64, Rn_GPR32, Rm_GPR32, Ra_GPR64
+is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=5 & Rm_GPR32 & op.dp3_o0=1 & Ra_GPR64 & Rn_GPR32 & Rd_GPR64
+{
+ tmp_3:8 = zext(Rn_GPR32);
+ tmp_4:8 = zext(Rm_GPR32);
+ tmp_2:8 = tmp_3 * tmp_4;
+ tmp_1:8 = Ra_GPR64 - tmp_2;
+ Rd_GPR64 = tmp_1;
+}
+
+# C6.2.392 UMULH page C6-2000 line 117098 MATCH x9bc00000/mask=xffe08000
+# CONSTRUCT x9bc00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst x9bc00000/mask=xffe08000 --status pass
+# To enforce SHOULD BE ONE fields add: b_1014=0b11111
+
+:umulh Rd_GPR64, Rn_GPR64, Rm_GPR64
+is sf=1 & op.dp3=0 & b_2428=0x1b & op.dp3_op31=6 & Rm_GPR64 & op.dp3_o0=0 & Ra & Rn_GPR64 & Rd_GPR64
+{
+ local tmpq:16 = zext(Rn_GPR64) * zext(Rm_GPR64);
+ Rd_GPR64 = tmpq(8);
+}
+
+# C6.2.393 UMULL page C6-2001 line 117165 MATCH x9ba07c00/mask=xffe0fc00
+# C6.2.389 UMADDL page C6-1995 line 116855 MATCH x9ba00000/mask=xffe08000
+# CONSTRUCT x9ba07c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst x9ba07c00/mask=xffe0fc00 --status pass
+
+:umull Rd_GPR64, Rn_GPR32, Rm_GPR32
+is sf=1 & op.dp3_op54=0 & b_2428=0x1b & op.dp3_op31=5 & Rm_GPR32 & op.dp3_o0=0 & Ra=0x1f & Rn_GPR32 & Rd_GPR64
+{
+ tmp_3:8 = zext(Rn_GPR32);
+ tmp_4:8 = zext(Rm_GPR32);
+ tmp_2:8 = tmp_3 * tmp_4;
+ Rd_GPR64 = tmp_2;
+}
+
+# C6.2.394 UXTB page C6-2002 line 117228 MATCH x53001c00/mask=xfffffc00
+# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000
+# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000
+# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000
+# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000
+# CONSTRUCT x53001c10/mask=xfffffc1e MATCHED 5 DOCUMENTED OPCODES
+# AUNIT --inst x53001c10/mask=xfffffc1e --status pass
+
+# Alias for ubfm where immr=='000000' and imms='000111'
+# These imply things about the inequalities
+
+:uxtb Rd_GPR32, Rn_GPR32
+is ImmR=0x0 & ImmS=0x7 & ImmS_ne_1f=1 & ImmS_LT_ImmR=0 & ImmS_LT_ImmR_minus_1=0 & ImmS_EQ_ImmR=0 & sf=0 & opc=2 & b_2428=0x13 & b_2323=0 & n=0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp:4 = Rn_GPR32;
+ Rd_GPR64 = zext(tmp:1);
+}
+
+# C6.2.395 UXTH page C6-2003 line 117288 MATCH x53003c00/mask=xfffffc00
+# C6.2.213 LSL (immediate) page C6-1654 line 98214 MATCH x53000000/mask=x7f800000
+# C6.2.384 UBFIZ page C6-1986 line 116416 MATCH x53000000/mask=x7f800000
+# C6.2.385 UBFM page C6-1988 line 116507 MATCH x53000000/mask=x7f800000
+# C6.2.386 UBFX page C6-1991 line 116651 MATCH x53000000/mask=x7f800000
+# CONSTRUCT x53003c10/mask=xfffffc1e MATCHED 5 DOCUMENTED OPCODES
+# AUNIT --inst x53003c10/mask=xfffffc1e --status pass
+
+# Alias for ubfm where immr=='000000' and imms='001111'
+# These imply things about the inequalities
+
+:uxth Rd_GPR32, Rn_GPR32
+is ImmR=0x0 & ImmS=0x0f & ImmS_ne_1f=1 & ImmS_LT_ImmR=0 & ImmS_LT_ImmR_minus_1=0 & ImmS_EQ_ImmR=0 & sf=0 & opc=2 & b_2428=0x13 & b_2323=0 & n=0 & Rn_GPR32 & Rd_GPR32 & Rd_GPR64
+{
+ tmp:4 = Rn_GPR32;
+ Rd_GPR64 = zext(tmp:2);
+}
+
+# C6.2.396 WFE page C6-2004 line 117348 MATCH xd503205f/mask=xffffffff
+# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f
+# CONSTRUCT xd503205f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd503205f/mask=xffffffff --status nodest
+
+:wfe
+is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low=2 & Rt=0x1f
+{
+ WaitForEvent();
+}
+
+# C6.2.397 WFET page C6-2005 line 117387 MATCH xd5031000/mask=xffffffe0
+# CONSTRUCT xd5031000/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES
+# xd5031000/mask=xffffffe0 NOT MATCHED BY ANY CONSTRUCTOR
+# b_0031=110101010000001100010000000.....
+
+:wfet Rd_GPR64
+is b_0531=0x6a81880 & Rd_GPR64
+{
+ WaitForEvent(Rd_GPR64);
+}
+
+# C6.2.398 WFI page C6-2006 line 117439 MATCH xd503207f/mask=xffffffff
+# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f
+# CONSTRUCT xd503207f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd503207f/mask=xffffffff --status nodest
+
+:wfi
+is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low=3 & Rt=0x1f
+{
+ WaitForInterrupt();
+}
+
+# C6.2.399 WFIT page C6-2007 line 117477 MATCH xd5031020/mask=xffffffe0
+# CONSTRUCT xd5031020/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES
+# xd5031020/mask=xffffffe0 NOT MATCHED BY ANY CONSTRUCTOR
+# b_0031=110101010000001100010000001.....
+
+:wfit Rd_GPR64
+is b_0531=0x6a81881 & Rd_GPR64
+{
+ WaitForInterrupt(Rd_GPR64);
+}
+
+# C6.2.401 XPACD, XPACI, XPACLRI page C6-2009 line 117573 MATCH xdac143e0/mask=xfffffbe0
+# CONSTRUCT xdac147e0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xdac147e0/mask=xffffffe0 --status noqemu
+# D == 1 XPACD variant
+
+:xpacd Rd_GPR64
+is xpacd__PACpart & b_1131=0b110110101100000101000 & b_0509=0b11111 & b_10=1 & Rd_GPR64
+{
+ build xpacd__PACpart;
+}
+
+# C6.2.401 XPACD, XPACI, XPACLRI page C6-2009 line 117573 MATCH xdac143e0/mask=xfffffbe0
+# CONSTRUCT xdac143e0/mask=xffffffe0 MATCHED 1 DOCUMENTED OPCODES
+# AUNIT --inst xdac143e0/mask=xffffffe0 --status noqemu
+# D == 0 XPACI variant
+
+:xpaci Rd_GPR64
+is xpaci__PACpart & b_1131=0b110110101100000101000 & b_0509=0b11111 & b_10=0 & Rd_GPR64
+{
+ build xpaci__PACpart;
+}
+
+# C6.2.401 XPACD, XPACI, XPACLRI page C6-2009 line 117573 MATCH xd50320ff/mask=xffffffff
+# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f
+# CONSTRUCT xd50320ff/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd50320ff/mask=xffffffff --status nodest
+# System variant
+
+:xpaclri
+is xpaclri__PACpart & b_0031=0b11010101000000110010000011111111
+{
+ build xpaclri__PACpart;
+}
+
+# C6.2.402 YIELD page C6-2011 line 117656 MATCH xd503203f/mask=xffffffff
+# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f
+# CONSTRUCT xd503203f/mask=xffffffff MATCHED 2 DOCUMENTED OPCODES
+# AUNIT --inst xd503203f/mask=xffffffff --status nodest
+
+:yield
+is b_2431=0xd5 & b_2223=0 & l=0 & Op0=0 & Op1=3 & CRn=0x2 & imm7Low=1 & Rt=0x1f
+{
+ Yield();
+}
+
+# C6.2.6 ADDG page C6-787 line 46877 MATCH KEEPWITH
+
+with : ShowMemTag=1 {
+
+# C6.2.6 ADDG page C6-1155 line 68448 MATCH x91800000/mask=xffc00000
+# CONSTRUCT x91800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+
+:addg Rd_GPR64xsp, Rn_GPR64xsp, "#"^shifted_imm, "#"^b_1013
+is sf=1 & op=0 & S=0 & b_2328=0b100011 & b_22=0 & b_1621 & b_1013 & Rd_GPR64xsp & Rn_GPR64xsp
+# " & b_1415=0" is not required by the spec (op3 doesn't have any requirements and is not used)
+[ shifted_imm = b_1621 << $(LOG2_TAG_GRANULE); ]
+{
+ # we don't actually modify the target register, so Ghidra understands the pointer target is still the same.
+ # pseudo-ops let us do that, but it means that the decompiler can put an unintuitive value in the
+ # "CopyPtrTag_AddToPtrTag_Exclude" argument, e.g. "param_2 + 0x20".
+ uimm4:1 = b_1013;
+ exclude:2 = 0;
+ Or2BytesWithExcludedTags(exclude);
+ Rd_GPR64xsp = Rn_GPR64xsp + shifted_imm;
+ CopyPtrTag_AddToPtrTag_Exclude(Rd_GPR64xsp, Rn_GPR64xsp, uimm4, exclude);
+}
+
+}
+
+# C6.2.6 ADDG page C6-787 line 44223 KEEPWITH
+with : ShowMemTag=0 {
+
+# C6.2.6 ADDG page C6-1155 line 68448 MATCH x91800000/mask=xffc00000
+# CONSTRUCT x91800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+
+:addg Rd_GPR64xsp, Rn_GPR64xsp, "#"^shifted_imm, "#"^b_1013
+is sf=1 & op=0 & S=0 & b_2328=0b100011 & b_22=0 & b_1621 & b_1013 & Rd_GPR64xsp & Rn_GPR64xsp
+# " & b_1415=0" is not required by the spec (op3 doesn't have any requirements and is not used)
+[ shifted_imm = b_1621 << $(LOG2_TAG_GRANULE); ]
+{
+ Rd_GPR64xsp = Rn_GPR64xsp + shifted_imm;
+}
+
+}
+
+
+# C6.2.24 AXFLAG page C6-1189 line 70222 MATCH xd500405f/mask=xfffff0ff
+# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f
+# CONSTRUCT xd500405f/mask=xfffff0ff MATCHED 2 DOCUMENTED OPCODES
+# To enforce SHOULD BE ZERO fields add: b_0811=0b0000
+:axflag
+is b_1231=0b11010101000000000100 & b_0007=0b01011111
+{
+ tmpZR = ZR | OV;
+ tmpCY = CY & !OV;
+
+ NG = 0;
+ ZR = tmpZR;
+ CY = tmpCY;
+ OV = 0;
+}
+
+# C6.2.41 BTI page C6-1214 line 71457 MATCH xd503241f/mask=xffffff3f
+# C6.2.126 HINT page C6-1480 line 88030 MATCH xd503201f/mask=xfffff01f
+# CONSTRUCT xd503241f/mask=xffffff1f MATCHED 2 DOCUMENTED OPCODES
+
+:bti BTI_BTITARGETS
+is BTI_BTITARGETS & b_1231=0xd5032 & b_0811=4 & b_0004=0x1f
+{
+ # This instruction is a valid target for jumps, calls, or both; see the BTI_BTITARGETS table.
+}
+
+# C6.2.53 CFP page C6-1237 line 72667 MATCH xd50b7380/mask=xffffffe0
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50b7380/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES
+
+:cfp "RCTX", Rt_GPR64
+is b_1931=0b1101010100001 & Op1_uimm3=3 & b_1215=7 & b_0811=3 & Op2_uimm3=4 & Rt_GPR64
+{
+ ControlFlowPredictionRestrictionByContext(Rt_GPR64);
+}
+
+
+# C6.2.65 CMPP page C6-1258 line 73720 MATCH xbac0001f/mask=xffe0fc1f
+# C6.2.361 SUBPS page C6-1949 line 114470 MATCH xbac00000/mask=xffe0fc00
+# CONSTRUCT xbac0001f/mask=xffe0fc1f MATCHED 2 DOCUMENTED OPCODES
+# CMPP: Compare Pointers
+# Compare two pointer 56-bit pointer values and set flags
+:cmpp Rn_GPR64xsp, Rm_GPR64xsp
+is sf=1 & b_30=0 & S=1 & b_2128=0b11010110 & Rm_GPR64xsp & b_1015=0b000000 & Rd=0b11111 & Rn_GPR64xsp
+{
+ # out of a 64-bit value, keep the lowest 56 bits, which is 7 bytes.
+ # sign-extend a 7-byte value to an 8-byte value. If the boundary weren't byte-aligned,
+ # sext() wouldn't work so well.
+ tmp_2:8 = Rm_GPR64xsp;
+ tmp_2 = sext(tmp_2:7); # if Rm:7 is used here, the decompiler considers the Rm register an int7 for the whole function.
+ tmp_1:8 = Rn_GPR64xsp;
+ tmp_1 = sext(tmp_1:7);
+ subflags(tmp_1, tmp_2);
+ tmp_1 = tmp_1 - tmp_2;
+ resultflags(tmp_1);
+ affectflags();
+}
+
+
+# C6.2.67 CPP page C6-1261 line 73861 MATCH xd50b73e0/mask=xffffffe0
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50b73e0/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES
+
+:cpp "RCTX", Rt_GPR64
+is b_1931=0b1101010100001 & Op1_uimm3=3 & b_1215=7 & b_0811=3 & Op2_uimm3=7 & Rt_GPR64
+{
+ CachePrefetchPredictionRestrictionByContext(Rt_GPR64);
+}
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5087660/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+# the new DC instruction types from ARMv8.5
+
+:dc "IGVAC", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b0110 & b_0507=0b011 & Rt_GPR64
+{ DC_IGVAC(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5087680/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+
+:dc "IGSW", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b0110 & b_0507=0b100 & Rt_GPR64
+{ DC_IGSW(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50876a0/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+
+:dc "IGDVAC", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b0110 & b_0507=0b101 & Rt_GPR64
+{ DC_IGDVAC(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50876c0/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+
+:dc "IGDSW", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b0110 & b_0507=0b110 & Rt_GPR64
+{ DC_IGDSW(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5087a80/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+
+:dc "CGSW", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1010 & b_0507=0b100 & Rt_GPR64
+{ DC_CGSW(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5087ac0/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+
+:dc "CGDSW", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1010 & b_0507=0b110 & Rt_GPR64
+{ DC_CGDSW(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5087e80/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+
+:dc "CIGSW", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1110 & b_0507=0b100 & Rt_GPR64
+{ DC_CIGSW(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd5087ec0/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+
+:dc "CIGDSW", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b000 & b_1215=0b0111 & b_0811=0b1110 & b_0507=0b110 & Rt_GPR64
+{ DC_CIGDSW(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50b7460/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+
+:dc "GVA", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b0100 & b_0507=0b011 & Rt_GPR64
+{ DC_GVA(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50b7480/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+
+:dc "GZVA", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b0100 & b_0507=0b100 & Rt_GPR64
+{ DC_GZVA(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50b7a60/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+
+:dc "CGVAC", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1010 & b_0507=0b011 & Rt_GPR64
+{ DC_CGVAC(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50b7aa0/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+
+:dc "CGDVAC", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1010 & b_0507=0b101 & Rt_GPR64
+{ DC_CGDVAC(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50b7c60/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+
+:dc "CGVAP", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1100 & b_0507=0b011 & Rt_GPR64
+{ DC_CGVAP(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50b7ca0/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+
+:dc "CGDVAP", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1100 & b_0507=0b101 & Rt_GPR64
+{ DC_CGDVAP(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50b7d60/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+
+:dc "CGVADP", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1101 & b_0507=0b011 & Rt_GPR64
+{ DC_CGVADP(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50b7da0/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+
+:dc "CGDVADP", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1101 & b_0507=0b101 & Rt_GPR64
+{ DC_CGDVADP(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50b7e60/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+
+:dc "CIGVAC", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1110 & b_0507=0b011 & Rt_GPR64
+{ DC_CIGVAC(Rt_GPR64); }
+
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50b7ea0/mask=xffffffe0 MATCHED 3 DOCUMENTED OPCODES
+
+:dc "CIGDVAC", Rt_GPR64
+is b_1931=0b1101010100001 & b_1618=0b011 & b_1215=0b0111 & b_0811=0b1110 & b_0507=0b101 & Rt_GPR64
+{ DC_CIGDVAC(Rt_GPR64); }
+
+# C6.2.117 DVP page C6-1467 line 87355 MATCH xd50b73a0/mask=xffffffe0
+# C6.2.109 DC page C6-1455 line 86693 MATCH xd5087000/mask=xfff8f000
+# C6.2.129 IC page C6-1484 line 88281 MATCH xd5087000/mask=xfff8f000
+# C6.2.372 SYS page C6-1969 line 115559 MATCH xd5080000/mask=xfff80000
+# CONSTRUCT xd50b73a0/mask=xffffffe0 MATCHED 4 DOCUMENTED OPCODES
+
+:dvp "RCTX", Rt_GPR64
+is b_1931=0b1101010100001 & Op1_uimm3=3 & b_1215=7 & b_0811=3 & Op2_uimm3=5 & Rt_GPR64
+{
+ DataValuePredictionRestrictionByContext(Rt_GPR64);
+}
+
+
+# GMI: Tag Mask Insert
+# Extracts tag from first source register (Xn) and adds as an excluded tag to list of excluded
+# tags in second source register, writing the updated exclusion set to the destination register
+
+with : ShowMemTag=1 {
+
+# C6.2.125 GMI page C6-1479 line 87976 MATCH x9ac01400/mask=xffe0fc00
+# CONSTRUCT x9ac01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+
+:gmi Rd_GPR64, Rn_GPR64xsp, Rm_GPR64
+is sf=1 & b_30=0 & S=0 & b_2128=0b11010110 & Rm_GPR64 & b_1015=0b000101 & Rn_GPR64xsp & Rd_GPR64
+{
+ # get tag from address
+ #tag:8 = (Rn_GPR64xsp >> 56) & 0xf;
+ tag:8 = 0;
+ AllocationTagFromAddress(tag, Rn_GPR64xsp);
+ Rd_GPR64 = Rm_GPR64 | (1 << tag);
+}
+
+}
+with : ShowMemTag=0 {
+
+# C6.2.125 GMI page C6-1479 line 87976 MATCH x9ac01400/mask=xffe0fc00
+# CONSTRUCT x9ac01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+
+:gmi Rd_GPR64, Rn_GPR64xsp, Rm_GPR64
+is sf=1 & b_30=0 & S=0 & b_2128=0b11010110 & Rm_GPR64 & b_1015=0b000101 & Rn_GPR64xsp & Rd_GPR64
+{
+ # The only expected use of the output of this instruction is in "exclude" arguments, which will be totally ignored
+ # with ShowMemTag off anyway, so for the sake of more concise code don't set any mask bits at all.
+ Rd_GPR64 = Rm_GPR64;
+}
+
+}
+
+# IRG: Insert Random Tag
+# Generates random tag (honoring excluded tags specified in optional second source register
+# and GCR_EL1.Exclude) into the address from first source register, writing the result to the
+# destination register.
+with : ShowMemTag=1 {
+
+# C6.2.130 IRG page C6-1485 line 88340 MATCH x9ac01000/mask=xffe0fc00
+# CONSTRUCT x9ac01000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+
+:irg Rd_GPR64xsp, Rn_GPR64xsp^OPTIONAL_XM
+is sf=1 & b_30=0 & S=0 & b_2128=0b11010110 & OPTIONAL_XM & b_1015=0b000100 & Rn_GPR64xsp & Rd_GPR64xsp
+{
+ tmp:8 = OPTIONAL_XM;
+ exclude:2 = tmp:2;
+ Or2BytesWithExcludedTags(exclude);
+ Rd_GPR64xsp = Rn_GPR64xsp;
+ RandomizePtrTag_Exclude(Rd_GPR64xsp, exclude);
+}
+
+}
+with : ShowMemTag=0 {
+
+# C6.2.130 IRG page C6-1485 line 88340 MATCH x9ac01000/mask=xffe0fc00
+# CONSTRUCT x9ac01000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+
+:irg Rd_GPR64xsp, Rn_GPR64xsp^OPTIONAL_XM
+is sf=1 & b_30=0 & S=0 & b_2128=0b11010110 & OPTIONAL_XM & b_1015=0b000100 & Rn_GPR64xsp & Rd_GPR64xsp
+{
+ Rd_GPR64xsp = Rn_GPR64xsp;
+}
+
+}
+
+
+with : ShowMemTag=1 {
+
+# C6.2.158 LDG page C6-1538 line 91337 MATCH xd9600000/mask=xffe00c00
+# CONSTRUCT xd9600000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+
+:ldg Rt_GPR64, addr_granuleSIMM
+is b_2131=0b11011001011 & addr_granuleSIMM & b_1011=0b00 & Rt_GPR64
+{
+ tmp:8 = addr_granuleSIMM;
+ Align(tmp, $(TAG_GRANULE));
+ tag:8 = LoadMemTag(tmp);
+ SetPtrTag(Rt_GPR64, tag);
+}
+
+}
+with : ShowMemTag=0 {
+
+# C6.2.158 LDG page C6-1538 line 91337 MATCH xd9600000/mask=xffe00c00
+# CONSTRUCT xd9600000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+
+:ldg Rt_GPR64, addr_granuleSIMM
+is b_2131=0b11011001011 & addr_granuleSIMM & b_1011=0b00 & Rt_GPR64
+{
+}
+
+}
+
+
+with : ShowMemTag=1 {
+
+# C6.2.159 LDGM page C6-1539 line 91400 MATCH xd9e00000/mask=xfffffc00
+# CONSTRUCT xd9e00000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+
+:ldgm Rt_GPR64, "["^Rn_GPR64xsp^"]"
+is b_1031=0b1101100111100000000000 & Rt_GPR64 & Rn_GPR64xsp
+{
+ sze:8 = 4 << (gmid_el1 & 0xf); # The value in parentheses (GMID_EL1.BS) varies between 2 and 6.
+ address:8 = Rn_GPR64xsp;
+ Align(address, sze); # this ensures that address will be granule-aligned, so we don't need to check it
+ count:8 = sze >> $(LOG2_TAG_GRANULE);
+ data:8 = 0:8; # output value
+ index:8 = (address >> $(LOG2_TAG_GRANULE)) & 0xf;
+ # for tmp = 0 to count-1
+ tmp:8 = 0;
+
+ tag:8 = LoadMemTag(address) & 0xf;
+ # The 0xf doesn't do anything to streamline the representation of this
+ # instruction in the decompiler, but it shows the size of a tag.
+ data = data | (tag << (index * 4));
+ address = address + $(TAG_GRANULE);
+ index = index + 1;
+ tmp = tmp + 1;
+ # next tmp
+ if (tmp < count) goto ;
+ Rt_GPR64 = data;
+}
+
+}
+with : ShowMemTag=0 {
+
+# C6.2.159 LDGM page C6-1539 line 91400 MATCH xd9e00000/mask=xfffffc00
+# CONSTRUCT xd9e00000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+
+:ldgm Rt_GPR64, "["^Rn_GPR64xsp^"]"
+is b_1031=0b1101100111100000000000 & Rt_GPR64 & Rn_GPR64xsp
+{
+ data:8 = 0:8; # output value
+ Rt_GPR64 = data;
+}
+
+}
+
+# C6.2.132 LD64B page C6-1488 line 88475 MATCH xf83fd000/mask=xfffffc00
+# CONSTRUCT xf83fd000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# xf83fd000/mask=xfffffc00 NOT MATCHED BY ANY CONSTRUCTOR
+# b_0031=1111100000111111110100..........
+
+# Single-copy Atomic 64-byte Load
+:ld64b Rn_GPR64, [Rt_GPR64xsp]
+is b_1031=0x3e0ff4 & Rn_GPR64 & Rt_GPR64xsp {
+ Rn_GPR64 = *Rt_GPR64xsp;
+}
+
+
+# C6.2.292 ST64B page C6-1813 line 107121 MATCH xf83f9000/mask=xfffffc00
+# CONSTRUCT xf83f9000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+
+:st64b Rn_GPR64, [Rt_GPR64xsp]
+is b_1031=0x3e0fe4 & Rn_GPR64 & Rt_GPR64xsp {
+ *Rt_GPR64xsp = Rn_GPR64;
+}
+
+
+# C6.2.293 ST64BV page C6-1814 line 107190 MATCH xf820b000/mask=xffe0fc00
+# CONSTRUCT xf820b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+define pcodeop store64ByteAtomic;
+:st64bv Rs_GPR64, Rn_GPR64, [Rt_GPR64xsp]
+is b_2131=0x7c1 & Rs_GPR64 & b_1015=0x2c & Rn_GPR64 & Rt_GPR64xsp {
+ *Rt_GPR64xsp = Rn_GPR64;
+ Rs_GPR64 = store64ByteAtomic(Rn_GPR64, Rt_GPR64xsp);
+}
+
+
+# C6.2.294 ST64BV0 page C6-1816 line 107284 MATCH xf820a000/mask=xffe0fc00
+# CONSTRUCT xf820a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+
+:st64bv0
+is b_2131=0b11111000001 & Rs_GPR64 & b_1015=0x28 & Rn_GPR64 & Rt_GPR64xsp {
+ local st64bv_addr:8 = (Rt_GPR64xsp & 0xffff0000) | (accdata & 0xffff);
+ *st64bv_addr = Rn_GPR64;
+ Rs_GPR64 = store64ByteAtomic(Rn_GPR64, st64bv_addr);
+}
+
+
+addrGranuleIndexed_checkAlignment: addrGranuleIndexed is Rn=0b11111 & addrGranuleIndexed { export addrGranuleIndexed; } # don't check alignment if we're working with the stack, it's assumed to be 16-byte-aligned, though that is technically optional
+addrGranuleIndexed_checkAlignment: addrGranuleIndexed is Rn & addrGranuleIndexed { tmp:8 = addrGranuleIndexed; RequireGranuleAlignment(tmp); export tmp; } # if the address in tmp is derived from sp, the error condition in RequireGranuleAlignment can still be an unreachable block; it doesn't seem possible to avoid the decompiler message in that case
+
+addrPairGranuleIndexed_checkAlignment: addrPairGranuleIndexed is Rn=0b11111 & addrPairGranuleIndexed { export addrPairGranuleIndexed; } # don't check alignment if we're working with the stack, it's assumed to be 16-byte-aligned, though that is technically optional
+addrPairGranuleIndexed_checkAlignment: addrPairGranuleIndexed is Rn & addrPairGranuleIndexed { tmp:8 = addrPairGranuleIndexed; RequireGranuleAlignment(tmp); export tmp; } # if the address in tmp is derived from sp, the error condition in RequireGranuleAlignment can still be an unreachable block; it doesn't seem possible to avoid the decompiler message in that case
+
+
+with : ShowMemTag=1 {
+
+# C6.2.291 ST2G page C6-1811 line 106987 MATCH xd9a00400/mask=xffe00c00
+# C6.2.291 ST2G page C6-1811 line 106987 MATCH xd9a00c00/mask=xffe00c00
+# C6.2.291 ST2G page C6-1811 line 106987 MATCH xd9a00800/mask=xffe00c00
+# CONSTRUCT xd9a00000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES
+
+:st2g Rt_GPR64xsp, addrGranuleIndexed_checkAlignment
+is b_2131=0b11011001101 & (b_10=1 | b_11=1) & Rt_GPR64xsp & addrGranuleIndexed_checkAlignment
+{
+ # in case Rt == Rn, get the tag first so any updates in addrGranuleIndexed_checkAlignment don't affect it
+ tag:8 = 0;
+ AllocationTagFromAddress(tag, Rt_GPR64xsp);
+
+ build addrGranuleIndexed_checkAlignment;
+
+ # this instruction throws an alignment fault if address is not granule-aligned
+ address:8 = addrGranuleIndexed_checkAlignment;
+
+ StoreMemTag(address, tag );
+ StoreMemTag(address + $(TAG_GRANULE), tag );
+}
+
+}
+with : ShowMemTag=0 {
+
+# C6.2.291 ST2G page C6-1811 line 106987 MATCH xd9a00400/mask=xffe00c00
+# C6.2.291 ST2G page C6-1811 line 106987 MATCH xd9a00c00/mask=xffe00c00
+# C6.2.291 ST2G page C6-1811 line 106987 MATCH xd9a00800/mask=xffe00c00
+# CONSTRUCT xd9a00000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES
+
+:st2g Rt_GPR64xsp, addrGranuleIndexed
+is b_2131=0b11011001101 & (b_10=1 | b_11=1) & Rt_GPR64xsp & addrGranuleIndexed
+{
+ # for the sake of simplified output, omit the alignment check when ShowMemTag is off
+}
+
+}
+
+
+with : ShowMemTag=1 {
+
+# C6.2.304 STG page C6-1836 line 108242 MATCH xd9200400/mask=xffe00c00
+# C6.2.304 STG page C6-1836 line 108242 MATCH xd9200c00/mask=xffe00c00
+# C6.2.304 STG page C6-1836 line 108242 MATCH xd9200800/mask=xffe00c00
+# CONSTRUCT xd9200000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES
+
+:stg Rt_GPR64xsp, addrGranuleIndexed_checkAlignment
+is b_2131=0b11011001001 & (b_10=1 | b_11=1) & Rt_GPR64xsp & addrGranuleIndexed_checkAlignment
+{
+ # in case Rt == Rn, get the tag first so any updates in addrGranuleIndexed_checkAlignment don't affect it
+ tag:8 = 0;
+ AllocationTagFromAddress(tag, Rt_GPR64xsp);
+
+ build addrGranuleIndexed_checkAlignment;
+
+ # this instruction throws an alignment fault if address is not granule-aligned
+ address:8 = addrGranuleIndexed_checkAlignment;
+
+ StoreMemTag(address, tag );
+}
+
+}
+with : ShowMemTag=0 {
+
+# C6.2.304 STG page C6-1836 line 108242 MATCH xd9200400/mask=xffe00c00
+# C6.2.304 STG page C6-1836 line 108242 MATCH xd9200c00/mask=xffe00c00
+# C6.2.304 STG page C6-1836 line 108242 MATCH xd9200800/mask=xffe00c00
+# CONSTRUCT xd9200000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES
+
+:stg Rt_GPR64xsp, addrGranuleIndexed
+is b_2131=0b11011001001 & (b_10=1 | b_11=1) & Rt_GPR64xsp & addrGranuleIndexed
+{
+ # for the sake of simplified output, omit the alignment check when ShowMemTag is off
+}
+
+}
+
+
+with : ShowMemTag=1 {
+
+# C6.2.305 STGM page C6-1838 line 108375 MATCH xd9a00000/mask=xfffffc00
+# CONSTRUCT xd9a00000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+
+:stgm Rt_GPR64, "["^Rn_GPR64xsp^"]"
+is b_1031=0b1101100110100000000000 & Rt_GPR64 & Rn_GPR64xsp
+{
+ sze:8 = 4 << (gmid_el1 & 0xf); # The value of GMID_EL1.BS varies between 2 and 6. Can that be asserted somehow?
+ address:8 = Rn_GPR64xsp;
+ Align(address, sze); # this ensures that address will be granule-aligned, so we don't need to check it
+ count:8 = sze >> $(LOG2_TAG_GRANULE);
+ data:8 = Rt_GPR64;
+ index:8 = (address >> $(LOG2_TAG_GRANULE)) & 0xf;
+ # for tmp = 0 to count-1
+ tmp:8 = 0;
+
+ # This could also be done by leaving index and address constant and adding a tmp-based
+ # offset to them both, but that crams everything together into the StoreMemTag line in
+ # the decompiler and makes it harder to assign names and figure out what's going on.
+ # (Or at least, my opinion is that it's harder that way.)
+ # Also in favor of this design is that the ARM spec pseudocode describes it this way,
+ # so it's easier to see that this code matches the pseudocode.
+ tag:8 = (data >> (index * 4)) & 0xf;
+ StoreMemTag(address, tag );
+ address = address + $(TAG_GRANULE);
+ index = index + 1;
+ tmp = tmp + 1;
+ # next tmp
+ if (tmp < count) goto ;
+}
+
+}
+with : ShowMemTag=0 {
+
+# C6.2.305 STGM page C6-1838 line 108375 MATCH xd9a00000/mask=xfffffc00
+# CONSTRUCT xd9a00000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+
+:stgm Rt_GPR64, "["^Rn_GPR64xsp^"]"
+is b_1031=0b1101100110100000000000 & Rt_GPR64 & Rn_GPR64xsp
+{
+}
+
+}
+
+
+with : ShowMemTag=1 {
+
+# C6.2.306 STGP page C6-1839 line 108445 MATCH x68800000/mask=xffc00000
+# C6.2.306 STGP page C6-1839 line 108445 MATCH x69800000/mask=xffc00000
+# C6.2.306 STGP page C6-1839 line 108445 MATCH x69000000/mask=xffc00000
+# CONSTRUCT x68000000/mask=xfe400000 MATCHED 3 DOCUMENTED OPCODES
+
+:stgp Rt_GPR64, Rt2_GPR64, addrPairGranuleIndexed_checkAlignment
+is b_3031=0b01 & b_2529=0b10100 & (b_23=1 | b_24=1) & b_22=0 & Rt2_GPR64 & addrPairGranuleIndexed_checkAlignment & Rt_GPR64
+{
+ # Read all registers before addrPairGranuleIndexed_checkAlignment takes effect, or pre-index writeback could modify their values
+ # (unusually, this instruction does not have unpredictable behavior in that case).
+ data1:8 = Rt_GPR64;
+ data2:8 = Rt2_GPR64;
+
+ build addrPairGranuleIndexed_checkAlignment;
+ address:8 = addrPairGranuleIndexed_checkAlignment; # StoreMemTag requires granule alignment
+
+ tag:8 = 0;
+ AllocationTagFromAddress(tag, address);
+
+ # The decompiler apparently doesn't show changes to [sp+X] unless the new values
+ # are used in the function. However, the changes really are happening.
+ *address = data1;
+ *(address + 8) = data2;
+ StoreMemTag(address, tag);
+}
+
+}
+with : ShowMemTag=0 {
+
+# C6.2.306 STGP page C6-1839 line 108445 MATCH x68800000/mask=xffc00000
+# C6.2.306 STGP page C6-1839 line 108445 MATCH x69800000/mask=xffc00000
+# C6.2.306 STGP page C6-1839 line 108445 MATCH x69000000/mask=xffc00000
+# CONSTRUCT x68000000/mask=xfe400000 MATCHED 3 DOCUMENTED OPCODES
+
+:stgp Rt_GPR64, Rt2_GPR64, addrPairGranuleIndexed
+is b_3031=0b01 & b_2529=0b10100 & (b_23=1 | b_24=1) & b_22=0 & Rt2_GPR64 & addrPairGranuleIndexed & Rt_GPR64
+{
+ # Read all registers before addrPairGranuleIndexed takes effect, or pre-index writeback could modify their values
+ # (unusually, this instruction does not have unpredictable behavior in this case).
+ data1:8 = Rt_GPR64;
+ data2:8 = Rt2_GPR64;
+
+ # for the sake of simplified output, omit the alignment check when ShowMemTag is off
+ build addrPairGranuleIndexed;
+ address:8 = addrPairGranuleIndexed;
+
+ # The decompiler apparently doesn't show changes to [sp+X] unless the new values
+ # are used in the function. However, the changes really are happening.
+ *address = data1;
+ *(address + 8) = data2;
+}
+
+}
+
+
+with : ShowMemTag=1 {
+
+# C6.2.353 STZ2G page C6-1935 line 113626 MATCH xd9e00400/mask=xffe00c00
+# C6.2.353 STZ2G page C6-1935 line 113626 MATCH xd9e00c00/mask=xffe00c00
+# C6.2.353 STZ2G page C6-1935 line 113626 MATCH xd9e00800/mask=xffe00c00
+# CONSTRUCT xd9e00000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES
+
+:stz2g Rt_GPR64xsp, addrGranuleIndexed_checkAlignment
+is b_2131=0b11011001111 & (b_10=1 | b_11=1) & addrGranuleIndexed_checkAlignment & Rt_GPR64xsp
+{
+ tag:8 = 0;
+ AllocationTagFromAddress(tag, Rt_GPR64xsp);
+
+ # Although the zero-storage is not required to be granule-aligned, the tag-updating is,
+ # so effectively the entire operation must be at a granule-aligned address.
+ build addrGranuleIndexed_checkAlignment;
+ address:8 = addrGranuleIndexed_checkAlignment;
+
+ # store two granules worth of zeros and tag it from Rt
+ tmp:8 = 0;
+ addr:8 = 0;
+ count:8 = $(TAG_GRANULE) * 2;
+
+ addr = address + tmp;
+ *addr = 0:8;
+ tmp = tmp + 8;
+ if (tmp < count) goto ;
+
+ StoreMemTag(address, tag);
+ StoreMemTag(address + $(TAG_GRANULE), tag);
+}
+
+}
+with : ShowMemTag=0 {
+
+# C6.2.353 STZ2G page C6-1935 line 113626 MATCH xd9e00400/mask=xffe00c00
+# C6.2.353 STZ2G page C6-1935 line 113626 MATCH xd9e00c00/mask=xffe00c00
+# C6.2.353 STZ2G page C6-1935 line 113626 MATCH xd9e00800/mask=xffe00c00
+# CONSTRUCT xd9e00000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES
+
+:stz2g Rt_GPR64xsp, addrGranuleIndexed
+is b_2131=0b11011001111 & (b_10=1 | b_11=1) & addrGranuleIndexed & Rt_GPR64xsp
+{
+ # for the sake of simplified output, omit the alignment check when ShowMemTag is off
+ build addrGranuleIndexed;
+ address:8 = addrGranuleIndexed;
+
+ # store two granules worth of zeros
+ tmp:8 = 0;
+ addr:8 = 0;
+ count:8 = $(TAG_GRANULE) * 2;
+
+ addr = address + tmp;
+ *addr = 0:8;
+ tmp = tmp + 8;
+ if (tmp < count) goto ;
+}
+
+}
+
+
+with : ShowMemTag=1 {
+
+# C6.2.354 STZG page C6-1937 line 113766 MATCH xd9600400/mask=xffe00c00
+# C6.2.354 STZG page C6-1937 line 113766 MATCH xd9600c00/mask=xffe00c00
+# C6.2.354 STZG page C6-1937 line 113766 MATCH xd9600800/mask=xffe00c00
+# CONSTRUCT xd9600000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES
+
+:stzg Rt_GPR64xsp, addrGranuleIndexed_checkAlignment
+is b_2131=0b11011001011 & (b_10=1 | b_11=1) & addrGranuleIndexed_checkAlignment & Rt_GPR64xsp
+{
+ tag:8 = 0;
+ AllocationTagFromAddress(tag, Rt_GPR64xsp);
+
+ # Although the zero-storage is not required to be granule-aligned, the tag-updating is,
+ # so effectively the entire operation must be at a granule-aligned address.
+ build addrGranuleIndexed_checkAlignment;
+ address:8 = addrGranuleIndexed_checkAlignment;
+
+ # store one granule worth of zeros and tag it from Rt
+ tmp:8 = 0;
+ addr:8 = 0;
+ count:8 = $(TAG_GRANULE);
+
+ addr = address + tmp;
+ *addr = 0:8;
+ tmp = tmp + 8;
+ if (tmp < count) goto ;
+
+ StoreMemTag(address, tag);
+}
+
+}
+with : ShowMemTag=0 {
+
+# C6.2.354 STZG page C6-1937 line 113766 MATCH xd9600400/mask=xffe00c00
+# C6.2.354 STZG page C6-1937 line 113766 MATCH xd9600c00/mask=xffe00c00
+# C6.2.354 STZG page C6-1937 line 113766 MATCH xd9600800/mask=xffe00c00
+# CONSTRUCT xd9600000/mask=xffe00000 MATCHED 3 DOCUMENTED OPCODES
+
+:stzg Rt_GPR64xsp, addrGranuleIndexed
+is b_2131=0b11011001011 & (b_10=1 | b_11=1) & addrGranuleIndexed & Rt_GPR64xsp
+{
+ # for the sake of simplified output, omit the alignment check when ShowMemTag is off
+ build addrGranuleIndexed;
+ address:8 = addrGranuleIndexed;
+
+ # store one granule worth of zeros
+ tmp:8 = 0;
+ addr:8 = 0;
+ count:8 = $(TAG_GRANULE);
+
+ addr = address + tmp;
+ *addr = 0:8;
+ tmp = tmp + 8;
+ if (tmp < count) goto ;
+}
+
+}
+
+
+
+with : ShowMemTag=1 {
+
+# C6.2.355 STZGM page C6-1939 line 113904 MATCH xd9200000/mask=xfffffc00
+# CONSTRUCT xd9200000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+
+:stzgm Rt_GPR64, "["^Rn_GPR64xsp^"]"
+is b_1031=0b1101100100100000000000 & Rt_GPR64 & Rn_GPR64xsp
+{
+ sze:8 = 4 << (dczid_el0 & 0xf); # the last value (DCZID_EL0.BS) can be up to 9 (for a size of 2KB) and seems
+ # to be hardware-dependent and unwriteable (sysreg spec doesn't show how to write it).
+ # minimum is probably 2, which would make the size equal to a tag granule
+ address:8 = Rn_GPR64xsp;
+ Align(address, sze); # based on the educated guess above, address is probably granule-aligned by this, so we won't check it explicitly (compare to LDGM or STGM)
+ count:8 = sze >> $(LOG2_TAG_GRANULE);
+ data:8 = Rt_GPR64;
+ tag:8 = data & 0xf;
+ # for tmp = 0 to count-1
+ tmp:8 = 0;
+
+ StoreMemTag(address, tag );
+
+ # store zeros to the entire granule
+ tmp_zero:8 = 0;
+ addr_zero:8 = address;
+ count_zero:8 = $(TAG_GRANULE);
+
+ addr_zero = address + tmp_zero;
+ *addr_zero = 0:8;
+ tmp_zero = tmp_zero + 8;
+ if (tmp_zero < count_zero) goto ;
+
+ address = address + $(TAG_GRANULE);
+ # next tmp
+ tmp = tmp + 1;
+ if (tmp < count) goto ;
+}
+
+}
+with : ShowMemTag=0 {
+
+# C6.2.355 STZGM page C6-1939 line 113904 MATCH xd9200000/mask=xfffffc00
+# CONSTRUCT xd9200000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+
+:stzgm Rt_GPR64, "["^Rn_GPR64xsp^"]"
+is b_1031=0b1101100100100000000000 & Rt_GPR64 & Rn_GPR64xsp
+{
+ sze:8 = 4 << (dczid_el0 & 0xf); # the last value (DCZID_EL0.BS) can be up to 9 (for a size of 2KB) and seems
+ # to be hardware-dependent and unwriteable (sysreg spec doesn't show how to write it).
+ # minimum is probably 2, which would make the size equal to a tag granule
+ address:8 = Rn_GPR64xsp;
+ Align(address, sze); # based on the educated guess above, address is probably granule-aligned by this, so we won't check it explicitly (compare to LDGM or STGM)
+ count:8 = sze >> $(LOG2_TAG_GRANULE);
+ # for tmp = 0 to count-1
+ tmp:8 = 0;
+
+
+ # store zeros to the entire granule
+ tmp_zero:8 = 0;
+ addr_zero:8 = address;
+ count_zero:8 = $(TAG_GRANULE);
+
+ addr_zero = address + tmp_zero;
+ *addr_zero = 0:8;
+ tmp_zero = tmp_zero + 8;
+ if (tmp_zero < count_zero) goto ;
+
+ address = address + $(TAG_GRANULE);
+ # next tmp
+ tmp = tmp + 1;
+ if (tmp < count) goto ;
+}
+
+}
+
+
+# To enforce SHOULD BE ZERO fields add: b_1415=0b00
+
+with : ShowMemTag=1 {
+
+# C6.2.359 SUBG page C6-1947 line 114340 MATCH xd1800000/mask=xffc00000
+# CONSTRUCT xd1800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+
+:subg Rd_GPR64xsp, Rn_GPR64xsp, "#"^shifted_imm, "#"^b_1013
+is sf=1 & op=1 & S=0 & b_2328=0b100011 & b_22=0 & b_1621 & b_1013 & Rd_GPR64xsp & Rn_GPR64xsp
+# " & b_1415=0" is not required by the spec (op3 doesn't have any requirements and is not used)
+[ shifted_imm = b_1621 << $(LOG2_TAG_GRANULE); ]
+{
+ # we don't actually modify the target register, so Ghidra understands the pointer target is still the same.
+ # pseudo-ops let us do that, but it means that the decompiler can put an unintuitive value in the
+ # "CopyPtrTag_AddToPtrTag_Exclude" argument, e.g. "param_2 - 0x20".
+ uimm4:1 = b_1013;
+ exclude:2 = 0;
+ Or2BytesWithExcludedTags(exclude);
+ Rd_GPR64xsp = Rn_GPR64xsp - shifted_imm;
+ CopyPtrTag_AddToPtrTag_Exclude(Rd_GPR64xsp, Rn_GPR64xsp, uimm4, exclude);
+}
+
+}
+with : ShowMemTag=0 {
+
+# C6.2.359 SUBG page C6-1947 line 114340 MATCH xd1800000/mask=xffc00000
+# CONSTRUCT xd1800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+
+:subg Rd_GPR64xsp, Rn_GPR64xsp, "#"^shifted_imm, "#"^b_1013
+is sf=1 & op=1 & S=0 & b_2328=0b100011 & b_22=0 & b_1621 & b_1013 & Rd_GPR64xsp & Rn_GPR64xsp
+# " & b_1415=0" is not required by the spec (op3 doesn't have any requirements and is not used)
+[ shifted_imm = b_1621 << $(LOG2_TAG_GRANULE); ]
+{
+ Rd_GPR64xsp = Rn_GPR64xsp - shifted_imm;
+}
+
+}
+
+
+# Subtract Pointer [setting Flags]:
+# Subtract the 56-bit address held in the second operand from the first and store the result
+# in the destination register. If the destination register is XZR, then just use as a side-
+# effect of being a pointer comparison (CMPP).
+# C6.2.360 SUBP page C6-1948 line 114410 MATCH x9ac00000/mask=xffe0fc00
+# C6.2.361 SUBPS page C6-1949 line 114470 MATCH xbac00000/mask=xffe0fc00
+# CONSTRUCT x9ac00000/mask=xdfe0fc00 MATCHED 2 DOCUMENTED OPCODES
+
+:subp^SBIT_CZNO Rd_GPR64, Rn_GPR64xsp, Rm_GPR64xsp
+is sf=1 & b_30=0 & S & SBIT_CZNO & b_2128=0b11010110 & b_1015=0b000000 & Rd_GPR64 & Rn_GPR64xsp & Rm_GPR64xsp
+{
+ # out of a 64-bit value, keep the lowest 56 bits, which is 7 bytes.
+ # sign-extend a 7-byte value to an 8-byte value. If the boundary weren't byte-aligned,
+ # sext() wouldn't work so well.
+ tmp_2:8 = Rm_GPR64xsp;
+ tmp_2 = sext(tmp_2:7); # if Rm:7 is used here, the decompiler considers the Rm register an int7 for the whole function.
+ tmp_1:8 = Rn_GPR64xsp;
+ tmp_1 = sext(tmp_1:7);
+ subflags(tmp_1, tmp_2);
+ tmp_1 = tmp_1 - tmp_2;
+ resultflags(tmp_1);
+ Rd_GPR64 = tmp_1;
+ build SBIT_CZNO;
+}
+
+
+# C6.2.376 TCANCEL page C6-1974 line 115824 MATCH xd4600000/mask=xffe0001f
+# CONSTRUCT xd4600000/mask=xffe0001f MATCHED 1 DOCUMENTED OPCODES
+
+define pcodeop cancelTransaction;
+:tcancel "#"^imm16
+is b_2131=0x6a3 & imm16 & b_0519 & b_2020 & b_0004=0x0 {
+ local tmp:2 = imm16;
+ local reason:2 = b_0519;
+ local retry:1 = b_2020;
+ cancelTransaction(reason, retry);
+}
+
+
+# C6.2.377 TCOMMIT page C6-1975 line 115871 MATCH xd503307f/mask=xffffffff
+# CONSTRUCT xd503307f/mask=xffffffff MATCHED 1 DOCUMENTED OPCODES
+
+define pcodeop commitTransaction;
+:tcommit
+is b_0031=0xd503307f {
+ commitTransaction();
+}
+
+
+# C6.2.379 TSTART page C6-1979 line 116075
+
+define pcodeop transactionStart;
+:tstart Rd_GPR64
+is b_0531=0x6a9193a & Rd_GPR64 {
+ transactionStart(Rd_GPR64);
+}
+
+
+# C6.2.380 TTEST page C6-1981 line 116175
+
+define pcodeop transactionDepth;
+:ttest Rd_GPR64
+is b_0531=0x6a9198b & Rd_GPR64 {
+ Rd_GPR64 = transactionDepth();
+}
+
+
+
+# C6.2.387 UDF page C6-1993 line 116744 MATCH x00000000/mask=xffff0000
+# CONSTRUCT x00000000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
+# Undefined instruction
+:udf b_0015
+is b_1631=0b0000000000000000 & b_0015
+{
+ local excaddr:8 = inst_start;
+ local id:2 = b_0015;
+ local target:8 = UndefinedInstructionException(id, excaddr);
+ goto [target];
+}
+
+
+# C6.2.400 XAFLAG page C6-2008 line 117528 MATCH xd500403f/mask=xfffff0ff
+# C6.2.229 MSR (immediate) page C6-1684 line 99649 MATCH xd500401f/mask=xfff8f01f
+# CONSTRUCT xd500403f/mask=xfffff0ff MATCHED 2 DOCUMENTED OPCODES
+
+:xaflag
+is b_1231=0b11010101000000000100 & b_0007=0b00111111
+{
+ tmpNG = !CY & !ZR;
+ tmpZR = ZR & CY;
+ tmpCY = CY | ZR;
+ tmpOV = !CY & ZR;
+
+ NG = tmpNG;
+ ZR = tmpZR;
+ CY = tmpCY;
+ OV = tmpOV;
+}
+
+
diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64instructions.sinc b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64instructions.sinc
new file mode 100644
index 0000000..c6bd81d
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64instructions.sinc
@@ -0,0 +1,4006 @@
+# Specification for the AARCH64 64-bit ARM instruction set
+#
+# See "ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile"
+# opcodes are always Little endian, although the data can be Big/Little Endian.
+
+# TODO Collapse SUB/SUBS forms
+# TODO MSR/MRS's need to be specified with special registers, coproc
+# TODO Many special case opcodes for UBFM and BFM, For example BFI
+
+# TODO? Floating point numbers don't display correctly as IEEE floats
+# TODO? Many special case opcodes like
+
+# TODO When writing to 32-bit Rd32, the upper bits of the bigger 64-bit Rd64 are zero'ed
+# Most pcode does this, but this needs to be carefully checked. There may be some
+# that do not zero extend into Rd64, and some that do extend into Rd64 but shouldn't.
+# If it's not done right (or naively) the decompiler gets confused. So
+# the accepted pattern for doing this is:
+#
+# ... calculate and set destination register ...
+# local tmps:SIZE = destination_register;
+# big_register = zext(tmps);
+# destination_register = big_register;
+
+# Note Implemented 2/2016
+#
+# UBFM/SBFM/BFM is implemented
+#
+# When the destination is a 32-bit register, the upper 32 bits of the register must be set to 0.
+# This includes the wsp stack pointer, which might clobber the upper part of an address.
+#
+# And when the destination is a Rd_VPR vector register but the operand size is less than 128 bits,
+# and the destination is not the upper half of the register (ie, bit 30 q=0)
+# then the unused remaining upper bits must be set to 0.
+
+@if DATA_ENDIAN == "little"
+define endian=little;
+@else
+define endian=big;
+@endif
+define alignment=4;
+
+# Unlike the above, these are preprocessor macros. Use them with e.g. $(TAG_GRANULE) in SLEIGH statements.
+@define LOG2_TAG_GRANULE "4"
+@define TAG_GRANULE "16"
+
+# SECTION registers
+
+define space ram type=ram_space size=8 default;
+define space register type=register_space size=4;
+
+# See "ABOUT THE ENDIAN IFDEFS" below for an explanation of the endian
+# ifdefs
+
+@if DATA_ENDIAN == "little"
+define register offset=0x0000 size=8 [ pc sp ];
+define register offset=0x0000 size=4 [ _ _ wsp _ ];
+@else
+define register offset=0x0000 size=8 [ pc sp ];
+define register offset=0x0000 size=4 [ _ _ _ wsp ];
+@endif
+
+define register offset=0x0100 size=1 [ NG ZR CY OV shift_carry tmpCY tmpOV tmpNG tmpZR ];
+
+define register offset=0x0200 size=4 [ glob_mask32 ];
+define register offset=0x0204 size=8 [ glob_mask64 ];
+
+# address set to load/store a value from memory in/out of vectors
+define register offset=0x0300 size=8 [ VecMemAddr VectorSelem ];
+
+# register address to load/store a value from memory in/out of registers
+define register offset=0x0310 size=4 [ VecRegAddr ];
+
+# Special Purpose Registers - most of these are really 1 bit and part
+# of a status register, however they all need to be consistent
+
+# 26 registers 0xd0 bytes
+
+define register offset=0x1000 size=8
+[
+ spsr_el1
+ elr_el1
+ sp_el0
+ spsel
+ daif
+ currentel
+ nzcv
+ fpcr
+ fpsr
+ dspsr_el0
+ dlr_el0
+ spsr_el2
+ elr_el2
+ sp_el1
+ spsr_irq
+ spsr_abt
+ spsr_und
+ spsr_fiq
+ spsr_el3
+ elr_el3
+ sp_el2
+ spsr_svc
+ spsr_hyp
+ uao
+ pan
+ tco
+ accdata
+];
+
+# System Registers
+
+# 202 registers 0x330 bytes
+define register offset=0x1100 size=8
+[
+ midr_el1
+ mpidr_el1
+ revidr_el1
+ id_dfr0_el1
+ id_pfr0_el1
+ id_pfr1_el1
+ id_afr0_el1
+ id_mmfr0_el1
+ id_mmfr1_el1
+ id_mmfr2_el1
+ id_mmfr3_el1
+ id_isar0_el1
+ id_isar1_el1
+ id_isar2_el1
+ id_isar3_el1
+ id_isar4_el1
+ id_isar5_el1
+ mvfr0_el1
+ mvfr1_el1
+ mvfr2_el1
+ ccsidr_el1
+ id_aa64pfr0_el1
+ id_aa64pfr1_el1
+ id_aa64dfr0_el1
+ id_aa64dfr1_el1
+ id_aa64isar0_el1
+ id_aa64isar1_el1
+ id_aa64mmfr0_el1
+ id_aa64mmfr1_el1
+ id_aa64afr0_el1
+ id_aa64afr1_el1
+ clidr_el1
+ aidr_el1
+ csselr_el1
+ ctr_el0
+ dczid_el0
+ vpidr_el2
+ vmpidr_el2
+ sctlr_el1
+ actlr_el1
+ cpacr_el1
+ sctlr_el2
+ actlr_el2
+ hcr_el2
+ mdcr_el2
+ cptr_el2
+ hstr_el2
+ hacr_el2
+ sctlr_el3
+ actlr_el3
+ scr_el3
+ cptr_el3
+ mdcr_el3
+ ttbr0_el1
+ ttbr1_el1
+ ttbr0_el2
+ ttbr0_el3
+ vttbr_el2
+ tcr_el1
+ tcr_el2
+ tcr_el3
+ vtcr_el2
+ afsr0_el1
+ afsr1_el1
+ afsr0_el2
+ afsr1_el2
+ afsr0_el3
+ afsr1_el3
+ esr_el1
+ esr_el2
+ esr_el3
+ fpexc32_el2
+ far_el1
+ far_el2
+ far_el3
+ hpfar_el2
+ par_el1
+ pmintenset_el1
+ pmintenclr_el1
+ pmcr_el0
+ pmcntenset_el0
+ pmcntenclr_el0
+ pmovsclr_el0
+ pmswinc_el0
+ pmselr_el0
+ pmceid0_el0
+ pmceid1_el0
+ pmccntr_el0
+ pmxevtyper_el0
+ pmxevcntr_el0
+ pmuserenr_el0
+ pmovsset_el0
+ pmevcntr0_el0
+ pmevcntr1_el0
+ pmevcntr2_el0
+ pmevcntr3_el0
+ pmevcntr4_el0
+ pmevcntr5_el0
+ pmevcntr6_el0
+ pmevcntr7_el0
+ pmevcntr8_el0
+ pmevcntr9_el0
+ pmevcntr10_el0
+ pmevcntr11_el0
+ pmevcntr12_el0
+ pmevcntr13_el0
+ pmevcntr14_el0
+ pmevcntr15_el0
+ pmevcntr16_el0
+ pmevcntr17_el0
+ pmevcntr18_el0
+ pmevcntr19_el0
+ pmevcntr20_el0
+ pmevcntr21_el0
+ pmevcntr22_el0
+ pmevcntr23_el0
+ pmevcntr24_el0
+ pmevcntr25_el0
+ pmevcntr26_el0
+ pmevcntr27_el0
+ pmevcntr28_el0
+ pmevcntr29_el0
+ pmevcntr30_el0
+ pmevtyper0_el0
+ pmevtyper1_el0
+ pmevtyper2_el0
+ pmevtyper3_el0
+ pmevtyper4_el0
+ pmevtyper5_el0
+ pmevtyper6_el0
+ pmevtyper7_el0
+ pmevtyper8_el0
+ pmevtyper9_el0
+ pmevtyper10_el0
+ pmevtyper11_el0
+ pmevtyper12_el0
+ pmevtyper13_el0
+ pmevtyper14_el0
+ pmevtyper15_el0
+ pmevtyper16_el0
+ pmevtyper17_el0
+ pmevtyper18_el0
+ pmevtyper19_el0
+ pmevtyper20_el0
+ pmevtyper21_el0
+ pmevtyper22_el0
+ pmevtyper23_el0
+ pmevtyper24_el0
+ pmevtyper25_el0
+ pmevtyper26_el0
+ pmevtyper27_el0
+ pmevtyper28_el0
+ pmevtyper29_el0
+ pmevtyper30_el0
+ pmccfiltr_el0
+ mair_el1
+ mair_el2
+ mair_el3
+ amair_el1
+ amair_el2
+ amair_el3
+ vbar_el1
+ vbar_el2
+ vbar_el3
+ rvbar_el1
+ rvbar_el2
+ rvbar_el3
+ rmr_el1
+ rmr_el2
+ rmr_el3
+ isr_el1
+ contextidr_el1
+ tpidr_el0
+ tpidrro_el0
+ tpidr_el1
+ tpidr_el2
+ tpidr_el3
+ teecr32_el1
+ cntfrq_el0
+ cntpct_el0
+ cntvct_el0
+ cntvoff_el2
+ cntkctl_el1
+ cnthctl_el2
+ cntp_tval_el0
+ cntp_ctl_el0
+ cntp_cval_el0
+ cntv_tval_el0
+ cntv_ctl_el0
+ cntv_cval_el0
+ cnthp_tval_el2
+ cnthp_ctl_el2
+ cnthp_cval_el2
+ cntps_tval_el1
+ cntps_ctl_el1
+ cntps_cval_el1
+ dacr32_el2
+ ifsr32_el2
+ teehbr32_el1
+ sder32_el3
+ gmid_el1
+ gcr_el1
+ ssbs
+ allint
+ dit
+ svcr
+];
+
+# bitrange definitions are [,]
+
+define bitrange gcr_el1.exclude=gcr_el1[0,16];
+
+# Debug Registers
+# 82 registers 0x290 bytes
+
+define register offset=0x1800 size=8
+[
+ osdtrrx_el1
+ mdccint_el1
+ mdscr_el1
+ osdtrtx_el1
+ oseccr_el1
+ dbgbvr0_el1
+ dbgbvr1_el1
+ dbgbvr2_el1
+ dbgbvr3_el1
+ dbgbvr4_el1
+ dbgbvr5_el1
+ dbgbvr6_el1
+ dbgbvr7_el1
+ dbgbvr8_el1
+ dbgbvr9_el1
+ dbgbvr10_el1
+ dbgbvr11_el1
+ dbgbvr12_el1
+ dbgbvr13_el1
+ dbgbvr14_el1
+ dbgbvr15_el1
+ dbgbcr0_el1
+ dbgbcr1_el1
+ dbgbcr2_el1
+ dbgbcr3_el1
+ dbgbcr4_el1
+ dbgbcr5_el1
+ dbgbcr6_el1
+ dbgbcr7_el1
+ dbgbcr8_el1
+ dbgbcr9_el1
+ dbgbcr10_el1
+ dbgbcr11_el1
+ dbgbcr12_el1
+ dbgbcr13_el1
+ dbgbcr14_el1
+ dbgbcr15_el1
+ dbgwvr0_el1
+ dbgwvr1_el1
+ dbgwvr2_el1
+ dbgwvr3_el1
+ dbgwvr4_el1
+ dbgwvr5_el1
+ dbgwvr6_el1
+ dbgwvr7_el1
+ dbgwvr8_el1
+ dbgwvr9_el1
+ dbgwvr10_el1
+ dbgwvr11_el1
+ dbgwvr12_el1
+ dbgwvr13_el1
+ dbgwvr14_el1
+ dbgwvr15_el1
+ dbgwcr0_el1
+ dbgwcr1_el1
+ dbgwcr2_el1
+ dbgwcr3_el1
+ dbgwcr4_el1
+ dbgwcr5_el1
+ dbgwcr6_el1
+ dbgwcr7_el1
+ dbgwcr8_el1
+ dbgwcr9_el1
+ dbgwcr10_el1
+ dbgwcr11_el1
+ dbgwcr12_el1
+ dbgwcr13_el1
+ dbgwcr14_el1
+ dbgwcr15_el1
+ mdrar_el1
+ oslar_el1
+ oslsr_el1
+ osdlr_el1
+ dbgprcr_el1
+ dbgclaimset_el1
+ dbgclaimclr_el1
+ dbgauthstatus_el1
+ mdccsr_el0
+ dbgdtr_el0
+ dbgdtrrx_el0
+ dbgdtrtx_el0
+ dbgvcr32_el2
+];
+
+define register offset=0x3000 size=4 contextreg;
+
+# value loaded from memory to store in register
+# or computed to store in memory
+define register offset=0x3100 size=4 tmp_ldWn;
+define register offset=0x3104 size=8 tmp_ldXn;
+define register offset=0x310c size=4 tmp_stWn;
+define register offset=0x3110 size=8 tmp_stXn;
+
+# General purpose and SIMD registers
+#
+# These will start at 0x3800 and there should be no defined registers
+# after this address (this is because the size of the registers is
+# potentially variable).
+#
+# ABOUT THE ENDIAN IFDEFS
+# the *address* of the overlain registers depends on if the underlying
+# memory is in big or little endian order. In little endian order, the
+# LSB is byte 0, so (for example) w0 and x0 have the same address *in
+# register memory*. But in big endian order, the LSB of x0 is byte 7,
+# and so w0 starts at byte 4. All of that just gets at the address in
+# register memory. Any time a value is loaded into a varnode and
+# manipulated in sleigh code, it is always in big endian order. It is
+# only byte reversed when read or written to little endian memory. All
+# that means is that there are endian ifdefs for the overlain
+# registers here, but that can and should be ignored when writing
+# semantics.
+
+# General purpose registers R0-R30 (R31=zero register ZR)
+# They are accessed as
+# 64-bit register named X0-X30
+# 32-bit registers named W0-W30
+
+define register offset=0x4000 size=8
+[
+ x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15
+ x16 x17 x18 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28 x29 x30 xzr
+];
+
+@if DATA_ENDIAN == "little"
+define register offset=0x4000 size=4
+[
+ w0 _
+ w1 _
+ w2 _
+ w3 _
+ w4 _
+ w5 _
+ w6 _
+ w7 _
+ w8 _
+ w9 _
+ w10 _
+ w11 _
+ w12 _
+ w13 _
+ w14 _
+ w15 _
+ w16 _
+ w17 _
+ w18 _
+ w19 _
+ w20 _
+ w21 _
+ w22 _
+ w23 _
+ w24 _
+ w25 _
+ w26 _
+ w27 _
+ w28 _
+ w29 _
+ w30 _
+ wzr _
+];
+@else
+define register offset=0x4000 size=4
+[
+ _ w0
+ _ w1
+ _ w2
+ _ w3
+ _ w4
+ _ w5
+ _ w6
+ _ w7
+ _ w8
+ _ w9
+ _ w10
+ _ w11
+ _ w12
+ _ w13
+ _ w14
+ _ w15
+ _ w16
+ _ w17
+ _ w18
+ _ w19
+ _ w20
+ _ w21
+ _ w22
+ _ w23
+ _ w24
+ _ w25
+ _ w26
+ _ w27
+ _ w28
+ _ w29
+ _ w30
+ _ wzr
+];
+@endif
+
+# SIMD&FP registers V0-V31 at 0x5000
+# They are accessed as:
+# 128-bit registers named Q0-Q31
+# 64-bit registers named D0-D31
+# 32-bit registers named S0-S31
+# 16-bit registers named H0-H31
+# 8-bit registers named B0-B31
+# a 128-bit vector of elements
+# a 64-bit vector of elements
+# The packing is endian dependent
+# For SVE, registers Z0-Z31 can be any size that is a multiple of 128
+# up to 2048 bits, and they overlap the V0-V31 registers
+
+# temporary SIMD registers, needed for calculations in SIMD semantics
+
+define register offset=0x4800 size=32 [ TMPZ1 TMPZ2 TMPZ3 TMPZ4 TMPZ5 TMPZ6 ];
+
+@if DATA_ENDIAN == "little"
+
+define register offset=0x4800 size=16
+[
+ TMPQ1 _
+ TMPQ2 _
+ TMPQ3 _
+ TMPQ4 _
+ TMPQ5 _
+ TMPQ6 _
+];
+
+define register offset=0x4800 size=8
+[
+ TMPD1 _ _ _
+ TMPD2 _ _ _
+ TMPD3 _ _ _
+ TMPD4 _ _ _
+ TMPD5 _ _ _
+ TMPD6 _ _ _
+];
+
+define register offset=0x4800 size=4
+[
+ TMPS1 _ _ _ _ _ _ _
+ TMPS2 _ _ _ _ _ _ _
+ TMPS3 _ _ _ _ _ _ _
+ TMPS4 _ _ _ _ _ _ _
+ TMPS5 _ _ _ _ _ _ _
+ TMPS6 _ _ _ _ _ _ _
+];
+
+@else # this is DATA_ENDIAN == "big"
+
+define register offset=0x4800 size=16
+[
+ _ TMPQ1
+ _ TMPQ2
+ _ TMPQ3
+ _ TMPQ4
+ _ TMPQ5
+ _ TMPQ6
+];
+
+define register offset=0x4800 size=8
+[
+ _ _ _ TMPD1
+ _ _ _ TMPD2
+ _ _ _ TMPD3
+ _ _ _ TMPD4
+ _ _ _ TMPD5
+ _ _ _ TMPD6
+];
+
+define register offset=0x4800 size=4
+[
+ _ _ _ _ _ _ _ TMPS1
+ _ _ _ _ _ _ _ TMPS2
+ _ _ _ _ _ _ _ TMPS3
+ _ _ _ _ _ _ _ TMPS4
+ _ _ _ _ _ _ _ TMPS5
+ _ _ _ _ _ _ _ TMPS6
+];
+
+@endif
+
+# The size of the simd (z) register (in bytes) can be any multiple of
+# 16 from 32 to 256 bytes. There are also 16 predicate registers are
+# 1/8 the size of the corresponding simd registers.
+
+@define SIMD_SIZE "32"
+@define PRED_SIZE "4"
+
+# In order to "move" the overlain registers to the right place, use
+# these defines to locate within the z register. The __128 is for an
+# 128-bit vector overlaid in a z-register, etc. For this to work
+# SIMD_SIZE must be at least 32.
+
+define register offset=0x5000 size=$(SIMD_SIZE)
+[
+ z0 z1 z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15
+ z16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31
+];
+
+define register offset=0x6000 size=$(PRED_SIZE)
+[
+ p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15
+];
+
+# define the overlaid simd registers
+
+@if DATA_ENDIAN == "little"
+
+define register offset=0x5000 size=16
+[
+ q0 _
+ q1 _
+ q2 _
+ q3 _
+ q4 _
+ q5 _
+ q6 _
+ q7 _
+ q8 _
+ q9 _
+ q10 _
+ q11 _
+ q12 _
+ q13 _
+ q14 _
+ q15 _
+ q16 _
+ q17 _
+ q18 _
+ q19 _
+ q20 _
+ q21 _
+ q22 _
+ q23 _
+ q24 _
+ q25 _
+ q26 _
+ q27 _
+ q28 _
+ q29 _
+ q30 _
+ q31 _
+];
+
+define register offset=0x5000 size=8
+[
+ d0 _ _ _
+ d1 _ _ _
+ d2 _ _ _
+ d3 _ _ _
+ d4 _ _ _
+ d5 _ _ _
+ d6 _ _ _
+ d7 _ _ _
+ d8 _ _ _
+ d9 _ _ _
+ d10 _ _ _
+ d11 _ _ _
+ d12 _ _ _
+ d13 _ _ _
+ d14 _ _ _
+ d15 _ _ _
+ d16 _ _ _
+ d17 _ _ _
+ d18 _ _ _
+ d19 _ _ _
+ d20 _ _ _
+ d21 _ _ _
+ d22 _ _ _
+ d23 _ _ _
+ d24 _ _ _
+ d25 _ _ _
+ d26 _ _ _
+ d27 _ _ _
+ d28 _ _ _
+ d29 _ _ _
+ d30 _ _ _
+ d31 _ _ _
+];
+
+define register offset=0x5000 size=4
+[
+ s0 _ _ _ _ _ _ _
+ s1 _ _ _ _ _ _ _
+ s2 _ _ _ _ _ _ _
+ s3 _ _ _ _ _ _ _
+ s4 _ _ _ _ _ _ _
+ s5 _ _ _ _ _ _ _
+ s6 _ _ _ _ _ _ _
+ s7 _ _ _ _ _ _ _
+ s8 _ _ _ _ _ _ _
+ s9 _ _ _ _ _ _ _
+ s10 _ _ _ _ _ _ _
+ s11 _ _ _ _ _ _ _
+ s12 _ _ _ _ _ _ _
+ s13 _ _ _ _ _ _ _
+ s14 _ _ _ _ _ _ _
+ s15 _ _ _ _ _ _ _
+ s16 _ _ _ _ _ _ _
+ s17 _ _ _ _ _ _ _
+ s18 _ _ _ _ _ _ _
+ s19 _ _ _ _ _ _ _
+ s20 _ _ _ _ _ _ _
+ s21 _ _ _ _ _ _ _
+ s22 _ _ _ _ _ _ _
+ s23 _ _ _ _ _ _ _
+ s24 _ _ _ _ _ _ _
+ s25 _ _ _ _ _ _ _
+ s26 _ _ _ _ _ _ _
+ s27 _ _ _ _ _ _ _
+ s28 _ _ _ _ _ _ _
+ s29 _ _ _ _ _ _ _
+ s30 _ _ _ _ _ _ _
+ s31 _ _ _ _ _ _ _
+];
+
+define register offset=0x5000 size=2
+[
+ h0 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h2 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h3 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h4 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h5 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h6 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h7 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h8 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h9 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h10 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h11 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h12 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h13 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h14 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h15 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h16 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h17 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h18 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h19 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h20 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h21 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h22 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h23 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h24 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h25 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h26 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h27 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h28 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h29 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h30 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ h31 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+];
+
+define register offset=0x5000 size=1
+[
+ b0 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b2 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b3 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b4 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b5 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b6 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b7 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b8 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b9 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b10 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b11 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b12 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b13 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b14 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b15 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b16 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b17 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b18 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b19 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b20 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b21 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b22 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b23 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b24 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b25 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b26 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b27 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b28 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b29 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b30 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+ b31 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+];
+
+@else # this is DATA_ENDIAN == "big"
+
+define register offset=0x5000 size=16
+[
+ _ q0
+ _ q1
+ _ q2
+ _ q3
+ _ q4
+ _ q5
+ _ q6
+ _ q7
+ _ q8
+ _ q9
+ _ q10
+ _ q11
+ _ q12
+ _ q13
+ _ q14
+ _ q15
+ _ q16
+ _ q17
+ _ q18
+ _ q19
+ _ q20
+ _ q21
+ _ q22
+ _ q23
+ _ q24
+ _ q25
+ _ q26
+ _ q27
+ _ q28
+ _ q29
+ _ q30
+ _ q31
+];
+
+define register offset=0x5000 size=8
+[
+ _ _ _ d0
+ _ _ _ d1
+ _ _ _ d2
+ _ _ _ d3
+ _ _ _ d4
+ _ _ _ d5
+ _ _ _ d6
+ _ _ _ d7
+ _ _ _ d8
+ _ _ _ d9
+ _ _ _ d10
+ _ _ _ d11
+ _ _ _ d12
+ _ _ _ d13
+ _ _ _ d14
+ _ _ _ d15
+ _ _ _ d16
+ _ _ _ d17
+ _ _ _ d18
+ _ _ _ d19
+ _ _ _ d20
+ _ _ _ d21
+ _ _ _ d22
+ _ _ _ d23
+ _ _ _ d24
+ _ _ _ d25
+ _ _ _ d26
+ _ _ _ d27
+ _ _ _ d28
+ _ _ _ d29
+ _ _ _ d30
+ _ _ _ d31
+];
+
+define register offset=0x5000 size=4
+[
+ _ _ _ _ _ _ _ s0
+ _ _ _ _ _ _ _ s1
+ _ _ _ _ _ _ _ s2
+ _ _ _ _ _ _ _ s3
+ _ _ _ _ _ _ _ s4
+ _ _ _ _ _ _ _ s5
+ _ _ _ _ _ _ _ s6
+ _ _ _ _ _ _ _ s7
+ _ _ _ _ _ _ _ s8
+ _ _ _ _ _ _ _ s9
+ _ _ _ _ _ _ _ s10
+ _ _ _ _ _ _ _ s11
+ _ _ _ _ _ _ _ s12
+ _ _ _ _ _ _ _ s13
+ _ _ _ _ _ _ _ s14
+ _ _ _ _ _ _ _ s15
+ _ _ _ _ _ _ _ s16
+ _ _ _ _ _ _ _ s17
+ _ _ _ _ _ _ _ s18
+ _ _ _ _ _ _ _ s19
+ _ _ _ _ _ _ _ s20
+ _ _ _ _ _ _ _ s21
+ _ _ _ _ _ _ _ s22
+ _ _ _ _ _ _ _ s23
+ _ _ _ _ _ _ _ s24
+ _ _ _ _ _ _ _ s25
+ _ _ _ _ _ _ _ s26
+ _ _ _ _ _ _ _ s27
+ _ _ _ _ _ _ _ s28
+ _ _ _ _ _ _ _ s29
+ _ _ _ _ _ _ _ s30
+ _ _ _ _ _ _ _ s31
+];
+
+define register offset=0x5000 size=2
+[
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h0
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h1
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h2
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h3
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h4
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h5
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h6
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h7
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h8
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h9
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h10
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h11
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h12
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h13
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h14
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h15
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h16
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h17
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h18
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h19
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h20
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h21
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h22
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h23
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h24
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h25
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h26
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h27
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h28
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h29
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h30
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ h31
+];
+
+define register offset=0x5000 size=1
+[
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b0
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b1
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b2
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b3
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b4
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b5
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b6
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b7
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b8
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b9
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b10
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b11
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b12
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b13
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b14
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b15
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b16
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b17
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b18
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b19
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b20
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b21
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b22
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b23
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b24
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b25
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b26
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b27
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b28
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b29
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b30
+ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ b31
+];
+@endif
+
+# SECTION token fields and context variables
+
+# "noflow" limits register changes to a single instruction (or a highlighted region) rather than following control flow.
+# This allows the select-clear-SetRegister-disassemble procedure to be done without affecting
+# any instructions other than those that are selected.
+define context contextreg
+ ImmS_ImmR_TestSet = (0,0)
+ ImmS_LT_ImmR = (1,1)
+ ImmS_EQ_ImmR = (2,2)
+ ImmS_LT_ImmR_minus_1 = (3,3)
+ ImmS_ne_1f = (4,4)
+ ImmS_ne_3f = (5,5)
+ ShowPAC = (21,21) noflow
+ PAC_clobber = (22,22) noflow
+ ShowBTI = (23,23) noflow
+ ShowMemTag = (24,24) noflow
+;
+
+define token instrAARCH64 (32) endian = little
+
+ Rm = (16,20)
+ Rn = (5,9)
+ Rd = (0,4)
+ Rt = (0,4)
+ Ra = (10,14)
+ Rt2 = (10,14)
+
+ Rm_FPR8 = (16,20)
+ Rn_FPR8 = (5,9)
+ Rd_FPR8 = (0,4)
+ Rd_FPR8_2 = (0,4)
+ Rt_FPR8 = (0,4)
+ Rm_FPR16 = (16,20)
+ Rn_FPR16 = (5,9)
+ Rd_FPR16 = (0,4)
+ Rd_FPR16_2 = (0,4)
+ Rt_FPR16 = (0,4)
+ Ra_FPR16 = (10,14)
+ Rm_FPR32 = (16,20)
+ Rn_FPR32 = (5,9)
+ Rd_FPR32 = (0,4)
+ Rd_FPR32_2 = (0,4)
+ Ra_FPR32 = (10,14)
+ Rm_FPR64 = (16,20)
+ Rn_FPR64 = (5,9)
+ Rd_FPR64 = (0,4)
+ Rd_FPR64_2 = (0,4)
+ Rt_FPR64 = (0,4)
+ Rt_FPR32 = (0,4)
+ Ra_FPR64 = (10,14)
+ Rt2_FPR128 = (10,14)
+ Rt2_FPR32 = (10,14)
+ Rt2_FPR64 = (10,14)
+ Ra_VPR128 = (10,14)
+
+ Rm_VPR64 = (16,20)
+ Rn_VPR64 = (5,9)
+ Rd_VPR64 = (0,4)
+
+ Re_VPR128 = (16,20)
+ Re_VPR128Lo = (16,19)
+ Rm_VPR128 = (16,20)
+ Rm_VPR128Lo = (16,19)
+ Rn_VPR128 = (5,9)
+ Rnn_VPR128 = (5,9)
+ Rnnn_VPR128 = (5,9)
+ Rnnnn_VPR128 = (5,9)
+ Rd_VPR128 = (0,4)
+ Rt_VPR128 = (0,4)
+ Rtt_VPR128 = (0,4)
+ Rttt_VPR128 = (0,4)
+ Rtttt_VPR128 = (0,4)
+ Rt_VPR64 = (0,4)
+ Rtt_VPR64 = (0,4)
+ Rttt_VPR64 = (0,4)
+ Rtttt_VPR64 = (0,4)
+ Rt_FPR128 = (0,4)
+ vRm_VPR64 = (16,20)
+ vRm_VPR128Lo = (16,19)
+ vRe_VPR128 = (16,20)
+ vRe_VPR128Lo = (16,19)
+ vRn_VPR64 = (5,9)
+ vRd_VPR64 = (0,4)
+ vRm_VPR128 = (16,20)
+ vRn_VPR128 = (5,9)
+ vRnn_VPR128 = (5,9)
+ vRnnn_VPR128 = (5,9)
+ vRnnnn_VPR128 = (5,9)
+ vRd_VPR128 = (0,4)
+ vRa_VPR128 = (10,14)
+
+ Vt = (0,4)
+ Vtt = (0,4)
+ Vttt = (0,4)
+ Vtttt = (0,4)
+
+ vVt = (0,4)
+ vVtt = (0,4)
+ vVttt = (0,4)
+ vVtttt = (0,4)
+
+ aa_Xm = (16,20)
+ aa_Xn = (5,9)
+ aa_Xd = (0,4)
+ aa_Xs = (16,20)
+ aa_Xss = (16,20)
+ aa_Xt = (0,4)
+ aa_Xtt = (0,4)
+ aa_Xa = (10,14)
+ aa_Wm = (16,20)
+ aa_Wn = (5,9)
+ aa_Wd = (0,4)
+ aa_Ws = (16,20)
+ aa_Wss = (16,20)
+ aa_Wt = (0,4)
+ aa_Wtt = (0,4)
+ aa_Wa = (10,14)
+ aa_Wa2 = (10,14)
+ aa_CRm = (8,11)
+
+ br_cond_op = (0,3)
+ cond_op = (12,15)
+
+ aa_prefetch = (0,4)
+
+ aa_hw = (21,22)
+
+ aa_extreg_imm3 = (10,12)
+ aa_extreg_shift = (22,23)
+ aa_extreg_option = (13,15)
+
+ imm6 = (10,15)
+ aa_imm7 = (15,21)
+ imm12 = (10,21)
+ imm16 = (5,20)
+
+ simm7 = (15,21) signed
+ simm9 = (12,20) signed
+ simm14 = (5,18) signed
+ simm19 = (5,23) signed
+ simm26 = (0,25) signed
+
+ immlo = (29,30)
+ immhi = (5,23) signed
+
+ # Arbitrary bit fields
+
+ b_00 = (0,0)
+ b_01 = (1,1)
+ b_02 = (2,2)
+ b_03 = (3,3)
+ b_04 = (4,4)
+ b_05 = (5,5)
+ b_06 = (6,6)
+ b_07 = (7,7)
+ b_08 = (8,8)
+ b_09 = (9,9)
+ b_10 = (10,10)
+ b_11 = (11,11)
+ b_12 = (12,12)
+ b_13 = (13,13)
+ b_14 = (14,14)
+ b_15 = (15,15)
+ b_16 = (16,16)
+ b_17 = (17,17)
+ b_18 = (18,18)
+ b_19 = (19,19)
+ b_20 = (20,20)
+ b_21 = (21,21)
+ b_22 = (22,22)
+ b_23 = (23,23)
+ b_24 = (24,24)
+ b_25 = (25,25)
+ b_26 = (26,26)
+ b_27 = (27,27)
+ b_28 = (28,28)
+ b_29 = (29,29)
+ b_30 = (30,30)
+ b_31 = (31,31)
+
+ b_0001 = (0,1)
+ b_0003 = (0,3)
+ b_0004 = (0,4)
+ b_0006 = (0,6)
+ b_0007 = (0,7)
+ b_0009 = (0,9)
+ b_0011 = (0,11)
+ b_0015 = (0,15)
+ b_0027 = (0,27)
+ b_0031 = (0,31)
+ b_0102 = (1,2)
+ b_0103 = (1,3)
+ b_0204 = (2,4)
+ b_0304 = (3,4)
+ b_0405 = (4,5)
+ b_0406 = (4,6)
+ b_0407 = (4,7)
+ b_0409 = (4,9)
+ b_0411 = (4,11)
+ b_0427 = (4,27)
+ b_0431 = (4,31)
+ b_0506 = (5,6)
+ b_0507 = (5,7)
+ b_0508 = (5,8)
+ b_0509 = (5,9)
+ b_0510 = (5,10)
+ b_0515 = (5,15)
+ b_0519 = (5,19)
+ b_0531 = (5,31)
+ b_0607 = (6,7)
+ b_0609 = (6,9)
+ b_0610 = (6,10)
+ b_0611 = (6,11)
+ b_0708 = (7,8)
+ b_0709 = (7,9)
+ b_0710 = (7,10)
+ b_0711 = (7,11)
+ b_0809 = (8,9)
+ b_0810 = (8,10)
+ b_0811 = (8,11)
+ b_0910 = (9,10)
+ b_0911 = (9,11)
+ b_0916 = (9,16)
+ b_1010 = (10,10)
+ b_1011 = (10,11)
+ b_1012 = (10,12)
+ b_1013 = (10,13)
+ b_1014 = (10,14)
+ b_1015 = (10,15)
+ b_1021 = (10,21)
+ b_1022 = (10,22)
+ b_1028 = (10,28)
+ b_1029 = (10,29)
+ b_1031 = (10,31)
+ b_1111 = (11,11)
+ b_1112 = (11,12)
+ b_1113 = (11,13)
+ b_1114 = (11,14)
+ b_1115 = (11,15)
+ b_1116 = (11,16)
+ b_1131 = (11,31)
+ b_1212 = (12,12)
+ b_1213 = (12,13)
+ b_1214 = (12,14)
+ b_1215 = (12,15)
+ b_1216 = (12,16)
+ b_1217 = (12,17)
+ b_1220 = (12,20)
+ b_1223 = (12,23)
+ b_1229 = (12,29)
+ b_1230 = (12,30)
+ b_1231 = (12,31)
+ b_1313 = (13,13)
+ b_1314 = (13,14)
+ b_1315 = (13,15)
+ b_1317 = (13,17)
+ b_1321 = (13,21)
+ b_1322 = (13,22)
+ b_1414 = (14,14)
+ b_1417 = (14,17)
+ b_1415 = (14,15)
+ b_1431 = (14,31)
+ b_1515 = (15,15)
+ b_1517 = (15,17)
+ b_1520 = (15,20)
+ b_1531 = (15,31)
+ b_1616 = (16,16)
+ b_1617 = (16,17)
+ b_1618 = (16,18)
+ b_1619 = (16,19)
+ b_1620 = (16,20)
+ b_1621 = (16,21)
+ b_1623 = (16,23)
+ b_1627 = (16,27)
+ b_1629 = (16,29)
+ b_1631 = (16,31)
+ b_1718 = (17,18)
+ b_1719 = (17,19)
+ b_1720 = (17,20)
+ b_1721 = (17,21)
+ b_1722 = (17,22)
+ b_1818 = (18,18)
+ b_1819 = (18,19)
+ b_1820 = (18,20)
+ b_1821 = (18,21)
+ b_1920 = (19,20)
+ b_1921 = (19,21)
+ b_1922 = (19,22)
+ b_1923 = (19,23)
+ b_1928 = (19,28)
+ b_1929 = (19,29)
+ b_1931 = (19,31)
+ b_2020 = (20,20)
+ b_2021 = (20,21)
+ b_2022 = (20,22)
+ b_2023 = (20,23)
+ b_2024 = (20,24)
+ b_2027 = (20,27)
+ b_2121 = (21,21)
+ b_2122 = (21,22)
+ b_2123 = (21,23)
+ b_2124 = (21,24)
+ b_2125 = (21,25)
+ b_2127 = (21,27)
+ b_2128 = (21,28)
+ b_2129 = (21,29)
+ b_2130 = (21,30)
+ b_2131 = (21,31)
+ b_2222 = (22,22)
+ b_2223 = (22,23)
+ b_2224 = (22,24)
+ b_2225 = (22,25)
+ b_2229 = (22,29)
+ b_2231 = (22,31)
+ b_2323 = (23,23)
+ b_2324 = (23,24)
+ b_2325 = (23,25)
+ b_2327 = (23,27)
+ b_2328 = (23,28)
+ b_2329 = (23,29)
+ b_2331 = (23,31)
+ b_2425 = (24,25)
+ b_2427 = (24,27)
+ b_2428 = (24,28)
+ b_2429 = (24,29)
+ b_2430 = (24,30)
+ b_2431 = (24,31)
+ b_2525 = (25,25)
+ b_2527 = (25,27)
+ b_2529 = (25,29)
+ b_2530 = (25,30)
+ b_2531 = (25,31)
+ b_2627 = (26,27)
+ b_2629 = (26,29)
+ b_2630 = (26,30)
+ b_2631 = (26,31)
+ b_2729 = (27,29)
+ b_2929 = (29,29)
+ b_2930 = (29,30)
+ b_2931 = (29,31)
+ b_3030 = (30,30)
+ b_3031 = (30,31)
+ b_3131 = (31,31)
+
+ cmpr_op = (24,24)
+ sf = (31,31)
+
+ imm_neon_uimm1 = (20,20)
+ imm_neon_uimm2 = (19,20)
+ imm_neon_uimm3 = (18,20)
+ imm_neon_uimm4 = (17,20)
+ immN_neon_uimm1 = (14,14)
+ immN_neon_uimm2 = (13,14)
+ immN_neon_uimm3 = (12,14)
+ immN_neon_uimm4 = (11,14)
+
+ fpOpcode = (16,18)
+ fpDpOpcode = (15,20)
+
+ CRm_CRx = (8,11)
+ CRm_32 = (10,11)
+ CRm_10 = (8,9)
+ CRm_dbarrier_op = (8,11)
+ CRm_isb_op = (8,11)
+
+ CRn = (12,15)
+ CRm = (8,11)
+ CRn_CRx = (12,15)
+
+ Imm4 = (11,13)
+
+ # C2.2.3 Modified immediate constants in A64 instructions page C2-158
+
+ Imm8_fmov_sign = (20,20) # a
+ Imm8_fmov_exph = (19,19) # b
+ Imm8_fmov_expl = (17,18) # cd
+ Imm8_fmov_frac = (13,16) # efgh
+
+ ImmN = (22,22)
+ ImmR = (16,21)
+ ImmS = (10,15)
+ Imm_imm0_63 = (16,21)
+
+ n_uimm8L = (5,9)
+ n_uimm8H = (16,18)
+
+ Imm_uimm3 = (16,18)
+ Imm_uimm4 = (16,19)
+ Imm_uimm5 = (16,20)
+ Imm_uimm5_31 = (31,31)
+ Imm_uimm6 = (31,31)
+
+ L = (22,22)
+
+ N = (21,21)
+
+ Op0 = (19,20)
+ Op1 = (16,18)
+ Op1_uimm3 = (16,18)
+ Op2 = (5,7)
+ Op2_uimm3 = (5,7)
+ Q = (30,30)
+ S = (29,29)
+
+ Scale = (10,15)
+
+ excCode = (21,23)
+ excCode2 = (2,4)
+
+ imm7Low = (5,11)
+
+ cmode = (12,15)
+ imm4 = (11,14)
+ imm5 = (5,9)
+ l = (21,21)
+ ll = (0,1)
+ m = (31,31)
+ mode = (19,20)
+ n = (22,22)
+ o0 = (4,4)
+ o1 = (24,24)
+ o2 = (10,10)
+
+ o3 = (4,4)
+ op = (30,30)
+
+ fpccmp.op = (4,4)
+ fpcmp.op = (14,15)
+
+ op2 = (16,20)
+
+ op3 = (10,15)
+ op4 = (0,4)
+ opc = (29,30)
+ opc.indexmode = (10,11)
+
+ op.dp3 = (29,30)
+ op.dp3_o0 = (15,15)
+ op.dp3_op31 = (21,23)
+ op.dp3_op54 = (29,30)
+
+ opcode2 = (10,15)
+ dp1.opcode2 = (16,20)
+ fpcmp.opcode2 = (0,4)
+ opt = (22,23)
+ option = (13,15)
+ optionlo = (13,13)
+ q = (30,30)
+ rmode = (19,20)
+ s = (29,29)
+
+ size.ldstr = (30,31)
+
+ shift = (22,23)
+ advSIMD3.size = (22,23)
+ size.neon = (10,11)
+
+ size_high = (23,23)
+ ftype = (22,23)
+ u = (29,29)
+ v = (26,26)
+
+ # SVE tokens
+
+ Zd = (0,4)
+ Zt = (0,4)
+ Ztt = (0,4)
+ Zttt = (0,4)
+ Ztttt = (0,4)
+ Ze = (16,20)
+ Zm = (16,20)
+ Zn = (5,9)
+ Zt2 = (10,14)
+
+ sve_b_00 = (0,0)
+ sve_b_0001 = (0,1)
+ sve_b_01 = (1,1)
+ sve_b_02 = (2,2)
+ sve_b_03 = (3,3)
+ sve_b_04 = (4,4)
+ sve_b_0409 = (4,9)
+ sve_b_0609 = (6,9)
+ sve_b_09 = (9,9)
+ sve_b_10 = (10,10)
+ sve_b_1015 = (10,15)
+ sve_b_1019 = (10,19)
+ sve_b_1021 = (10,21)
+ sve_b_11 = (11,11)
+ sve_b_1112 = (11,12)
+ sve_b_1115 = (11,15)
+ sve_b_12 = (12,12)
+ sve_b_1215 = (12,15)
+ sve_b_13 = (13,13)
+ sve_b_1315 = (13,15)
+ sve_b_1321 = (13,21)
+ sve_b_14 = (14,14)
+ sve_b_1415 = (14,15)
+ sve_b_1416 = (14,16)
+ sve_b_1419 = (14,19)
+ sve_b_1421 = (14,21)
+ sve_b_15 = (15,15)
+ sve_b_16 = (16,16)
+ sve_b_17 = (17,17)
+ sve_b_1718 = (17,18)
+ sve_b_1719 = (17,19)
+ sve_b_1720 = (17,20)
+ sve_b_1721 = (17,21)
+ sve_b_1731 = (17,31)
+ sve_b_18 = (18,18)
+ sve_b_1821 = (18,21)
+ sve_b_1831 = (18,31)
+ sve_b_1921 = (19,21)
+ sve_b_20 = (20,20)
+ sve_b_2021 = (20,21)
+ sve_b_2022 = (20,22)
+ sve_b_21 = (21,21)
+ sve_b_2122 = (21,22)
+ sve_b_2131 = (21,31)
+ sve_b_22 = (22,22)
+ sve_b_2224 = (22,24)
+ sve_b_2231 = (22,31)
+ sve_b_23 = (23,23)
+ sve_b_2331 = (23,31)
+ sve_b_24 = (24,24)
+ sve_b_2429 = (24,29)
+ sve_b_2431 = (24,31)
+ sve_b_2531 = (25,31)
+ sve_b_3031 = (30,31)
+ sve_float_dec = (5,8)
+ sve_float_exp = (9,11)
+ sve_i1_05 = (5,5)
+ sve_i1_20 = (20,20)
+ sve_i2_1920 = (19,20)
+ sve_i3h_22 = (22,22)
+ sve_i3l_1920 = (19,20)
+ sve_imm13_0517 = (5,17)
+ sve_imm2_2223 = (22,23)
+ sve_imm3_0507 = (5,7)
+ sve_imm3_1618 = (16,18)
+ sve_imm4_1619 = (16,19)
+ sve_imm4s_1619 = (16,19) signed
+ sve_imm5_0509 = (5,9)
+ sve_imm5s_0509 = (5,9) signed
+ sve_imm5_1620 = (16,20)
+ sve_imm5s_1620 = (16,20) signed
+ sve_imm5b_1620 = (16,20) signed
+ sve_imm6_0510 = (5,10)
+ sve_imm6s_0510 = (5,10) signed
+ sve_imm6_1621 = (16,21)
+ sve_imm6s_1621 = (16,21) signed
+ sve_imm7_1420 = (14,20)
+ sve_imm8_0512 = (5,12)
+ sve_imm8s_0512 = (5,12) signed
+ sve_imm8h_1620 = (16,20)
+ sve_imm8l_1012 = (10,12)
+ sve_imm9h_1621 = (16,21)
+ sve_imm9hs_1621 = (16,21) signed
+ sve_imm9l_1012 = (10,12)
+ sve_m_04 = (4,4)
+ sve_m_14 = (14,14)
+ sve_m_16 = (16,16)
+ sve_msz_1011 = (10,11)
+ sve_pattern_0509 = (5,9)
+ sve_pd_0003 = (0,3)
+ sve_pdm_0003 = (0,3)
+ sve_pdn_0003 = (0,3)
+ sve_pg_0508 = (5,8)
+ sve_pg_1012 = (10,12)
+ sve_pg_1013 = (10,13)
+ sve_pg_1619 = (16,19)
+ sve_pm_1619 = (16,19)
+ sve_pn_0508 = (5,8)
+ sve_prfop_0003 = (0,3)
+ sve_pt_0003 = (0,3)
+ sve_rd_0004 = (0,4)
+ sve_rdn_0004 = (0,4)
+ sve_rm_0509 = (5,9)
+ sve_rm_1620 = (16,20)
+ sve_rn_0509 = (5,9)
+ sve_rn_1620 = (16,20)
+ sve_rot_1011 = (10,11)
+ sve_rot_1314 = (13,14)
+ sve_rot_16 = (16,16)
+ sve_s_22 = (22,22)
+ sve_sf_12 = (12,12)
+ sve_sh_13 = (13,13)
+ sve_size_2122 = (21,22)
+ sve_size_2223 = (22,23)
+ sve_sz_22 = (22,22)
+ sve_tsz_1620 = (16,20)
+ sve_tszh_2223 = (22,23)
+ sve_tszl_0809 = (8,9)
+ sve_tszl_1920 = (19,20)
+ sve_vd_0004 = (0,4)
+ sve_vdn_0004 = (0,4)
+ sve_vm_0509 = (5,9)
+ sve_vn_0509 = (5,9)
+ sve_xs_14 = (14,14)
+ sve_xs_22 = (22,22)
+ sve_za_0509 = (5,9)
+ sve_za_1620 = (16,20)
+ sve_zd_0004 = (0,4)
+ sve_zda_0004 = (0,4)
+ sve_zdn_0004 = (0,4)
+ sve_zm_0509 = (5,9)
+ sve_zm_1618 = (16,18)
+ sve_zm_1619 = (16,19)
+ sve_zm_1620 = (16,20)
+ sve_zn_0509 = (5,9)
+ sve_zt_0004 = (0,4)
+ sve_ztt_0004 = (0,4)
+ sve_zttt_0004 = (0,4)
+ sve_ztttt_0004 = (0,4)
+;
+
+# SECTION variables and variable names
+
+attach variables [ Zd Ze Zm Zn Zt Zt2 ]
+[
+ z0 z1 z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15
+ z16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31
+];
+
+attach variables [ Ztt ]
+[
+ z1 z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15
+ z16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31 z0
+];
+
+attach variables [ Zttt ]
+[
+ z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15
+ z16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31 z0 z1
+];
+
+attach variables [ Ztttt ]
+[
+ z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15
+ z16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31 z0 z1 z2
+];
+
+attach variables [ aa_Xn aa_Xm aa_Xs aa_Xd aa_Xt aa_Xa ]
+[
+ x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15
+ x16 x17 x18 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28 x29 x30 xzr
+];
+
+attach variables [ aa_Xss aa_Xtt ]
+[
+ x1 _ x3 _ x5 _ x7 _ x9 _ x11 _ x13 _ x15
+ _ x17 _ x19 _ x21 _ x23 _ x25 _ x27 _ x29 _ xzr _
+];
+
+attach variables [ aa_Wn aa_Wm aa_Ws aa_Wd aa_Wt aa_Wa ]
+[
+ w0 w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 w14 w15
+ w16 w17 w18 w19 w20 w21 w22 w23 w24 w25 w26 w27 w28 w29 w30 wzr
+];
+
+attach variables [ aa_Wss aa_Wtt ]
+[
+ w1 _ w3 _ w5 _ w7 _ w9 _ w11 _ w13 _ w15
+ _ w17 _ w19 _ w21 _ w23 _ w25 _ w27 _ w29 _ wzr _
+];
+
+attach variables [ Rm_VPR128 Rn_VPR128 Rd_VPR128 Rt_VPR128 Rt2_FPR128 Re_VPR128 Rt_FPR128 Ra_VPR128 ]
+[
+ q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15
+ q16 q17 q18 q19 q20 q21 q22 q23 q24 q25 q26 q27 q28 q29 q30 q31
+];
+
+attach variables [ Rnn_VPR128 Rtt_VPR128 ]
+[
+ q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15
+ q16 q17 q18 q19 q20 q21 q22 q23 q24 q25 q26 q27 q28 q29 q30 q31
+ q0
+];
+
+attach variables [ Rnnn_VPR128 Rttt_VPR128 ]
+[
+ q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15
+ q16 q17 q18 q19 q20 q21 q22 q23 q24 q25 q26 q27 q28 q29 q30 q31
+ q0 q1
+];
+
+attach variables [ Rnnnn_VPR128 Rtttt_VPR128 ]
+[
+ q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15
+ q16 q17 q18 q19 q20 q21 q22 q23 q24 q25 q26 q27 q28 q29 q30 q31
+ q0 q1 q2
+];
+
+attach names [ vRm_VPR128 vRn_VPR128 vRd_VPR128 vRe_VPR128 vRa_VPR128 ]
+[
+ v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15
+ v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31
+];
+
+attach names [ vRnn_VPR128 ]
+[
+ v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15
+ v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31
+ v0
+];
+
+attach names [ vRnnn_VPR128 ]
+[
+ v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15
+ v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31
+ v0 v1
+];
+
+attach names [ vRnnnn_VPR128 ]
+[
+ v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15
+ v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31
+ v0 v1 v2
+];
+
+attach variables [ Rm_VPR128Lo Re_VPR128Lo ] [ q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 ];
+
+attach names [ vRm_VPR128Lo vRe_VPR128Lo ] [ v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 ];
+
+attach variables [ Rm_VPR64 Rn_VPR64 Rd_VPR64 Rt_VPR64 ]
+[
+ d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15
+ d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31
+];
+
+attach variables [ Rtt_VPR64 ]
+[
+ d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15
+ d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 d0
+];
+
+attach variables [ Rttt_VPR64 ]
+[
+ d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15
+ d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 d0 d1
+];
+
+attach variables [ Rtttt_VPR64 ]
+[
+ d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15
+ d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 d0 d1 d2
+];
+
+attach names [ vRm_VPR64 vRn_VPR64 vRd_VPR64 ]
+[
+ v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15
+ v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31
+];
+
+attach variables [ Rm_FPR64 Rn_FPR64 Rd_FPR64 Rd_FPR64_2 Rt2_FPR64 Ra_FPR64 Rt_FPR64 ]
+[
+ d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15
+ d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31
+];
+
+attach variables [ Rm_FPR32 Rn_FPR32 Rd_FPR32 Rd_FPR32_2 Rt2_FPR32 Ra_FPR32 Rt_FPR32 ]
+[
+ s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15
+ s16 s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31
+];
+
+attach variables [ Rm_FPR16 Rn_FPR16 Rd_FPR16 Rd_FPR16_2 Rt_FPR16 Ra_FPR16 ]
+[
+ h0 h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14 h15
+ h16 h17 h18 h19 h20 h21 h22 h23 h24 h25 h26 h27 h28 h29 h30 h31
+];
+
+attach variables [ Rm_FPR8 Rn_FPR8 Rd_FPR8 Rd_FPR8_2 Rt_FPR8 ]
+[
+ b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15
+ b16 b17 b18 b19 b20 b21 b22 b23 b24 b25 b26 b27 b28 b29 b30 b31
+];
+
+attach variables [ Vt ]
+[
+ q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15
+ q16 q17 q18 q19 q20 q21 q22 q23 q24 q25 q26 q27 q28 q29 q30 q31
+];
+
+attach variables [ Vtt ]
+[
+ q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15
+ q16 q17 q18 q19 q20 q21 q22 q23 q24 q25 q26 q27 q28 q29 q30 q31 q0
+];
+
+attach variables [ Vttt ]
+[
+ q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15
+ q16 q17 q18 q19 q20 q21 q22 q23 q24 q25 q26 q27 q28 q29 q30 q31 q0 q1
+];
+
+attach variables [ Vtttt ]
+[
+ q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15
+ q16 q17 q18 q19 q20 q21 q22 q23 q24 q25 q26 q27 q28 q29 q30 q31 q0 q1 q2
+];
+
+attach names [ vVt ]
+[
+ v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15
+ v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31
+];
+
+attach names [ vVtt ]
+[
+ v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15
+ v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 v0
+];
+
+attach names [ vVttt ]
+[
+ v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15
+ v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 v0 v1
+];
+
+attach names [ vVtttt ]
+[
+ v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15
+ v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 v0 v1 v2
+];
+
+attach names [ aa_prefetch ]
+[
+ PLDL1KEEP PLDL1STRM PLDL2KEEP PLDL2STRM PLDL3KEEP PLDL3STRM P_0x06 P_0x07
+ PLIL1KEEP PLIL1STRM PLIL2KEEP PLIL2STRM PLIL3KEEP PLIL3STRM P_0x0e P_0x0f
+ PSTL1KEEP PSTL1STRM PSTL2KEEP PSTL2STRM PSTL3KEEP PSTL3STRM
+ P_0x16 P_0x17 P_0x18 P_0x19 P_0x1a P_0x1b P_0x1c P_0x1d P_0x1e P_0x1f
+];
+
+attach names [ CRm_dbarrier_op ] [ _ OSHLD OSHST OSH _ NSHLD NSHST NSH _ ISHLD ISHST ISH _ LD ST SY ];
+
+# SVE registers and names
+
+attach variables [ sve_zm_1618 ]
+[
+ z0 z1 z2 z3 z4 z5 z6 z7
+];
+
+attach variables [ sve_zm_1619 ]
+[
+ z0 z1 z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15
+];
+
+attach variables [ sve_za_0509 sve_za_1620 sve_zd_0004 sve_zda_0004 sve_zdn_0004 sve_zm_0509 sve_zm_1620 sve_zn_0509 sve_zt_0004 ]
+[
+ z0 z1 z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15
+ z16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31
+];
+
+attach variables [ sve_ztt_0004 ]
+[
+ z1 z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15
+ z16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31 z0
+];
+
+attach variables [ sve_zttt_0004 ]
+[
+ z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15
+ z16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31 z0 z1
+];
+
+attach variables [ sve_ztttt_0004 ]
+[
+ z3 z4 z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15
+ z16 z17 z18 z19 z20 z21 z22 z23 z24 z25 z26 z27 z28 z29 z30 z31 z0 z1 z2
+];
+
+attach variables [ sve_pg_1012 ]
+[
+ p0 p1 p2 p3 p4 p5 p6 p7
+];
+
+attach variables [ sve_pd_0003 sve_pdm_0003 sve_pdn_0003 sve_pg_0508 sve_pg_1013 sve_pg_1619 sve_pm_1619 sve_pn_0508 sve_pt_0003 ]
+[
+ p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15
+];
+
+attach names [ sve_sz_22 ] [ b h ];
+attach names [ sve_msz_1011 ] [ "" " #1" " #2" " #3" ];
+attach names [ sve_rot_16 ] [ "#90" "#270" ];
+attach names [ sve_rot_1314 ] [ "#0" "#90" "#180" "#270" ];
+attach names [ sve_rot_1011 ] [ "#0" "#90" "#180" "#270" ];
+
+# SECTION subtables
+
+Rm_GPR32: aa_Wm is aa_Wm { export aa_Wm; }
+Rm_GPR32: wzr is aa_Wm=31 & wzr { tmp:4 = 0; export tmp; }
+
+Rd_GPR32: aa_Wd is aa_Wd { export aa_Wd; }
+Rd_GPR32: wzr is aa_Wd=31 & wzr { tmp:4 = 0; export tmp; }
+Rd_GPR32_2: aa_Wd is aa_Wd { export aa_Wd; }
+Rd_GPR32_2: wzr is aa_Wd=31 & wzr { tmp:4 = 0; export tmp; }
+
+Rd_GPR32xsp: aa_Wd is aa_Wd { export aa_Wd; }
+Rd_GPR32xsp: wsp is aa_Wd=31 & wsp { export wsp; }
+
+Rd_GPR32wsp: Rd_GPR32xsp is Rd_GPR32xsp { export Rd_GPR32xsp; }
+
+Rn_GPR32: aa_Wn is aa_Wn { export aa_Wn; }
+Rn_GPR32: wzr is aa_Wn=31 & wzr { tmp:4 = 0; export tmp; }
+
+Ra_GPR32: aa_Wa is aa_Wa { export aa_Wa; }
+Ra_GPR32: wzr is aa_Wa=31 & wzr { tmp:4 = 0; export tmp; }
+
+Rt2_GPR32: aa_Wa is aa_Wa { export aa_Wa; }
+Rt2_GPR32: wzr is aa_Wa=31 & wzr { tmp:4 = 0; export tmp; }
+
+Rn_GPR32xsp: aa_Wn is aa_Wn { export aa_Wn; }
+Rn_GPR32xsp: wsp is aa_Wn=31 & wsp { export wsp; }
+
+Rn_GPR32wsp: aa_Wn is aa_Wn { export aa_Wn; }
+Rn_GPR32wsp: wsp is aa_Wn=31 & wsp { export wsp; }
+
+Rt_GPR32: aa_Wt is aa_Wt { export aa_Wt; }
+Rt_GPR32: wzr is aa_Wt=31 & wzr { tmp:4 = 0; export tmp; }
+
+Rm_GPR64: aa_Xm is aa_Xm { export aa_Xm; }
+Rm_GPR64: xzr is aa_Xm=31 & xzr { export 0:8; }
+
+Rd_GPR64: aa_Xd is aa_Xd { export aa_Xd; }
+Rd_GPR64: xzr is aa_Xd=31 & xzr { tmp:8 = 0; export tmp; }
+Rd_GPR64_2: aa_Xd is aa_Xd { export aa_Xd; }
+Rd_GPR64_2: xzr is aa_Xd=31 & xzr { tmp:8 = 0; export tmp; }
+
+Ra_GPR64: aa_Xa is aa_Xa { export aa_Xa; }
+Ra_GPR64: xzr is aa_Xa=31 & xzr { tmp:8 = 0; export tmp; }
+
+Rt2_GPR64: aa_Xa is aa_Xa { export aa_Xa; }
+Rt2_GPR64: xzr is aa_Xa=31 & xzr { tmp:8 = 0; export tmp; }
+
+Rd_GPR64xsp: aa_Xd is aa_Xd { export aa_Xd; }
+Rd_GPR64xsp: sp is aa_Xd=31 & sp { export sp; }
+
+Rn_GPR64: aa_Xn is aa_Xn { export aa_Xn; }
+Rn_GPR64: xzr is aa_Xn=31 & xzr { tmp:8 = 0; export tmp; }
+
+Rt_GPR64: aa_Xt is aa_Xt { export aa_Xt; }
+Rt_GPR64: xzr is aa_Xt=31 & xzr { tmp:8 = 0; export tmp; }
+
+Rn_GPR64xsp: aa_Xn is aa_Xn { export aa_Xn; }
+Rn_GPR64xsp: sp is aa_Xn=31 & sp { export sp; }
+
+Rm_GPR64xsp: aa_Xm is aa_Xm { export aa_Xm; }
+Rm_GPR64xsp: sp is aa_Xm=31 & sp { export sp; }
+
+Rt_GPR64xsp: aa_Xt is aa_Xt { export aa_Xt; }
+Rt_GPR64xsp: sp is aa_Xt=31 & sp { export sp; }
+
+Rs_GPR32: Rm_GPR32 is Rm_GPR32 { export Rm_GPR32; }
+Rs_GPR64: Rm_GPR64 is Rm_GPR64 { export Rm_GPR64; }
+
+Rm_fpz16: "#0.0" is Rm { tmp:2 = int2float(0:2); export tmp; }
+Rm_fpz32: "#0.0" is Rm { tmp:4 = int2float(0:4); export tmp; }
+Rm_fpz64: "#0.0" is Rm { tmp:8 = int2float(0:8); export tmp; }
+
+Rd_VPR128.16B: vRd_VPR128^".16B" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; }
+Rd_VPR128.8H: vRd_VPR128^".8H" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; }
+Rd_VPR128.4S: vRd_VPR128^".4S" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; }
+Rd_VPR128.2S: vRd_VPR128^".2S" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; }
+Rd_VPR128.2D: vRd_VPR128^".2D" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; }
+Rd_VPR128.1Q: vRd_VPR128^".1Q" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; }
+
+Rn_VPR128.16B: vRn_VPR128^".16B" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; }
+Rnn_VPR128.16B: vRnn_VPR128^".16B" is Rnn_VPR128 & vRnn_VPR128 { export Rnn_VPR128; }
+Rnnn_VPR128.16B: vRnnn_VPR128^".16B" is Rnnn_VPR128 & vRnnn_VPR128 { export Rnnn_VPR128; }
+Rnnnn_VPR128.16B: vRnnnn_VPR128^".16B" is Rnnnn_VPR128 & vRnnnn_VPR128 { export Rnnnn_VPR128; }
+
+Rn_VPR128.8B: vRn_VPR128^".8B" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; }
+Rn_VPR128.8H: vRn_VPR128^".8H" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; }
+Rn_VPR128.4S: vRn_VPR128^".4S" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; }
+Rn_VPR128.4H: vRn_VPR128^".4H" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; }
+Rn_VPR128.2D: vRn_VPR128^".2D" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; }
+
+Rm_VPR128.8B: vRm_VPR128^".8B" is Rm_VPR128 & vRm_VPR128 { export Rm_VPR128; }
+Rm_VPR128.16B: vRm_VPR128^".16B" is Rm_VPR128 & vRm_VPR128 { export Rm_VPR128; }
+Rm_VPR128.8H: vRm_VPR128^".8H" is Rm_VPR128 & vRm_VPR128 { export Rm_VPR128; }
+Rm_VPR128.4S: vRm_VPR128^".4S" is Rm_VPR128 & vRm_VPR128 { export Rm_VPR128; }
+Rm_VPR128.4H: vRm_VPR128^".4H" is Rm_VPR128 & vRm_VPR128 { export Rm_VPR128; }
+Rm_VPR128.2D: vRm_VPR128^".2D" is Rm_VPR128 & vRm_VPR128 { export Rm_VPR128; }
+
+Ra_VPR128.16B: vRa_VPR128^".16B" is Ra_VPR128 & vRa_VPR128 { export Ra_VPR128; }
+# Ra_VPR128.8H: vRa_VPR128^".8H" is Ra_VPR128 & vRa_VPR128 { export Ra_VPR128; }
+Ra_VPR128.4S: vRa_VPR128^".4S" is Ra_VPR128 & vRa_VPR128 { export Ra_VPR128; }
+# Ra_VPR128.2D: vRa_VPR128^".2D" is Ra_VPR128 & vRa_VPR128 { export Ra_VPR128; }
+# Ra_VPR128.1Q: vRa_VPR128^".1Q" is Ra_VPR128 & vRa_VPR128 { export Ra_VPR128; }
+
+Rd_VPR64.8B: vRd_VPR64^".8B" is Rd_VPR64 & vRd_VPR64 { export Rd_VPR64; }
+Rd_VPR64.4H: vRd_VPR64^".4H" is Rd_VPR64 & vRd_VPR64 { export Rd_VPR64; }
+Rd_VPR64.2S: vRd_VPR64^".2S" is Rd_VPR64 & vRd_VPR64 { export Rd_VPR64; }
+Rd_VPR64.1D: vRd_VPR64^".1D" is Rd_VPR64 & vRd_VPR64 { export Rd_VPR64; }
+
+Rn_VPR64.8B: vRn_VPR64^".8B" is Rn_VPR64 & vRn_VPR64 { export Rn_VPR64; }
+Rn_VPR64.4H: vRn_VPR64^".4H" is Rn_VPR64 & vRn_VPR64 { export Rn_VPR64; }
+Rn_VPR64.2S: vRn_VPR64^".2S" is Rn_VPR64 & vRn_VPR64 { export Rn_VPR64; }
+Rn_VPR64.1D: vRn_VPR64^".1D" is Rn_VPR64 & vRn_VPR64 { export Rn_VPR64; }
+
+Rm_VPR64.8B: vRm_VPR64^".8B" is Rm_VPR64 & vRm_VPR64 { export Rm_VPR64; }
+Rm_VPR64.4H: vRm_VPR64^".4H" is Rm_VPR64 & vRm_VPR64 { export Rm_VPR64; }
+Rm_VPR64.2S: vRm_VPR64^".2S" is Rm_VPR64 & vRm_VPR64 { export Rm_VPR64; }
+Rm_VPR64.1D: vRm_VPR64^".1D" is Rm_VPR64 & vRm_VPR64 { export Rm_VPR64; }
+
+Rd_VPR128.B: vRd_VPR128^".B" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; }
+Rd_VPR128.H: vRd_VPR128^".H" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; }
+Rd_VPR128.S: vRd_VPR128^".S" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; }
+Rd_VPR128.D: vRd_VPR128^".D" is Rd_VPR128 & vRd_VPR128 { export Rd_VPR128; }
+
+Rn_VPR128.B: vRn_VPR128^".B" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; }
+Rn_VPR128.H: vRn_VPR128^".H" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; }
+Rn_VPR128.S: vRn_VPR128^".S" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; }
+Rn_VPR128.D: vRn_VPR128^".D" is Rn_VPR128 & vRn_VPR128 { export Rn_VPR128; }
+
+Re_VPR128.B: vRe_VPR128^".B" is Re_VPR128 & vRe_VPR128 { export Re_VPR128; }
+Re_VPR128.H: vRe_VPR128^".H" is Re_VPR128 & vRe_VPR128 { export Re_VPR128; }
+Re_VPR128.S: vRe_VPR128^".S" is Re_VPR128 & vRe_VPR128 { export Re_VPR128; }
+Re_VPR128.D: vRe_VPR128^".D" is Re_VPR128 & vRe_VPR128 { export Re_VPR128; }
+
+Re_VPR128Lo.H: vRe_VPR128Lo^".H" is Re_VPR128Lo & vRe_VPR128Lo { export Re_VPR128Lo; }
+
+br_cc_op: "eq" is br_cond_op=0 { export ZR; }
+br_cc_op: "ne" is br_cond_op=1 { tmp:1 = !ZR; export tmp; }
+br_cc_op: "cs" is br_cond_op=2 { export CY; }
+br_cc_op: "cc" is br_cond_op=3 { tmp:1 = !CY; export tmp; }
+br_cc_op: "mi" is br_cond_op=4 { export NG; }
+br_cc_op: "pl" is br_cond_op=5 { tmp:1 = !NG; export tmp; }
+br_cc_op: "vs" is br_cond_op=6 { export OV; }
+br_cc_op: "vc" is br_cond_op=7 { tmp:1 = !OV; export tmp; }
+br_cc_op: "hi" is br_cond_op=8 { tmp:1 = CY && (!ZR); export tmp; }
+br_cc_op: "ls" is br_cond_op=9 { tmp:1 = (!CY) || ZR; export tmp; }
+br_cc_op: "ge" is br_cond_op=10 { tmp:1 = (NG==OV); export tmp; }
+br_cc_op: "lt" is br_cond_op=11 { tmp:1 = (NG!=OV); export tmp; }
+br_cc_op: "gt" is br_cond_op=12 { tmp:1 = (!ZR) && (NG==OV); export tmp; }
+br_cc_op: "le" is br_cond_op=13 { tmp:1 = ZR || (NG!=OV); export tmp; }
+br_cc_op: "al" is br_cond_op=14 { export 1:1; }
+br_cc_op: "nv" is br_cond_op=15 { export 1:1; }
+
+BranchCondOp: br_cc_op is br_cc_op { export br_cc_op; }
+
+cc_op: "eq" is cond_op=0 { export ZR; }
+cc_op: "ne" is cond_op=1 { tmp:1 = !ZR; export tmp; }
+cc_op: "cs" is cond_op=2 { export CY; }
+cc_op: "cc" is cond_op=3 { tmp:1 = !CY; export tmp; }
+cc_op: "mi" is cond_op=4 { export NG; }
+cc_op: "pl" is cond_op=5 { tmp:1 = !NG; export tmp; }
+cc_op: "vs" is cond_op=6 { export OV; }
+cc_op: "vc" is cond_op=7 { tmp:1 = !OV; export tmp; }
+cc_op: "hi" is cond_op=8 { tmp:1 = CY && (!ZR); export tmp; }
+cc_op: "ls" is cond_op=9 { tmp:1 = (!CY) || ZR; export tmp; }
+cc_op: "ge" is cond_op=10 { tmp:1 = (NG==OV); export tmp; }
+cc_op: "lt" is cond_op=11 { tmp:1 = (NG!=OV); export tmp; }
+cc_op: "gt" is cond_op=12 { tmp:1 = (!ZR) && (NG==OV); export tmp; }
+cc_op: "le" is cond_op=13 { tmp:1 = ZR || (NG!=OV); export tmp; }
+cc_op: "al" is cond_op=14 { export 1:1; }
+cc_op: "nv" is cond_op=15 { export 1:1; }
+
+CondOp: cc_op is cc_op { export cc_op; }
+
+inv_cc_op: "eq" is cond_op=1 { export ZR; }
+inv_cc_op: "ne" is cond_op=0 { tmp:1 = !ZR; export tmp; }
+inv_cc_op: "cs" is cond_op=3 { export CY; }
+inv_cc_op: "cc" is cond_op=2 { tmp:1 = !CY; export tmp; }
+inv_cc_op: "mi" is cond_op=5 { export NG; }
+inv_cc_op: "pl" is cond_op=4 { tmp:1 = !NG; export tmp; }
+inv_cc_op: "vs" is cond_op=7 { export OV; }
+inv_cc_op: "vc" is cond_op=6 { tmp:1 = !OV; export tmp; }
+inv_cc_op: "hi" is cond_op=9 { tmp:1 = CY && (!ZR); export tmp; }
+inv_cc_op: "ls" is cond_op=8 { tmp:1 = (!CY) || ZR; export tmp; }
+inv_cc_op: "ge" is cond_op=11 { tmp:1 = (NG==OV); export tmp; }
+inv_cc_op: "lt" is cond_op=10 { tmp:1 = (NG!=OV); export tmp; }
+inv_cc_op: "gt" is cond_op=13 { tmp:1 = (!ZR) && (NG==OV); export tmp; }
+inv_cc_op: "le" is cond_op=12 { tmp:1 = ZR || (NG!=OV); export tmp; }
+inv_cc_op: "al" is cond_op=15 { export 1:1; }
+inv_cc_op: "nv" is cond_op=14 { export 1:1; }
+
+InvCondOp: inv_cc_op is inv_cc_op { export inv_cc_op; }
+
+SBIT_CZNO: is b_29=0 { } # Do nothing to the flag bits
+SBIT_CZNO: "s" is b_29=1 { CY = tmpCY; ZR = tmpZR; NG = tmpNG; OV = tmpOV; }
+
+Imm_uimm_exact8: "#"^value is aa_extreg_shift [ value = 8 << aa_extreg_shift; ] { export *[const]:4 value; }
+Imm_uimm_exact16: "#"^value is aa_extreg_shift [ value = 8 << aa_extreg_shift; ] { export *[const]:4 value; }
+Imm_uimm_exact32: "#"^value is aa_extreg_shift [ value = 8 << aa_extreg_shift; ] { export *[const]:4 value; }
+
+Imm_shr_imm8: "#"^val is b_1922 & b_1618 [ val = (8*2) - (b_1922 << 3 | b_1618); ] { export *[const]:4 val; }
+Imm_shr_imm16: "#"^val is b_1922 & b_1618 [ val = (16*2) - (b_1922 << 3 | b_1618); ] { export *[const]:4 val; }
+Imm_shr_imm32: "#"^val is b_1922 & b_1618 [ val = (32*2) - (b_1922 << 3 | b_1618); ] { export *[const]:4 val; }
+Imm_shr_imm64: "#"^val is b_1922 & b_1618 [ val = (64*2) - (b_1922 << 3 | b_1618); ] { export *[const]:4 val; }
+
+NZCVImm_uimm4: "#"^b_0003 is b_0003 { export *[const]:1 b_0003; }
+UImm5: "#"^b_1620 is b_1620 { export *[const]:4 b_1620; }
+UImm6: "#"^b_1520 is b_1520 { export *[const]:4 b_1520; }
+
+CRm_uimm4: "#"^b_0811 is b_0811 { export *[const]:1 b_0811; }
+
+CRm_uimm4_def15: "#"^b_0811 is b_0811 { export *[const]:1 b_0811; }
+CRm_uimm4_def15: is b_0811=0xf { export 15:1; }
+
+LSB_bitfield32_imm: "#"^imm6 is b_1515=0 & imm6 { export *[const]:8 imm6; }
+LSB_bitfield64_imm: "#"^imm6 is imm6 { export *[const]:8 imm6; }
+
+LSB_bitfield32_imm_shift: "#"^shift is b_1515=0 & imm6 [ shift = 31 - imm6; ] { export *[const]:4 shift; }
+LSB_bitfield64_imm_shift: "#"^shift is imm6 [ shift = 63 - imm6; ] { export *[const]:8 shift; }
+
+AddrLoc14: reloc is simm14 [ reloc = inst_start + (4*simm14); ] { export *[const]:8 reloc; }
+
+AddrLoc19: reloc is simm19 [ reloc = inst_start + (4*simm19); ] { export *[const]:8 reloc; }
+
+AddrLoc26: reloc is simm26 [ reloc = inst_start + (4*simm26); ] { export *[const]:8 reloc; }
+
+Addr14: AddrLoc14 is AddrLoc14 { export *:8 AddrLoc14; }
+
+Addr19: AddrLoc19 is AddrLoc19 { export *:8 AddrLoc19; }
+
+Addr26: AddrLoc26 is AddrLoc26 { export *:8 AddrLoc26; }
+
+AdrReloff: reloff is b_31=1 & immlo & immhi [ reloff = ((inst_start) & ~0xfff) + ( ((immhi << 2) | immlo) << 12 ); ] { export *[const]:8 reloff; }
+AdrReloff: reloff is b_31=0 & immlo & immhi [ reloff = (inst_start) + ( ((immhi << 2) | immlo) ); ] { export *[const]:8 reloff; }
+
+ImmShift32: "#"^imm12 is aa_extreg_shift=0 & imm12 { export *[const]:4 imm12; }
+ImmShift32: "#"^imm12, "LSL #12" is aa_extreg_shift=1 & imm12 { tmp:4 = imm12 << 12; export tmp; }
+
+ImmShift64: "#"^imm12 is aa_extreg_shift=0 & imm12 { export *[const]:8 imm12; }
+ImmShift64: "#"^imm12, "LSL #12" is aa_extreg_shift=1 & imm12 { tmp:8 = imm12 << 12; export tmp; }
+
+# TODO some instructions can't do ROR operation on immediate!
+
+RegShift32: Rm_GPR32, "LSL #"^imm6 is Rm_GPR32 & aa_extreg_shift = 0 & imm6 & b_1515=0 { tmp:4 = Rm_GPR32 << imm6; export tmp; }
+RegShift32: Rm_GPR32 is Rm_GPR32 & aa_extreg_shift = 0 & imm6=0 { export Rm_GPR32; }
+RegShift32: Rm_GPR32, "LSR #"^imm6 is Rm_GPR32 & aa_extreg_shift = 1 & imm6 & b_1515=0 { tmp:4 = Rm_GPR32 >> imm6; export tmp; }
+RegShift32: Rm_GPR32, "ASR #"^imm6 is Rm_GPR32 & aa_extreg_shift = 2 & imm6 & b_1515=0 { tmp:4 = Rm_GPR32 s>> imm6; export tmp; }
+
+RegShift32Log: RegShift32 is aa_extreg_shift & RegShift32 { export RegShift32; }
+RegShift32Log: Rm_GPR32, "ROR #"^imm6 is aa_extreg_shift=3 & Rm_GPR32 & imm6 & b_1515=0 { tmp:4 = (Rm_GPR32 >> imm6) | (Rm_GPR32 << (32 - imm6)); export tmp; }
+
+RegShift64: Rm_GPR64, "LSL #"^imm6 is Rm_GPR64 & aa_extreg_shift = 0 & imm6 { tmp:8 = Rm_GPR64 << imm6; export tmp; }
+RegShift64: Rm_GPR64 is Rm_GPR64 & aa_extreg_shift = 0 & imm6=0 { export Rm_GPR64; }
+RegShift64: Rm_GPR64, "LSR #"^imm6 is Rm_GPR64 & aa_extreg_shift = 1 & imm6 { tmp:8 = Rm_GPR64 >> imm6; export tmp; }
+RegShift64: Rm_GPR64, "ASR #"^imm6 is Rm_GPR64 & aa_extreg_shift = 2 & imm6 { tmp:8 = Rm_GPR64 s>> imm6; export tmp; }
+
+RegShift64Log: RegShift64 is aa_extreg_shift & RegShift64 & aa_Xn & aa_Xm & imm6 { export RegShift64; }
+RegShift64Log: Rm_GPR64, "ROR #"^imm6 is aa_extreg_shift=3 & Rm_GPR64 & aa_Xn & aa_Xm & imm6 { tmp:8 = (Rm_GPR64 >> imm6) | (Rm_GPR64 << (64 - imm6)); export tmp; }
+
+RegShiftVal32: " #"^b_1012 is aa_extreg_imm3=1 & b_1012 { export 1:4; }
+RegShiftVal32: " #"^b_1012 is aa_extreg_imm3=2 & b_1012 { export 2:4; }
+RegShiftVal32: " #"^b_1012 is aa_extreg_imm3=3 & b_1012 { export 3:4; }
+RegShiftVal32: " #"^b_1012 is aa_extreg_imm3=4 & b_1012 { export 4:4; }
+RegShiftVal32: "" is aa_extreg_imm3=0 { export 0:4; }
+
+LSL_Sp_Special32: Rm_GPR32, "LSL " is Rm_GPR32 & aa_extreg_imm3 { export Rm_GPR32; }
+LSL_Sp_Special32: Rm_GPR32 is Rm_GPR32 & aa_extreg_imm3=0 { export Rm_GPR32; }
+
+ExtendReg32: Rm_GPR32, "UXTB " is Rm_GPR32 & b_2121=1 & aa_extreg_option=0 { tmp0:4 = Rm_GPR32; tmp:4 = zext(tmp0:1); export tmp; }
+ExtendReg32: Rm_GPR32, "UXTH " is Rm_GPR32 & b_2121=1 & aa_extreg_option=1 { tmp0:4 = Rm_GPR32; tmp:4 = zext(tmp0:2); export tmp; }
+ExtendReg32: LSL_Sp_Special32 is Rm_GPR32 & b_2121=1 & aa_extreg_option=2 & b_29=1 & (Rn=0x1f) & LSL_Sp_Special32 { export Rm_GPR32; }
+ExtendReg32: LSL_Sp_Special32 is Rm_GPR32 & b_2121=1 & aa_extreg_option=2 & b_29=0 & (Rd=0x1f | Rn=0x1f) & LSL_Sp_Special32 { export Rm_GPR32; }
+ExtendReg32: Rm_GPR32, "UXTW " is Rm_GPR32 & b_2121=1 & aa_extreg_option=2 { tmp:4 = Rm_GPR32; export tmp; }
+ExtendReg32: Rm_GPR32, "UXTX " is Rm_GPR32 & b_2121=1 & aa_extreg_option=3 { tmp:4 = Rm_GPR32; export tmp; }
+ExtendReg32: Rm_GPR32, "SXTB " is Rm_GPR32 & b_2121=1 & aa_extreg_option=4 { tmp0:4 = Rm_GPR32; tmp:4 = sext(tmp0:1); export tmp; }
+ExtendReg32: Rm_GPR32, "SXTH " is Rm_GPR32 & b_2121=1 & aa_extreg_option=5 { tmp0:4 = Rm_GPR32; tmp:4 = sext(tmp0:2); export tmp; }
+
+ExtendReg32: Rm_GPR32, "SXTW " is Rm_GPR32 & b_2121=1 & aa_extreg_option=6 { tmp:4 = Rm_GPR32; export tmp; }
+ExtendReg32: Rm_GPR32, "SXTX " is Rm_GPR32 & b_2121=1 & aa_extreg_option=7 { tmp:4 = Rm_GPR32; export tmp; }
+
+ExtendRegShift32: ExtendReg32^RegShiftVal32 is aa_extreg_shift = 0 & aa_extreg_option & aa_extreg_imm3 & ExtendReg32 & RegShiftVal32 { tmp:4 = ExtendReg32; tmp = tmp << RegShiftVal32; export tmp; }
+ExtendRegShift32: ExtendReg32 is Rm_GPR32 & aa_extreg_shift = 0 & aa_extreg_option=2 & aa_extreg_imm3=0 & ExtendReg32 & RegShiftVal32 { export Rm_GPR32; }
+ExtendRegShift32: ExtendReg32 is Rm_GPR32 & aa_extreg_shift = 0 & aa_extreg_option=3 & aa_extreg_imm3=0 & ExtendReg32 & RegShiftVal32 { export Rm_GPR32; }
+ExtendRegShift32: ExtendReg32 is Rm_GPR32 & aa_extreg_shift = 0 & aa_extreg_option=6 & aa_extreg_imm3=0 & ExtendReg32 & RegShiftVal32 { export Rm_GPR32; }
+ExtendRegShift32: ExtendReg32 is Rm_GPR32 & aa_extreg_shift = 0 & aa_extreg_option=7 & aa_extreg_imm3=0 & ExtendReg32 & RegShiftVal32 { export Rm_GPR32; }
+
+Imm12_addsubimm_operand_i32_negimm_lsl0: ImmShift32 is ImmShift32 { export ImmShift32; }
+Imm12_addsubimm_operand_i32_negimm_lsl12: ImmShift32 is ImmShift32 { export ImmShift32; }
+Imm12_addsubimm_operand_i32_posimm_lsl0: ImmShift32 is ImmShift32 { export ImmShift32; }
+Imm12_addsubimm_operand_i32_posimm_lsl12: ImmShift32 is ImmShift32 { export ImmShift32; }
+Imm12_addsubimm_operand_i64_negimm_lsl0: ImmShift64 is ImmShift64 { export ImmShift64; }
+Imm12_addsubimm_operand_i64_negimm_lsl12: ImmShift64 is ImmShift64 { export ImmShift64; }
+Imm12_addsubimm_operand_i64_posimm_lsl0: ImmShift64 is ImmShift64 { export ImmShift64; }
+Imm12_addsubimm_operand_i64_posimm_lsl12: ImmShift64 is ImmShift64 { export ImmShift64; }
+
+RegShiftVal64: " #"^b_1012 is aa_extreg_imm3=1 & b_1012 { export 1:8; }
+RegShiftVal64: " #"^b_1012 is aa_extreg_imm3=2 & b_1012 { export 2:8; }
+RegShiftVal64: " #"^b_1012 is aa_extreg_imm3=3 & b_1012 { export 3:8; }
+RegShiftVal64: " #"^b_1012 is aa_extreg_imm3=4 & b_1012 { export 4:8; }
+RegShiftVal64: "" is aa_extreg_imm3=0 { export 0:8; }
+
+LSL_Sp_Special64: Rm_GPR64, "LSL " is Rm_GPR64 & aa_extreg_imm3 { export Rm_GPR64; }
+LSL_Sp_Special64: Rm_GPR64 is Rm_GPR64 & aa_extreg_imm3=0 { export Rm_GPR64; }
+
+ExtendReg64: Rm_GPR32, "UXTB " is Rm_GPR32 & b_2121=1 & aa_extreg_option=0 { tmp0:4 = Rm_GPR32; tmp:8 = zext(tmp0:1); export tmp; }
+ExtendReg64: Rm_GPR32, "UXTH " is Rm_GPR32 & b_2121=1 & aa_extreg_option=1 { tmp0:4 = Rm_GPR32; tmp:8 = zext(tmp0:2); export tmp; }
+ExtendReg64: Rm_GPR32, "UXTW " is Rm_GPR32 & b_2121=1 & aa_extreg_option=2 { tmp:8 = zext(Rm_GPR32); export tmp; }
+ExtendReg64: LSL_Sp_Special64 is Rm_GPR64 & b_2121=1 & aa_extreg_option=3 & b_29=1 & b_25=1 & (Rn=0x1f) & LSL_Sp_Special64 { tmp:8 = Rm_GPR64; export tmp; }
+ExtendReg64: LSL_Sp_Special64 is Rm_GPR64 & b_2121=1 & aa_extreg_option=3 & b_29=0 & b_25=1 & (Rd=0x1f | Rn=0x1f) & LSL_Sp_Special64 { tmp:8 = Rm_GPR64; export tmp; }
+ExtendReg64: Rm_GPR64, "LSL " is Rm_GPR64 & b_2121=1 & aa_extreg_option=3 & b_29 & b_25=0 { tmp:8 = Rm_GPR64; export tmp; }
+ExtendReg64: Rm_GPR64, "UXTX " is Rm_GPR64 & b_2121=1 & aa_extreg_option=3 { tmp:8 = Rm_GPR64; export tmp; }
+ExtendReg64: Rm_GPR32, "SXTB " is Rm_GPR32 & b_2121=1 & aa_extreg_option=4 { tmp0:4 = Rm_GPR32; tmp:8 = sext(tmp0:1); export tmp; }
+ExtendReg64: Rm_GPR32, "SXTH " is Rm_GPR32 & b_2121=1 & aa_extreg_option=5 { tmp0:4 = Rm_GPR32; tmp:8 = sext(tmp0:2); export tmp; }
+ExtendReg64: Rm_GPR32, "SXTW " is Rm_GPR32 & b_2121=1 & aa_extreg_option=6 { tmp:8 = sext(Rm_GPR32); export tmp; }
+ExtendReg64: Rm_GPR64, "SXTX " is Rm_GPR64 & b_2121=1 & aa_extreg_option=7 { tmp:8 = Rm_GPR64; export tmp; }
+
+ExtendRegShift64: ExtendReg64^RegShiftVal64
+is aa_extreg_shift = 0 & aa_extreg_option & aa_extreg_imm3 & ExtendReg64 & RegShiftVal64
+{
+ build ExtendReg64;
+ build RegShiftVal64;
+ tmp:8 = ExtendReg64;
+ tmp = tmp << RegShiftVal64;
+ export tmp;
+}
+
+ExtendRegShift64: ExtendReg64 is Rm_GPR64 & aa_extreg_shift = 0 & aa_extreg_option=3 & aa_extreg_imm3=0 & ExtendReg64 & RegShiftVal64 { export Rm_GPR64; }
+ExtendRegShift64: ExtendReg64 is Rm_GPR64 & aa_extreg_shift = 0 & aa_extreg_option=7 & aa_extreg_imm3=0 & ExtendReg64 & RegShiftVal64 { export Rm_GPR64; }
+
+UnscPriv: "u" is b_1011=0 { }
+UnscPriv: "t" is b_1011=2 { }
+
+# Simple register load or store
+addrReg: "["^Rn_GPR64xsp^"]" is Rn_GPR64xsp { export Rn_GPR64xsp; }
+
+# Scaled Offset
+addrUIMM: "["^Rn_GPR64xsp, "#"^pimm^"]" is size.ldstr=0 & b_2729=7 & v & b_2425=1 & b_2323 & Rn_GPR64xsp & imm12 [ pimm = imm12 << 0; ] { tmp:8 = Rn_GPR64xsp + pimm; export tmp; }
+addrUIMM: "["^Rn_GPR64xsp, "#"^pimm^"]" is size.ldstr=1 & b_2729=7 & v & b_2425=1 & b_2323 & Rn_GPR64xsp & imm12 [ pimm = imm12 << 1; ] { tmp:8 = Rn_GPR64xsp + pimm; export tmp; }
+addrUIMM: "["^Rn_GPR64xsp, "#"^pimm^"]" is size.ldstr=2 & b_2729=7 & v & b_2425=1 & b_2323 & Rn_GPR64xsp & imm12 [ pimm = imm12 << 2; ] { tmp:8 = Rn_GPR64xsp + pimm; export tmp; }
+addrUIMM: "["^Rn_GPR64xsp, "#"^pimm^"]" is size.ldstr=3 & b_2729=7 & v & b_2425=1 & b_2323 & Rn_GPR64xsp & imm12 [ pimm = imm12 << 3; ] { tmp:8 = Rn_GPR64xsp + pimm; export tmp; }
+
+addrUIMM: "["^Rn_GPR64xsp, "#"^pimm^"]" is size.ldstr=0 & b_2729=7 & v=1 & b_2425=1 & b_2323=1 & Rn_GPR64xsp & imm12 [ pimm = imm12 << 4; ] { tmp:8 = Rn_GPR64xsp + pimm; export tmp; }
+addrUIMM: "["^Rn_GPR64xsp^"]" is size.ldstr=0 & b_2729=7 & v & b_2425=1 & b_2323 & Rn_GPR64xsp & imm12=0 { tmp:8 = Rn_GPR64xsp; export tmp; }
+addrUIMM: "["^Rn_GPR64xsp^"]" is size.ldstr=1 & b_2729=7 & v & b_2425=1 & b_2323 & Rn_GPR64xsp & imm12=0 { tmp:8 = Rn_GPR64xsp; export tmp; }
+addrUIMM: "["^Rn_GPR64xsp^"]" is size.ldstr=2 & b_2729=7 & v & b_2425=1 & b_2323 & Rn_GPR64xsp & imm12=0 { tmp:8 = Rn_GPR64xsp; export tmp; }
+addrUIMM: "["^Rn_GPR64xsp^"]" is size.ldstr=3 & b_2729=7 & v & b_2425=1 & b_2323 & Rn_GPR64xsp & imm12=0 { tmp:8 = Rn_GPR64xsp; export tmp; }
+addrUIMM: "["^Rn_GPR64xsp^"]" is size.ldstr=0 & b_2729=7 & v=1 & b_2425=1 & b_2323=1 & Rn_GPR64xsp & imm12=0 { tmp:8 = Rn_GPR64xsp; export tmp; }
+
+# Address Reg + signed offset -256 to 255
+addr_SIMM9: "["^Rn_GPR64xsp, "#"^simm9^"]" is Rn_GPR64xsp & simm9 { tmp:8 = Rn_GPR64xsp + simm9; export tmp; }
+addr_SIMM9: "["^Rn_GPR64xsp^"]" is Rn_GPR64xsp & simm9=0 { tmp:8 = Rn_GPR64xsp; export tmp; }
+
+addrRegShift64: "#"^val is size.ldstr=0 & v=0 & opt & b_1212=1 [ val = 0 & 0xff; ] { export *[const]:8 val; }
+addrRegShift64: "" is size.ldstr=0 & v=0 & opt & b_1212=0 { export 0:8; }
+
+addrRegShift64: "#"^val is size.ldstr=0 & v=1 & opt=0 & b_1212=1 [ val = 0 & 0xff; ] { export *[const]:8 val; }
+addrRegShift64: "" is size.ldstr=0 & v=1 & opt=0 & b_1212=0 { export 0:8; }
+addrRegShift64: "#"^val is size.ldstr=0 & v=1 & opt=1 & b_1212=1 [ val = 0 & 0xff; ] { export *[const]:8 val; }
+addrRegShift64: "" is size.ldstr=0 & v=1 & opt=1 & b_1212=0 { export 0:8; }
+addrRegShift64: "#"^val is size.ldstr=0 & v=1 & opt=2 & b_1212 [ val = b_1212 * 4; ] { export *[const]:8 val; }
+addrRegShift64: "#"^val is size.ldstr=0 & v=1 & opt=3 & b_1212 [ val = b_1212 * 4; ] { export *[const]:8 val; }
+
+addrRegShift64: "#"^val is size.ldstr=1 & v=0 & opt & b_1212 [ val = b_1212 * 1; ] { export *[const]:8 val; }
+addrRegShift64: "#"^val is size.ldstr=1 & v=1 & opt & b_1212 [ val = b_1212 * 1; ] { export *[const]:8 val; }
+
+addrRegShift64: "#"^val is size.ldstr=2 & v=0 & opt & b_1212 [ val = b_1212 * 2; ] { export *[const]:8 val; }
+addrRegShift64: "#"^val is size.ldstr=2 & v=1 & opt & b_1212 [ val = b_1212 * 2; ] { export *[const]:8 val; }
+
+addrRegShift64: "#"^val is size.ldstr=3 & v=0 & opt & b_1212 [ val = b_1212 * 3; ] { export *[const]:8 val; }
+addrRegShift64: "#"^val is size.ldstr=3 & v=1 & opt & b_1212 [ val = b_1212 * 3; ] { export *[const]:8 val; }
+
+addrExtendRegShift64: ExtendReg64^addrRegShift64 is aa_extreg_option=2 & aa_extreg_imm3 & addrRegShift64 & ExtendReg64 { tmp:8 = ExtendReg64; tmp = tmp << addrRegShift64; export tmp; }
+addrExtendRegShift64: ExtendReg64^addrRegShift64 is aa_extreg_option=3 & aa_extreg_imm3 & addrRegShift64 & ExtendReg64 { tmp:8 = ExtendReg64; tmp = tmp << addrRegShift64; export tmp; }
+addrExtendRegShift64: ExtendReg64^addrRegShift64 is aa_extreg_option=6 & aa_extreg_imm3 & addrRegShift64 & ExtendReg64 { tmp:8 = ExtendReg64; tmp = tmp << addrRegShift64; export tmp; }
+addrExtendRegShift64: ExtendReg64^addrRegShift64 is aa_extreg_option=7 & aa_extreg_imm3 & addrRegShift64 & ExtendReg64 { tmp:8 = ExtendReg64; tmp = tmp << addrRegShift64; export tmp; }
+addrExtendRegShift64: Rm_GPR64 is Rm_GPR64 & aa_extreg_option=3 & aa_extreg_imm3=0 & ExtendReg64 { export Rm_GPR64; }
+addrExtendRegShift64: Rm_GPR64 is Rm_GPR64 & aa_extreg_option=7 & aa_extreg_imm3=0 & ExtendReg64 { export Rm_GPR64; }
+
+# unsigned offset
+addrIndexed: addrUIMM is size.ldstr & b_2729=7 & b_2425=1 & addrUIMM { export addrUIMM; }
+
+# unsinged offset unscaled immediate
+addrIndexed: addr_SIMM9 is size.ldstr & b_2729=7 & b_2425=0 & b_2121=0 & opc.indexmode=0 & addr_SIMM9 { export addr_SIMM9; }
+
+# register unpriviledged
+addrIndexed: addr_SIMM9 is size.ldstr & b_2729=7 & b_2425=0 & b_2121=0 & opc.indexmode=2 & addr_SIMM9 { export addr_SIMM9; }
+
+# post indexed wback
+addrIndexed: "["^Rn_GPR64xsp^"]", "#"^simm9
+is size.ldstr & b_2729=7 & b_2425=0 & b_2121=0 & Rn_GPR64xsp & simm9 & opc.indexmode=1
+{
+ tmp:8 = Rn_GPR64xsp;
+ Rn_GPR64xsp = Rn_GPR64xsp + simm9;
+ export tmp;
+}
+
+# Register, Register offset extended
+addrIndexed: "["^Rn_GPR64xsp, addrExtendRegShift64^"]"
+is size.ldstr & b_2729=7 & b_2425=0 & b_2121=1 & Rn_GPR64xsp & opc.indexmode=2 & addrExtendRegShift64
+{
+ tmp:8 = Rn_GPR64xsp + addrExtendRegShift64;
+ export tmp;
+}
+
+# pre indexed wback
+addrIndexed: "["^Rn_GPR64xsp, "#"^simm9^"]!"
+is size.ldstr & b_2729=7 & b_2425=0 & b_2121=0 & Rn_GPR64xsp & simm9 & opc.indexmode=3
+{
+ Rn_GPR64xsp = Rn_GPR64xsp + simm9;
+ export Rn_GPR64xsp;
+}
+
+# For LDRAA/LDRAB
+
+# no offset (with S)
+addrIndexed: "["^Rn_GPR64xsp^"]"
+is size.ldstr & b_2729=7 & b_2425=0 & b_22=0 & b_2121=1 & Rn_GPR64xsp & simm9=0 & opc.indexmode=1
+{
+ export Rn_GPR64xsp;
+}
+
+# offset (with S)
+addrIndexed: "["^Rn_GPR64xsp, "#"^sim^"]"
+is size.ldstr & b_2729=7 & b_2425=0 & b_22 & b_2121=1 & Rn_GPR64xsp & simm9 & opc.indexmode=1
+[ sim = (b_22 * (-1<<9) | (simm9 & 0x1ff)) << 3; ]
+{
+ tmp:8 = Rn_GPR64xsp + sim;
+ export tmp;
+}
+
+# no offset writeback (with S)
+addrIndexed: "["^Rn_GPR64xsp^"]!"
+is size.ldstr & b_2729=7 & b_2425=0 & b_22=0 & b_2121=1 & Rn_GPR64xsp & simm9=0 & opc.indexmode=3
+{
+ export Rn_GPR64xsp;
+}
+
+# pre indexed wback (with S)
+addrIndexed: "["^Rn_GPR64xsp, "#"^sim^"]!"
+is size.ldstr & b_2729=7 & b_2425=0 & b_22 & b_2121=1 & Rn_GPR64xsp & simm9 & opc.indexmode=3
+[ sim = (b_22 * (-1<<9) | (simm9 & 0x1ff)) << 3; ]
+{
+ Rn_GPR64xsp = Rn_GPR64xsp + sim;
+ export Rn_GPR64xsp;
+}
+
+addrPairScale: pimm is b_3031=0 & v=0 & simm7 [ pimm = simm7 << 2; ] { export *[const]:8 pimm; }
+addrPairScale: pimm is b_3031=0 & v=1 & simm7 [ pimm = simm7 << 2; ] { export *[const]:8 pimm; }
+addrPairScale: pimm is b_3031=2 & v=0 & simm7 [ pimm = simm7 << 3; ] { export *[const]:8 pimm; }
+addrPairScale: pimm is b_3031=1 & v=0 & simm7 [ pimm = simm7 << 2; ] { export *[const]:8 pimm; }
+addrPairScale: pimm is b_3031=1 & v=1 & simm7 [ pimm = simm7 << 3; ] { export *[const]:8 pimm; }
+addrPairScale: pimm is b_3031=2 & v=1 & simm7 [ pimm = simm7 << 4; ] { export *[const]:8 pimm; }
+
+# Scaled Offset
+addrPairUIMM: "["^Rn_GPR64xsp, "#"^addrPairScale^"]"
+is sf & Rn_GPR64xsp & addrPairScale & simm7
+{
+ tmp:8 = Rn_GPR64xsp + addrPairScale;
+ export tmp;
+}
+
+addrPairUIMM: "["^Rn_GPR64xsp^"]"
+is sf & Rn_GPR64xsp & addrPairScale & simm7=0
+{
+ tmp:8 = Rn_GPR64xsp;
+ export tmp;
+}
+
+# unsigned offset
+addrPairIndexed: addrPairUIMM
+is b_2729=0b101 & b_2325=0b010 & addrPairUIMM
+{ export addrPairUIMM; }
+
+# unsigned offset, non-temporal hint
+addrPairIndexed: addrPairUIMM
+is b_2729=0b101 & b_2325=0b000 & addrPairUIMM
+{ export addrPairUIMM; }
+
+# post indexed wback
+addrPairIndexed: "["^Rn_GPR64xsp^"]", "#"^addrPairScale
+is b_2729=0b101 & b_2325=0b001 & Rn_GPR64xsp & addrPairScale
+{
+ tmp:8 = Rn_GPR64xsp;
+ Rn_GPR64xsp = Rn_GPR64xsp + addrPairScale;
+ export tmp;
+}
+
+# pre indexed wback
+addrPairIndexed: "["^Rn_GPR64xsp, "#"^addrPairScale^"]!"
+is b_2729=0b101 & b_2325=0b011 & Rn_GPR64xsp & addrPairScale
+{
+ Rn_GPR64xsp = Rn_GPR64xsp + addrPairScale;
+ export Rn_GPR64xsp;
+}
+
+#### Undefined behavior on writeback ####
+#
+# Most instructions with writeback have unpredictable behavior when their address input register Rn
+# is the same register as another input, e.g. Rt. For example, LDR x1, [x1, 0x8]! has unpredictable
+# behavior in the ARM spec. Similarly, STR x5, [x5], 0x28 has unpredictable behavior in the spec
+# (but with slightly different possibilities for what forms that unpredictable behavior might take!).
+#
+# One of the few exceptions is STGP, which has no mention of unpredictable behavior. In such cases,
+# it's important to read all registers before addrGranuleIndexed or addrPairGranuleIndexed takes effect,
+# or pre-index writeback will modify the register values used if Rn is the same register as another R.
+#
+# This is an example of how to code a definition for an instruction with no unpredictable behavior:
+#{
+# # save the initial register values
+# data1:8 = Rt_GPR64;
+# data2:8 = Rt2_GPR64;
+#
+# build addrPairGranuleIndexed; # may modify Rt or Rt2, so use data1/data2 instead afterward
+#
+# ...etc...
+#}
+
+OPTIONAL_XM: is Rm=0b11111 { export 0:8; } # default to XZR if Xm is absent
+OPTIONAL_XM: ,Rm_GPR64 is Rm_GPR64 { export Rm_GPR64; }
+
+addr_granuleSIMM: "["^Rn_GPR64xsp, "#"^pimm^"]" is Rn_GPR64xsp & simm9 [ pimm = simm9 << $(LOG2_TAG_GRANULE); ] { tmp:8 = Rn_GPR64xsp + ( simm9 << $(LOG2_TAG_GRANULE) ); export tmp; }
+addr_granuleSIMM: "["^Rn_GPR64xsp^"]" is Rn_GPR64xsp & simm9=0 { tmp:8 = Rn_GPR64xsp; export tmp; }
+
+# signed offset
+addrGranuleIndexed: addr_granuleSIMM is opc.indexmode=2 & addr_granuleSIMM { export addr_granuleSIMM; }
+
+# post indexed wback
+addrGranuleIndexed: "["^Rn_GPR64xsp^"]", "#"^pimm
+is Rn_GPR64xsp & simm9 & opc.indexmode=1
+[ pimm = simm9 << $(LOG2_TAG_GRANULE); ]
+{
+ tmp:8 = Rn_GPR64xsp;
+ Rn_GPR64xsp = Rn_GPR64xsp + pimm;
+ export tmp;
+}
+
+# pre indexed wback
+addrGranuleIndexed: "["^Rn_GPR64xsp, "#"^pimm^"]!"
+is Rn_GPR64xsp & simm9 & opc.indexmode=3
+[ pimm = simm9 << $(LOG2_TAG_GRANULE); ]
+{
+ Rn_GPR64xsp = Rn_GPR64xsp + pimm;
+ tmp:8 = Rn_GPR64xsp;
+ export tmp;
+}
+
+addrPairGranuleScale: pimm is simm7 [ pimm = simm7 << $(LOG2_TAG_GRANULE); ] { export *[const]:8 pimm; }
+
+# Scaled Offset
+addrPairGranuleSIMM: "["^Rn_GPR64xsp, "#"^addrPairGranuleScale^"]"
+is sf & Rn_GPR64xsp & addrPairGranuleScale & simm7
+{
+ tmp:8 = Rn_GPR64xsp + addrPairGranuleScale;
+ export tmp;
+}
+
+addrPairGranuleSIMM: "["^Rn_GPR64xsp^"]"
+is sf & Rn_GPR64xsp & addrPairGranuleScale & simm7=0
+{
+ tmp:8 = Rn_GPR64xsp;
+ export tmp;
+}
+
+
+# signed offset
+addrPairGranuleIndexed: addrPairGranuleSIMM
+is b_2729=0b101 & b_2325=0b010 & addrPairGranuleSIMM
+{ export addrPairGranuleSIMM; }
+
+# post indexed wback
+addrPairGranuleIndexed: "["^Rn_GPR64xsp^"]", "#"^addrPairGranuleScale
+is b_2729=0b101 & b_2325=0b001 & Rn_GPR64xsp & addrPairGranuleScale
+{
+ tmp:8 = Rn_GPR64xsp;
+ Rn_GPR64xsp = Rn_GPR64xsp + addrPairGranuleScale;
+ export tmp;
+}
+
+# pre indexed wback
+addrPairGranuleIndexed: "["^Rn_GPR64xsp, "#"^addrPairGranuleScale^"]!"
+is b_2729=0b101 & b_2325=0b011 & Rn_GPR64xsp & addrPairGranuleScale
+{
+ Rn_GPR64xsp = Rn_GPR64xsp + addrPairGranuleScale;
+ export Rn_GPR64xsp;
+}
+
+# esize=32, len=5, levels=0x1f: 32 bits with b_1014+1 1s; rotate right b_1620; replicate 1 time
+DecodeWMask32: "#"^wmask is b_31=0 & b_22=0 & b_15=0 & b_1014 & b_1620
+[ wmask=(((~(-1<<(b_1014+1)))*0x100000001)>>b_1620)&0xffffffff; ]
+{ export * [const]:4 wmask; }
+
+# esize=32, len=5, levels=0x1f: 32 bits with |b_1014-b_1620|+1 1s; replicate 1 time
+DecodeTMask32: "#"^tmask is b_31=0 & b_22=0 & b_15=0 & b_1014 & b_1620
+[ tmask=(~(-1<<(((b_1014-b_1620)&0x1f)+1)))&0xffffffff; ]
+{ export * [const]:4 tmask; }
+
+# esize=16, len=4, levels=0xf: 16 bits with b_1013+1 1s; rotate right b_1619; replicate 2 times
+DecodeWMask32: "#"^wmask is b_31=0 & b_22=0 & b_1415=0x2 & b_1013 & b_1619
+[ wmask=((((~(-1<<(b_1013+1)))*0x10001)>>b_1619)&0xffff)*0x10001; ]
+{ export * [const]:4 wmask; }
+
+# esize=16, len=4, levels=0xf: 16 bits with |b_1013-b_1619|+1 1s; replicate 2 times
+DecodeTMask32: "#"^tmask is b_31=0 & b_22=0 & b_1415=0x2 & b_1013 & b_1619
+[ tmask=((~(-1<<(((b_1013-b_1619)&0xf)+1)))&0xffff)*0x10001; ]
+{ export * [const]:4 tmask; }
+
+# esize=8, len=3, levels=0x7: 8 bits with b_1012+1 1s; rotate right b_1618; replicate 4 times
+DecodeWMask32: "#"^wmask is b_31=0 & b_22=0 & b_1315=0x6 & b_1012 & b_1618
+[ wmask=((((~(-1<<(b_1012+1)))*0x101)>>b_1618)&0xff)*0x101*0x10001; ]
+{ export * [const]:4 wmask; }
+
+# esize=8, len=3, levels=0x7: 8 bits with |b_1012-b_1618|+1 1s; replicate 4 times
+DecodeTMask32: "#"^tmask is b_31=0 & b_22=0 & b_1315=0x6 & b_1012 & b_1618
+[ tmask=((~(-1<<(((b_1012-b_1618)&0x7)+1)))&0xff)*0x101*0x10001; ]
+{ export * [const]:4 tmask; }
+
+# esize=4, len=2, levels=0x3: 4 bits with b_1011+1 1s; rotate right b_1617; replicate 8 times
+DecodeWMask32: "#"^wmask is b_31=0 & b_22=0 & b_1215=0xe & b_1011 & b_1617
+[ wmask=((((~(-1<<(b_1011+1)))*0x11)>>b_1617)&0xf)*0x11*0x101*0x10001; ]
+{ export * [const]:4 wmask; }
+
+# esize=4, len=2, levels=0x3: 4 bits with |b_1011-b_1617|+1 1s; replicate 8 times
+DecodeTMask32: "#"^tmask is b_31=0 & b_22=0 & b_1215=0xe & b_1011 & b_1617
+[ tmask=((~(-1<<(((b_1011-b_1617)&0x7)+1)))&0xf)*0x11*0x101*0x10001; ]
+{ export * [const]:4 tmask; }
+
+# esize=2, len=1, levels=0x1: 2 bits with b_1010+1 1s; rotate right b_1616; replicate 16 times
+DecodeWMask32: "#"^wmask is b_31=0 & b_22=0 & b_1115=0x1e & b_1010 & b_1616
+[ wmask=((((~(-1<<(b_1010+1)))*0x5)>>b_1616)&0x3)*0x5*0x11*0x101*0x10001; ]
+{ export * [const]:4 wmask; }
+
+# esize=2, len=1, levels=0x1: 2 bits with |b_1010-b_1616|+1 1s; replicate 16 times
+DecodeTMask32: "#"^tmask is b_31=0 & b_22=0 & b_1115=0x1e & b_1010 & b_1616
+[ tmask=((~(-1<<(((b_1010-b_1616)&0x1)+1)))&0x3)*0x5*0x11*0x101*0x10001; ]
+{ export * [const]:4 tmask; }
+
+# esize=64, len=6, levels=0x3f: 64 bits with b_1015+1 1s; rotate right b_1621; repeat 1 time
+# can't rotate 64 bits by multiplying, and can't shift by 64 bits all at once
+DecodeWMask64: "#"^wmask is b_31=1 & b_22=1 & b_1015 & b_1621
+[ wmask=((~((-1<>b_1621)|((~((-1<>b_1620)&0xffffffff)*0x100000001; ]
+{ export * [const]:8 wmask; }
+
+# esize=32, len=5, levels=0x1f: 32 bits with |b_1014-b_1620|+1 1s; replicate 2 times
+DecodeTMask64: "#"^tmask is b_31=1 & b_22=0 & b_15=0 & b_1014 & b_1620
+[ tmask=((~(-1<<(((b_1014-b_1620)&0x1f)+1)))&0xffffffff)*0x100000001; ]
+{ export * [const]:8 tmask; }
+
+# returned 0xffcfffdefcfffcf
+# shouldbe 0xffcfffcfffcfffcf
+# esize=16, len=4, levels=0xf: 16 bits with b_1013+1 1s; rotate right b_1619; replicate 4 times
+DecodeWMask64: "#"^wmask is b_31=1 & b_22=0 & b_1415=0x2 & b_1013 & b_1619
+[ wmask=((((~(-1<<(b_1013+1)))*0x10001)>>b_1619)&0xffff)*0x10001*0x100000001; ]
+{ export * [const]:8 wmask; }
+
+# esize=16, len=4, levels=0xf: 16 bits with |b_1013-b_1619|+1 1s; replicate 4 times
+DecodeTMask64: "#"^tmask is b_31=1 & b_22=0 & b_1415=0x2 & b_1013 & b_1619
+[ tmask=((~(-1<<(((b_1013-b_1619)&0xf)+1)))&0xffff)*0x10001*0x100000001; ]
+{ export * [const]:8 tmask; }
+
+# esize=8, len=3, levels=0x7: 8 bits with b_1012+1 1s; rotate right b_1618; replicate 8 times
+DecodeWMask64: "#"^wmask is b_31=1 & b_22=0 & b_1315=0x6 & b_1012 & b_1618
+[ wmask=((((~(-1<<(b_1012+1)))*0x101)>>b_1618)&0xff)*0x101*0x10001*0x100000001; ]
+{ export * [const]:8 wmask; }
+
+# esize=8, len=3, levels=0x7: 8 bits with |b_1012-b_1618|+1 1s; replicate 8 times
+DecodeTMask64: "#"^tmask is b_31=1 & b_22=0 & b_1315=0x6 & b_1012 & b_1618
+[ tmask=((~(-1<<(((b_1012-b_1618)&0x7)+1)))&0xff)*0x101*0x10001*0x100000001; ]
+{ export * [const]:8 tmask; }
+
+# esize=4, len=2, levels=0x3: 4 bits with b_1011+1 1s; rotate right b_1617; replicate 16 times
+DecodeWMask64: "#"^wmask is b_31=1 & b_22=0 & b_1215=0xe & b_1011 & b_1617
+[ wmask=((((~(-1<<(b_1011+1)))*0x11)>>b_1617)&0xf)*0x11*0x101*0x10001*0x100000001; ]
+{ export * [const]:8 wmask; }
+
+# esize=4, len=2, levels=0x3: 4 bits with |b_1011-b_1617|+1 1s; replicate 16 times
+DecodeTMask64: "#"^tmask is b_31=1 & b_22=0 & b_1215=0xe & b_1011 & b_1617
+[ tmask=((~(-1<<(((b_1011-b_1617)&0x3)+1)))&0xf)*0x11*0x101*0x10001*0x100000001; ]
+{ export * [const]:8 tmask; }
+
+# esize=2, len=1, levels=0x1: 2 bits with b_1010+1 1s; rotate right b_1616; replicate 32 times
+DecodeWMask64: "#"^wmask is b_31=1 & b_22=0 & b_1115=0x1e & b_1010 & b_1616
+[ wmask=((((~((-1)<<(b_1010+1)))*0x5)>>b_1616)&0x3)*0x5*0x11*0x101*0x10001*0x100000001; ]
+{ export * [const]:8 wmask; }
+
+# esize=2, len=1, levels=0x1: 2 bits with |b_1010-b_1616|+1 1s; replicate 32 times
+DecodeTMask64: "#"^tmask is b_31=1 & b_22=0 & b_1115=0x1e & b_1010 & b_1616
+[ tmask=((~(-1<<(((b_1010-b_1616)&0x1)+1)))&0x3)*0x5*0x11*0x101*0x10001*0x100000001; ]
+{ export * [const]:8 tmask; }
+
+ImmRConst32: "#"^ImmR is ImmR { export *[const]:4 ImmR; }
+ImmRConst64: "#"^ImmR is ImmR { export *[const]:8 ImmR; }
+
+ImmSConst32: "#"^ImmS is ImmS { export *[const]:4 ImmS; }
+ImmSConst64: "#"^ImmS is ImmS { export *[const]:8 ImmS; }
+
+ImmR_bitfield64_imm: "#"^ImmR is ImmR & DecodeWMask64 { export DecodeWMask64; }
+ImmR_bitfield32_imm: "#"^ImmR is ImmR & DecodeWMask32 { export DecodeWMask32; }
+
+ImmS_bitfield64_imm: "#"^ImmS is ImmS & DecodeTMask64 { export DecodeTMask64; }
+ImmS_bitfield32_imm: "#"^ImmS is ImmS & DecodeTMask32 { export DecodeTMask32; }
+
+abcdefgh: "#"^imm is n_uimm8H & n_uimm8L [ imm = ((n_uimm8H << 5 | n_uimm8L)); ] { export *[const]:8 imm; }
+
+repl000: "#"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((n_uimm8H << 5 | n_uimm8L) << 32) | ((n_uimm8H << 5 | n_uimm8L)); ] { export *[const]:8 imm; }
+repl001: "#"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((n_uimm8H << 5 | n_uimm8L) << 40) | ((n_uimm8H << 5 | n_uimm8L) << 8); ] { export *[const]:8 imm; }
+repl010: "#"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((n_uimm8H << 5 | n_uimm8L) << 48) | ((n_uimm8H << 5 | n_uimm8L) << 16); ] { export *[const]:8 imm; }
+repl011: "#"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((n_uimm8H << 5 | n_uimm8L) << 56) | ((n_uimm8H << 5 | n_uimm8L) << 24); ] { export *[const]:8 imm; }
+repl100: "#"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((n_uimm8H << 5 | n_uimm8L) << 48) | ((n_uimm8H << 5 | n_uimm8L) << 32) | ((n_uimm8H << 5 | n_uimm8L) << 16) | ((n_uimm8H << 5 | n_uimm8L)); ] { export *[const]:8 imm; }
+repl101: "#"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((n_uimm8H << 5 | n_uimm8L) << 56) | ((n_uimm8H << 5 | n_uimm8L) << 40) | ((n_uimm8H << 5 | n_uimm8L) << 24) | ((n_uimm8H << 5 | n_uimm8L) << 8); ] { export *[const]:8 imm; }
+repl1100: "#"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((((n_uimm8H << 5 | n_uimm8L) << 8) | 0xff) << 32) | (((n_uimm8H << 5 | n_uimm8L) << 8) | 0xff); ] { export *[const]:8 imm; }
+repl1101: "#"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((((n_uimm8H << 5 | n_uimm8L) << 16) | 0xffff) << 32) | (((n_uimm8H << 5 | n_uimm8L) << 16) | 0xffff); ] { export *[const]:8 imm; }
+repl11100: "#"^imm is abcdefgh & n_uimm8H & n_uimm8L [ imm = ((n_uimm8H << 5 | n_uimm8L) << 56) | ((n_uimm8H << 5 | n_uimm8L) << 48) | ((n_uimm8H << 5 | n_uimm8L) << 40) | ((n_uimm8H << 5 | n_uimm8L) << 32) | ((n_uimm8H << 5 | n_uimm8L) << 24) | ((n_uimm8H << 5 | n_uimm8L) << 16) | ((n_uimm8H << 5 | n_uimm8L) << 8) | (n_uimm8H << 5 | n_uimm8L); ] { export *[const]:8 imm; }
+repl11101: "#"^imm is abcdefgh & b_18 & b_17 & b_16 & b_09 & b_08 & b_07 & b_06 & b_05 [ imm = ((b_18 * 0xff) << 56) | ((b_17 * 0xff) << 48) | ((b_16 * 0xff) << 40) | ((b_09 * 0xff) << 32) | ((b_08 * 0xff) << 24) | ((b_07 * 0xff) << 16) | ((b_06 * 0xff) << 8) | (b_05 * 0xff); ] { export *[const]:8 imm; }
+repl11110: "#"^imm is abcdefgh & b_18 & b_17 & b_16 & b_09 & b_08 & b_07 & b_06 & b_05 [ imm = (b_18 << 31) | ((b_17 $xor 1) << 30) | ((b_17 * 0x1f) << 25) | (b_16 << 24) | (b_09 << 23) | (b_08 << 22) | (b_07 << 21) | (b_06 << 20) | (b_05 << 19); ] { tmp:8 = imm; tmp = (tmp << 32) | tmp; export tmp; }
+repl11111: "#"^imm is abcdefgh & b_18 & b_17 & b_16 & b_09 & b_08 & b_07 & b_06 & b_05 [ imm = (b_18 << 63) | ((b_17 $xor 1) << 62) | ((b_17 * 0xff) << 54) | (b_16 << 53) | (b_09 << 52) | (b_08 << 51) | (b_07 << 50) | (b_06 << 49) | (b_05 << 48); ] { tmp:8 = imm; export tmp; }
+
+Imm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0x0 & b_29=0 & repl000 { export repl000; }
+Imm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0x1 & b_29=0 & repl000 { export repl000; }
+Imm_neon_uimm8Shift: abcdefgh^", LSL #8" is abcdefgh & cmode=0x2 & b_29=0 & repl001 { export repl001; }
+Imm_neon_uimm8Shift: abcdefgh^", LSL #8" is abcdefgh & cmode=0x3 & b_29=0 & repl001 { export repl001; }
+Imm_neon_uimm8Shift: abcdefgh^", LSL #16" is abcdefgh & cmode=0x4 & b_29=0 & repl010 { export repl010; }
+Imm_neon_uimm8Shift: abcdefgh^", LSL #16" is abcdefgh & cmode=0x5 & b_29=0 & repl010 { export repl010; }
+Imm_neon_uimm8Shift: abcdefgh^", LSL #24" is abcdefgh & cmode=0x6 & b_29=0 & repl011 { export repl011; }
+Imm_neon_uimm8Shift: abcdefgh^", LSL #24" is abcdefgh & cmode=0x7 & b_29=0 & repl011 { export repl011; }
+Imm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0x8 & b_29=0 & repl100 { export repl100; }
+Imm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0x9 & b_29=0 & repl100 { export repl100; }
+Imm_neon_uimm8Shift: abcdefgh^", LSL #8" is abcdefgh & cmode=0xa & b_29=0 & repl101 { export repl101; }
+Imm_neon_uimm8Shift: abcdefgh^", LSL #8" is abcdefgh & cmode=0xb & b_29=0 & repl101 { export repl101; }
+Imm_neon_uimm8Shift: abcdefgh^", MSL #8" is abcdefgh & cmode=0xc & b_29=0 & repl1100 { export repl1100; }
+Imm_neon_uimm8Shift: abcdefgh^", MSL #16" is abcdefgh & cmode=0xd & b_29=0 & repl1101 { export repl1101; }
+Imm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0xe & b_29=0 & repl11100 { export repl11100; }
+Imm_neon_uimm8Shift: repl11101 is abcdefgh & cmode=0xe & b_29=1 & repl11101 { export repl11101; } # MOVI 64
+Imm_neon_uimm8Shift: repl11110 is abcdefgh & cmode=0xf & b_29=0 & repl11110 { export repl11110; } # FMOV
+Imm_neon_uimm8Shift: repl11111 is abcdefgh & cmode=0xf & b_29=1 & repl11111 { export repl11111; } # FMOV
+
+Imm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0x1 & b_29=1 & repl000 { export repl000; } # BIC32
+Imm_neon_uimm8Shift: abcdefgh^", LSL 8" is abcdefgh & cmode=0x3 & b_29=1 & repl001 { export repl001; }
+Imm_neon_uimm8Shift: abcdefgh^", LSL 16" is abcdefgh & cmode=0x5 & b_29=1 & repl010 { export repl010; }
+Imm_neon_uimm8Shift: abcdefgh^", LSL 24" is abcdefgh & cmode=0x7 & b_29=1 & repl011 { export repl011; } # BIC16
+Imm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0x9 & b_29=1 & repl000 { export repl000; }
+Imm_neon_uimm8Shift: abcdefgh^", LSL 8" is abcdefgh & cmode=0xb & b_29=1 & repl001 { export repl001; }
+
+Imm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0x0 & b_29=1 & repl000 { export repl000; } # MVNI
+Imm_neon_uimm8Shift: abcdefgh^", LSL 8" is abcdefgh & cmode=0x2 & b_29=1 & repl001 { export repl001; }
+Imm_neon_uimm8Shift: abcdefgh^", LSL 16" is abcdefgh & cmode=0x4 & b_29=1 & repl010 { export repl010; }
+Imm_neon_uimm8Shift: abcdefgh^", LSL 24" is abcdefgh & cmode=0x6 & b_29=1 & repl011 { export repl011; }
+Imm_neon_uimm8Shift: abcdefgh is abcdefgh & cmode=0x8 & b_29=1 & repl000 { export repl000; } # MVNI
+Imm_neon_uimm8Shift: abcdefgh^", LSL 8" is abcdefgh & cmode=0xa & b_29=1 & repl001 { export repl001; }
+Imm_neon_uimm8Shift: abcdefgh^", MSL 8" is abcdefgh & cmode=0xc & b_29=1 & repl1100 { export repl1100; } # MVNI
+Imm_neon_uimm8Shift: abcdefgh^", MSL 16" is abcdefgh & cmode=0xd & b_29=1 & repl1101 { export repl1101; }
+
+vIndex: val is b_2222=0 & b_2121 & b_1111 [ val = b_1111 << 1 | b_2121; ] { export *[const]:8 val; }
+vIndex: val is b_2222=1 & b_2121=0 & b_1111 [ val = b_1111 & 0x1; ] { export *[const]:8 val; }
+
+vIndexHLM: val is b_2223=2 & b_2121 & b_1111 [ val = b_1111 << 1 | b_2121; ] { export *[const]:8 val; }
+vIndexHLM: val is b_2223=1 & b_2121 & b_1111 & b_2020 [ val = b_1111 << 2 | b_2121 << 1 | b_2020; ] { export *[const]:8 val; }
+vIndexHLM: val is b_2223=0 & b_2121 & b_1111 & b_2020 [ val = b_1111 << 2 | b_2121 << 1 | b_2020; ] { export *[const]:8 val; }
+
+vIndexHL: val is b_2223=0b01 & b_21 & b_11 [ val = b_11 << 1 | b_21; ] { export *[const]:8 val; }
+vIndexHL: b_11 is b_2223=0b10 & b_11 { export *[const]:8 b_11; }
+
+@if DATA_ENDIAN == "little"
+Re_VPR128.B.sel: Re_VPR128, val is Re_VPR128 & b_2222=0 & b_2121 & b_1111 [ val = 0x5000 + 32*Re_VPR128 + b_1111 * 2 + b_2121; ] { export *[register]:1 val; }
+Re_VPR128.B.sel: Re_VPR128, val is Re_VPR128 & b_2222=1 & b_2121=0 & b_1111 [ val = 0x5000 + 32*Re_VPR128 + b_1111; ] { export *[register]:1 val; }
+Re_VPR128.S.sel: Re_VPR128, val is Re_VPR128 & b_2222=0 & b_2121 & b_1111 [ val = 0x5000 + 32*Re_VPR128 + (b_1111 * 2 + b_2121) * 4; ] { export *[register]:4 val; }
+Re_VPR128.S.sel: Re_VPR128, val is Re_VPR128 & b_2222=1 & b_2121=0 & b_1111 [ val = 0x5000 + 32*Re_VPR128 + b_1111 * 4; ] { export *[register]:4 val; }
+Re_VPR128.D.sel: Re_VPR128, val is Re_VPR128 & b_2222=0 & b_2121 & b_1111 [ val = 0x5000 + 32*Re_VPR128 + (b_1111 * 2 + b_2121) * 8; ] { export *[register]:8 val; }
+Re_VPR128.D.sel: Re_VPR128, val is Re_VPR128 & b_2222=1 & b_2121=0 & b_1111 [ val = 0x5000 + 32*Re_VPR128 + b_1111 * 8; ] { export *[register]:8 val; }
+@else
+Re_VPR128.B.sel: Re_VPR128, val is Re_VPR128 & b_2222=0 & b_2121 & b_1111 [ val = 0x501f + 32*Re_VPR128 - b_1111 * 2 - b_2121; ] { export *[register]:1 val; }
+Re_VPR128.B.sel: Re_VPR128, val is Re_VPR128 & b_2222=1 & b_2121=0 & b_1111 [ val = 0x501f + 32*Re_VPR128 - b_1111; ] { export *[register]:1 val; }
+Re_VPR128.S.sel: Re_VPR128, val is Re_VPR128 & b_2222=0 & b_2121 & b_1111 [ val = 0x501c + 32*Re_VPR128 - (b_1111 * 2 + b_2121) * 4; ] { export *[register]:4 val; }
+Re_VPR128.S.sel: Re_VPR128, val is Re_VPR128 & b_2222=1 & b_2121=0 & b_1111 [ val = 0x501c + 32*Re_VPR128 - b_1111 * 4; ] { export *[register]:4 val; }
+Re_VPR128.D.sel: Re_VPR128, val is Re_VPR128 & b_2222=0 & b_2121 & b_1111 [ val = 0x5018 + 32*Re_VPR128 - (b_1111 * 2 + b_2121) * 8; ] { export *[register]:8 val; }
+Re_VPR128.D.sel: Re_VPR128, val is Re_VPR128 & b_2222=1 & b_2121=0 & b_1111 [ val = 0x5018 + 32*Re_VPR128 - b_1111 * 8; ] { export *[register]:8 val; }
+@endif
+
+Re_VPR128.B.vIndex: Re_VPR128.B^"["^vIndex^"]" is Re_VPR128.B & vIndex & Re_VPR128.B.sel { export Re_VPR128.B.sel; }
+Re_VPR128.S.vIndex: Re_VPR128.S^"["^vIndex^"]" is Re_VPR128.S & vIndex & Re_VPR128.S.sel { export Re_VPR128.S.sel; }
+Re_VPR128.D.vIndex: Re_VPR128.D^"["^vIndex^"]" is Re_VPR128.D & vIndex & Re_VPR128.D.sel { export Re_VPR128.D.sel; }
+
+@if DATA_ENDIAN == "little"
+Rd_VPR128.B.sel: Rd_VPR128, val is Rd_VPR128 & imm_neon_uimm4 [ val = 0x5000 + 32*Rd_VPR128 + imm_neon_uimm4; ] { export *[register]:1 val; }
+Rd_VPR128.H.sel: Rd_VPR128, val is Rd_VPR128 & imm_neon_uimm3 [ val = 0x5000 + 32*Rd_VPR128 + 2*imm_neon_uimm3; ] { export *[register]:2 val; }
+Rd_VPR128.S.sel: Rd_VPR128, val is Rd_VPR128 & imm_neon_uimm2 [ val = 0x5000 + 32*Rd_VPR128 + 4*imm_neon_uimm2; ] { export *[register]:4 val; }
+Rd_VPR128.D.sel: Rd_VPR128, val is Rd_VPR128 & imm_neon_uimm1 [ val = 0x5000 + 32*Rd_VPR128 + 8*imm_neon_uimm1; ] { export *[register]:8 val; }
+@else
+Rd_VPR128.B.sel: Rd_VPR128, val is Rd_VPR128 & imm_neon_uimm4 [ val = 0x501f + 32*Rd_VPR128 - imm_neon_uimm4; ] { export *[register]:1 val; }
+Rd_VPR128.H.sel: Rd_VPR128, val is Rd_VPR128 & imm_neon_uimm3 [ val = 0x501e + 32*Rd_VPR128 - 2*imm_neon_uimm3; ] { export *[register]:2 val; }
+Rd_VPR128.S.sel: Rd_VPR128, val is Rd_VPR128 & imm_neon_uimm2 [ val = 0x501c + 32*Rd_VPR128 - 4*imm_neon_uimm2; ] { export *[register]:4 val; }
+Rd_VPR128.D.sel: Rd_VPR128, val is Rd_VPR128 & imm_neon_uimm1 [ val = 0x5018 + 32*Rd_VPR128 - 8*imm_neon_uimm1; ] { export *[register]:8 val; }
+@endif
+Rd_VPR128.B.imm_neon_uimm4: Rd_VPR128.B^"["^imm_neon_uimm4^"]" is Rd_VPR128.B & imm_neon_uimm4 & Rd_VPR128.B.sel { export Rd_VPR128.B.sel; }
+Rd_VPR128.H.imm_neon_uimm3: Rd_VPR128.H^"["^imm_neon_uimm3^"]" is Rd_VPR128.H & imm_neon_uimm3 & Rd_VPR128.H.sel { export Rd_VPR128.H.sel; }
+Rd_VPR128.S.imm_neon_uimm2: Rd_VPR128.S^"["^imm_neon_uimm2^"]" is Rd_VPR128.S & imm_neon_uimm2 & Rd_VPR128.S.sel { export Rd_VPR128.S.sel; }
+Rd_VPR128.D.imm_neon_uimm1: Rd_VPR128.D^"["^imm_neon_uimm1^"]" is Rd_VPR128.D & imm_neon_uimm1 & Rd_VPR128.D.sel { export Rd_VPR128.D.sel; }
+
+@if DATA_ENDIAN == "little"
+Rn_VPR128.B.selN: Rn_VPR128, val is Rn_VPR128 & immN_neon_uimm4 [ val = 0x5000 + 32*Rn_VPR128 + immN_neon_uimm4; ] { export *[register]:1 val; }
+Rn_VPR128.H.selN: Rn_VPR128, val is Rn_VPR128 & immN_neon_uimm3 [ val = 0x5000 + 32*Rn_VPR128 + 2*immN_neon_uimm3; ] { export *[register]:2 val; }
+Rn_VPR128.S.selN: Rn_VPR128, val is Rn_VPR128 & immN_neon_uimm2 [ val = 0x5000 + 32*Rn_VPR128 + 4*immN_neon_uimm2; ] { export *[register]:4 val; }
+Rn_VPR128.D.selN: Rn_VPR128, val is Rn_VPR128 & immN_neon_uimm1 [ val = 0x5000 + 32*Rn_VPR128 + 8*immN_neon_uimm1; ] { export *[register]:8 val; }
+@else
+Rn_VPR128.B.selN: Rn_VPR128, val is Rn_VPR128 & immN_neon_uimm4 [ val = 0x501f + 32*Rn_VPR128 - immN_neon_uimm4; ] { export *[register]:1 val; }
+Rn_VPR128.H.selN: Rn_VPR128, val is Rn_VPR128 & immN_neon_uimm3 [ val = 0x501e + 32*Rn_VPR128 - 2*immN_neon_uimm3; ] { export *[register]:2 val; }
+Rn_VPR128.S.selN: Rn_VPR128, val is Rn_VPR128 & immN_neon_uimm2 [ val = 0x501c + 32*Rn_VPR128 - 4*immN_neon_uimm2; ] { export *[register]:4 val; }
+Rn_VPR128.D.selN: Rn_VPR128, val is Rn_VPR128 & immN_neon_uimm1 [ val = 0x5018 + 32*Rn_VPR128 - 8*immN_neon_uimm1; ] { export *[register]:8 val; }
+@endif
+Rn_VPR128.B.immN_neon_uimm4: Rn_VPR128.B^"["^immN_neon_uimm4^"]" is Rn_VPR128.B & immN_neon_uimm4 & Rn_VPR128.B.selN { export Rn_VPR128.B.selN; }
+Rn_VPR128.H.immN_neon_uimm3: Rn_VPR128.H^"["^immN_neon_uimm3^"]" is Rn_VPR128.H & immN_neon_uimm3 & Rn_VPR128.H.selN { export Rn_VPR128.H.selN; }
+Rn_VPR128.S.immN_neon_uimm2: Rn_VPR128.S^"["^immN_neon_uimm2^"]" is Rn_VPR128.S & immN_neon_uimm2 & Rn_VPR128.S.selN { export Rn_VPR128.S.selN; }
+Rn_VPR128.D.immN_neon_uimm1: Rn_VPR128.D^"["^immN_neon_uimm1^"]" is Rn_VPR128.D & immN_neon_uimm1 & Rn_VPR128.D.selN { export Rn_VPR128.D.selN; }
+
+@if DATA_ENDIAN == "little"
+Rn_VPR128.B.sel: Rn_VPR128, val is Rn_VPR128 & imm_neon_uimm4 [ val = 0x5000 + 32*Rn_VPR128 + imm_neon_uimm4; ] { export *[register]:1 val; }
+Rn_VPR128.H.sel: Rn_VPR128, val is Rn_VPR128 & imm_neon_uimm3 [ val = 0x5000 + 32*Rn_VPR128 + 2*imm_neon_uimm3; ] { export *[register]:2 val; }
+Rn_VPR128.S.sel: Rn_VPR128, val is Rn_VPR128 & imm_neon_uimm2 [ val = 0x5000 + 32*Rn_VPR128 + 4*imm_neon_uimm2; ] { export *[register]:4 val; }
+Rn_VPR128.D.sel: Rn_VPR128, val is Rn_VPR128 & imm_neon_uimm1 [ val = 0x5000 + 32*Rn_VPR128 + 8*imm_neon_uimm1; ] { export *[register]:8 val; }
+@else
+Rn_VPR128.B.sel: Rn_VPR128, val is Rn_VPR128 & imm_neon_uimm4 [ val = 0x501f + 32*Rn_VPR128 - imm_neon_uimm4; ] { export *[register]:1 val; }
+Rn_VPR128.H.sel: Rn_VPR128, val is Rn_VPR128 & imm_neon_uimm3 [ val = 0x501e + 32*Rn_VPR128 - 2*imm_neon_uimm3; ] { export *[register]:2 val; }
+Rn_VPR128.S.sel: Rn_VPR128, val is Rn_VPR128 & imm_neon_uimm2 [ val = 0x501c + 32*Rn_VPR128 - 4*imm_neon_uimm2; ] { export *[register]:4 val; }
+Rn_VPR128.D.sel: Rn_VPR128, val is Rn_VPR128 & imm_neon_uimm1 [ val = 0x5018 + 32*Rn_VPR128 - 8*imm_neon_uimm1; ] { export *[register]:8 val; }
+@endif
+Rn_VPR128.B.imm_neon_uimm4: Rn_VPR128.B^"["^imm_neon_uimm4^"]" is Rn_VPR128.B & imm_neon_uimm4 & Rn_VPR128.B.sel { export Rn_VPR128.B.sel; }
+Rn_VPR128.H.imm_neon_uimm3: Rn_VPR128.H^"["^imm_neon_uimm3^"]" is Rn_VPR128.H & imm_neon_uimm3 & Rn_VPR128.H.sel { export Rn_VPR128.H.sel; }
+Rn_VPR128.S.imm_neon_uimm2: Rn_VPR128.S^"["^imm_neon_uimm2^"]" is Rn_VPR128.S & imm_neon_uimm2 & Rn_VPR128.S.sel { export Rn_VPR128.S.sel; }
+Rn_VPR128.D.imm_neon_uimm1: Rn_VPR128.D^"["^imm_neon_uimm1^"]" is Rn_VPR128.D & imm_neon_uimm1 & Rn_VPR128.D.sel { export Rn_VPR128.D.sel; }
+
+Re_VPR128.H.vIndexHL: Re_VPR128.H^"["^vIndexHL^"]" is Re_VPR128.H & vIndexHL { }
+
+@if DATA_ENDIAN == "little"
+Re_VPR128Lo.H.sel: Re_VPR128, val is Re_VPR128 & b_2223=2 & b_2121 & b_1111 [ val = 0x5000 + 32*Re_VPR128 + (b_1111 * 2 + b_2121)*2; ] { export *[register]:2 val; }
+Re_VPR128Lo.H.sel: Re_VPR128, val is Re_VPR128 & b_2223=1 & b_2121 & b_1111 & b_2020 [ val = 0x5000 + 32*Re_VPR128 + (b_1111*4 + b_2121*2 + b_2020)*2; ] { export *[register]:2 val; }
+Re_VPR128Lo.H.sel: Re_VPR128, val is Re_VPR128 & b_2223=0 & b_2121 & b_1111 & b_2020 [ val = 0x5000 + 32*Re_VPR128 + (b_1111*4 + b_2121*2 + b_2020)*2; ] { export *[register]:2 val; }
+@else
+Re_VPR128Lo.H.sel: Re_VPR128, val is Re_VPR128 & b_2223=2 & b_2121 & b_1111 [ val = 0x501e + 32*Re_VPR128 - (b_1111 * 2 + b_2121)*2; ] { export *[register]:2 val; }
+Re_VPR128Lo.H.sel: Re_VPR128, val is Re_VPR128 & b_2223=1 & b_2121 & b_1111 & b_2020 [ val = 0x501e + 32*Re_VPR128 - (b_1111*4 + b_2121*2 + b_2020)*2; ] { export *[register]:2 val; }
+Re_VPR128Lo.H.sel: Re_VPR128, val is Re_VPR128 & b_2223=0 & b_2121 & b_1111 & b_2020 [ val = 0x501e + 32*Re_VPR128 - (b_1111*4 + b_2121*2 + b_2020)*2; ] { export *[register]:2 val; }
+@endif
+Re_VPR128Lo.H.vIndexHLM: Re_VPR128Lo.H^"["^vIndexHLM^"]" is Re_VPR128Lo.H & vIndexHLM & Re_VPR128Lo.H.sel { export Re_VPR128Lo.H.sel; }
+
+FBitsOp: "#"^fbits is Scale [ fbits = 64 - Scale; ] { export *[const]:2 fbits; }
+
+FBits64: factor is FBitsOp & Scale [ factor = 1 << (64 - Scale); ] { fval:8 = int2float(factor:8); export fval; }
+FBits32: factor is FBitsOp & Scale [ factor = 1 << (64 - Scale); ] { fval:4 = int2float(factor:8); export fval; }
+FBits16: factor is FBitsOp & Scale [ factor = 1 << (64 - Scale); ] { fval:2 = int2float(factor:8); export fval; }
+
+# float
+
+Imm8_fmov16_operand: imm is Imm8_fmov_sign & Imm8_fmov_exph & Imm8_fmov_expl & Imm8_fmov_frac & ftype=3 [ imm = (Imm8_fmov_sign << 15) | ((Imm8_fmov_exph $xor 1) << 14) | ((Imm8_fmov_exph * 0x3) << 12) | (Imm8_fmov_expl << 10) | (Imm8_fmov_frac << 6); ] { export *[const]:2 imm; }
+
+Imm8_fmov32_operand: imm is Imm8_fmov_sign & Imm8_fmov_exph & Imm8_fmov_expl & Imm8_fmov_frac & ftype=0 [ imm = (Imm8_fmov_sign << 31) | ((Imm8_fmov_exph $xor 1) << 30) | ((Imm8_fmov_exph * 0x1f) << 25) | (Imm8_fmov_expl << 23) | (Imm8_fmov_frac << 19); ] { export *[const]:4 imm; }
+
+# double
+Imm8_fmov64_operand: imm is Imm8_fmov_sign & Imm8_fmov_exph & Imm8_fmov_expl & Imm8_fmov_frac & ftype=1 [ imm = (Imm8_fmov_sign << 63) | ((Imm8_fmov_exph $xor 1) << 62) | ((Imm8_fmov_exph * 0xff) << 54) | (Imm8_fmov_expl << 52) | (Imm8_fmov_frac << 48); ] { export *[const]:8 imm; }
+
+# SVE subtables
+
+# The size qualifer (T) is encoded in several different ways. The
+# majority of encodings are in sve_size_2223
+
+# encoded in "size" -- Is the size specifier, size 00 B 01 H 10 S 11 D
+
+T: "B" is sve_size_2223=0b00 { export 1:1; }
+T: "H" is sve_size_2223=0b01 { export 2:1; }
+T: "S" is sve_size_2223=0b10 { export 4:1; }
+T: "D" is sve_size_2223=0b11 { export 8:1; }
+
+T_sz: "S" is sve_sz_22=0 { export 4:1; }
+T_sz: "D" is sve_sz_22=1 { export 8:1; }
+
+# encoded in "tszh:tszl" -- Is the size specifier, tszh tszl 00 00 RESERVED 00 01 B 00 1x H 01 xx S 1x xx D
+# Note that tszl is either in b_0809 (if b_21=0) or b_1920 (if b_21=1)
+
+T_tszh: "B" is sve_tszh_2223=0b00 & b_21=0 & sve_tszl_0809=0b01 { export 1:1; }
+T_tszh: "B" is sve_tszh_2223=0b00 & b_21=1 & sve_tszl_1920=0b01 { export 1:1; }
+T_tszh: "H" is sve_tszh_2223=0b00 & b_21=0 & b_09=1 { export 2:1; }
+T_tszh: "H" is sve_tszh_2223=0b00 & b_21=1 & b_20=1 { export 2:1; }
+T_tszh: "S" is sve_tszh_2223=0b01 { export 4:1; }
+T_tszh: "D" is b_23=1 { export 8:1; }
+
+# encoded in "size" -- Is the size specifier, size 00 B 01 H 10 S 11 D
+
+T_size_2122: "B" is sve_size_2122=0b00 { export 1:1; }
+T_size_2122: "H" is sve_size_2122=0b01 { export 2:1; }
+T_size_2122: "S" is sve_size_2122=0b10 { export 4:1; }
+T_size_2122: "D" is sve_size_2122=0b11 { export 8:1; }
+
+# encoded in "tsz" -- Is the size specifier, tsz 00000 RESERVED xxxx1 B xxx10 H xx100 S x1000 D 10000 Q
+
+T_tsz: "B" is b_16=1 { export 1:1; }
+T_tsz: "H" is b_1617=0b10 { export 2:1; }
+T_tsz: "S" is b_1618=0b100 { export 4:1; }
+T_tsz: "D" is b_1619=0b1000 { export 8:1; }
+T_tsz: "Q" is b_1620=0b10000 { export 16:1; }
+sve_imm2_tsz: tmp is b_16=1 & sve_imm2_2223 & b_1720 [ tmp = sve_imm2_2223 * 16 + b_1720; ] { export *[const]:1 tmp; }
+sve_imm2_tsz: tmp is b_1617=0b10 & sve_imm2_2223 & b_1820 [ tmp = sve_imm2_2223 * 8 + b_1820; ] { export *[const]:1 tmp; }
+sve_imm2_tsz: tmp is b_1618=0b100 & sve_imm2_2223 & b_1920 [ tmp = sve_imm2_2223 * 4 + b_1920; ] { export *[const]:1 tmp; }
+sve_imm2_tsz: tmp is b_1619=0b1000 & sve_imm2_2223 & b_20 [ tmp = sve_imm2_2223 * 2 + b_20; ] { export *[const]:1 tmp; }
+sve_imm2_tsz: tmp is b_1620=0b10000 & sve_imm2_2223 [ tmp = sve_imm2_2223 + 0; ] { export *[const]:1 tmp; }
+
+# encoded in "imm13<12>:imm13<5:0>" -- Is the size specifier, imm13<12> imm13<5:0> 0 0xxxxx S 0 10xxxx H 0 110xxx B 0 1110xx B 0 11110x B 0 111110 RESERVED 0 111111 RESERVED 1 xxxxxx D
+
+T_imm13: "S" is b_17=0 & b_10=0 { export 4:1; }
+T_imm13: "H" is b_17=0 & b_0910=0b10 { export 2:1; }
+T_imm13: "B" is b_17=0 & b_0810=0b110 { export 1:1; }
+T_imm13: "B" is b_17=0 & b_0710=0b1110 { export 1:1; }
+T_imm13: "B" is b_17=0 & b_0610=0b11110 { export 1:1; }
+T_imm13: "D" is b_17=1 { export 8:1; }
+
+Zd.T: Zd^"."^T is Zd & T { export Zd; }
+Zd.T_2: Zd^"."^T is Zd & T { export Zd; }
+Zd.T_tszh: Zd^"."^T_tszh is Zd & T_tszh { export Zd; }
+Zd.T_tszh_2: Zd^"."^T_tszh is Zd & T_tszh { export Zd; }
+Zd.T_tsz: Zd^"."^T_tsz is Zd & T_tsz { export Zd; }
+Zd.T_imm13: Zd^"."^T_imm13 is Zd & T_imm13 { export Zd; }
+Zd.T_imm13_2: Zd^"."^T_imm13 is Zd & T_imm13 { export Zd; }
+Zd.T_sz: Zd^"."^T_sz is Zd & T_sz { export Zd; }
+Zd.T_sz_2: Zd^"."^T_sz is Zd & T_sz { export Zd; }
+Zd.T_size_2122: Zd^"."^T_size_2122 is Zd & T_size_2122 { export Zd; }
+
+Zd.B: Zd^".B" is Zd { export Zd; }
+Zd.B_2: Zd^".B" is Zd { export Zd; }
+Zd.H: Zd^".H" is Zd { export Zd; }
+Zd.S: Zd^".S" is Zd { export Zd; }
+Zd.D: Zd^".D" is Zd { export Zd; }
+
+Zt.B: sve_zt_0004^".B" is sve_zt_0004 { export sve_zt_0004; }
+Ztt.B: sve_ztt_0004^".B" is sve_ztt_0004 { export sve_ztt_0004; }
+Zttt.B: sve_zttt_0004^".B" is sve_zttt_0004 { export sve_zttt_0004; }
+Ztttt.B: sve_ztttt_0004^".B" is sve_ztttt_0004 { export sve_ztttt_0004; }
+Zt.H: sve_zt_0004^".H" is sve_zt_0004 { export sve_zt_0004; }
+Ztt.H: sve_ztt_0004^".H" is sve_ztt_0004 { export sve_ztt_0004; }
+Zttt.H: sve_zttt_0004^".H" is sve_zttt_0004 { export sve_zttt_0004; }
+Ztttt.H: sve_ztttt_0004^".H" is sve_ztttt_0004 { export sve_ztttt_0004; }
+Zt.S: sve_zt_0004^".S" is sve_zt_0004 { export sve_zt_0004; }
+Ztt.S: sve_ztt_0004^".S" is sve_ztt_0004 { export sve_ztt_0004; }
+Zttt.S: sve_zttt_0004^".S" is sve_zttt_0004 { export sve_zttt_0004; }
+Ztttt.S: sve_ztttt_0004^".S" is sve_ztttt_0004 { export sve_ztttt_0004; }
+Zt.D: sve_zt_0004^".D" is sve_zt_0004 { export sve_zt_0004; }
+Ztt.D: sve_ztt_0004^".D" is sve_ztt_0004 { export sve_ztt_0004; }
+Zttt.D: sve_zttt_0004^".D" is sve_zttt_0004 { export sve_zttt_0004; }
+Ztttt.D: sve_ztttt_0004^".D" is sve_ztttt_0004 { export sve_ztttt_0004; }
+
+Zn.T: sve_zn_0509^"."^T is sve_zn_0509 & T { export sve_zn_0509; }
+Zn.T_sz: sve_zn_0509^"."^T_sz is sve_zn_0509 & T_sz { export sve_zn_0509; }
+Zn.T_tszh: sve_zn_0509^"."^T_tszh is sve_zn_0509 & T_tszh { export sve_zn_0509; }
+Zn.T_tsz: sve_zn_0509^"."^T_tsz is sve_zn_0509 & T_tsz { export sve_zn_0509; }
+Zn.Tb_sz: sve_zn_0509^".B" is sve_zn_0509 & sve_sz_22=0 { export sve_zn_0509; }
+Zn.Tb_sz: sve_zn_0509^".H" is sve_zn_0509 & sve_sz_22=1 { export sve_zn_0509; }
+Zn.Tb: sve_zn_0509^".B" is sve_zn_0509 & sve_size_2223=0b01 { export sve_zn_0509; }
+Zn.Tb: sve_zn_0509^".H" is sve_zn_0509 & sve_size_2223=0b10 { export sve_zn_0509; }
+Zn.Tb: sve_zn_0509^".S" is sve_zn_0509 & sve_size_2223=0b11 { export sve_zn_0509; }
+
+Zn.B: sve_zn_0509^".B" is sve_zn_0509 { export sve_zn_0509; }
+Zn.H: sve_zn_0509^".H" is sve_zn_0509 { export sve_zn_0509; }
+Zn.S: sve_zn_0509^".S" is sve_zn_0509 { export sve_zn_0509; }
+Zn.D: sve_zn_0509^".D" is sve_zn_0509 { export sve_zn_0509; }
+
+Zm.T: sve_zm_1620^"."^T is sve_zm_1620 & T { export sve_zm_1620; }
+Zm.T_sz: sve_zm_1620^"."^T_sz is sve_zm_1620 & T_sz { export sve_zm_1620; }
+Zm.Tb_sz: sve_zm_1620^".B" is sve_zm_1620 & sve_sz_22=0 { export sve_zm_1620; }
+Zm.Tb_sz: sve_zm_1620^".H" is sve_zm_1620 & sve_sz_22=1 { export sve_zm_1620; }
+# Zm.Tb: sve_zm_1620^".B" is sve_zm_1620 & sve_size_2223=0b01 { export sve_zm_1620; }
+# Zm.Tb: sve_zm_1620^".H" is sve_zm_1620 & sve_size_2223=0b10 { export sve_zm_1620; }
+# Zm.Tb: sve_zm_1620^".S" is sve_zm_1620 & sve_size_2223=0b11 { export sve_zm_1620; }
+
+# Zm.B: sve_zm_1620^".B" is sve_zm_1620 { export sve_zm_1620; }
+# Zm.H: sve_zm_1620^".H" is sve_zm_1620 { export sve_zm_1620; }
+Zm.S: sve_zm_1620^".S" is sve_zm_1620 { export sve_zm_1620; }
+Zm.D: sve_zm_1620^".D" is sve_zm_1620 { export sve_zm_1620; }
+
+Zm3.B: sve_zm_1618^".B" is sve_zm_1618 { export sve_zm_1618; }
+Zm3.H: sve_zm_1618^".H" is sve_zm_1618 { export sve_zm_1618; }
+Zm3.S: sve_zm_1618^".S" is sve_zm_1618 { export sve_zm_1618; }
+# Zm3.D: sve_zm_1618^".D" is sve_zm_1618 { export sve_zm_1618; }
+
+# Zm4.B: sve_zm_1619^".B" is sve_zm_1619 { export sve_zm_1619; }
+Zm4.H: sve_zm_1619^".H" is sve_zm_1619 { export sve_zm_1619; }
+Zm4.S: sve_zm_1619^".S" is sve_zm_1619 { export sve_zm_1619; }
+Zm4.D: sve_zm_1619^".D" is sve_zm_1619 { export sve_zm_1619; }
+
+Pg: sve_pg_1013 is sve_pg_1013 { export sve_pg_1013; }
+Pg_z: sve_pg_1013^"/z" is sve_pg_1013 { export sve_pg_1013; }
+Pg_zm: sve_pg_1013^"/z" is sve_pg_1013 & sve_m_04=0 { export sve_pg_1013; }
+Pg_zm: sve_pg_1013^"/m" is sve_pg_1013 & sve_m_04=1 { export sve_pg_1013; }
+Pg3: sve_pg_1012 is sve_pg_1012 { export sve_pg_1012; }
+Pg3_m: sve_pg_1012^"/m" is sve_pg_1012 { export sve_pg_1012; }
+Pg3_z: sve_pg_1012^"/z" is sve_pg_1012 { export sve_pg_1012; }
+Pg3_zm: sve_pg_1012^"/z" is sve_pg_1012 & sve_m_16=0 { export sve_pg_1012; }
+Pg3_zm: sve_pg_1012^"/m" is sve_pg_1012 & sve_m_16=1 { export sve_pg_1012; }
+
+Pd.T: sve_pd_0003^"."^T is sve_pd_0003 & T { export sve_pd_0003; }
+Pd.T_2: sve_pd_0003^"."^T is sve_pd_0003 & T { export sve_pd_0003; }
+Pd: sve_pd_0003 is sve_pd_0003 { export sve_pd_0003; }
+Pd.B: sve_pd_0003^".B" is sve_pd_0003 { export sve_pd_0003; }
+Pd.B_2: sve_pd_0003^".B" is sve_pd_0003 { export sve_pd_0003; }
+Pd.H: sve_pd_0003^".H" is sve_pd_0003 { export sve_pd_0003; }
+# Pd.S: sve_pd_0003^".S" is sve_pd_0003 { export sve_pd_0003; }
+# Pd.D: sve_pd_0003^".D" is sve_pd_0003 { export sve_pd_0003; }
+
+Pn: sve_pn_0508 is sve_pn_0508 { export sve_pn_0508; }
+Pn_z: sve_pn_0508^"/z" is sve_pn_0508 { export sve_pn_0508; }
+Pn.T: sve_pn_0508^"."^T is sve_pn_0508 & T { export sve_pn_0508; }
+Pn.B: sve_pn_0508^".B" is sve_pn_0508 { export sve_pn_0508; }
+# Pn.H: sve_pn_0508^".H" is sve_pn_0508 { export sve_pn_0508; }
+# Pn.S: sve_pn_0508^".S" is sve_pn_0508 { export sve_pn_0508; }
+# Pn.D: sve_pn_0508^".D" is sve_pn_0508 { export sve_pn_0508; }
+
+Pm_m: sve_pm_1619^"/m" is sve_pm_1619 { export sve_pm_1619; }
+Pm_zm: sve_pm_1619^"/z" is sve_pm_1619 & sve_m_14=0 { export sve_pm_1619; }
+Pm_zm: sve_pm_1619^"/m" is sve_pm_1619 & sve_m_14=1 { export sve_pm_1619; }
+Pm.T: sve_pm_1619^"."^T is sve_pm_1619 & T { export sve_pm_1619; }
+Pm.B: sve_pm_1619^".B" is sve_pm_1619 { export sve_pm_1619; }
+# Pm.H: sve_pm_1619^".H" is sve_pm_1619 { export sve_pm_1619; }
+# Pm.S: sve_pm_1619^".S" is sve_pm_1619 { export sve_pm_1619; }
+# Pm.D: sve_pm_1619^".D" is sve_pm_1619 { export sve_pm_1619; }
+
+sve_i3h_i3l: tmp is sve_i3h_22 & sve_i3l_1920 [ tmp = sve_i3h_22 * 4 + sve_i3l_1920; ] { export *[const]:1 tmp; }
+sve_imm3_1_0to7: sve_imm3_1618 is sve_imm3_1618 { export *[const]:1 sve_imm3_1618; }
+sve_imm4_1_1to16: tmp is sve_imm4_1619 [ tmp = sve_imm4_1619 + 1; ] { export *[const]:1 tmp; }
+sve_imm4_1_m128to112: tmp is sve_imm4s_1619 [ tmp = sve_imm4s_1619 * 16; ] { export *[const]:1 tmp; }
+sve_opt4_1_m128to112: "" is sve_imm4s_1619=0 { export 0:1; }
+sve_opt4_1_m128to112: ", #"^sve_imm4_1_m128to112 is sve_imm4_1_m128to112 { export sve_imm4_1_m128to112; }
+sve_imm4_1_m16to14: tmp is sve_imm4s_1619 [ tmp = sve_imm4s_1619 * 2; ] { export *[const]:1 tmp; }
+sve_mul4_1_m16to14: "" is sve_imm4s_1619=0 { export 0:1; }
+sve_mul4_1_m16to14: ", #"^sve_imm4_1_m16to14^", mul vl" is sve_imm4_1_m16to14 { export *[const]:1 sve_imm4_1_m16to14; }
+sve_imm4_1_m24to21: tmp is sve_imm4s_1619 [ tmp = sve_imm4s_1619 * 3; ] { export *[const]:1 tmp; }
+sve_mul4_1_m24to21: "" is sve_imm4s_1619=0 { export 0:1; }
+sve_mul4_1_m24to21: ", #"^sve_imm4_1_m24to21^", mul vl" is sve_imm4_1_m24to21 { export *[const]:1 sve_imm4_1_m24to21; }
+sve_imm4_1_m32to28: tmp is sve_imm4s_1619 [ tmp = sve_imm4s_1619 * 4; ] { export *[const]:1 tmp; }
+sve_mul4_1_m32to28: "" is sve_imm4s_1619=0 { export 0:1; }
+sve_mul4_1_m32to28: ", #"^sve_imm4_1_m32to28^", mul vl" is sve_imm4_1_m32to28 { export *[const]:1 sve_imm4_1_m32to28; }
+sve_imm4_1_m8to7: tmp is sve_imm4s_1619 [ tmp = sve_imm4s_1619 * 1; ] { export *[const]:1 tmp; }
+sve_mul4_1_m8to7: "" is sve_imm4s_1619=0 { export 0:1; }
+sve_mul4_1_m8to7: ", #"^sve_imm4_1_m8to7^", mul vl" is sve_imm4_1_m8to7 { export *[const]:1 sve_imm4_1_m8to7; }
+sve_imm5_1_0to124: tmp is sve_imm5_1620 [ tmp = sve_imm5_1620 * 4; ] { export *[const]:1 tmp; }
+sve_opt5_1_0to124: "" is sve_imm5_1620=0 { export 0:1; }
+sve_opt5_1_0to124: ", #"^sve_imm5_1_0to124 is sve_imm5_1_0to124 { export sve_imm5_1_0to124; }
+sve_imm5_1_0to248: tmp is sve_imm5_1620 [ tmp = sve_imm5_1620 * 8; ] { export *[const]:1 tmp; }
+sve_opt5_1_0to248: "" is sve_imm5_1620=0 { export 0:1; }
+sve_opt5_1_0to248: ", #"^sve_imm5_1_0to248 is sve_imm5_1_0to248 { export sve_imm5_1_0to248; }
+sve_imm5_1_0to31: sve_imm5_1620 is sve_imm5_1620 { export *[const]:1 sve_imm5_1620; }
+sve_opt5_1_0to31: "" is sve_imm5_1620=0 { export 0:1; }
+sve_opt5_1_0to31: ", #"^sve_imm5_1_0to31 is sve_imm5_1_0to31 { export sve_imm5_1_0to31; }
+sve_imm5_1_0to62: tmp is sve_imm5_1620 [ tmp = sve_imm5_1620 * 2; ] { export *[const]:1 tmp; }
+sve_opt5_1_0to62: "" is sve_imm5_1620=0 { export 0:1; }
+sve_opt5_1_0to62: ", #"^sve_imm5_1_0to62 is sve_imm5_1_0to62 { export sve_imm5_1_0to62; }
+sve_imm5_1_m16to15: sve_imm5s_1620 is sve_b_1015=0b010001 & sve_imm5s_1620 { export *[const]:1 sve_imm5s_1620; }
+sve_imm5_1_m16to15: sve_imm5s_0509 is sve_b_1015=0b010010 & sve_imm5s_0509 { export *[const]:1 sve_imm5s_0509; }
+sve_imm6_1_0to126: tmp is sve_imm6_1621 [ tmp = sve_imm6_1621 * 2; ] { export *[const]:1 tmp; }
+sve_opt6_1_0to126: "" is sve_imm6_1621=0 { export 0:1; }
+sve_opt6_1_0to126: ", #"^sve_imm6_1_0to126 is sve_imm6_1_0to126 { export sve_imm6_1_0to126; }
+sve_imm6_1_0to252: tmp is sve_imm6_1621 [ tmp = sve_imm6_1621 * 4; ] { export *[const]:1 tmp; }
+sve_opt6_1_0to252: "" is sve_imm6_1621=0 { export 0:1; }
+sve_opt6_1_0to252: ", #"^sve_imm6_1_0to252 is sve_imm6_1_0to252 { export sve_imm6_1_0to252; }
+sve_imm6_1_0to504: tmp is sve_imm6_1621 [ tmp = sve_imm6_1621 * 8; ] { export *[const]:2 tmp; }
+sve_opt6_1_0to504: "" is sve_imm6_1621=0 { export 0:2; }
+sve_opt6_1_0to504: ", #"^sve_imm6_1_0to504 is sve_imm6_1_0to504 { export sve_imm6_1_0to504; }
+sve_imm6_1_0to63: sve_imm6_1621 is sve_imm6_1621 { export *[const]:1 sve_imm6_1621; }
+sve_opt6_1_0to63: "" is sve_imm6_1621=0 { export 0:1; }
+sve_opt6_1_0to63: ", #"^sve_imm6_1_0to63 is sve_imm6_1_0to63 { export sve_imm6_1_0to63; }
+sve_imm6_1_m32to31: sve_imm6s_0510 is sve_imm6s_0510 { export *[const]:1 sve_imm6s_0510; }
+sve_mul6_1_m32to31: "" is sve_imm6_1621=0 { export 0:1; }
+sve_mul6_1_m32to31: ", #"^sve_imm6s_1621^", mul vl" is sve_imm6s_1621 { export *[const]:1 sve_imm6s_1621; }
+sve_imm8_1_0to255: sve_imm8_0512 is sve_imm8_0512 { export *[const]:1 sve_imm8_0512; }
+sve_shf8_1_0to255: "#0, LSL #8" is sve_imm8_0512=0 & sve_sh_13=1 { export 0:2; }
+sve_shf8_1_0to255: "#"^tmp is sve_imm8_0512 & sve_sh_13 [ tmp = sve_imm8_0512 << (8 * sve_sh_13); ] { export *[const]:2 tmp; }
+sve_imm8_1_m128to127: sve_imm8s_0512 is sve_imm8s_0512 { export *[const]:1 sve_imm8s_0512; }
+sve_shf8_1_m128to127: "#0, LSL #8" is sve_imm8s_0512=0 & sve_sh_13=1 { export 0:2; }
+sve_shf8_1_m128to127: "#"^tmp is sve_imm8s_0512 & sve_sh_13 [ tmp = sve_imm8s_0512 << (8 * sve_sh_13); ] { export *[const]:2 tmp; }
+sve_imm8_2_0to255: tmp is sve_imm8h_1620 & sve_imm8l_1012 [ tmp = sve_imm8h_1620 * 8 + sve_imm8l_1012; ] { export *[const]:1 tmp; }
+sve_imm9_2_m256to255: tmp is sve_imm9hs_1621 & sve_imm9l_1012 [ tmp = sve_imm9hs_1621 * 8 + sve_imm9l_1012; ] { export *[const]:2 tmp; }
+sve_mul9_2_m256to255: "" is sve_imm6_1621=0 & sve_imm9l_1012=0 { export 0:2; }
+sve_mul9_2_m256to255: ", #"^sve_imm9_2_m256to255^", mul vl" is sve_imm9_2_m256to255 { export sve_imm9_2_m256to255; }
+
+sve_pattern: "POW2" is sve_pattern_0509=0b00000 { export 0b00000:1; }
+sve_pattern: "VL1" is sve_pattern_0509=0b00001 { export 0b00001:1; }
+sve_pattern: "VL2" is sve_pattern_0509=0b00010 { export 0b00010:1; }
+sve_pattern: "VL3" is sve_pattern_0509=0b00011 { export 0b00011:1; }
+sve_pattern: "VL4" is sve_pattern_0509=0b00100 { export 0b00100:1; }
+sve_pattern: "VL5" is sve_pattern_0509=0b00101 { export 0b00101:1; }
+sve_pattern: "VL6" is sve_pattern_0509=0b00110 { export 0b00110:1; }
+sve_pattern: "VL7" is sve_pattern_0509=0b00111 { export 0b00111:1; }
+sve_pattern: "VL8" is sve_pattern_0509=0b01000 { export 0b01000:1; }
+sve_pattern: "VL16" is sve_pattern_0509=0b01001 { export 0b01001:1; }
+sve_pattern: "VL32" is sve_pattern_0509=0b01010 { export 0b01010:1; }
+sve_pattern: "VL64" is sve_pattern_0509=0b01011 { export 0b01011:1; }
+sve_pattern: "VL128" is sve_pattern_0509=0b01100 { export 0b01100:1; }
+sve_pattern: "VL256" is sve_pattern_0509=0b01101 { export 0b01101:1; }
+sve_pattern: "#"^sve_pattern_0509 is b_0609=0b0111 & sve_pattern_0509 { export *[const]:1 sve_pattern_0509; }
+sve_pattern: "#"^sve_pattern_0509 is b_0709=0b101 & b_05=1 & sve_pattern_0509 { export *[const]:1 sve_pattern_0509; }
+sve_pattern: "#"^sve_pattern_0509 is b_0509=0b10110 & sve_pattern_0509 { export *[const]:1 sve_pattern_0509; }
+sve_pattern: "#"^sve_pattern_0509 is b_09=1 & b_07=0 & b_05=1 & sve_pattern_0509 { export *[const]:1 sve_pattern_0509; }
+sve_pattern: "#"^sve_pattern_0509 is b_09=1 & b_0507=0b010 & sve_pattern_0509 { export *[const]:1 sve_pattern_0509; }
+sve_pattern: "#"^sve_pattern_0509 is b_09=1 & b_0506=0b00 & sve_pattern_0509 { export *[const]:1 sve_pattern_0509; }
+sve_pattern: "MUL4" is sve_pattern_0509=0b11101 { export 0b11101:1; }
+sve_pattern: "MUL3" is sve_pattern_0509=0b11110 { export 0b11110:1; }
+sve_pattern: "ALL" is sve_pattern_0509=0b11111 { export 0b11111:1; }
+
+sve_opt_pattern: "" is sve_pattern_0509=0b11111 { export 0b11111:1; }
+sve_opt_pattern: ", "^sve_pattern is sve_pattern { export sve_pattern; }
+
+sve_mul_pattern: "" is sve_pattern_0509=0b11111 & sve_imm4_1619=0b0000 { export 0b11111:1; }
+sve_mul_pattern: ", "^sve_pattern is sve_pattern & sve_imm4_1619=0b0000 { export sve_pattern; }
+sve_mul_pattern: ", "^sve_pattern^", mul #"^sve_imm4_1_1to16 is sve_pattern & sve_imm4_1_1to16 { export sve_pattern; }
+
+sve_mod_amount: "" is sve_msz_1011=0b00 { export 0:1; }
+sve_mod_amount: ", LSL #1" is sve_msz_1011=0b01 { export 1:1; }
+sve_mod_amount: ", LSL #2" is sve_msz_1011=0b10 { export 2:1; }
+sve_mod_amount: ", LSL #3" is sve_msz_1011=0b11 { export 3:1; }
+
+sve_mod: "UXTW" is b_15=1 & b_14=0 { export 2:1; }
+sve_mod: "SXTW" is b_15=1 & b_14=1 { export 3:1; }
+sve_mod: "UXTW" is b_15=0 & b_22=0 { export 0:1; }
+sve_mod: "SXTW" is b_15=0 & b_22=1 { export 1:1; }
+
+sve_prfop: "PLDL1KEEP" is sve_prfop_0003=0b0000 { export 0b0000:1; }
+sve_prfop: "PLDL1STRM" is sve_prfop_0003=0b0001 { export 0b0001:1; }
+sve_prfop: "PLDL2KEEP" is sve_prfop_0003=0b0010 { export 0b0010:1; }
+sve_prfop: "PLDL2STRM" is sve_prfop_0003=0b0011 { export 0b0011:1; }
+sve_prfop: "PLDL3KEEP" is sve_prfop_0003=0b0100 { export 0b0100:1; }
+sve_prfop: "PLDL3STRM" is sve_prfop_0003=0b0101 { export 0b0101:1; }
+sve_prfop: "#"^sve_prfop_0003 is b_02 & b_01=1 & sve_prfop_0003 { export *[const]:1 sve_prfop_0003; }
+sve_prfop: "PSTL1KEEP" is sve_prfop_0003=0b1000 { export 0b1000:1; }
+sve_prfop: "PSTL1STRM" is sve_prfop_0003=0b1001 { export 0b1001:1; }
+sve_prfop: "PSTL2KEEP" is sve_prfop_0003=0b1010 { export 0b1010:1; }
+sve_prfop: "PSTL2STRM" is sve_prfop_0003=0b1011 { export 0b1011:1; }
+sve_prfop: "PSTL3KEEP" is sve_prfop_0003=0b1100 { export 0b1100:1; }
+sve_prfop: "PSTL3STRM" is sve_prfop_0003=0b1101 { export 0b1101:1; }
+
+sve_decode_bit_mask: wmask is b_17=0 & b_0510=0b111100 & b_11 [ wmask = (0x5555 >> b_11) & 0xff; ] { export *[const]:8 wmask; }
+sve_decode_bit_mask: wmask is b_17=0 & b_0710=0b1110 & b_0506=0b00 & b_1112 [ wmask = (0x1111 >> b_1112) & 0xff; ] { export *[const]:8 wmask; }
+sve_decode_bit_mask: wmask is b_17=0 & b_0710=0b1110 & b_0506=0b01 & b_1112 [ wmask = (0x3333 >> b_1112) & 0xff; ] { export *[const]:8 wmask; }
+sve_decode_bit_mask: wmask is b_17=0 & b_0710=0b1110 & b_0506=0b10 & b_1112 [ wmask = (0x7777 >> b_1112) & 0xff; ] { export *[const]:8 wmask; }
+sve_decode_bit_mask: wmask is b_17=0 & b_0810=0b110 & b_0507 & b_1113 [ wmask = (((~(-1<<(b_0507+1))) | (~(-1<<(b_0507+9)) & 0xff00)) >> b_1113) & 0xff; ] { export *[const]:8 wmask; }
+sve_decode_bit_mask: wmask is b_17=0 & b_0910=0b10 & b_0508 & b_1114 [ wmask = (((~(-1<<(b_0508+1))) | (~(-1<<(b_0508+17)) & 0xffff0000)) >> b_1114) & 0xffff; ] { export *[const]:8 wmask; }
+sve_decode_bit_mask: wmask is b_17=0 & b_10=0 & b_0509 & b_1115 [ wmask = (((~(-1<<(b_0509+1))) | (~(-1<<(b_0509+33)) & 0xffffffff00000000)) >> b_1115) & 0xffffffff; ] { export *[const]:8 wmask; }
+sve_decode_bit_mask: wmask is b_17=1 & b_0510 & b_1116 [ wmask = ( (((~(-1<<(b_0510+1)))) >> b_1116) | (((~(-1<<(b_0510+1)))) << (64-b_1116))) & 0xffffffffffffffff; ] { export *[const]:8 wmask; }
+
+sve_shift_13: "" is sve_sh_13=0 { export 0:1; }
+sve_shift_13: ", LSL #8" is sve_sh_13=1 { export 8:1; }
+
+# The immediate shift is computed from tszh, tszl, imm8. The formula
+# depends on the instruction, as does the location of tszl and imm8.
+# The conditions b_21=0/1 and b_17/b_11=0/1 were found by inspecting
+# the differences between the instructions.
+
+# Instructions where the immediate shift is 2 * esize - UInt(tsz:imm3)
+sve_imm_shift: tmp is b_21=0 & b_17=0 & sve_tszh_2223=0b00 & sve_tszl_0809=0b01 & sve_imm3_0507 [ tmp = 16 - ( 8 + sve_imm3_0507); ] { export *[const]:1 tmp; }
+sve_imm_shift: tmp is b_21=0 & b_17=0 & sve_tszh_2223=0b00 & b_09=1 & sve_tszl_0809 & sve_imm3_0507 [ tmp = 32 - ( 8 * sve_tszl_0809 + sve_imm3_0507); ] { export *[const]:1 tmp; }
+sve_imm_shift: tmp is b_21=0 & b_17=0 & sve_tszh_2223=0b01 & sve_tszl_0809 & sve_imm3_0507 [ tmp = 64 - (32 + 8 * sve_tszl_0809 + sve_imm3_0507); ] { export *[const]:1 tmp; }
+sve_imm_shift: tmp is b_21=0 & b_17=0 & b_23=1 & sve_tszh_2223 & sve_tszl_0809 & sve_imm3_0507 [ tmp = 128 - (32 * sve_tszh_2223 + 8 * sve_tszl_0809 + sve_imm3_0507); ] { export *[const]:1 tmp; }
+sve_imm_shift: tmp is b_21=1 & b_11=0 & sve_tszh_2223=0b00 & sve_tszl_1920=0b01 & sve_imm3_1618 [ tmp = 16 - ( 8 + sve_imm3_1618); ] { export *[const]:1 tmp; }
+sve_imm_shift: tmp is b_21=1 & b_11=0 & sve_tszh_2223=0b00 & b_20=1 & sve_tszl_1920 & sve_imm3_1618 [ tmp = 32 - ( 8 * sve_tszl_1920 + sve_imm3_1618); ] { export *[const]:1 tmp; }
+sve_imm_shift: tmp is b_21=1 & b_11=0 & sve_tszh_2223=0b01 & sve_tszl_1920 & sve_imm3_1618 [ tmp = 64 - (32 + 8 * sve_tszl_1920 + sve_imm3_1618); ] { export *[const]:1 tmp; }
+sve_imm_shift: tmp is b_21=1 & b_11=0 & b_23=1 & sve_tszh_2223 & sve_tszl_1920 & sve_imm3_1618 [ tmp = 128 - (32 * sve_tszh_2223 + 8 * sve_tszl_1920 + sve_imm3_1618); ] { export *[const]:1 tmp; }
+
+# Instructions where the immediate shift is UInt(tsz:imm3) - esize
+sve_imm_shift: tmp is b_21=0 & b_17=1 & sve_tszh_2223=0b00 & sve_tszl_0809=0b01 & sve_imm3_0507 [ tmp = ( 8 + sve_imm3_0507) - 8; ] { export *[const]:1 tmp; }
+sve_imm_shift: tmp is b_21=0 & b_17=1 & sve_tszh_2223=0b00 & b_09=1 & sve_tszl_0809 & sve_imm3_0507 [ tmp = ( 8 * sve_tszl_0809 + sve_imm3_0507) - 16; ] { export *[const]:1 tmp; }
+sve_imm_shift: tmp is b_21=0 & b_17=1 & sve_tszh_2223=0b01 & sve_tszl_0809 & sve_imm3_0507 [ tmp = (32 + 8 * sve_tszl_0809 + sve_imm3_0507) - 32; ] { export *[const]:1 tmp; }
+sve_imm_shift: tmp is b_21=0 & b_17=1 & b_23=1 & sve_tszh_2223 & sve_tszl_0809 & sve_imm3_0507 [ tmp = (32 * sve_tszh_2223 + 8 * sve_tszl_0809 + sve_imm3_0507) - 64; ] { export *[const]:1 tmp; }
+sve_imm_shift: tmp is b_21=1 & b_11=1 & sve_tszh_2223=0b00 & sve_tszl_1920=0b01 & sve_imm3_1618 [ tmp = ( 8 + sve_imm3_1618) - 8; ] { export *[const]:1 tmp; }
+sve_imm_shift: tmp is b_21=1 & b_11=1 & sve_tszh_2223=0b00 & b_20=1 & sve_tszl_1920 & sve_imm3_1618 [ tmp = ( 8 * sve_tszl_1920 + sve_imm3_1618) - 16; ] { export *[const]:1 tmp; }
+sve_imm_shift: tmp is b_21=1 & b_11=1 & sve_tszh_2223=0b01 & sve_tszl_1920 & sve_imm3_1618 [ tmp = (32 + 8 * sve_tszl_1920 + sve_imm3_1618) - 32; ] { export *[const]:1 tmp; }
+sve_imm_shift: tmp is b_21=1 & b_11=1 & b_23=1 & sve_tszh_2223 & sve_tszl_1920 & sve_imm3_1618 [ tmp = (32 * sve_tszh_2223 + 8 * sve_tszl_1920 + sve_imm3_1618) - 64; ] { export *[const]:1 tmp; }
+
+sve_float_0510: "#0.5" is sve_i1_05=0 { export 0:1; }
+sve_float_0510: "#1.0" is sve_i1_05=1 { export 1:1; }
+sve_float_0520: "#0.5" is sve_i1_05=0 { export 0:1; }
+sve_float_0520: "#2.0" is sve_i1_05=1 { export 1:1; }
+sve_float_0010: "#0.0" is sve_i1_05=0 { export 0:1; }
+sve_float_0010: "#1.0" is sve_i1_05=1 { export 1:1; }
+
+# there are no floating point constants in SLEIGH
+# generate equivalent hex floating point constant
+
+attach names [ sve_float_dec ] [ "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "a" "b" "c" "d" "e" "f" ];
+attach names [ sve_float_exp ] [ "+1" "+2" "+3" "+4" "-3" "-2" "-1" "+0" ];
+
+sve_float_imm8: s^"."^sve_float_dec^"p"^sve_float_exp is sve_imm8_0512 & sve_float_dec & sve_float_exp & b_12 [ s = (1 - 2 * b_12); ] { export *[const]:1 sve_imm8_0512; }
+
+# SECTION pcodeops
+
+# The following SIMD and MP versions of SLEIGH primitives are
+# implemented in java for AARCH64
+
+define pcodeop MP_INT_ABS;
+define pcodeop MP_INT_RIGHT;
+define pcodeop MP_INT_MULT;
+define pcodeop MP_INT_UMULT;
+
+# The following AARCH64 instructions are implemented in java as a
+# pcodeop
+
+define pcodeop a64_TBL;
+
+# The following pcode ops are not implemented
+
+define pcodeop AT_S12E0R;
+define pcodeop AT_S12E0W;
+define pcodeop AT_S12E1R;
+define pcodeop AT_S12E1W;
+define pcodeop AT_S1E0R;
+define pcodeop AT_S1E0W;
+define pcodeop AT_S1E1R;
+define pcodeop AT_S1E1RP;
+define pcodeop AT_S1E1W;
+define pcodeop AT_S1E1WP;
+define pcodeop AT_S1E2R;
+define pcodeop AT_S1E2W;
+define pcodeop AT_S1E3R;
+define pcodeop AT_S1E3W;
+define pcodeop AuthIA;
+define pcodeop AuthIB;
+define pcodeop AuthDA;
+define pcodeop AuthDB;
+define pcodeop CallHyperVisor;
+define pcodeop CallSecureMonitor;
+define pcodeop CallSupervisor;
+define pcodeop ClearExclusiveLocal;
+define pcodeop crc32b; define pcodeop crc32h;
+define pcodeop crc32w;
+define pcodeop crc32x;
+define pcodeop DataMemoryBarrier;
+define pcodeop DataSynchronizationBarrier;
+define pcodeop DC_CISW;
+define pcodeop DC_CIVAC;
+define pcodeop DC_CSW;
+define pcodeop DC_CVAC;
+define pcodeop DC_CVAP;
+define pcodeop DC_CVAU;
+define pcodeop DC_ISW;
+define pcodeop DC_IVAC;
+define pcodeop DC_IGVAC;
+define pcodeop DC_IGSW;
+define pcodeop DC_IGDVAC;
+define pcodeop DC_IGDSW;
+define pcodeop DC_CGSW;
+define pcodeop DC_CGDSW;
+define pcodeop DC_CIGSW;
+define pcodeop DC_CIGDSW;
+define pcodeop DC_GVA;
+define pcodeop DC_GZVA;
+define pcodeop DC_CGVAC;
+define pcodeop DC_CGDVAC;
+define pcodeop DC_CGVAP;
+define pcodeop DC_CGDVAP;
+define pcodeop DC_CGVADP;
+define pcodeop DC_CGDVADP;
+define pcodeop DC_CIGVAC;
+define pcodeop DC_CIGDVAC;
+define pcodeop DCPSInstruction;
+define pcodeop DC_ZVA;
+define pcodeop DRPSInstruction;
+define pcodeop ExceptionReturn;
+define pcodeop ExclusiveMonitorPass;
+define pcodeop ExclusiveMonitorsStatus;
+define pcodeop HaltBreakPoint;
+define pcodeop Hint_Prefetch;
+define pcodeop IC_IALLU;
+define pcodeop IC_IALLUIS;
+define pcodeop IC_IVAU;
+define pcodeop InstructionSynchronizationBarrier;
+define pcodeop LOAcquire;
+define pcodeop LORelease;
+define pcodeop pacda;
+define pcodeop pacdb;
+define pcodeop pacdza;
+define pcodeop pacdzb;
+define pcodeop pacga;
+define pcodeop pacia;
+define pcodeop paciza;
+define pcodeop pacib;
+define pcodeop pacizb;
+define pcodeop SendEvent;
+define pcodeop SendEventLocally;
+define pcodeop SoftwareBreakpoint;
+define pcodeop SpeculationBarrier;
+define pcodeop SysOp_R;
+define pcodeop SysOp_W;
+define pcodeop TLBI_ALLE1;
+define pcodeop TLBI_ALLE1IS;
+define pcodeop TLBI_ALLE2;
+define pcodeop TLBI_ALLE2IS;
+define pcodeop TLBI_ALLE3;
+define pcodeop TLBI_ALLE3IS;
+define pcodeop TLBI_ASIDE1;
+define pcodeop TLBI_ASIDE1IS;
+define pcodeop TLBI_IPAS2E1;
+define pcodeop TLBI_IPAS2E1IS;
+define pcodeop TLBI_IPAS2LE1;
+define pcodeop TLBI_IPAS2LE1IS;
+define pcodeop TLBI_VAAE1;
+define pcodeop TLBI_VAALE1;
+define pcodeop TLBI_VAAE1IS;
+define pcodeop TLBI_VAALE1IS;
+define pcodeop TLBI_VAE1;
+define pcodeop TLBI_VAE1IS;
+define pcodeop TLBI_VAE2;
+define pcodeop TLBI_VAE2IS;
+define pcodeop TLBI_VAE3;
+define pcodeop TLBI_VAE3IS;
+define pcodeop TLBI_VALE1;
+define pcodeop TLBI_VALE1IS;
+define pcodeop TLBI_VALE2;
+define pcodeop TLBI_VALE2IS;
+define pcodeop TLBI_VALE3;
+define pcodeop TLBI_VALE3IS;
+define pcodeop TLBI_VMALLE1;
+define pcodeop TLBI_VMALLE1IS;
+define pcodeop TLBI_VMALLS12E1;
+define pcodeop TLBI_VMALLS12E1IS;
+define pcodeop UndefinedInstructionException;
+define pcodeop UnkSytemRegRead;
+define pcodeop UnkSytemRegWrite;
+define pcodeop WaitForEvent;
+define pcodeop WaitForInterrupt;
+define pcodeop xpac;
+define pcodeop Yield;
+
+# BTI and MemTag pseudo ops
+
+define pcodeop CopyPtrTag_AddToPtrTag_Exclude; # a combination of the ARM spec's ChooseNonExcludedTag and AddressWithAllocationTag
+define pcodeop ValidCallTarget;
+define pcodeop ValidJumpTarget; # jumps are valid regardless of the register holding the target
+define pcodeop ValidJumpTargetWhenDestIsX16OrX17; # jumps are valid if the register holding the target is x16 or x17, e.g. "br x16"
+define pcodeop ValidJumpTargetIfPermittedBySCTLR; # depending on EL and SCTLR[35,36], jumps using arbitrary registers may or may not be valid.
+define pcodeop ControlFlowPredictionRestrictionByContext;
+define pcodeop CachePrefetchPredictionRestrictionByContext;
+define pcodeop DataValuePredictionRestrictionByContext;
+define pcodeop RandomizePtrTag_Exclude;
+define pcodeop SetPtrTag; # this could be implemented in pcode, but it would break the data flow of the original ptr value
+define pcodeop LoadMemTag;
+define pcodeop StoreMemTag;
+define pcodeop AlignmentFault;
+
+# BTI show/hide operations, which use pcodeops defined above
+
+# for BTI
+BTI_BTITARGETS: is b_0607=0 { } # Not a valid target for jumps or calls
+BTI_BTITARGETS: "c" is ShowBTI=1 & b_0607=1 { ValidCallTarget(); ValidJumpTargetWhenDestIsX16OrX17(); } # BR x16 is valid, BR x5 isn't
+BTI_BTITARGETS: "j" is ShowBTI=1 & b_0607=2 { ValidJumpTarget(); }
+BTI_BTITARGETS: "jc" is ShowBTI=1 & b_0607=3 { ValidJumpTarget(); ValidCallTarget(); }
+# hidden versions of the above; use to prevent ValidXXXXTarget calls from cluttering decompiled code in switch statements etc.
+BTI_BTITARGETS: "c" is ShowBTI=0 & b_0607=1 { }
+BTI_BTITARGETS: "j" is ShowBTI=0 & b_0607=2 { }
+BTI_BTITARGETS: "jc" is ShowBTI=0 & b_0607=3 { }
+
+# for BRK and HLT
+ALL_BTITARGETS: is ShowBTI=1 { ValidJumpTarget(); ValidCallTarget(); }
+ALL_BTITARGETS: is ShowBTI=0 { }
+
+# for PACIASP and PACIBSP
+PACIXSP_BTITARGETS: is ShowBTI=1 {
+ ValidCallTarget();
+ ValidJumpTargetWhenDestIsX16OrX17();
+ # global jump target in the following cases:
+ # EL == 0 and SCTLR[35] == 0
+ # EL != 0 and SCTLR[36] == 0
+ ValidJumpTargetIfPermittedBySCTLR(); # this doesn't seem important enough to clutter decompilations with a decision tree
+}
+PACIXSP_BTITARGETS: is ShowBTI=0 { }
+
+
+# These pseudo ops are used in neon
+
+define pcodeop SIMD_PIECE;
+
+define pcodeop NEON_addv;
+define pcodeop NEON_aesd;
+define pcodeop NEON_aese;
+define pcodeop NEON_aesimc;
+define pcodeop NEON_aesmc;
+define pcodeop NEON_bfdot;
+define pcodeop NEON_bfmlalb;
+define pcodeop NEON_bfmlalt;
+define pcodeop NEON_bfmmla;
+define pcodeop NEON_bif;
+define pcodeop NEON_bit;
+define pcodeop NEON_bsl;
+define pcodeop NEON_cls;
+define pcodeop NEON_clz;
+define pcodeop NEON_cmeq;
+define pcodeop NEON_cmge;
+define pcodeop NEON_cmgt;
+define pcodeop NEON_cmhi;
+define pcodeop NEON_cmhs;
+define pcodeop NEON_cmle;
+define pcodeop NEON_cmlt;
+define pcodeop NEON_cmtst;
+define pcodeop NEON_cnt;
+define pcodeop NEON_ext;
+define pcodeop NEON_facge;
+define pcodeop NEON_facgt;
+define pcodeop NEON_fcadd;
+define pcodeop NEON_fcmeq;
+define pcodeop NEON_fcmge;
+define pcodeop NEON_fcmgt;
+define pcodeop NEON_fcmla;
+define pcodeop NEON_fcmle;
+define pcodeop NEON_fcmlt;
+define pcodeop NEON_fcvtzs;
+define pcodeop NEON_fcvtzu;
+define pcodeop NEON_fmadd;
+define pcodeop NEON_fmax;
+define pcodeop NEON_fmaxnm;
+define pcodeop NEON_fmaxnmp;
+define pcodeop NEON_fmaxnmv;
+define pcodeop NEON_fmaxp;
+define pcodeop NEON_fmaxv;
+define pcodeop NEON_fmin;
+define pcodeop NEON_fminnm;
+define pcodeop NEON_fminnmp;
+define pcodeop NEON_fminnmv;
+define pcodeop NEON_fminp;
+define pcodeop NEON_fminv;
+define pcodeop NEON_fmov;
+define pcodeop NEON_fmsub;
+define pcodeop NEON_fmulx;
+define pcodeop NEON_fnmadd;
+define pcodeop NEON_fnmsub;
+define pcodeop NEON_frecpe;
+define pcodeop NEON_frecps;
+define pcodeop NEON_frecpx;
+define pcodeop NEON_frsqrte;
+define pcodeop NEON_frsqrts;
+define pcodeop NEON_fsqrt;
+define pcodeop NEON_neg;
+define pcodeop NEON_pmul;
+define pcodeop NEON_pmull;
+define pcodeop NEON_pmull2;
+define pcodeop NEON_raddhn;
+define pcodeop NEON_rbit;
+define pcodeop NEON_rev16;
+define pcodeop NEON_rev32;
+define pcodeop NEON_rev64;
+define pcodeop NEON_rshrn;
+define pcodeop NEON_rshrn2;
+define pcodeop NEON_rsubhn;
+define pcodeop NEON_rsubhn2;
+define pcodeop NEON_saba;
+define pcodeop NEON_sabd;
+define pcodeop NEON_saddlv;
+define pcodeop NEON_scvtf;
+define pcodeop NEON_sdot;
+define pcodeop NEON_sha1c;
+define pcodeop NEON_sha1m;
+define pcodeop NEON_sha1p;
+define pcodeop NEON_sha1su0;
+define pcodeop NEON_sha1su1;
+define pcodeop NEON_sha256h;
+define pcodeop NEON_sha256h2;
+define pcodeop NEON_sha256su0;
+define pcodeop NEON_sha256su1;
+define pcodeop NEON_sha512h;
+define pcodeop NEON_sha512h2;
+define pcodeop NEON_sha512su0;
+define pcodeop NEON_sha512su1;
+define pcodeop NEON_shadd;
+define pcodeop NEON_shl;
+define pcodeop NEON_shsub;
+define pcodeop NEON_sli;
+define pcodeop NEON_sm3partw1;
+define pcodeop NEON_sm3partw2;
+define pcodeop NEON_sm3ss1;
+define pcodeop NEON_sm3tt1a;
+define pcodeop NEON_sm3tt1b;
+define pcodeop NEON_sm3tt2a;
+define pcodeop NEON_sm3tt2b;
+define pcodeop NEON_sm4e;
+define pcodeop NEON_sm4ekey;
+define pcodeop NEON_smax;
+define pcodeop NEON_smaxp;
+define pcodeop NEON_smaxv;
+define pcodeop NEON_smin;
+define pcodeop NEON_sminp;
+define pcodeop NEON_sminv;
+define pcodeop NEON_smmla;
+define pcodeop NEON_sqadd;
+define pcodeop NEON_sqdmulh;
+define pcodeop NEON_sqdmull;
+define pcodeop NEON_sqrdml_as_h;
+define pcodeop NEON_sqrdmulh;
+define pcodeop NEON_sqrshl;
+define pcodeop NEON_sqrshrn;
+define pcodeop NEON_sqrshrn2;
+define pcodeop NEON_sqrshrun;
+define pcodeop NEON_sqrshrun2;
+define pcodeop NEON_sqshl;
+define pcodeop NEON_sqshlu;
+define pcodeop NEON_sqshrn;
+define pcodeop NEON_sqshrn2;
+define pcodeop NEON_sqshrun;
+define pcodeop NEON_sqshrun2;
+define pcodeop NEON_sqsub;
+define pcodeop NEON_sqxtn;
+define pcodeop NEON_sqxtn2;
+define pcodeop NEON_sqxtun;
+define pcodeop NEON_sqxtun2;
+define pcodeop NEON_srhadd;
+define pcodeop NEON_sri;
+define pcodeop NEON_srshl;
+define pcodeop NEON_srshr;
+define pcodeop NEON_sshl;
+define pcodeop NEON_sshr;
+define pcodeop NEON_sudot;
+define pcodeop NEON_uaba;
+define pcodeop NEON_uabd;
+define pcodeop NEON_uaddlv;
+define pcodeop NEON_ucvtf;
+define pcodeop NEON_udot;
+define pcodeop NEON_uhadd;
+define pcodeop NEON_uhsub;
+define pcodeop NEON_umax;
+define pcodeop NEON_umaxp;
+define pcodeop NEON_umaxv;
+define pcodeop NEON_umin;
+define pcodeop NEON_uminp;
+define pcodeop NEON_uminv;
+define pcodeop NEON_ummla;
+define pcodeop NEON_umull;
+define pcodeop NEON_uqadd;
+define pcodeop NEON_uqrshl;
+define pcodeop NEON_uqrshrn;
+define pcodeop NEON_uqrshrn2;
+define pcodeop NEON_uqshl;
+define pcodeop NEON_uqshrn;
+define pcodeop NEON_uqshrn2;
+define pcodeop NEON_uqsub;
+define pcodeop NEON_uqxtn;
+define pcodeop NEON_uqxtn2;
+define pcodeop NEON_urecpe;
+define pcodeop NEON_urhadd;
+define pcodeop NEON_urshl;
+define pcodeop NEON_urshr;
+define pcodeop NEON_ursqrte;
+define pcodeop NEON_usdot;
+define pcodeop NEON_ushl;
+define pcodeop NEON_usmmla;
+define pcodeop NEON_usqadd;
+
+# These pseudo ops are automatically generated
+
+define pcodeop SVE_abs;
+define pcodeop SVE_add;
+define pcodeop SVE_addpl;
+define pcodeop SVE_addvl;
+define pcodeop SVE_adr;
+define pcodeop SVE_and;
+define pcodeop SVE_ands;
+define pcodeop SVE_andv;
+define pcodeop SVE_asr;
+define pcodeop SVE_asrd;
+define pcodeop SVE_asrr;
+define pcodeop SVE_bic;
+define pcodeop SVE_bics;
+define pcodeop SVE_brka;
+define pcodeop SVE_brkas;
+define pcodeop SVE_brkb;
+define pcodeop SVE_brkbs;
+define pcodeop SVE_brkn;
+define pcodeop SVE_brkns;
+define pcodeop SVE_brkpa;
+define pcodeop SVE_brkpas;
+define pcodeop SVE_brkpb;
+define pcodeop SVE_brkpbs;
+define pcodeop SVE_clasta;
+define pcodeop SVE_clastb;
+define pcodeop SVE_cls;
+define pcodeop SVE_clz;
+define pcodeop SVE_cmpeq;
+define pcodeop SVE_cmpge;
+define pcodeop SVE_cmpgt;
+define pcodeop SVE_cmphi;
+define pcodeop SVE_cmphs;
+define pcodeop SVE_cmple;
+define pcodeop SVE_cmplo;
+define pcodeop SVE_cmpls;
+define pcodeop SVE_cmplt;
+define pcodeop SVE_cmpne;
+define pcodeop SVE_cnot;
+define pcodeop SVE_cnt;
+define pcodeop SVE_cntb;
+define pcodeop SVE_cntd;
+define pcodeop SVE_cnth;
+define pcodeop SVE_cntp;
+define pcodeop SVE_cntw;
+define pcodeop SVE_compact;
+define pcodeop SVE_cpy;
+define pcodeop SVE_ctermeq;
+define pcodeop SVE_ctermne;
+define pcodeop SVE_decb;
+define pcodeop SVE_decd;
+define pcodeop SVE_dech;
+define pcodeop SVE_decp;
+define pcodeop SVE_decw;
+define pcodeop SVE_dup;
+define pcodeop SVE_dupm;
+define pcodeop SVE_eon;
+define pcodeop SVE_eor;
+define pcodeop SVE_eors;
+define pcodeop SVE_eorv;
+define pcodeop SVE_ext;
+define pcodeop SVE_fabd;
+define pcodeop SVE_fabs;
+define pcodeop SVE_facge;
+define pcodeop SVE_facgt;
+define pcodeop SVE_fadd;
+define pcodeop SVE_fadda;
+define pcodeop SVE_faddv;
+define pcodeop SVE_fcadd;
+define pcodeop SVE_fcmeq;
+define pcodeop SVE_fcmge;
+define pcodeop SVE_fcmgt;
+define pcodeop SVE_fcmla;
+define pcodeop SVE_fcmle;
+define pcodeop SVE_fcmlt;
+define pcodeop SVE_fcmne;
+define pcodeop SVE_fcmuo;
+define pcodeop SVE_fcpy;
+define pcodeop SVE_fcvt;
+define pcodeop SVE_fcvtzs;
+define pcodeop SVE_fcvtzu;
+define pcodeop SVE_fdiv;
+define pcodeop SVE_fdivr;
+define pcodeop SVE_fdup;
+define pcodeop SVE_fexpa;
+define pcodeop SVE_fmad;
+define pcodeop SVE_fmax;
+define pcodeop SVE_fmaxnm;
+define pcodeop SVE_fmaxnmv;
+define pcodeop SVE_fmaxv;
+define pcodeop SVE_fmin;
+define pcodeop SVE_fminnm;
+define pcodeop SVE_fminnmv;
+define pcodeop SVE_fminv;
+define pcodeop SVE_fmla;
+define pcodeop SVE_fmls;
+define pcodeop SVE_fmov;
+define pcodeop SVE_fmsb;
+define pcodeop SVE_fmul;
+define pcodeop SVE_fmulx;
+define pcodeop SVE_fneg;
+define pcodeop SVE_fnmad;
+define pcodeop SVE_fnmla;
+define pcodeop SVE_fnmls;
+define pcodeop SVE_fnmsb;
+define pcodeop SVE_frecpe;
+define pcodeop SVE_frecps;
+define pcodeop SVE_frecpx;
+define pcodeop SVE_frinta;
+define pcodeop SVE_frinti;
+define pcodeop SVE_frintm;
+define pcodeop SVE_frintn;
+define pcodeop SVE_frintp;
+define pcodeop SVE_frintx;
+define pcodeop SVE_frintz;
+define pcodeop SVE_frsqrte;
+define pcodeop SVE_frsqrts;
+define pcodeop SVE_fscale;
+define pcodeop SVE_fsqrt;
+define pcodeop SVE_fsub;
+define pcodeop SVE_fsubr;
+define pcodeop SVE_ftmad;
+define pcodeop SVE_ftsmul;
+define pcodeop SVE_ftssel;
+define pcodeop SVE_incb;
+define pcodeop SVE_incd;
+define pcodeop SVE_inch;
+define pcodeop SVE_incp;
+define pcodeop SVE_incw;
+define pcodeop SVE_index;
+define pcodeop SVE_insr;
+define pcodeop SVE_lasta;
+define pcodeop SVE_lastb;
+define pcodeop SVE_ld1b;
+define pcodeop SVE_ld1d;
+define pcodeop SVE_ld1h;
+define pcodeop SVE_ld1rb;
+define pcodeop SVE_ld1rd;
+define pcodeop SVE_ld1rh;
+define pcodeop SVE_ld1rqb;
+define pcodeop SVE_ld1rqd;
+define pcodeop SVE_ld1rqh;
+define pcodeop SVE_ld1rqw;
+define pcodeop SVE_ld1rsb;
+define pcodeop SVE_ld1rsh;
+define pcodeop SVE_ld1rsw;
+define pcodeop SVE_ld1rw;
+define pcodeop SVE_ld1sb;
+define pcodeop SVE_ld1sh;
+define pcodeop SVE_ld1sw;
+define pcodeop SVE_ld1w;
+define pcodeop SVE_ld2b;
+define pcodeop SVE_ld2d;
+define pcodeop SVE_ld2h;
+define pcodeop SVE_ld2w;
+define pcodeop SVE_ld3b;
+define pcodeop SVE_ld3d;
+define pcodeop SVE_ld3h;
+define pcodeop SVE_ld3w;
+define pcodeop SVE_ld4b;
+define pcodeop SVE_ld4d;
+define pcodeop SVE_ld4h;
+define pcodeop SVE_ld4w;
+define pcodeop SVE_ldff1b;
+define pcodeop SVE_ldff1d;
+define pcodeop SVE_ldff1h;
+define pcodeop SVE_ldff1sb;
+define pcodeop SVE_ldff1sh;
+define pcodeop SVE_ldff1sw;
+define pcodeop SVE_ldff1w;
+define pcodeop SVE_ldnf1b;
+define pcodeop SVE_ldnf1d;
+define pcodeop SVE_ldnf1h;
+define pcodeop SVE_ldnf1sb;
+define pcodeop SVE_ldnf1sh;
+define pcodeop SVE_ldnf1sw;
+define pcodeop SVE_ldnf1w;
+define pcodeop SVE_ldnt1b;
+define pcodeop SVE_ldnt1d;
+define pcodeop SVE_ldnt1h;
+define pcodeop SVE_ldnt1w;
+define pcodeop SVE_ldr;
+define pcodeop SVE_lsl;
+define pcodeop SVE_lslr;
+define pcodeop SVE_lsr;
+define pcodeop SVE_lsrr;
+define pcodeop SVE_mad;
+define pcodeop SVE_mla;
+define pcodeop SVE_mls;
+define pcodeop SVE_movprfx;
+define pcodeop SVE_msb;
+define pcodeop SVE_mul;
+define pcodeop SVE_nand;
+define pcodeop SVE_nands;
+define pcodeop SVE_neg;
+define pcodeop SVE_nor;
+define pcodeop SVE_nors;
+define pcodeop SVE_not;
+define pcodeop SVE_orn;
+define pcodeop SVE_orns;
+define pcodeop SVE_orr;
+define pcodeop SVE_orrs;
+define pcodeop SVE_orv;
+define pcodeop SVE_pfalse;
+define pcodeop SVE_pfirst;
+define pcodeop SVE_pnext;
+define pcodeop SVE_prfb;
+define pcodeop SVE_prfd;
+define pcodeop SVE_prfh;
+define pcodeop SVE_prfw;
+define pcodeop SVE_ptest;
+define pcodeop SVE_ptrue;
+define pcodeop SVE_ptrues;
+define pcodeop SVE_punpkhi;
+define pcodeop SVE_punpklo;
+define pcodeop SVE_rbit;
+define pcodeop SVE_rdffr;
+define pcodeop SVE_rdffrs;
+define pcodeop SVE_rdvl;
+define pcodeop SVE_rev;
+define pcodeop SVE_revb;
+define pcodeop SVE_revh;
+define pcodeop SVE_revw;
+define pcodeop SVE_sabd;
+define pcodeop SVE_saddv;
+define pcodeop SVE_scvtf;
+define pcodeop SVE_sdiv;
+define pcodeop SVE_sdivr;
+define pcodeop SVE_sdot;
+define pcodeop SVE_sel;
+define pcodeop SVE_smax;
+define pcodeop SVE_smaxv;
+define pcodeop SVE_smin;
+define pcodeop SVE_sminv;
+define pcodeop SVE_smulh;
+define pcodeop SVE_splice;
+define pcodeop SVE_sqadd;
+define pcodeop SVE_sqdecb;
+define pcodeop SVE_sqdecd;
+define pcodeop SVE_sqdech;
+define pcodeop SVE_sqdecp;
+define pcodeop SVE_sqdecw;
+define pcodeop SVE_sqincb;
+define pcodeop SVE_sqincd;
+define pcodeop SVE_sqinch;
+define pcodeop SVE_sqincp;
+define pcodeop SVE_sqincw;
+define pcodeop SVE_sqsub;
+define pcodeop SVE_st1b;
+define pcodeop SVE_st1d;
+define pcodeop SVE_st1h;
+define pcodeop SVE_st1w;
+define pcodeop SVE_st2b;
+define pcodeop SVE_st2d;
+define pcodeop SVE_st2h;
+define pcodeop SVE_st2w;
+define pcodeop SVE_st3b;
+define pcodeop SVE_st3d;
+define pcodeop SVE_st3h;
+define pcodeop SVE_st3w;
+define pcodeop SVE_st4b;
+define pcodeop SVE_st4d;
+define pcodeop SVE_st4h;
+define pcodeop SVE_st4w;
+define pcodeop SVE_stnt1b;
+define pcodeop SVE_stnt1d;
+define pcodeop SVE_stnt1h;
+define pcodeop SVE_stnt1w;
+define pcodeop SVE_str;
+define pcodeop SVE_sub;
+define pcodeop SVE_subr;
+define pcodeop SVE_sunpkhi;
+define pcodeop SVE_sunpklo;
+define pcodeop SVE_sxtb;
+define pcodeop SVE_sxth;
+define pcodeop SVE_sxtw;
+define pcodeop SVE_tbl;
+define pcodeop SVE_trn1;
+define pcodeop SVE_trn2;
+define pcodeop SVE_uabd;
+define pcodeop SVE_uaddv;
+define pcodeop SVE_ucvtf;
+define pcodeop SVE_udiv;
+define pcodeop SVE_udivr;
+define pcodeop SVE_udot;
+define pcodeop SVE_umax;
+define pcodeop SVE_umaxv;
+define pcodeop SVE_umin;
+define pcodeop SVE_uminv;
+define pcodeop SVE_umulh;
+define pcodeop SVE_uqadd;
+define pcodeop SVE_uqdecb;
+define pcodeop SVE_uqdecd;
+define pcodeop SVE_uqdech;
+define pcodeop SVE_uqdecp;
+define pcodeop SVE_uqdecw;
+define pcodeop SVE_uqincb;
+define pcodeop SVE_uqincd;
+define pcodeop SVE_uqinch;
+define pcodeop SVE_uqincp;
+define pcodeop SVE_uqincw;
+define pcodeop SVE_uqsub;
+define pcodeop SVE_uunpkhi;
+define pcodeop SVE_uunpklo;
+define pcodeop SVE_uxtb;
+define pcodeop SVE_uxth;
+define pcodeop SVE_uxtw;
+define pcodeop SVE_uzp1;
+define pcodeop SVE_uzp2;
+define pcodeop SVE_whilele;
+define pcodeop SVE_whilelo;
+define pcodeop SVE_whilels;
+define pcodeop SVE_whilelt;
+define pcodeop SVE_wrffr;
+define pcodeop SVE_zip1;
+define pcodeop SVE_zip2;
+
+# SECTION macros
+
+# begin macros related to memory-tagging
+
+macro AllocationTagFromAddress(result, op)
+{
+ # Summary: Sometimes the decompiler won't show this, but that's usually okay.
+ #
+ # A potential downside to actually implementing this, rather than using a pseudo-op,
+ # is that the whole operation can get optimized out to zero by the decompiler when
+ # tags are being ignored/non-populated by the user. (This zero-tagging is helped along by
+ # SetPtrTag being a pseudo-op rather than a macro, which is done to preserve data-flow.)
+ # The optimization makes it harder to tell that tag-related things are happening;
+ # however, it's arguably convenient to omit a bunch of tag-related stuff when tags
+ # are being ignored by the user.
+
+ result = (op >> 56) & 0xf;
+ # decompiler output: return unaff_x30 | 1 << ((ulonglong)register0x00000008 >> 0x38 & 0xf);
+ # An alternate implementation is the following, which has the downside of adding at least one extra length conversion:
+ # result = zext(op[56,4]);
+ # decompiler output: return unaff_x30 | 1 << (ulonglong)((byte)((ulonglong)register0x00000008 >> 0x38) & 0xf);
+}
+
+macro Align(value, sze)
+{
+ value = value & ~(sze - 1);
+}
+
+macro RequireGranuleAlignment(addr)
+{
+ misalignment:8 = addr & ($(TAG_GRANULE) - 1);
+ if (misalignment == 0) goto ;
+ AlignmentFault();
+
+}
+
+macro Or2BytesWithExcludedTags(tmp)
+{
+ tmp = (tmp | gcr_el1.exclude) & 0xffff;
+}
+
+# end of memory-tagging macros
+
+macro addflags(op1, op2)
+{
+ tmpCY = carry(op1, op2);
+ tmpOV = scarry(op1, op2);
+}
+
+macro add_with_carry_flags(op1,op2){
+ local carry_in = zext(CY);
+ local tempResult = op1 + op2;
+ tmpCY = carry(op1,op2) || carry(tempResult, carry_in);
+ tmpOV = scarry(op1,op2) ^^ scarry(tempResult, carry_in);
+}
+
+macro affectflags()
+{
+ NG = tmpNG; ZR = tmpZR; CY = tmpCY; OV = tmpOV;
+}
+
+macro affectLflags()
+{
+ NG = tmpNG; ZR = tmpZR; CY = 0; OV = 0;
+}
+
+# NOTE unlike x86, carry flag is SET if there is NO borrow
+macro subflags(op1, op2)
+{
+ tmpCY = op1 >= op2;
+ tmpOV = sborrow(op1, op2);
+}
+
+# Special case when the first op of the macro call is 0
+macro subflags0(op2)
+{
+ tmpCY = 0 == op2;
+ tmpOV = sborrow(0, op2);
+}
+
+macro logicflags()
+{
+ tmpCY = shift_carry;
+ tmpOV = OV;
+}
+
+macro CVunaffected()
+{
+ tmpCY = CY;
+ tmpOV = OV;
+}
+
+macro resultflags(result)
+{
+ tmpNG = result s< 0;
+ tmpZR = result == 0;
+}
+
+macro fcomp(a, b)
+{
+ NG = a f< b;
+ ZR = a f== b;
+ CY = a f>= b;
+ OV = 0;
+}
+
+macro ftestNAN(a, b)
+{
+ NG = 0;
+ ZR = 0;
+ CY = 0;
+ OV = 0;
+ tst:1 = nan(a) || nan(b);
+ if (tst) goto inst_next;
+}
+
+macro ROR32(out, val, rotate)
+{
+ out = ( val >> rotate) | ( val << ( 32 - rotate ) );
+}
+
+macro ROR64(out, val, rotate)
+{
+ out = ( val >> rotate) | ( val << ( 64 - rotate ) );
+}
+
+macro selectCC(result, val1, val2, condition)
+{
+ result = (zext(condition) * val1) + (zext(!condition) * val2);
+}
+
+macro setCC_NZCV(condMask)
+{
+ NG = (condMask & 0x8) == 0x8;
+ ZR = (condMask & 0x4) == 0x4;
+ CY = (condMask & 0x2) == 0x2;
+ OV = (condMask & 0x1) == 0x1;
+}
+
+macro set_NZCV(value, condMask)
+{
+ setNG:1 = (condMask & 0x8) == 0x8;
+ NG = ((setNG==0) * NG) | ((setNG==1) * (((value >> 3) & 1) ==1));
+ setZR:1 = (condMask & 0x4) == 0x4;
+ ZR = ((setZR==0) * NG) | ((setZR==1) * (((value >> 2) & 1) ==1));
+ setCY:1 = (condMask & 0x2) == 0x2;
+ CY = ((setCY==0) * NG) | ((setCY==1) * (((value >> 1) & 1) == 1));
+ setOV:1 = (condMask & 0x1) == 0x1;
+ OV = ((setOV==0) * NG) | ((setOV==1) * (((value >> 0) & 1) == 1));
+}
+
+# Macro to access simd lanes
+
+# Macros to zero the high bits of the Z or Q registers
+# These are friendlier to the decompiler
+
+macro zext_zb(reg)
+{
+ reg[8,56] = 0;
+ reg[64,64] = 0;
+ reg[128,64] = 0;
+ reg[192,64] = 0;
+}
+
+macro zext_zh(reg)
+{
+ reg[16,48] = 0;
+ reg[64,64] = 0;
+ reg[128,64] = 0;
+ reg[192,64] = 0;
+}
+
+macro zext_zs(reg)
+{
+ reg[32,32] = 0;
+ reg[64,64] = 0;
+ reg[128,64] = 0;
+ reg[192,64] = 0;
+}
+
+macro zext_zd(reg)
+{
+ reg[64,64] = 0;
+ reg[128,64] = 0;
+ reg[192,64] = 0;
+}
+
+macro zext_zq(reg)
+{
+ reg[128,64] = 0;
+ reg[192,64] = 0;
+}
+
+macro zext_rb(reg)
+{
+ reg[8,56] = 0;
+}
+
+macro zext_rh(reg)
+{
+ reg[16,48] = 0;
+}
+
+macro zext_rs(reg)
+{
+ reg[32,32] = 0;
+}
+
+# SECTION instructions
+
+:^instruction
+is ImmS_ImmR_TestSet=0 & ImmR & ImmS & instruction
+[
+ ImmS_LT_ImmR = (((ImmS - ImmR) >> 6) $and 1);
+ ImmS_EQ_ImmR = ~((((ImmS - ImmR) >> 6) $and 1) | (((ImmR - ImmS) >> 6) $and 1));
+ # For ubfm, lsl is the preferred alias when imms + 1 == immr, so we must subtract an extra one
+ # to determine when ubfiz is the preferred alias.
+ ImmS_LT_ImmR_minus_1 = (((ImmS - (ImmR - 1)) >> 6) & 0x1) & (((ImmS - (ImmR - 1)) >> 7) & 0x1);
+ ImmS_ne_1f = (((ImmS - 0x1f) >> 6) & 0x1) | (((0x1f - ImmS) >> 6) & 0x1);
+ ImmS_ne_3f = (((ImmS - 0x3f) >> 6) & 0x1) | (((0x3f - ImmS) >> 6) & 0x1);
+ ImmS_ImmR_TestSet=1;
+]{}
+
+with : ImmS_ImmR_TestSet=1 {
+
+@include "AARCH64_base_PACoptions.sinc"
+
+@include "AARCH64base.sinc"
+@include "AARCH64neon.sinc"
+@include "AARCH64ldst.sinc"
+@include "AARCH64sve.sinc"
+
+# TODO These are placeholders until the correction instruction implementations can be found
+
+:NotYetImplemented_UNK1
+is b_0031=0xe7ffdeff
+unimpl
+
+:NotYetImplemented_UNK2
+is b_0031=0x00200820
+unimpl
+
+:NotYetImplemented_UNK3
+is b_0031=0x00200c20
+unimpl
+
+} # end with ImmS_ImmR_TestSet=1
+
diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64ldst.sinc b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64ldst.sinc
new file mode 100644
index 0000000..28e0b75
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64ldst.sinc
@@ -0,0 +1,10258 @@
+# C7.2.162 LD1 (multiple structures) page C7-1359 line 78995 KEEPWITH
+# INFO This file automatically generated by andre on Fri Jun 8 10:47:29 2018
+# INFO Direct edits to this file may be lost in future updates
+# INFO Command line arguments: ['../../../ProcessorTest/test/andre/scrape/a64ldst.py']
+
+ldst_imm: tmp is b_24=1 & b_21=0 & b_15=0 & b_14=0 & b_13=0 [ tmp = 1; ] { }
+ldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=1 & b_13=0 & b_12=0 & b_11=0 & b_10=0 [ tmp = 1; ] { }
+ldst_imm: tmp is b_24=1 & b_21=1 & b_15=0 & b_14=0 & b_13=0 [ tmp = 2; ] { }
+ldst_imm: tmp is b_24=1 & b_21=0 & b_15=0 & b_14=1 & b_13=0 & b_10=0 [ tmp = 2; ] { }
+ldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=1 & b_13=0 & b_12=0 & b_11=0 & b_10=1 [ tmp = 2; ] { }
+ldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=1 & b_13=0 & b_12=0 & b_11=0 & b_10=0 [ tmp = 2; ] { }
+ldst_imm: tmp is b_24=1 & b_21=0 & b_15=0 & b_14=0 & b_13=1 [ tmp = 3; ] { }
+ldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=1 & b_13=1 & b_12=0 & b_11=0 & b_10=0 [ tmp = 3; ] { }
+ldst_imm: tmp is b_24=1 & b_21=1 & b_15=0 & b_14=0 & b_13=1 [ tmp = 4; ] { }
+ldst_imm: tmp is b_24=1 & b_21=1 & b_15=0 & b_14=1 & b_13=0 & b_10=0 [ tmp = 4; ] { }
+ldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=0 & b_13=0 & b_11=0 & b_10=0 [ tmp = 4; ] { }
+ldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=1 & b_13=0 & b_12=0 & b_11=1 & b_10=0 [ tmp = 4; ] { }
+ldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=1 & b_13=0 & b_12=0 & b_11=0 & b_10=1 [ tmp = 4; ] { }
+ldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=1 & b_13=1 & b_12=0 & b_11=0 & b_10=0 [ tmp = 4; ] { }
+ldst_imm: tmp is b_24=1 & b_21=0 & b_15=0 & b_14=1 & b_13=1 & b_10=0 [ tmp = 6; ] { }
+ldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=1 & b_13=1 & b_12=0 & b_11=0 & b_10=1 [ tmp = 6; ] { }
+ldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=0 & b_14=1 & b_13=1 & b_12=1 [ tmp = 8; ] { }
+ldst_imm: tmp is b_24=1 & b_21=1 & b_15=0 & b_14=1 & b_13=1 & b_10=0 [ tmp = 8; ] { }
+ldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=0 & b_13=0 & b_11=0 & b_10=0 [ tmp = 8; ] { }
+ldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=0 & b_13=0 & b_12=0 & b_11=0 & b_10=1 [ tmp = 8; ] { }
+ldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=1 & b_13=0 & b_12=0 & b_11=1 & b_10=1 [ tmp = 8; ] { }
+ldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=1 & b_13=0 & b_12=0 & b_11=1 & b_10=0 [ tmp = 8; ] { }
+ldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=1 & b_13=1 & b_12=0 & b_11=0 & b_10=1 [ tmp = 8; ] { }
+ldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=0 & b_13=1 & b_11=0 & b_10=0 [ tmp = 12; ] { }
+ldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=1 & b_13=1 & b_12=0 & b_11=1 & b_10=0 [ tmp = 12; ] { }
+ldst_imm: tmp is b_30=1 & b_24=0 & b_21=0 & b_15=0 & b_14=1 & b_13=1 & b_12=1 [ tmp = 16; ] { }
+ldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=1 & b_14=0 & b_12=0 & b_11=0 [ tmp = 16; ] { }
+ldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=1 & b_14=0 & b_12=0 & b_11=1 & b_10=0 [ tmp = 16; ] { }
+ldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=1 & b_14=0 & b_13=1 & b_12=0 & b_11=1 & b_10=1 [ tmp = 16; ] { }
+ldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=0 & b_13=0 & b_12=0 & b_11=0 & b_10=1 [ tmp = 16; ] { }
+ldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=0 & b_13=1 & b_11=0 & b_10=0 [ tmp = 16; ] { }
+ldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=1 & b_13=0 & b_12=0 & b_11=1 & b_10=1 [ tmp = 16; ] { }
+ldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=1 & b_13=1 & b_12=0 & b_11=1 & b_10=0 [ tmp = 16; ] { }
+ldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=0 & b_14=1 & b_12=0 & b_11=0 [ tmp = 24; ] { }
+ldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=0 & b_14=1 & b_12=0 & b_11=1 & b_10=0 [ tmp = 24; ] { }
+ldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=0 & b_14=1 & b_13=1 & b_12=0 & b_11=1 & b_10=1 [ tmp = 24; ] { }
+ldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=0 & b_13=1 & b_12=0 & b_11=0 & b_10=1 [ tmp = 24; ] { }
+ldst_imm: tmp is b_24=1 & b_21=0 & b_15=1 & b_14=1 & b_13=1 & b_12=0 & b_11=1 & b_10=1 [ tmp = 24; ] { }
+ldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=0 & b_14=0 & b_12=0 & b_11=0 [ tmp = 32; ] { }
+ldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=0 & b_14=0 & b_12=0 & b_11=1 & b_10=0 [ tmp = 32; ] { }
+ldst_imm: tmp is b_30=0 & b_24=0 & b_21=0 & b_15=0 & b_14=0 & b_13=1 & b_12=0 & b_11=1 & b_10=1 [ tmp = 32; ] { }
+ldst_imm: tmp is b_30=1 & b_24=0 & b_21=0 & b_15=1 & b_14=0 & b_12=0 [ tmp = 32; ] { }
+ldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=0 & b_13=1 & b_12=0 & b_11=0 & b_10=1 [ tmp = 32; ] { }
+ldst_imm: tmp is b_24=1 & b_21=1 & b_15=1 & b_14=1 & b_13=1 & b_12=0 & b_11=1 & b_10=1 [ tmp = 32; ] { }
+ldst_imm: tmp is b_30=1 & b_24=0 & b_21=0 & b_15=0 & b_14=1 & b_12=0 [ tmp = 48; ] { }
+ldst_imm: tmp is b_30=1 & b_24=0 & b_21=0 & b_15=0 & b_14=0 & b_12=0 [ tmp = 64; ] { }
+
+ldst_wback: "" is b_23=0 & b_1620=0b00000 { }
+ldst_wback: ", #"^ldst_imm is b_23=1 & b_1620=0b11111 & Rn_GPR64xsp & ldst_imm { Rn_GPR64xsp = tmp_ldXn; }
+ldst_wback: ", "^Rm_GPR64 is b_23=1 & Rn_GPR64xsp & Rm_GPR64 { Rn_GPR64xsp = Rm_GPR64; }
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x0c402000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.8B, Vt2.8B, Vt3.8B, Vt4.8B}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".8B", vVtt^".8B", vVttt^".8B", vVtttt^".8B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0010 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR64[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR64[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR64[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR64[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR64[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR64[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR64[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR64[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x0c402400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.4H, Vt2.4H, Vt3.4H, Vt4.4H}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".4H", vVtt^".4H", vVttt^".4H", vVtttt^".4H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0010 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR64[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR64[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR64[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR64[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR64[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR64[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR64[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR64[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR64[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR64[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR64[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR64[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR64[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR64[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR64[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x0c402800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.2S, Vt2.2S, Vt3.2S, Vt4.2S}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".2S", vVtt^".2S", vVttt^".2S", vVtttt^".2S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0010 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR64[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR64[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR64[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR64[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR64[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtttt_VPR64[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtttt_VPR64[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x0c402c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.1D, Vt2.1D, Vt3.1D, Vt4.1D}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".1D", vVtt^".1D", vVttt^".1D", vVtttt^".1D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0010 & b_1011=0b11 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtt_VPR64[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rttt_VPR64[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtttt_VPR64[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x4c402000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.16B, Vt2.16B, Vt3.16B, Vt4.16B}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".16B", vVtt^".16B", vVttt^".16B", vVtttt^".16B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0010 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x4c402400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.8H, Vt2.8H, Vt3.8H, Vt4.8H}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".8H", vVtt^".8H", vVttt^".8H", vVtttt^".8H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0010 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x4c402800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.4S, Vt2.4S, Vt3.4S, Vt4.4S}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".4S", vVtt^".4S", vVttt^".4S", vVtttt^".4S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0010 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtttt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtttt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtttt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtttt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x4c402c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.2D, Vt2.2D, Vt3.2D, Vt4.2D}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".2D", vVtt^".2D", vVttt^".2D", vVtttt^".2D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0010 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rttt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rttt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtttt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtttt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x0c406000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.8B, Vt2.8B, Vt3.8B}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".8B", vVtt^".8B", vVttt^".8B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0110 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x0c406400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.4H, Vt2.4H, Vt3.4H}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".4H", vVtt^".4H", vVttt^".4H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0110 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR64[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR64[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR64[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR64[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR64[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR64[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR64[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR64[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR64[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR64[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR64[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x0c406800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.2S, Vt2.2S, Vt3.2S}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".2S", vVtt^".2S", vVttt^".2S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0110 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR64[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR64[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR64[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR64[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR64[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x0c406c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.1D, Vt2.1D, Vt3.1D}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".1D", vVtt^".1D", vVttt^".1D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0110 & b_1011=0b11 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtt_VPR64[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rttt_VPR64[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x4c406000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.16B, Vt2.16B, Vt3.16B}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".16B", vVtt^".16B", vVttt^".16B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0110 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x4c406400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.8H, Vt2.8H, Vt3.8H}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".8H", vVtt^".8H", vVttt^".8H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0110 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x4c406800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.4S, Vt2.4S, Vt3.4S}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".4S", vVtt^".4S", vVttt^".4S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0110 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x4c406c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.2D, Vt2.2D, Vt3.2D}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".2D", vVtt^".2D", vVttt^".2D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0110 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rttt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rttt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x0c407000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.8B}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".8B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0111 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x0c407400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.4H}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".4H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0111 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR64[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR64[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR64[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x0c407800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.2S}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".2S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0111 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR64[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x0c407c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.1D}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".1D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0111 & b_1011=0b11 & vVt & Rt_VPR64 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x4c407000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.16B}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".16B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0111 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x4c407400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.8H}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".8H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0111 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x4c407800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.4S}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".4S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0111 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x4c407c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.2D}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".2D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0111 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x0c40a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.8B, Vt2.8B}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".8B", vVtt^".8B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1010 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x0c40a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.4H, Vt2.4H}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".4H", vVtt^".4H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1010 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR64[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR64[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR64[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR64[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR64[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR64[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR64[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x0c40a800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.2S, Vt2.2S}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".2S", vVtt^".2S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1010 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR64[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR64[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR64[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x0c40ac00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.1D, Vt2.1D}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".1D", vVtt^".1D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1010 & b_1011=0b11 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtt_VPR64[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x4c40a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.16B, Vt2.16B}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".16B", vVtt^".16B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1010 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x4c40a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.8H, Vt2.8H}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".8H", vVtt^".8H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1010 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x4c40a800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.4S, Vt2.4S}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".4S", vVtt^".4S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1010 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0c402000/mask=xbfff2000
+# C7.2.177 LD1 (multiple structures) page C7-2415 line 141110 MATCH x0cc02000/mask=xbfe02000
+# CONSTRUCT x4c40ac00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.2D, Vt2.2D}, [Xn|SP] [, wback]
+
+:ld1 {vVt^".2D", vVtt^".2D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1010 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x0d400000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.B}[0], [Xn|SP] [, wback]
+
+:ld1 {vVt^".B"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x0d400400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.B}[1], [Xn|SP] [, wback]
+
+:ld1 {vVt^".B"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x0d400800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.B}[2], [Xn|SP] [, wback]
+
+:ld1 {vVt^".B"}[2], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x0d400c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.B}[3], [Xn|SP] [, wback]
+
+:ld1 {vVt^".B"}[3], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x0d401000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.B}[4], [Xn|SP] [, wback]
+
+:ld1 {vVt^".B"}[4], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x0d401400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.B}[5], [Xn|SP] [, wback]
+
+:ld1 {vVt^".B"}[5], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x0d401800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.B}[6], [Xn|SP] [, wback]
+
+:ld1 {vVt^".B"}[6], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x0d401c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.B}[7], [Xn|SP] [, wback]
+
+:ld1 {vVt^".B"}[7], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x4d400000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.B}[8], [Xn|SP] [, wback]
+
+:ld1 {vVt^".B"}[8], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x4d400400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.B}[9], [Xn|SP] [, wback]
+
+:ld1 {vVt^".B"}[9], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x4d400800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.B}[10], [Xn|SP] [, wback]
+
+:ld1 {vVt^".B"}[10], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x4d400c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.B}[11], [Xn|SP] [, wback]
+
+:ld1 {vVt^".B"}[11], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x4d401000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.B}[12], [Xn|SP] [, wback]
+
+:ld1 {vVt^".B"}[12], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x4d401400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.B}[13], [Xn|SP] [, wback]
+
+:ld1 {vVt^".B"}[13], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x4d401800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.B}[14], [Xn|SP] [, wback]
+
+:ld1 {vVt^".B"}[14], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x4d401c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.B}[15], [Xn|SP] [, wback]
+
+:ld1 {vVt^".B"}[15], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x0d404000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.H}[0], [Xn|SP] [, wback]
+
+:ld1 {vVt^".H"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b010 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x0d404800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.H}[1], [Xn|SP] [, wback]
+
+:ld1 {vVt^".H"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b010 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x0d405000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.H}[2], [Xn|SP] [, wback]
+
+:ld1 {vVt^".H"}[2], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b010 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x0d405800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.H}[3], [Xn|SP] [, wback]
+
+:ld1 {vVt^".H"}[3], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b010 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x4d404000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.H}[4], [Xn|SP] [, wback]
+
+:ld1 {vVt^".H"}[4], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b010 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x4d404800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.H}[5], [Xn|SP] [, wback]
+
+:ld1 {vVt^".H"}[5], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b010 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x4d405000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.H}[6], [Xn|SP] [, wback]
+
+:ld1 {vVt^".H"}[6], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b010 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x4d405800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.H}[7], [Xn|SP] [, wback]
+
+:ld1 {vVt^".H"}[7], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b010 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x0d408000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.S}[0], [Xn|SP] [, wback]
+
+:ld1 {vVt^".S"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b100 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x0d409000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.S}[1], [Xn|SP] [, wback]
+
+:ld1 {vVt^".S"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b100 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x4d408000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.S}[2], [Xn|SP] [, wback]
+
+:ld1 {vVt^".S"}[2], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b100 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x4d409000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.S}[3], [Xn|SP] [, wback]
+
+:ld1 {vVt^".S"}[3], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b100 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x0d408400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.D}[0], [Xn|SP] [, wback]
+
+:ld1 {vVt^".D"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b100 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x4d408400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld1 {Vt.D}[1], [Xn|SP] [, wback]
+
+:ld1 {vVt^".D"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b100 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0d40c000/mask=xbffff000
+# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0dc0c000/mask=xbfe0f000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x0d40c000/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld1r {Vt.8B}, [Xn|SP] [, wback]
+
+:ld1r {vVt^".8B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b110 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:1 = 0;
+ tmpv = *:1 tmp_ldXn;
+ Rt_VPR64[0,8] = tmpv;
+ Rt_VPR64[8,8] = tmpv;
+ Rt_VPR64[16,8] = tmpv;
+ Rt_VPR64[24,8] = tmpv;
+ Rt_VPR64[32,8] = tmpv;
+ Rt_VPR64[40,8] = tmpv;
+ Rt_VPR64[48,8] = tmpv;
+ Rt_VPR64[56,8] = tmpv;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0d40c000/mask=xbffff000
+# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0dc0c000/mask=xbfe0f000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x0d40c400/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld1r {Vt.4H}, [Xn|SP] [, wback]
+
+:ld1r {vVt^".4H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b110 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:2 = 0;
+ tmpv = *:2 tmp_ldXn;
+ Rt_VPR64[0,16] = tmpv;
+ Rt_VPR64[16,16] = tmpv;
+ Rt_VPR64[32,16] = tmpv;
+ Rt_VPR64[48,16] = tmpv;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0d40c000/mask=xbffff000
+# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0dc0c000/mask=xbfe0f000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x0d40c800/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld1r {Vt.2S}, [Xn|SP] [, wback]
+
+:ld1r {vVt^".2S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b110 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:4 = 0;
+ tmpv = *:4 tmp_ldXn;
+ Rt_VPR64[0,32] = tmpv;
+ Rt_VPR64[32,32] = tmpv;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0d40c000/mask=xbffff000
+# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0dc0c000/mask=xbfe0f000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x0d40cc00/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld1r {Vt.1D}, [Xn|SP] [, wback]
+
+:ld1r {vVt^".1D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b110 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR64 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:8 = 0;
+ tmpv = *:8 tmp_ldXn;
+ Rt_VPR64[0,64] = tmpv;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0d40c000/mask=xbffff000
+# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0dc0c000/mask=xbfe0f000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x4d40c000/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld1r {Vt.16B}, [Xn|SP] [, wback]
+
+:ld1r {vVt^".16B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b110 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:1 = 0;
+ tmpv = *:1 tmp_ldXn;
+ Rt_VPR128[0,8] = tmpv;
+ Rt_VPR128[8,8] = tmpv;
+ Rt_VPR128[16,8] = tmpv;
+ Rt_VPR128[24,8] = tmpv;
+ Rt_VPR128[32,8] = tmpv;
+ Rt_VPR128[40,8] = tmpv;
+ Rt_VPR128[48,8] = tmpv;
+ Rt_VPR128[56,8] = tmpv;
+ Rt_VPR128[64,8] = tmpv;
+ Rt_VPR128[72,8] = tmpv;
+ Rt_VPR128[80,8] = tmpv;
+ Rt_VPR128[88,8] = tmpv;
+ Rt_VPR128[96,8] = tmpv;
+ Rt_VPR128[104,8] = tmpv;
+ Rt_VPR128[112,8] = tmpv;
+ Rt_VPR128[120,8] = tmpv;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0d40c000/mask=xbffff000
+# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0dc0c000/mask=xbfe0f000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x4d40c400/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld1r {Vt.8H}, [Xn|SP] [, wback]
+
+:ld1r {vVt^".8H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b110 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:2 = 0;
+ tmpv = *:2 tmp_ldXn;
+ Rt_VPR128[0,16] = tmpv;
+ Rt_VPR128[16,16] = tmpv;
+ Rt_VPR128[32,16] = tmpv;
+ Rt_VPR128[48,16] = tmpv;
+ Rt_VPR128[64,16] = tmpv;
+ Rt_VPR128[80,16] = tmpv;
+ Rt_VPR128[96,16] = tmpv;
+ Rt_VPR128[112,16] = tmpv;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0d40c000/mask=xbffff000
+# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0dc0c000/mask=xbfe0f000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x4d40c800/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld1r {Vt.4S}, [Xn|SP] [, wback]
+
+:ld1r {vVt^".4S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b110 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:4 = 0;
+ tmpv = *:4 tmp_ldXn;
+ Rt_VPR128[0,32] = tmpv;
+ Rt_VPR128[32,32] = tmpv;
+ Rt_VPR128[64,32] = tmpv;
+ Rt_VPR128[96,32] = tmpv;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0d40c000/mask=xbffff000
+# C7.2.179 LD1R page C7-2423 line 141626 MATCH x0dc0c000/mask=xbfe0f000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0d400000/mask=xbfff2000
+# C7.2.178 LD1 (single structure) page C7-2419 line 141371 MATCH x0dc00000/mask=xbfe02000
+# CONSTRUCT x4d40cc00/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld1r {Vt.2D}, [Xn|SP] [, wback]
+
+:ld1r {vVt^".2D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b110 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:8 = 0;
+ tmpv = *:8 tmp_ldXn;
+ Rt_VPR128[0,64] = tmpv;
+ Rt_VPR128[64,64] = tmpv;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0c408000/mask=xbffff000
+# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0cc08000/mask=xbfe0f000
+# CONSTRUCT x0c408000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.8B, Vt2.8B}, [Xn|SP] [, wback]
+
+:ld2 {vVt^".8B", vVtt^".8B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1000 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0c408000/mask=xbffff000
+# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0cc08000/mask=xbfe0f000
+# CONSTRUCT x0c408400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.4H, Vt2.4H}, [Xn|SP] [, wback]
+
+:ld2 {vVt^".4H", vVtt^".4H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1000 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR64[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR64[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR64[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR64[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR64[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR64[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR64[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0c408000/mask=xbffff000
+# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0cc08000/mask=xbfe0f000
+# CONSTRUCT x0c408800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.2S, Vt2.2S}, [Xn|SP] [, wback]
+
+:ld2 {vVt^".2S", vVtt^".2S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1000 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR64[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR64[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR64[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0c408000/mask=xbffff000
+# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0cc08000/mask=xbfe0f000
+# CONSTRUCT x4c408000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.16B, Vt2.16B}, [Xn|SP] [, wback]
+
+:ld2 {vVt^".16B", vVtt^".16B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1000 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0c408000/mask=xbffff000
+# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0cc08000/mask=xbfe0f000
+# CONSTRUCT x4c408400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.8H, Vt2.8H}, [Xn|SP] [, wback]
+
+:ld2 {vVt^".8H", vVtt^".8H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1000 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0c408000/mask=xbffff000
+# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0cc08000/mask=xbfe0f000
+# CONSTRUCT x4c408800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.4S, Vt2.4S}, [Xn|SP] [, wback]
+
+:ld2 {vVt^".4S", vVtt^".4S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1000 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0c408000/mask=xbffff000
+# C7.2.180 LD2 (multiple structures) page C7-2426 line 141824 MATCH x0cc08000/mask=xbfe0f000
+# CONSTRUCT x4c408c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.2D, Vt2.2D}, [Xn|SP] [, wback]
+
+:ld2 {vVt^".2D", vVtt^".2D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b1000 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x0d600000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.B, Vt2.B}[0], [Xn|SP] [, wback]
+
+:ld2 {vVt^".B", vVtt^".B"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x0d600400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.B, Vt2.B}[1], [Xn|SP] [, wback]
+
+:ld2 {vVt^".B", vVtt^".B"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x0d600800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.B, Vt2.B}[2], [Xn|SP] [, wback]
+
+:ld2 {vVt^".B", vVtt^".B"}[2], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x0d600c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.B, Vt2.B}[3], [Xn|SP] [, wback]
+
+:ld2 {vVt^".B", vVtt^".B"}[3], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x0d601000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.B, Vt2.B}[4], [Xn|SP] [, wback]
+
+:ld2 {vVt^".B", vVtt^".B"}[4], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x0d601400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.B, Vt2.B}[5], [Xn|SP] [, wback]
+
+:ld2 {vVt^".B", vVtt^".B"}[5], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x0d601800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.B, Vt2.B}[6], [Xn|SP] [, wback]
+
+:ld2 {vVt^".B", vVtt^".B"}[6], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x0d601c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.B, Vt2.B}[7], [Xn|SP] [, wback]
+
+:ld2 {vVt^".B", vVtt^".B"}[7], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x4d600000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.B, Vt2.B}[8], [Xn|SP] [, wback]
+
+:ld2 {vVt^".B", vVtt^".B"}[8], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x4d600400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.B, Vt2.B}[9], [Xn|SP] [, wback]
+
+:ld2 {vVt^".B", vVtt^".B"}[9], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x4d600800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.B, Vt2.B}[10], [Xn|SP] [, wback]
+
+:ld2 {vVt^".B", vVtt^".B"}[10], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x4d600c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.B, Vt2.B}[11], [Xn|SP] [, wback]
+
+:ld2 {vVt^".B", vVtt^".B"}[11], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x4d601000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.B, Vt2.B}[12], [Xn|SP] [, wback]
+
+:ld2 {vVt^".B", vVtt^".B"}[12], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x4d601400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.B, Vt2.B}[13], [Xn|SP] [, wback]
+
+:ld2 {vVt^".B", vVtt^".B"}[13], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x4d601800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.B, Vt2.B}[14], [Xn|SP] [, wback]
+
+:ld2 {vVt^".B", vVtt^".B"}[14], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x4d601c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.B, Vt2.B}[15], [Xn|SP] [, wback]
+
+:ld2 {vVt^".B", vVtt^".B"}[15], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x0d604000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.H, Vt2.H}[0], [Xn|SP] [, wback]
+
+:ld2 {vVt^".H", vVtt^".H"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b010 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x0d604800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.H, Vt2.H}[1], [Xn|SP] [, wback]
+
+:ld2 {vVt^".H", vVtt^".H"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b010 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x0d605000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.H, Vt2.H}[2], [Xn|SP] [, wback]
+
+:ld2 {vVt^".H", vVtt^".H"}[2], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b010 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x0d605800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.H, Vt2.H}[3], [Xn|SP] [, wback]
+
+:ld2 {vVt^".H", vVtt^".H"}[3], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b010 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x4d604000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.H, Vt2.H}[4], [Xn|SP] [, wback]
+
+:ld2 {vVt^".H", vVtt^".H"}[4], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b010 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x4d604800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.H, Vt2.H}[5], [Xn|SP] [, wback]
+
+:ld2 {vVt^".H", vVtt^".H"}[5], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b010 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x4d605000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.H, Vt2.H}[6], [Xn|SP] [, wback]
+
+:ld2 {vVt^".H", vVtt^".H"}[6], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b010 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x4d605800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.H, Vt2.H}[7], [Xn|SP] [, wback]
+
+:ld2 {vVt^".H", vVtt^".H"}[7], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b010 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x0d608000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.S, Vt2.S}[0], [Xn|SP] [, wback]
+
+:ld2 {vVt^".S", vVtt^".S"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b100 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x0d609000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.S, Vt2.S}[1], [Xn|SP] [, wback]
+
+:ld2 {vVt^".S", vVtt^".S"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b100 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x4d608000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.S, Vt2.S}[2], [Xn|SP] [, wback]
+
+:ld2 {vVt^".S", vVtt^".S"}[2], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b100 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x4d609000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.S, Vt2.S}[3], [Xn|SP] [, wback]
+
+:ld2 {vVt^".S", vVtt^".S"}[3], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b100 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x0d608400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.D, Vt2.D}[0], [Xn|SP] [, wback]
+
+:ld2 {vVt^".D", vVtt^".D"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b100 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x4d608400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld2 {Vt.D, Vt2.D}[1], [Xn|SP] [, wback]
+
+:ld2 {vVt^".D", vVtt^".D"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b100 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0d60c000/mask=xbffff000
+# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0de0c000/mask=xbfe0f000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x0d60c000/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld2r {Vt.8B, Vt2.8B}, [Xn|SP] [, wback]
+
+:ld2r {vVt^".8B", vVtt^".8B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b110 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:1 = 0;
+ tmpv = *:1 tmp_ldXn;
+ Rtt_VPR64[0,8] = tmpv;
+ Rtt_VPR64[8,8] = tmpv;
+ Rtt_VPR64[16,8] = tmpv;
+ Rtt_VPR64[24,8] = tmpv;
+ Rtt_VPR64[32,8] = tmpv;
+ Rtt_VPR64[40,8] = tmpv;
+ Rtt_VPR64[48,8] = tmpv;
+ Rtt_VPR64[56,8] = tmpv;
+ tmp_ldXn = tmp_ldXn + 1;
+ tmpv = *:1 tmp_ldXn;
+ Rtt_VPR64[0,8] = tmpv;
+ Rtt_VPR64[8,8] = tmpv;
+ Rtt_VPR64[16,8] = tmpv;
+ Rtt_VPR64[24,8] = tmpv;
+ Rtt_VPR64[32,8] = tmpv;
+ Rtt_VPR64[40,8] = tmpv;
+ Rtt_VPR64[48,8] = tmpv;
+ Rtt_VPR64[56,8] = tmpv;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0d60c000/mask=xbffff000
+# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0de0c000/mask=xbfe0f000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x0d60c400/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld2r {Vt.4H, Vt2.4H}, [Xn|SP] [, wback]
+
+:ld2r {vVt^".4H", vVtt^".4H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b110 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:2 = 0;
+ tmpv = *:2 tmp_ldXn;
+ Rtt_VPR64[0,16] = tmpv;
+ Rtt_VPR64[16,16] = tmpv;
+ Rtt_VPR64[32,16] = tmpv;
+ Rtt_VPR64[48,16] = tmpv;
+ tmp_ldXn = tmp_ldXn + 2;
+ tmpv = *:2 tmp_ldXn;
+ Rtt_VPR64[0,16] = tmpv;
+ Rtt_VPR64[16,16] = tmpv;
+ Rtt_VPR64[32,16] = tmpv;
+ Rtt_VPR64[48,16] = tmpv;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0d60c000/mask=xbffff000
+# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0de0c000/mask=xbfe0f000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x0d60c800/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld2r {Vt.2S, Vt2.2S}, [Xn|SP] [, wback]
+
+:ld2r {vVt^".2S", vVtt^".2S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b110 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:4 = 0;
+ tmpv = *:4 tmp_ldXn;
+ Rtt_VPR64[0,32] = tmpv;
+ Rtt_VPR64[32,32] = tmpv;
+ tmp_ldXn = tmp_ldXn + 4;
+ tmpv = *:4 tmp_ldXn;
+ Rtt_VPR64[0,32] = tmpv;
+ Rtt_VPR64[32,32] = tmpv;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0d60c000/mask=xbffff000
+# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0de0c000/mask=xbfe0f000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x0d60cc00/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld2r {Vt.1D, Vt2.1D}, [Xn|SP] [, wback]
+
+:ld2r {vVt^".1D", vVtt^".1D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b110 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:8 = 0;
+ tmpv = *:8 tmp_ldXn;
+ Rtt_VPR64[0,64] = tmpv;
+ tmp_ldXn = tmp_ldXn + 8;
+ tmpv = *:8 tmp_ldXn;
+ Rtt_VPR64[0,64] = tmpv;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0d60c000/mask=xbffff000
+# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0de0c000/mask=xbfe0f000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x4d60c000/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld2r {Vt.16B, Vt2.16B}, [Xn|SP] [, wback]
+
+:ld2r {vVt^".16B", vVtt^".16B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b110 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:1 = 0;
+ tmpv = *:1 tmp_ldXn;
+ Rtt_VPR128[0,8] = tmpv;
+ Rtt_VPR128[8,8] = tmpv;
+ Rtt_VPR128[16,8] = tmpv;
+ Rtt_VPR128[24,8] = tmpv;
+ Rtt_VPR128[32,8] = tmpv;
+ Rtt_VPR128[40,8] = tmpv;
+ Rtt_VPR128[48,8] = tmpv;
+ Rtt_VPR128[56,8] = tmpv;
+ Rtt_VPR128[64,8] = tmpv;
+ Rtt_VPR128[72,8] = tmpv;
+ Rtt_VPR128[80,8] = tmpv;
+ Rtt_VPR128[88,8] = tmpv;
+ Rtt_VPR128[96,8] = tmpv;
+ Rtt_VPR128[104,8] = tmpv;
+ Rtt_VPR128[112,8] = tmpv;
+ Rtt_VPR128[120,8] = tmpv;
+ tmp_ldXn = tmp_ldXn + 1;
+ tmpv = *:1 tmp_ldXn;
+ Rtt_VPR128[0,8] = tmpv;
+ Rtt_VPR128[8,8] = tmpv;
+ Rtt_VPR128[16,8] = tmpv;
+ Rtt_VPR128[24,8] = tmpv;
+ Rtt_VPR128[32,8] = tmpv;
+ Rtt_VPR128[40,8] = tmpv;
+ Rtt_VPR128[48,8] = tmpv;
+ Rtt_VPR128[56,8] = tmpv;
+ Rtt_VPR128[64,8] = tmpv;
+ Rtt_VPR128[72,8] = tmpv;
+ Rtt_VPR128[80,8] = tmpv;
+ Rtt_VPR128[88,8] = tmpv;
+ Rtt_VPR128[96,8] = tmpv;
+ Rtt_VPR128[104,8] = tmpv;
+ Rtt_VPR128[112,8] = tmpv;
+ Rtt_VPR128[120,8] = tmpv;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0d60c000/mask=xbffff000
+# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0de0c000/mask=xbfe0f000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x4d60c400/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld2r {Vt.8H, Vt2.8H}, [Xn|SP] [, wback]
+
+:ld2r {vVt^".8H", vVtt^".8H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b110 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:2 = 0;
+ tmpv = *:2 tmp_ldXn;
+ Rtt_VPR128[0,16] = tmpv;
+ Rtt_VPR128[16,16] = tmpv;
+ Rtt_VPR128[32,16] = tmpv;
+ Rtt_VPR128[48,16] = tmpv;
+ Rtt_VPR128[64,16] = tmpv;
+ Rtt_VPR128[80,16] = tmpv;
+ Rtt_VPR128[96,16] = tmpv;
+ Rtt_VPR128[112,16] = tmpv;
+ tmp_ldXn = tmp_ldXn + 2;
+ tmpv = *:2 tmp_ldXn;
+ Rtt_VPR128[0,16] = tmpv;
+ Rtt_VPR128[16,16] = tmpv;
+ Rtt_VPR128[32,16] = tmpv;
+ Rtt_VPR128[48,16] = tmpv;
+ Rtt_VPR128[64,16] = tmpv;
+ Rtt_VPR128[80,16] = tmpv;
+ Rtt_VPR128[96,16] = tmpv;
+ Rtt_VPR128[112,16] = tmpv;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0d60c000/mask=xbffff000
+# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0de0c000/mask=xbfe0f000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x4d60c800/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld2r {Vt.4S, Vt2.4S}, [Xn|SP] [, wback]
+
+:ld2r {vVt^".4S", vVtt^".4S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b110 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:4 = 0;
+ tmpv = *:4 tmp_ldXn;
+ Rtt_VPR128[0,32] = tmpv;
+ Rtt_VPR128[32,32] = tmpv;
+ Rtt_VPR128[64,32] = tmpv;
+ Rtt_VPR128[96,32] = tmpv;
+ tmp_ldXn = tmp_ldXn + 4;
+ tmpv = *:4 tmp_ldXn;
+ Rtt_VPR128[0,32] = tmpv;
+ Rtt_VPR128[32,32] = tmpv;
+ Rtt_VPR128[64,32] = tmpv;
+ Rtt_VPR128[96,32] = tmpv;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0d60c000/mask=xbffff000
+# C7.2.182 LD2R page C7-2433 line 142264 MATCH x0de0c000/mask=xbfe0f000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0d600000/mask=xbfff2000
+# C7.2.181 LD2 (single structure) page C7-2429 line 142006 MATCH x0de00000/mask=xbfe02000
+# CONSTRUCT x4d60cc00/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld2r {Vt.2D, Vt2.2D}, [Xn|SP] [, wback]
+
+:ld2r {vVt^".2D", vVtt^".2D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b110 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:8 = 0;
+ tmpv = *:8 tmp_ldXn;
+ Rtt_VPR128[0,64] = tmpv;
+ Rtt_VPR128[64,64] = tmpv;
+ tmp_ldXn = tmp_ldXn + 8;
+ tmpv = *:8 tmp_ldXn;
+ Rtt_VPR128[0,64] = tmpv;
+ Rtt_VPR128[64,64] = tmpv;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0c404000/mask=xbffff000
+# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0cc04000/mask=xbfe0f000
+# CONSTRUCT x0c404000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.8B, Vt2.8B, Vt3.8B}, [Xn|SP] [, wback]
+
+:ld3 {vVt^".8B", vVtt^".8B", vVttt^".8B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0100 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0c404000/mask=xbffff000
+# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0cc04000/mask=xbfe0f000
+# CONSTRUCT x0c404400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.4H, Vt2.4H, Vt3.4H}, [Xn|SP] [, wback]
+
+:ld3 {vVt^".4H", vVtt^".4H", vVttt^".4H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0100 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR64[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR64[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR64[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR64[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR64[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR64[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR64[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR64[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR64[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR64[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR64[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0c404000/mask=xbffff000
+# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0cc04000/mask=xbfe0f000
+# CONSTRUCT x0c404800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.2S, Vt2.2S, Vt3.2S}, [Xn|SP] [, wback]
+
+:ld3 {vVt^".2S", vVtt^".2S", vVttt^".2S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0100 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR64[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR64[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR64[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR64[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR64[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0c404000/mask=xbffff000
+# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0cc04000/mask=xbfe0f000
+# CONSTRUCT x4c404000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.16B, Vt2.16B, Vt3.16B}, [Xn|SP] [, wback]
+
+:ld3 {vVt^".16B", vVtt^".16B", vVttt^".16B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0100 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0c404000/mask=xbffff000
+# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0cc04000/mask=xbfe0f000
+# CONSTRUCT x4c404400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.8H, Vt2.8H, Vt3.8H}, [Xn|SP] [, wback]
+
+:ld3 {vVt^".8H", vVtt^".8H", vVttt^".8H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0100 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0c404000/mask=xbffff000
+# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0cc04000/mask=xbfe0f000
+# CONSTRUCT x4c404800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.4S, Vt2.4S, Vt3.4S}, [Xn|SP] [, wback]
+
+:ld3 {vVt^".4S", vVtt^".4S", vVttt^".4S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0100 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0c404000/mask=xbffff000
+# C7.2.183 LD3 (multiple structures) page C7-2436 line 142465 MATCH x0cc04000/mask=xbfe0f000
+# CONSTRUCT x4c404c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.2D, Vt2.2D, Vt3.2D}, [Xn|SP] [, wback]
+
+:ld3 {vVt^".2D", vVtt^".2D", vVttt^".2D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0100 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rttt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rttt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x0d402000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.B, Vt2.B, Vt3.B}[0], [Xn|SP] [, wback]
+
+:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x0d402400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.B, Vt2.B, Vt3.B}[1], [Xn|SP] [, wback]
+
+:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x0d402800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.B, Vt2.B, Vt3.B}[2], [Xn|SP] [, wback]
+
+:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[2], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x0d402c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.B, Vt2.B, Vt3.B}[3], [Xn|SP] [, wback]
+
+:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[3], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x0d403000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.B, Vt2.B, Vt3.B}[4], [Xn|SP] [, wback]
+
+:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[4], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x0d403400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.B, Vt2.B, Vt3.B}[5], [Xn|SP] [, wback]
+
+:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[5], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x0d403800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.B, Vt2.B, Vt3.B}[6], [Xn|SP] [, wback]
+
+:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[6], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x0d403c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.B, Vt2.B, Vt3.B}[7], [Xn|SP] [, wback]
+
+:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[7], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x4d402000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.B, Vt2.B, Vt3.B}[8], [Xn|SP] [, wback]
+
+:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[8], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x4d402400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.B, Vt2.B, Vt3.B}[9], [Xn|SP] [, wback]
+
+:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[9], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x4d402800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.B, Vt2.B, Vt3.B}[10], [Xn|SP] [, wback]
+
+:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[10], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x4d402c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.B, Vt2.B, Vt3.B}[11], [Xn|SP] [, wback]
+
+:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[11], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x4d403000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.B, Vt2.B, Vt3.B}[12], [Xn|SP] [, wback]
+
+:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[12], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x4d403400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.B, Vt2.B, Vt3.B}[13], [Xn|SP] [, wback]
+
+:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[13], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x4d403800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.B, Vt2.B, Vt3.B}[14], [Xn|SP] [, wback]
+
+:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[14], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x4d403c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.B, Vt2.B, Vt3.B}[15], [Xn|SP] [, wback]
+
+:ld3 {vVt^".B", vVtt^".B", vVttt^".B"}[15], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x0d406000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.H, Vt2.H, Vt3.H}[0], [Xn|SP] [, wback]
+
+:ld3 {vVt^".H", vVtt^".H", vVttt^".H"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b011 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x0d406800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.H, Vt2.H, Vt3.H}[1], [Xn|SP] [, wback]
+
+:ld3 {vVt^".H", vVtt^".H", vVttt^".H"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b011 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x0d407000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.H, Vt2.H, Vt3.H}[2], [Xn|SP] [, wback]
+
+:ld3 {vVt^".H", vVtt^".H", vVttt^".H"}[2], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b011 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x0d407800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.H, Vt2.H, Vt3.H}[3], [Xn|SP] [, wback]
+
+:ld3 {vVt^".H", vVtt^".H", vVttt^".H"}[3], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b011 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x4d406000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.H, Vt2.H, Vt3.H}[4], [Xn|SP] [, wback]
+
+:ld3 {vVt^".H", vVtt^".H", vVttt^".H"}[4], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b011 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x4d406800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.H, Vt2.H, Vt3.H}[5], [Xn|SP] [, wback]
+
+:ld3 {vVt^".H", vVtt^".H", vVttt^".H"}[5], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b011 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x4d407000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.H, Vt2.H, Vt3.H}[6], [Xn|SP] [, wback]
+
+:ld3 {vVt^".H", vVtt^".H", vVttt^".H"}[6], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b011 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x4d407800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.H, Vt2.H, Vt3.H}[7], [Xn|SP] [, wback]
+
+:ld3 {vVt^".H", vVtt^".H", vVttt^".H"}[7], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b011 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x0d40a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.S, Vt2.S, Vt3.S}[0], [Xn|SP] [, wback]
+
+:ld3 {vVt^".S", vVtt^".S", vVttt^".S"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b101 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x0d40b000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.S, Vt2.S, Vt3.S}[1], [Xn|SP] [, wback]
+
+:ld3 {vVt^".S", vVtt^".S", vVttt^".S"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b101 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x4d40a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.S, Vt2.S, Vt3.S}[2], [Xn|SP] [, wback]
+
+:ld3 {vVt^".S", vVtt^".S", vVttt^".S"}[2], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b101 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x4d40b000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.S, Vt2.S, Vt3.S}[3], [Xn|SP] [, wback]
+
+:ld3 {vVt^".S", vVtt^".S", vVttt^".S"}[3], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b101 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x0d40a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.D, Vt2.D, Vt3.D}[0], [Xn|SP] [, wback]
+
+:ld3 {vVt^".D", vVtt^".D", vVttt^".D"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b101 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rttt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x4d40a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld3 {Vt.D, Vt2.D, Vt3.D}[1], [Xn|SP] [, wback]
+
+:ld3 {vVt^".D", vVtt^".D", vVttt^".D"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b101 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rttt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0d40e000/mask=xbffff000
+# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0dc0e000/mask=xbfe0f000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x0d40e000/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld3r {Vt.8B, Vt2.8B, Vt3.8B}, [Xn|SP] [, wback]
+
+:ld3r {vVt^".8B", vVtt^".8B", vVttt^".8B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b111 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:1 = 0;
+ tmpv = *:1 tmp_ldXn;
+ Rttt_VPR64[0,8] = tmpv;
+ Rttt_VPR64[8,8] = tmpv;
+ Rttt_VPR64[16,8] = tmpv;
+ Rttt_VPR64[24,8] = tmpv;
+ Rttt_VPR64[32,8] = tmpv;
+ Rttt_VPR64[40,8] = tmpv;
+ Rttt_VPR64[48,8] = tmpv;
+ Rttt_VPR64[56,8] = tmpv;
+ tmp_ldXn = tmp_ldXn + 1;
+ tmpv = *:1 tmp_ldXn;
+ Rttt_VPR64[0,8] = tmpv;
+ Rttt_VPR64[8,8] = tmpv;
+ Rttt_VPR64[16,8] = tmpv;
+ Rttt_VPR64[24,8] = tmpv;
+ Rttt_VPR64[32,8] = tmpv;
+ Rttt_VPR64[40,8] = tmpv;
+ Rttt_VPR64[48,8] = tmpv;
+ Rttt_VPR64[56,8] = tmpv;
+ tmp_ldXn = tmp_ldXn + 1;
+ tmpv = *:1 tmp_ldXn;
+ Rttt_VPR64[0,8] = tmpv;
+ Rttt_VPR64[8,8] = tmpv;
+ Rttt_VPR64[16,8] = tmpv;
+ Rttt_VPR64[24,8] = tmpv;
+ Rttt_VPR64[32,8] = tmpv;
+ Rttt_VPR64[40,8] = tmpv;
+ Rttt_VPR64[48,8] = tmpv;
+ Rttt_VPR64[56,8] = tmpv;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0d40e000/mask=xbffff000
+# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0dc0e000/mask=xbfe0f000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x0d40e400/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld3r {Vt.4H, Vt2.4H, Vt3.4H}, [Xn|SP] [, wback]
+
+:ld3r {vVt^".4H", vVtt^".4H", vVttt^".4H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b111 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:2 = 0;
+ tmpv = *:2 tmp_ldXn;
+ Rttt_VPR64[0,16] = tmpv;
+ Rttt_VPR64[16,16] = tmpv;
+ Rttt_VPR64[32,16] = tmpv;
+ Rttt_VPR64[48,16] = tmpv;
+ tmp_ldXn = tmp_ldXn + 2;
+ tmpv = *:2 tmp_ldXn;
+ Rttt_VPR64[0,16] = tmpv;
+ Rttt_VPR64[16,16] = tmpv;
+ Rttt_VPR64[32,16] = tmpv;
+ Rttt_VPR64[48,16] = tmpv;
+ tmp_ldXn = tmp_ldXn + 2;
+ tmpv = *:2 tmp_ldXn;
+ Rttt_VPR64[0,16] = tmpv;
+ Rttt_VPR64[16,16] = tmpv;
+ Rttt_VPR64[32,16] = tmpv;
+ Rttt_VPR64[48,16] = tmpv;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0d40e000/mask=xbffff000
+# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0dc0e000/mask=xbfe0f000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x0d40e800/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld3r {Vt.2S, Vt2.2S, Vt3.2S}, [Xn|SP] [, wback]
+
+:ld3r {vVt^".2S", vVtt^".2S", vVttt^".2S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b111 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:4 = 0;
+ tmpv = *:4 tmp_ldXn;
+ Rttt_VPR64[0,32] = tmpv;
+ Rttt_VPR64[32,32] = tmpv;
+ tmp_ldXn = tmp_ldXn + 4;
+ tmpv = *:4 tmp_ldXn;
+ Rttt_VPR64[0,32] = tmpv;
+ Rttt_VPR64[32,32] = tmpv;
+ tmp_ldXn = tmp_ldXn + 4;
+ tmpv = *:4 tmp_ldXn;
+ Rttt_VPR64[0,32] = tmpv;
+ Rttt_VPR64[32,32] = tmpv;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0d40e000/mask=xbffff000
+# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0dc0e000/mask=xbfe0f000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x0d40ec00/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld3r {Vt.1D, Vt2.1D, Vt3.1D}, [Xn|SP] [, wback]
+
+:ld3r {vVt^".1D", vVtt^".1D", vVttt^".1D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b111 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:8 = 0;
+ tmpv = *:8 tmp_ldXn;
+ Rttt_VPR64[0,64] = tmpv;
+ tmp_ldXn = tmp_ldXn + 8;
+ tmpv = *:8 tmp_ldXn;
+ Rttt_VPR64[0,64] = tmpv;
+ tmp_ldXn = tmp_ldXn + 8;
+ tmpv = *:8 tmp_ldXn;
+ Rttt_VPR64[0,64] = tmpv;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0d40e000/mask=xbffff000
+# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0dc0e000/mask=xbfe0f000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x4d40e000/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld3r {Vt.16B, Vt2.16B, Vt3.16B}, [Xn|SP] [, wback]
+
+:ld3r {vVt^".16B", vVtt^".16B", vVttt^".16B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b111 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:1 = 0;
+ tmpv = *:1 tmp_ldXn;
+ Rttt_VPR128[0,8] = tmpv;
+ Rttt_VPR128[8,8] = tmpv;
+ Rttt_VPR128[16,8] = tmpv;
+ Rttt_VPR128[24,8] = tmpv;
+ Rttt_VPR128[32,8] = tmpv;
+ Rttt_VPR128[40,8] = tmpv;
+ Rttt_VPR128[48,8] = tmpv;
+ Rttt_VPR128[56,8] = tmpv;
+ Rttt_VPR128[64,8] = tmpv;
+ Rttt_VPR128[72,8] = tmpv;
+ Rttt_VPR128[80,8] = tmpv;
+ Rttt_VPR128[88,8] = tmpv;
+ Rttt_VPR128[96,8] = tmpv;
+ Rttt_VPR128[104,8] = tmpv;
+ Rttt_VPR128[112,8] = tmpv;
+ Rttt_VPR128[120,8] = tmpv;
+ tmp_ldXn = tmp_ldXn + 1;
+ tmpv = *:1 tmp_ldXn;
+ Rttt_VPR128[0,8] = tmpv;
+ Rttt_VPR128[8,8] = tmpv;
+ Rttt_VPR128[16,8] = tmpv;
+ Rttt_VPR128[24,8] = tmpv;
+ Rttt_VPR128[32,8] = tmpv;
+ Rttt_VPR128[40,8] = tmpv;
+ Rttt_VPR128[48,8] = tmpv;
+ Rttt_VPR128[56,8] = tmpv;
+ Rttt_VPR128[64,8] = tmpv;
+ Rttt_VPR128[72,8] = tmpv;
+ Rttt_VPR128[80,8] = tmpv;
+ Rttt_VPR128[88,8] = tmpv;
+ Rttt_VPR128[96,8] = tmpv;
+ Rttt_VPR128[104,8] = tmpv;
+ Rttt_VPR128[112,8] = tmpv;
+ Rttt_VPR128[120,8] = tmpv;
+ tmp_ldXn = tmp_ldXn + 1;
+ tmpv = *:1 tmp_ldXn;
+ Rttt_VPR128[0,8] = tmpv;
+ Rttt_VPR128[8,8] = tmpv;
+ Rttt_VPR128[16,8] = tmpv;
+ Rttt_VPR128[24,8] = tmpv;
+ Rttt_VPR128[32,8] = tmpv;
+ Rttt_VPR128[40,8] = tmpv;
+ Rttt_VPR128[48,8] = tmpv;
+ Rttt_VPR128[56,8] = tmpv;
+ Rttt_VPR128[64,8] = tmpv;
+ Rttt_VPR128[72,8] = tmpv;
+ Rttt_VPR128[80,8] = tmpv;
+ Rttt_VPR128[88,8] = tmpv;
+ Rttt_VPR128[96,8] = tmpv;
+ Rttt_VPR128[104,8] = tmpv;
+ Rttt_VPR128[112,8] = tmpv;
+ Rttt_VPR128[120,8] = tmpv;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0d40e000/mask=xbffff000
+# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0dc0e000/mask=xbfe0f000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x4d40e400/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld3r {Vt.8H, Vt2.8H, Vt3.8H}, [Xn|SP] [, wback]
+
+:ld3r {vVt^".8H", vVtt^".8H", vVttt^".8H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b111 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:2 = 0;
+ tmpv = *:2 tmp_ldXn;
+ Rttt_VPR128[0,16] = tmpv;
+ Rttt_VPR128[16,16] = tmpv;
+ Rttt_VPR128[32,16] = tmpv;
+ Rttt_VPR128[48,16] = tmpv;
+ Rttt_VPR128[64,16] = tmpv;
+ Rttt_VPR128[80,16] = tmpv;
+ Rttt_VPR128[96,16] = tmpv;
+ Rttt_VPR128[112,16] = tmpv;
+ tmp_ldXn = tmp_ldXn + 2;
+ tmpv = *:2 tmp_ldXn;
+ Rttt_VPR128[0,16] = tmpv;
+ Rttt_VPR128[16,16] = tmpv;
+ Rttt_VPR128[32,16] = tmpv;
+ Rttt_VPR128[48,16] = tmpv;
+ Rttt_VPR128[64,16] = tmpv;
+ Rttt_VPR128[80,16] = tmpv;
+ Rttt_VPR128[96,16] = tmpv;
+ Rttt_VPR128[112,16] = tmpv;
+ tmp_ldXn = tmp_ldXn + 2;
+ tmpv = *:2 tmp_ldXn;
+ Rttt_VPR128[0,16] = tmpv;
+ Rttt_VPR128[16,16] = tmpv;
+ Rttt_VPR128[32,16] = tmpv;
+ Rttt_VPR128[48,16] = tmpv;
+ Rttt_VPR128[64,16] = tmpv;
+ Rttt_VPR128[80,16] = tmpv;
+ Rttt_VPR128[96,16] = tmpv;
+ Rttt_VPR128[112,16] = tmpv;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0d40e000/mask=xbffff000
+# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0dc0e000/mask=xbfe0f000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x4d40e800/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld3r {Vt.4S, Vt2.4S, Vt3.4S}, [Xn|SP] [, wback]
+
+:ld3r {vVt^".4S", vVtt^".4S", vVttt^".4S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b111 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:4 = 0;
+ tmpv = *:4 tmp_ldXn;
+ Rttt_VPR128[0,32] = tmpv;
+ Rttt_VPR128[32,32] = tmpv;
+ Rttt_VPR128[64,32] = tmpv;
+ Rttt_VPR128[96,32] = tmpv;
+ tmp_ldXn = tmp_ldXn + 4;
+ tmpv = *:4 tmp_ldXn;
+ Rttt_VPR128[0,32] = tmpv;
+ Rttt_VPR128[32,32] = tmpv;
+ Rttt_VPR128[64,32] = tmpv;
+ Rttt_VPR128[96,32] = tmpv;
+ tmp_ldXn = tmp_ldXn + 4;
+ tmpv = *:4 tmp_ldXn;
+ Rttt_VPR128[0,32] = tmpv;
+ Rttt_VPR128[32,32] = tmpv;
+ Rttt_VPR128[64,32] = tmpv;
+ Rttt_VPR128[96,32] = tmpv;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0d40e000/mask=xbffff000
+# C7.2.185 LD3R page C7-2443 line 142925 MATCH x0dc0e000/mask=xbfe0f000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0d402000/mask=xbfff2000
+# C7.2.184 LD3 (single structure) page C7-2439 line 142666 MATCH x0dc02000/mask=xbfe02000
+# CONSTRUCT x4d40ec00/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld3r {Vt.2D, Vt2.2D, Vt3.2D}, [Xn|SP] [, wback]
+
+:ld3r {vVt^".2D", vVtt^".2D", vVttt^".2D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=0 & b_1315=0b111 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:8 = 0;
+ tmpv = *:8 tmp_ldXn;
+ Rttt_VPR128[0,64] = tmpv;
+ Rttt_VPR128[64,64] = tmpv;
+ tmp_ldXn = tmp_ldXn + 8;
+ tmpv = *:8 tmp_ldXn;
+ Rttt_VPR128[0,64] = tmpv;
+ Rttt_VPR128[64,64] = tmpv;
+ tmp_ldXn = tmp_ldXn + 8;
+ tmpv = *:8 tmp_ldXn;
+ Rttt_VPR128[0,64] = tmpv;
+ Rttt_VPR128[64,64] = tmpv;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0c400000/mask=xbffff000
+# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0cc00000/mask=xbfe0f000
+# CONSTRUCT x0c400000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.8B, Vt2.8B, Vt3.8B, Vt4.8B}, [Xn|SP] [, wback]
+
+:ld4 {vVt^".8B", vVtt^".8B", vVttt^".8B", vVtttt^".8B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0000 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR64[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR64[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR64[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR64[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR64[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR64[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR64[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR64[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR64[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR64[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR64[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0c400000/mask=xbffff000
+# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0cc00000/mask=xbfe0f000
+# CONSTRUCT x0c400400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.4H, Vt2.4H, Vt3.4H, Vt4.4H}, [Xn|SP] [, wback]
+
+:ld4 {vVt^".4H", vVtt^".4H", vVttt^".4H", vVtttt^".4H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0000 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR64[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR64[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR64[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR64[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR64[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR64[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR64[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR64[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR64[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR64[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR64[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR64[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR64[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR64[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR64[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0c400000/mask=xbffff000
+# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0cc00000/mask=xbfe0f000
+# CONSTRUCT x0c400800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.2S, Vt2.2S, Vt3.2S, Vt4.2S}, [Xn|SP] [, wback]
+
+:ld4 {vVt^".2S", vVtt^".2S", vVttt^".2S", vVtttt^".2S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0000 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR64[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR64[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR64[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtttt_VPR64[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR64[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR64[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR64[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtttt_VPR64[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0c400000/mask=xbffff000
+# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0cc00000/mask=xbfe0f000
+# CONSTRUCT x4c400000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.16B, Vt2.16B, Vt3.16B, Vt4.16B}, [Xn|SP] [, wback]
+
+:ld4 {vVt^".16B", vVtt^".16B", vVttt^".16B", vVtttt^".16B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0000 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0c400000/mask=xbffff000
+# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0cc00000/mask=xbfe0f000
+# CONSTRUCT x4c400400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.8H, Vt2.8H, Vt3.8H, Vt4.8H}, [Xn|SP] [, wback]
+
+:ld4 {vVt^".8H", vVtt^".8H", vVttt^".8H", vVtttt^".8H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0000 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0c400000/mask=xbffff000
+# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0cc00000/mask=xbfe0f000
+# CONSTRUCT x4c400800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.4S, Vt2.4S, Vt3.4S, Vt4.4S}, [Xn|SP] [, wback]
+
+:ld4 {vVt^".4S", vVtt^".4S", vVttt^".4S", vVtttt^".4S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0000 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtttt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtttt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtttt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtttt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0c400000/mask=xbffff000
+# C7.2.186 LD4 (multiple structures) page C7-2446 line 143128 MATCH x0cc00000/mask=xbfe0f000
+# CONSTRUCT x4c400c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.2D, Vt2.2D, Vt3.2D, Vt4.2D}, [Xn|SP] [, wback]
+
+:ld4 {vVt^".2D", vVtt^".2D", vVttt^".2D", vVtttt^".2D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=1 & b_21=0 & b_1215=0b0000 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rttt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtttt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rttt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtttt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x0d602000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[0], [Xn|SP] [, wback]
+
+:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[0,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x0d602400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[1], [Xn|SP] [, wback]
+
+:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[8,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x0d602800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[2], [Xn|SP] [, wback]
+
+:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[2], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[16,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x0d602c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[3], [Xn|SP] [, wback]
+
+:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[3], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[24,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x0d603000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[4], [Xn|SP] [, wback]
+
+:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[4], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[32,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x0d603400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[5], [Xn|SP] [, wback]
+
+:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[5], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[40,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x0d603800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[6], [Xn|SP] [, wback]
+
+:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[6], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[48,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x0d603c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[7], [Xn|SP] [, wback]
+
+:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[7], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[56,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x4d602000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[8], [Xn|SP] [, wback]
+
+:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[8], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[64,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x4d602400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[9], [Xn|SP] [, wback]
+
+:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[9], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[72,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x4d602800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[10], [Xn|SP] [, wback]
+
+:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[10], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[80,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x4d602c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[11], [Xn|SP] [, wback]
+
+:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[11], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[88,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x4d603000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[12], [Xn|SP] [, wback]
+
+:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[12], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[96,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x4d603400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[13], [Xn|SP] [, wback]
+
+:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[13], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[104,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x4d603800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[14], [Xn|SP] [, wback]
+
+:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[14], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[112,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x4d603c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[15], [Xn|SP] [, wback]
+
+:ld4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[15], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rttt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ Rtttt_VPR128[120,8] = *:1 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x0d606000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[0], [Xn|SP] [, wback]
+
+:ld4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b011 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR128[0,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x0d606800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[1], [Xn|SP] [, wback]
+
+:ld4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b011 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR128[16,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x0d607000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[2], [Xn|SP] [, wback]
+
+:ld4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[2], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b011 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR128[32,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x0d607800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[3], [Xn|SP] [, wback]
+
+:ld4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[3], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b011 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR128[48,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x4d606000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[4], [Xn|SP] [, wback]
+
+:ld4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[4], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b011 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR128[64,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x4d606800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[5], [Xn|SP] [, wback]
+
+:ld4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[5], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b011 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR128[80,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x4d607000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[6], [Xn|SP] [, wback]
+
+:ld4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[6], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b011 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR128[96,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x4d607800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[7], [Xn|SP] [, wback]
+
+:ld4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[7], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b011 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rttt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ Rtttt_VPR128[112,16] = *:2 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x0d60a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.S, Vt2.S, Vt3.S, Vt4.S}[0], [Xn|SP] [, wback]
+
+:ld4 {vVt^".S", vVtt^".S", vVttt^".S", vVtttt^".S"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b101 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtttt_VPR128[0,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x0d60b000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.S, Vt2.S, Vt3.S, Vt4.S}[1], [Xn|SP] [, wback]
+
+:ld4 {vVt^".S", vVtt^".S", vVttt^".S", vVtttt^".S"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b101 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtttt_VPR128[32,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x4d60a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.S, Vt2.S, Vt3.S, Vt4.S}[2], [Xn|SP] [, wback]
+
+:ld4 {vVt^".S", vVtt^".S", vVttt^".S", vVtttt^".S"}[2], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b101 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtttt_VPR128[64,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x4d60b000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.S, Vt2.S, Vt3.S, Vt4.S}[3], [Xn|SP] [, wback]
+
+:ld4 {vVt^".S", vVtt^".S", vVttt^".S", vVtttt^".S"}[3], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b101 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rttt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ Rtttt_VPR128[96,32] = *:4 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x0d60a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.D, Vt2.D, Vt3.D, Vt4.D}[0], [Xn|SP] [, wback]
+
+:ld4 {vVt^".D", vVtt^".D", vVttt^".D", vVtttt^".D"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b101 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rttt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtttt_VPR128[0,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x4d60a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# ld4 {Vt.D, Vt2.D, Vt3.D, Vt4.D}[1], [Xn|SP] [, wback]
+
+:ld4 {vVt^".D", vVtt^".D", vVttt^".D", vVtttt^".D"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b101 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ Rt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rttt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ Rtttt_VPR128[64,64] = *:8 tmp_ldXn;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0d60e000/mask=xbffff000
+# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0de0e000/mask=xbfe0f000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x0d60e000/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld4r {Vt.8B, Vt2.8B, Vt3.8B, Vt4.8B}, [Xn|SP] [, wback]
+
+:ld4r {vVt^".8B", vVtt^".8B", vVttt^".8B", vVtttt^".8B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b111 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:1 = 0;
+ tmpv = *:1 tmp_ldXn;
+ Rtttt_VPR64[0,8] = tmpv;
+ Rtttt_VPR64[8,8] = tmpv;
+ Rtttt_VPR64[16,8] = tmpv;
+ Rtttt_VPR64[24,8] = tmpv;
+ Rtttt_VPR64[32,8] = tmpv;
+ Rtttt_VPR64[40,8] = tmpv;
+ Rtttt_VPR64[48,8] = tmpv;
+ Rtttt_VPR64[56,8] = tmpv;
+ tmp_ldXn = tmp_ldXn + 1;
+ tmpv = *:1 tmp_ldXn;
+ Rtttt_VPR64[0,8] = tmpv;
+ Rtttt_VPR64[8,8] = tmpv;
+ Rtttt_VPR64[16,8] = tmpv;
+ Rtttt_VPR64[24,8] = tmpv;
+ Rtttt_VPR64[32,8] = tmpv;
+ Rtttt_VPR64[40,8] = tmpv;
+ Rtttt_VPR64[48,8] = tmpv;
+ Rtttt_VPR64[56,8] = tmpv;
+ tmp_ldXn = tmp_ldXn + 1;
+ tmpv = *:1 tmp_ldXn;
+ Rtttt_VPR64[0,8] = tmpv;
+ Rtttt_VPR64[8,8] = tmpv;
+ Rtttt_VPR64[16,8] = tmpv;
+ Rtttt_VPR64[24,8] = tmpv;
+ Rtttt_VPR64[32,8] = tmpv;
+ Rtttt_VPR64[40,8] = tmpv;
+ Rtttt_VPR64[48,8] = tmpv;
+ Rtttt_VPR64[56,8] = tmpv;
+ tmp_ldXn = tmp_ldXn + 1;
+ tmpv = *:1 tmp_ldXn;
+ Rtttt_VPR64[0,8] = tmpv;
+ Rtttt_VPR64[8,8] = tmpv;
+ Rtttt_VPR64[16,8] = tmpv;
+ Rtttt_VPR64[24,8] = tmpv;
+ Rtttt_VPR64[32,8] = tmpv;
+ Rtttt_VPR64[40,8] = tmpv;
+ Rtttt_VPR64[48,8] = tmpv;
+ Rtttt_VPR64[56,8] = tmpv;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0d60e000/mask=xbffff000
+# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0de0e000/mask=xbfe0f000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x0d60e400/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld4r {Vt.4H, Vt2.4H, Vt3.4H, Vt4.4H}, [Xn|SP] [, wback]
+
+:ld4r {vVt^".4H", vVtt^".4H", vVttt^".4H", vVtttt^".4H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b111 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:2 = 0;
+ tmpv = *:2 tmp_ldXn;
+ Rtttt_VPR64[0,16] = tmpv;
+ Rtttt_VPR64[16,16] = tmpv;
+ Rtttt_VPR64[32,16] = tmpv;
+ Rtttt_VPR64[48,16] = tmpv;
+ tmp_ldXn = tmp_ldXn + 2;
+ tmpv = *:2 tmp_ldXn;
+ Rtttt_VPR64[0,16] = tmpv;
+ Rtttt_VPR64[16,16] = tmpv;
+ Rtttt_VPR64[32,16] = tmpv;
+ Rtttt_VPR64[48,16] = tmpv;
+ tmp_ldXn = tmp_ldXn + 2;
+ tmpv = *:2 tmp_ldXn;
+ Rtttt_VPR64[0,16] = tmpv;
+ Rtttt_VPR64[16,16] = tmpv;
+ Rtttt_VPR64[32,16] = tmpv;
+ Rtttt_VPR64[48,16] = tmpv;
+ tmp_ldXn = tmp_ldXn + 2;
+ tmpv = *:2 tmp_ldXn;
+ Rtttt_VPR64[0,16] = tmpv;
+ Rtttt_VPR64[16,16] = tmpv;
+ Rtttt_VPR64[32,16] = tmpv;
+ Rtttt_VPR64[48,16] = tmpv;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0d60e000/mask=xbffff000
+# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0de0e000/mask=xbfe0f000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x0d60e800/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld4r {Vt.2S, Vt2.2S, Vt3.2S, Vt4.2S}, [Xn|SP] [, wback]
+
+:ld4r {vVt^".2S", vVtt^".2S", vVttt^".2S", vVtttt^".2S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b111 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:4 = 0;
+ tmpv = *:4 tmp_ldXn;
+ Rtttt_VPR64[0,32] = tmpv;
+ Rtttt_VPR64[32,32] = tmpv;
+ tmp_ldXn = tmp_ldXn + 4;
+ tmpv = *:4 tmp_ldXn;
+ Rtttt_VPR64[0,32] = tmpv;
+ Rtttt_VPR64[32,32] = tmpv;
+ tmp_ldXn = tmp_ldXn + 4;
+ tmpv = *:4 tmp_ldXn;
+ Rtttt_VPR64[0,32] = tmpv;
+ Rtttt_VPR64[32,32] = tmpv;
+ tmp_ldXn = tmp_ldXn + 4;
+ tmpv = *:4 tmp_ldXn;
+ Rtttt_VPR64[0,32] = tmpv;
+ Rtttt_VPR64[32,32] = tmpv;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0d60e000/mask=xbffff000
+# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0de0e000/mask=xbfe0f000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x0d60ec00/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld4r {Vt.1D, Vt2.1D, Vt3.1D, Vt4.1D}, [Xn|SP] [, wback]
+
+:ld4r {vVt^".1D", vVtt^".1D", vVttt^".1D", vVtttt^".1D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b111 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR64 & Zt & vVtt & Rtt_VPR64 & Ztt & vVttt & Rttt_VPR64 & Zttt & vVtttt & Rtttt_VPR64 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:8 = 0;
+ tmpv = *:8 tmp_ldXn;
+ Rtttt_VPR64[0,64] = tmpv;
+ tmp_ldXn = tmp_ldXn + 8;
+ tmpv = *:8 tmp_ldXn;
+ Rtttt_VPR64[0,64] = tmpv;
+ tmp_ldXn = tmp_ldXn + 8;
+ tmpv = *:8 tmp_ldXn;
+ Rtttt_VPR64[0,64] = tmpv;
+ tmp_ldXn = tmp_ldXn + 8;
+ tmpv = *:8 tmp_ldXn;
+ Rtttt_VPR64[0,64] = tmpv;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0d60e000/mask=xbffff000
+# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0de0e000/mask=xbfe0f000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x4d60e000/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld4r {Vt.16B, Vt2.16B, Vt3.16B, Vt4.16B}, [Xn|SP] [, wback]
+
+:ld4r {vVt^".16B", vVtt^".16B", vVttt^".16B", vVtttt^".16B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b111 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:1 = 0;
+ tmpv = *:1 tmp_ldXn;
+ Rtttt_VPR128[0,8] = tmpv;
+ Rtttt_VPR128[8,8] = tmpv;
+ Rtttt_VPR128[16,8] = tmpv;
+ Rtttt_VPR128[24,8] = tmpv;
+ Rtttt_VPR128[32,8] = tmpv;
+ Rtttt_VPR128[40,8] = tmpv;
+ Rtttt_VPR128[48,8] = tmpv;
+ Rtttt_VPR128[56,8] = tmpv;
+ Rtttt_VPR128[64,8] = tmpv;
+ Rtttt_VPR128[72,8] = tmpv;
+ Rtttt_VPR128[80,8] = tmpv;
+ Rtttt_VPR128[88,8] = tmpv;
+ Rtttt_VPR128[96,8] = tmpv;
+ Rtttt_VPR128[104,8] = tmpv;
+ Rtttt_VPR128[112,8] = tmpv;
+ Rtttt_VPR128[120,8] = tmpv;
+ tmp_ldXn = tmp_ldXn + 1;
+ tmpv = *:1 tmp_ldXn;
+ Rtttt_VPR128[0,8] = tmpv;
+ Rtttt_VPR128[8,8] = tmpv;
+ Rtttt_VPR128[16,8] = tmpv;
+ Rtttt_VPR128[24,8] = tmpv;
+ Rtttt_VPR128[32,8] = tmpv;
+ Rtttt_VPR128[40,8] = tmpv;
+ Rtttt_VPR128[48,8] = tmpv;
+ Rtttt_VPR128[56,8] = tmpv;
+ Rtttt_VPR128[64,8] = tmpv;
+ Rtttt_VPR128[72,8] = tmpv;
+ Rtttt_VPR128[80,8] = tmpv;
+ Rtttt_VPR128[88,8] = tmpv;
+ Rtttt_VPR128[96,8] = tmpv;
+ Rtttt_VPR128[104,8] = tmpv;
+ Rtttt_VPR128[112,8] = tmpv;
+ Rtttt_VPR128[120,8] = tmpv;
+ tmp_ldXn = tmp_ldXn + 1;
+ tmpv = *:1 tmp_ldXn;
+ Rtttt_VPR128[0,8] = tmpv;
+ Rtttt_VPR128[8,8] = tmpv;
+ Rtttt_VPR128[16,8] = tmpv;
+ Rtttt_VPR128[24,8] = tmpv;
+ Rtttt_VPR128[32,8] = tmpv;
+ Rtttt_VPR128[40,8] = tmpv;
+ Rtttt_VPR128[48,8] = tmpv;
+ Rtttt_VPR128[56,8] = tmpv;
+ Rtttt_VPR128[64,8] = tmpv;
+ Rtttt_VPR128[72,8] = tmpv;
+ Rtttt_VPR128[80,8] = tmpv;
+ Rtttt_VPR128[88,8] = tmpv;
+ Rtttt_VPR128[96,8] = tmpv;
+ Rtttt_VPR128[104,8] = tmpv;
+ Rtttt_VPR128[112,8] = tmpv;
+ Rtttt_VPR128[120,8] = tmpv;
+ tmp_ldXn = tmp_ldXn + 1;
+ tmpv = *:1 tmp_ldXn;
+ Rtttt_VPR128[0,8] = tmpv;
+ Rtttt_VPR128[8,8] = tmpv;
+ Rtttt_VPR128[16,8] = tmpv;
+ Rtttt_VPR128[24,8] = tmpv;
+ Rtttt_VPR128[32,8] = tmpv;
+ Rtttt_VPR128[40,8] = tmpv;
+ Rtttt_VPR128[48,8] = tmpv;
+ Rtttt_VPR128[56,8] = tmpv;
+ Rtttt_VPR128[64,8] = tmpv;
+ Rtttt_VPR128[72,8] = tmpv;
+ Rtttt_VPR128[80,8] = tmpv;
+ Rtttt_VPR128[88,8] = tmpv;
+ Rtttt_VPR128[96,8] = tmpv;
+ Rtttt_VPR128[104,8] = tmpv;
+ Rtttt_VPR128[112,8] = tmpv;
+ Rtttt_VPR128[120,8] = tmpv;
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0d60e000/mask=xbffff000
+# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0de0e000/mask=xbfe0f000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x4d60e400/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld4r {Vt.8H, Vt2.8H, Vt3.8H, Vt4.8H}, [Xn|SP] [, wback]
+
+:ld4r {vVt^".8H", vVtt^".8H", vVttt^".8H", vVtttt^".8H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b111 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:2 = 0;
+ tmpv = *:2 tmp_ldXn;
+ Rtttt_VPR128[0,16] = tmpv;
+ Rtttt_VPR128[16,16] = tmpv;
+ Rtttt_VPR128[32,16] = tmpv;
+ Rtttt_VPR128[48,16] = tmpv;
+ Rtttt_VPR128[64,16] = tmpv;
+ Rtttt_VPR128[80,16] = tmpv;
+ Rtttt_VPR128[96,16] = tmpv;
+ Rtttt_VPR128[112,16] = tmpv;
+ tmp_ldXn = tmp_ldXn + 2;
+ tmpv = *:2 tmp_ldXn;
+ Rtttt_VPR128[0,16] = tmpv;
+ Rtttt_VPR128[16,16] = tmpv;
+ Rtttt_VPR128[32,16] = tmpv;
+ Rtttt_VPR128[48,16] = tmpv;
+ Rtttt_VPR128[64,16] = tmpv;
+ Rtttt_VPR128[80,16] = tmpv;
+ Rtttt_VPR128[96,16] = tmpv;
+ Rtttt_VPR128[112,16] = tmpv;
+ tmp_ldXn = tmp_ldXn + 2;
+ tmpv = *:2 tmp_ldXn;
+ Rtttt_VPR128[0,16] = tmpv;
+ Rtttt_VPR128[16,16] = tmpv;
+ Rtttt_VPR128[32,16] = tmpv;
+ Rtttt_VPR128[48,16] = tmpv;
+ Rtttt_VPR128[64,16] = tmpv;
+ Rtttt_VPR128[80,16] = tmpv;
+ Rtttt_VPR128[96,16] = tmpv;
+ Rtttt_VPR128[112,16] = tmpv;
+ tmp_ldXn = tmp_ldXn + 2;
+ tmpv = *:2 tmp_ldXn;
+ Rtttt_VPR128[0,16] = tmpv;
+ Rtttt_VPR128[16,16] = tmpv;
+ Rtttt_VPR128[32,16] = tmpv;
+ Rtttt_VPR128[48,16] = tmpv;
+ Rtttt_VPR128[64,16] = tmpv;
+ Rtttt_VPR128[80,16] = tmpv;
+ Rtttt_VPR128[96,16] = tmpv;
+ Rtttt_VPR128[112,16] = tmpv;
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0d60e000/mask=xbffff000
+# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0de0e000/mask=xbfe0f000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x4d60e800/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld4r {Vt.4S, Vt2.4S, Vt3.4S, Vt4.4S}, [Xn|SP] [, wback]
+
+:ld4r {vVt^".4S", vVtt^".4S", vVttt^".4S", vVtttt^".4S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b111 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:4 = 0;
+ tmpv = *:4 tmp_ldXn;
+ Rtttt_VPR128[0,32] = tmpv;
+ Rtttt_VPR128[32,32] = tmpv;
+ Rtttt_VPR128[64,32] = tmpv;
+ Rtttt_VPR128[96,32] = tmpv;
+ tmp_ldXn = tmp_ldXn + 4;
+ tmpv = *:4 tmp_ldXn;
+ Rtttt_VPR128[0,32] = tmpv;
+ Rtttt_VPR128[32,32] = tmpv;
+ Rtttt_VPR128[64,32] = tmpv;
+ Rtttt_VPR128[96,32] = tmpv;
+ tmp_ldXn = tmp_ldXn + 4;
+ tmpv = *:4 tmp_ldXn;
+ Rtttt_VPR128[0,32] = tmpv;
+ Rtttt_VPR128[32,32] = tmpv;
+ Rtttt_VPR128[64,32] = tmpv;
+ Rtttt_VPR128[96,32] = tmpv;
+ tmp_ldXn = tmp_ldXn + 4;
+ tmpv = *:4 tmp_ldXn;
+ Rtttt_VPR128[0,32] = tmpv;
+ Rtttt_VPR128[32,32] = tmpv;
+ Rtttt_VPR128[64,32] = tmpv;
+ Rtttt_VPR128[96,32] = tmpv;
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0d60e000/mask=xbffff000
+# C7.2.188 LD4R page C7-2453 line 143575 MATCH x0de0e000/mask=xbfe0f000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0d602000/mask=xbfff2000
+# C7.2.187 LD4 (single structure) page C7-2449 line 143314 MATCH x0de02000/mask=xbfe02000
+# CONSTRUCT x4d60ec00/mask=xff60fc00 MATCHED 4 DOCUMENTED OPCODES
+# ld4r {Vt.2D, Vt2.2D, Vt3.2D, Vt4.2D}, [Xn|SP] [, wback]
+
+:ld4r {vVt^".2D", vVtt^".2D", vVttt^".2D", vVtttt^".2D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=1 & b_21=1 & b_1315=0b111 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Zt & vVtt & Rtt_VPR128 & Ztt & vVttt & Rttt_VPR128 & Zttt & vVtttt & Rtttt_VPR128 & Ztttt & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ local tmpv:8 = 0;
+ tmpv = *:8 tmp_ldXn;
+ Rtttt_VPR128[0,64] = tmpv;
+ Rtttt_VPR128[64,64] = tmpv;
+ tmp_ldXn = tmp_ldXn + 8;
+ tmpv = *:8 tmp_ldXn;
+ Rtttt_VPR128[0,64] = tmpv;
+ Rtttt_VPR128[64,64] = tmpv;
+ tmp_ldXn = tmp_ldXn + 8;
+ tmpv = *:8 tmp_ldXn;
+ Rtttt_VPR128[0,64] = tmpv;
+ Rtttt_VPR128[64,64] = tmpv;
+ tmp_ldXn = tmp_ldXn + 8;
+ tmpv = *:8 tmp_ldXn;
+ Rtttt_VPR128[0,64] = tmpv;
+ Rtttt_VPR128[64,64] = tmpv;
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x0c002000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.8B, Vt2.8B, Vt3.8B, Vt4.8B}, [Xn|SP] [, wback]
+
+:st1 {vVt^".8B", vVtt^".8B", vVttt^".8B", vVtttt^".8B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0010 & b_1011=0b00 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & vVtttt & Rtttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR64[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR64[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR64[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR64[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR64[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR64[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR64[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR64[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR64[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x0c002400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.4H, Vt2.4H, Vt3.4H, Vt4.4H}, [Xn|SP] [, wback]
+
+:st1 {vVt^".4H", vVtt^".4H", vVttt^".4H", vVtttt^".4H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0010 & b_1011=0b01 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & vVtttt & Rtttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR64[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR64[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR64[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR64[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR64[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR64[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR64[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR64[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR64[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR64[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR64[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR64[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR64[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR64[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR64[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR64[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x0c002800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.2S, Vt2.2S, Vt3.2S, Vt4.2S}, [Xn|SP] [, wback]
+
+:st1 {vVt^".2S", vVtt^".2S", vVttt^".2S", vVtttt^".2S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0010 & b_1011=0b10 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & vVtttt & Rtttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR64[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR64[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR64[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR64[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR64[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR64[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtttt_VPR64[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtttt_VPR64[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x0c002c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.1D, Vt2.1D, Vt3.1D, Vt4.1D}, [Xn|SP] [, wback]
+
+:st1 {vVt^".1D", vVtt^".1D", vVttt^".1D", vVtttt^".1D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0010 & b_1011=0b11 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & vVtttt & Rtttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:8 tmp_ldXn = Rt_VPR64[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtt_VPR64[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rttt_VPR64[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtttt_VPR64[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x4c002000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.16B, Vt2.16B, Vt3.16B, Vt4.16B}, [Xn|SP] [, wback]
+
+:st1 {vVt^".16B", vVtt^".16B", vVttt^".16B", vVtttt^".16B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0010 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x4c002400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.8H, Vt2.8H, Vt3.8H, Vt4.8H}, [Xn|SP] [, wback]
+
+:st1 {vVt^".8H", vVtt^".8H", vVttt^".8H", vVtttt^".8H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0010 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x4c002800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.4S, Vt2.4S, Vt3.4S, Vt4.4S}, [Xn|SP] [, wback]
+
+:st1 {vVt^".4S", vVtt^".4S", vVttt^".4S", vVtttt^".4S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0010 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtttt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtttt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtttt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtttt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x4c002c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.2D, Vt2.2D, Vt3.2D, Vt4.2D}, [Xn|SP] [, wback]
+
+:st1 {vVt^".2D", vVtt^".2D", vVttt^".2D", vVtttt^".2D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0010 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:8 tmp_ldXn = Rt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rttt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rttt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtttt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtttt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x0c006000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.8B, Vt2.8B, Vt3.8B}, [Xn|SP] [, wback]
+
+:st1 {vVt^".8B", vVtt^".8B", vVttt^".8B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0110 & b_1011=0b00 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR64[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x0c006400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.4H, Vt2.4H, Vt3.4H}, [Xn|SP] [, wback]
+
+:st1 {vVt^".4H", vVtt^".4H", vVttt^".4H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0110 & b_1011=0b01 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR64[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR64[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR64[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR64[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR64[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR64[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR64[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR64[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR64[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR64[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR64[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR64[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x0c006800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.2S, Vt2.2S, Vt3.2S}, [Xn|SP] [, wback]
+
+:st1 {vVt^".2S", vVtt^".2S", vVttt^".2S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0110 & b_1011=0b10 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR64[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR64[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR64[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR64[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR64[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR64[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x0c006c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.1D, Vt2.1D, Vt3.1D}, [Xn|SP] [, wback]
+
+:st1 {vVt^".1D", vVtt^".1D", vVttt^".1D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0110 & b_1011=0b11 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:8 tmp_ldXn = Rt_VPR64[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtt_VPR64[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rttt_VPR64[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x4c006000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.16B, Vt2.16B, Vt3.16B}, [Xn|SP] [, wback]
+
+:st1 {vVt^".16B", vVtt^".16B", vVttt^".16B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0110 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x4c006400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.8H, Vt2.8H, Vt3.8H}, [Xn|SP] [, wback]
+
+:st1 {vVt^".8H", vVtt^".8H", vVttt^".8H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0110 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x4c006800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.4S, Vt2.4S, Vt3.4S}, [Xn|SP] [, wback]
+
+:st1 {vVt^".4S", vVtt^".4S", vVttt^".4S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0110 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x4c006c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.2D, Vt2.2D, Vt3.2D}, [Xn|SP] [, wback]
+
+:st1 {vVt^".2D", vVtt^".2D", vVttt^".2D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0110 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:8 tmp_ldXn = Rt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rttt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rttt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x0c007000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.8B}, [Xn|SP] [, wback]
+
+:st1 {vVt^".8B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0111 & b_1011=0b00 & vVt & Rt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR64[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x0c007400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.4H}, [Xn|SP] [, wback]
+
+:st1 {vVt^".4H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0111 & b_1011=0b01 & vVt & Rt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR64[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR64[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR64[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR64[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x0c007800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.2S}, [Xn|SP] [, wback]
+
+:st1 {vVt^".2S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0111 & b_1011=0b10 & vVt & Rt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR64[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR64[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x0c007c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.1D}, [Xn|SP] [, wback]
+
+:st1 {vVt^".1D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0111 & b_1011=0b11 & vVt & Rt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:8 tmp_ldXn = Rt_VPR64[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x4c007000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.16B}, [Xn|SP] [, wback]
+
+:st1 {vVt^".16B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0111 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x4c007400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.8H}, [Xn|SP] [, wback]
+
+:st1 {vVt^".8H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0111 & b_1011=0b01 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x4c007800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.4S}, [Xn|SP] [, wback]
+
+:st1 {vVt^".4S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0111 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x4c007c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.2D}, [Xn|SP] [, wback]
+
+:st1 {vVt^".2D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0111 & b_1011=0b11 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:8 tmp_ldXn = Rt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x0c00a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.8B, Vt2.8B}, [Xn|SP] [, wback]
+
+:st1 {vVt^".8B", vVtt^".8B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1010 & b_1011=0b00 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR64[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x0c00a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.4H, Vt2.4H}, [Xn|SP] [, wback]
+
+:st1 {vVt^".4H", vVtt^".4H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1010 & b_1011=0b01 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR64[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR64[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR64[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR64[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR64[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR64[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR64[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR64[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x0c00a800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.2S, Vt2.2S}, [Xn|SP] [, wback]
+
+:st1 {vVt^".2S", vVtt^".2S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1010 & b_1011=0b10 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR64[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR64[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR64[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR64[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x0c00ac00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.1D, Vt2.1D}, [Xn|SP] [, wback]
+
+:st1 {vVt^".1D", vVtt^".1D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1010 & b_1011=0b11 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:8 tmp_ldXn = Rt_VPR64[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtt_VPR64[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x4c00a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.16B, Vt2.16B}, [Xn|SP] [, wback]
+
+:st1 {vVt^".16B", vVtt^".16B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1010 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x4c00a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.8H, Vt2.8H}, [Xn|SP] [, wback]
+
+:st1 {vVt^".8H", vVtt^".8H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1010 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x4c00a800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.4S, Vt2.4S}, [Xn|SP] [, wback]
+
+:st1 {vVt^".4S", vVtt^".4S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1010 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c002000/mask=xbfff2000
+# C7.2.321 ST1 (multiple structures) page C7-2748 line 160331 MATCH x0c802000/mask=xbfe02000
+# CONSTRUCT x4c00ac00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.2D, Vt2.2D}, [Xn|SP] [, wback]
+
+:st1 {vVt^".2D", vVtt^".2D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1010 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:8 tmp_ldXn = Rt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x0d000000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.B}[0], [Xn|SP] [, wback]
+
+:st1 {vVt^".B"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x0d000400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.B}[1], [Xn|SP] [, wback]
+
+:st1 {vVt^".B"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x0d000800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.B}[2], [Xn|SP] [, wback]
+
+:st1 {vVt^".B"}[2], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x0d000c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.B}[3], [Xn|SP] [, wback]
+
+:st1 {vVt^".B"}[3], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x0d001000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.B}[4], [Xn|SP] [, wback]
+
+:st1 {vVt^".B"}[4], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x0d001400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.B}[5], [Xn|SP] [, wback]
+
+:st1 {vVt^".B"}[5], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x0d001800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.B}[6], [Xn|SP] [, wback]
+
+:st1 {vVt^".B"}[6], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x0d001c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.B}[7], [Xn|SP] [, wback]
+
+:st1 {vVt^".B"}[7], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x4d000000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.B}[8], [Xn|SP] [, wback]
+
+:st1 {vVt^".B"}[8], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x4d000400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.B}[9], [Xn|SP] [, wback]
+
+:st1 {vVt^".B"}[9], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x4d000800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.B}[10], [Xn|SP] [, wback]
+
+:st1 {vVt^".B"}[10], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x4d000c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.B}[11], [Xn|SP] [, wback]
+
+:st1 {vVt^".B"}[11], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x4d001000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.B}[12], [Xn|SP] [, wback]
+
+:st1 {vVt^".B"}[12], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x4d001400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.B}[13], [Xn|SP] [, wback]
+
+:st1 {vVt^".B"}[13], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x4d001800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.B}[14], [Xn|SP] [, wback]
+
+:st1 {vVt^".B"}[14], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x4d001c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.B}[15], [Xn|SP] [, wback]
+
+:st1 {vVt^".B"}[15], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b000 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x0d004000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.H}[0], [Xn|SP] [, wback]
+
+:st1 {vVt^".H"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b010 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x0d004800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.H}[1], [Xn|SP] [, wback]
+
+:st1 {vVt^".H"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b010 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x0d005000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.H}[2], [Xn|SP] [, wback]
+
+:st1 {vVt^".H"}[2], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b010 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x0d005800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.H}[3], [Xn|SP] [, wback]
+
+:st1 {vVt^".H"}[3], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b010 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x4d004000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.H}[4], [Xn|SP] [, wback]
+
+:st1 {vVt^".H"}[4], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b010 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x4d004800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.H}[5], [Xn|SP] [, wback]
+
+:st1 {vVt^".H"}[5], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b010 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x4d005000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.H}[6], [Xn|SP] [, wback]
+
+:st1 {vVt^".H"}[6], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b010 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x4d005800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.H}[7], [Xn|SP] [, wback]
+
+:st1 {vVt^".H"}[7], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b010 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x0d008000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.S}[0], [Xn|SP] [, wback]
+
+:st1 {vVt^".S"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b100 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x0d009000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.S}[1], [Xn|SP] [, wback]
+
+:st1 {vVt^".S"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b100 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x4d008000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.S}[2], [Xn|SP] [, wback]
+
+:st1 {vVt^".S"}[2], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b100 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x4d009000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.S}[3], [Xn|SP] [, wback]
+
+:st1 {vVt^".S"}[3], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b100 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x0d008400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.D}[0], [Xn|SP] [, wback]
+
+:st1 {vVt^".D"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b100 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:8 tmp_ldXn = Rt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d000000/mask=xbfff2000
+# C7.2.322 ST1 (single structure) page C7-2752 line 160596 MATCH x0d800000/mask=xbfe02000
+# CONSTRUCT x4d008400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st1 {Vt.D}[1], [Xn|SP] [, wback]
+
+:st1 {vVt^".D"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b100 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:8 tmp_ldXn = Rt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c008000/mask=xbffff000
+# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c808000/mask=xbfe0f000
+# CONSTRUCT x0c008000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.8B, Vt2.8B}, [Xn|SP] [, wback]
+
+:st2 {vVt^".8B", vVtt^".8B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1000 & b_1011=0b00 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR64[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c008000/mask=xbffff000
+# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c808000/mask=xbfe0f000
+# CONSTRUCT x0c008400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.4H, Vt2.4H}, [Xn|SP] [, wback]
+
+:st2 {vVt^".4H", vVtt^".4H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1000 & b_1011=0b01 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR64[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR64[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR64[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR64[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR64[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR64[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR64[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR64[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c008000/mask=xbffff000
+# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c808000/mask=xbfe0f000
+# CONSTRUCT x0c008800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.2S, Vt2.2S}, [Xn|SP] [, wback]
+
+:st2 {vVt^".2S", vVtt^".2S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1000 & b_1011=0b10 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR64[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR64[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR64[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR64[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c008000/mask=xbffff000
+# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c808000/mask=xbfe0f000
+# CONSTRUCT x4c008000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.16B, Vt2.16B}, [Xn|SP] [, wback]
+
+:st2 {vVt^".16B", vVtt^".16B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1000 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c008000/mask=xbffff000
+# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c808000/mask=xbfe0f000
+# CONSTRUCT x4c008400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.8H, Vt2.8H}, [Xn|SP] [, wback]
+
+:st2 {vVt^".8H", vVtt^".8H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1000 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c008000/mask=xbffff000
+# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c808000/mask=xbfe0f000
+# CONSTRUCT x4c008800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.4S, Vt2.4S}, [Xn|SP] [, wback]
+
+:st2 {vVt^".4S", vVtt^".4S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1000 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c008000/mask=xbffff000
+# C7.2.323 ST2 (multiple structures) page C7-2756 line 160848 MATCH x0c808000/mask=xbfe0f000
+# CONSTRUCT x4c008c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.2D, Vt2.2D}, [Xn|SP] [, wback]
+
+:st2 {vVt^".2D", vVtt^".2D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b1000 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:8 tmp_ldXn = Rt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x0d200000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.B, Vt2.B}[0], [Xn|SP] [, wback]
+
+:st2 {vVt^".B", vVtt^".B"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x0d200400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.B, Vt2.B}[1], [Xn|SP] [, wback]
+
+:st2 {vVt^".B", vVtt^".B"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x0d200800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.B, Vt2.B}[2], [Xn|SP] [, wback]
+
+:st2 {vVt^".B", vVtt^".B"}[2], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x0d200c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.B, Vt2.B}[3], [Xn|SP] [, wback]
+
+:st2 {vVt^".B", vVtt^".B"}[3], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x0d201000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.B, Vt2.B}[4], [Xn|SP] [, wback]
+
+:st2 {vVt^".B", vVtt^".B"}[4], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x0d201400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.B, Vt2.B}[5], [Xn|SP] [, wback]
+
+:st2 {vVt^".B", vVtt^".B"}[5], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x0d201800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.B, Vt2.B}[6], [Xn|SP] [, wback]
+
+:st2 {vVt^".B", vVtt^".B"}[6], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x0d201c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.B, Vt2.B}[7], [Xn|SP] [, wback]
+
+:st2 {vVt^".B", vVtt^".B"}[7], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x4d200000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.B, Vt2.B}[8], [Xn|SP] [, wback]
+
+:st2 {vVt^".B", vVtt^".B"}[8], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x4d200400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.B, Vt2.B}[9], [Xn|SP] [, wback]
+
+:st2 {vVt^".B", vVtt^".B"}[9], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x4d200800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.B, Vt2.B}[10], [Xn|SP] [, wback]
+
+:st2 {vVt^".B", vVtt^".B"}[10], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x4d200c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.B, Vt2.B}[11], [Xn|SP] [, wback]
+
+:st2 {vVt^".B", vVtt^".B"}[11], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x4d201000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.B, Vt2.B}[12], [Xn|SP] [, wback]
+
+:st2 {vVt^".B", vVtt^".B"}[12], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x4d201400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.B, Vt2.B}[13], [Xn|SP] [, wback]
+
+:st2 {vVt^".B", vVtt^".B"}[13], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x4d201800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.B, Vt2.B}[14], [Xn|SP] [, wback]
+
+:st2 {vVt^".B", vVtt^".B"}[14], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x4d201c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.B, Vt2.B}[15], [Xn|SP] [, wback]
+
+:st2 {vVt^".B", vVtt^".B"}[15], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b000 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x0d204000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.H, Vt2.H}[0], [Xn|SP] [, wback]
+
+:st2 {vVt^".H", vVtt^".H"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b010 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x0d204800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.H, Vt2.H}[1], [Xn|SP] [, wback]
+
+:st2 {vVt^".H", vVtt^".H"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b010 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x0d205000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.H, Vt2.H}[2], [Xn|SP] [, wback]
+
+:st2 {vVt^".H", vVtt^".H"}[2], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b010 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x0d205800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.H, Vt2.H}[3], [Xn|SP] [, wback]
+
+:st2 {vVt^".H", vVtt^".H"}[3], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b010 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x4d204000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.H, Vt2.H}[4], [Xn|SP] [, wback]
+
+:st2 {vVt^".H", vVtt^".H"}[4], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b010 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x4d204800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.H, Vt2.H}[5], [Xn|SP] [, wback]
+
+:st2 {vVt^".H", vVtt^".H"}[5], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b010 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x4d205000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.H, Vt2.H}[6], [Xn|SP] [, wback]
+
+:st2 {vVt^".H", vVtt^".H"}[6], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b010 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x4d205800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.H, Vt2.H}[7], [Xn|SP] [, wback]
+
+:st2 {vVt^".H", vVtt^".H"}[7], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b010 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x0d208000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.S, Vt2.S}[0], [Xn|SP] [, wback]
+
+:st2 {vVt^".S", vVtt^".S"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b100 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x0d209000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.S, Vt2.S}[1], [Xn|SP] [, wback]
+
+:st2 {vVt^".S", vVtt^".S"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b100 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x4d208000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.S, Vt2.S}[2], [Xn|SP] [, wback]
+
+:st2 {vVt^".S", vVtt^".S"}[2], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b100 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x4d209000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.S, Vt2.S}[3], [Xn|SP] [, wback]
+
+:st2 {vVt^".S", vVtt^".S"}[3], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b100 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x0d208400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.D, Vt2.D}[0], [Xn|SP] [, wback]
+
+:st2 {vVt^".D", vVtt^".D"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b100 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:8 tmp_ldXn = Rt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0d200000/mask=xbfff2000
+# C7.2.324 ST2 (single structure) page C7-2759 line 161029 MATCH x0da00000/mask=xbfe02000
+# CONSTRUCT x4d208400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st2 {Vt.D, Vt2.D}[1], [Xn|SP] [, wback]
+
+:st2 {vVt^".D", vVtt^".D"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b100 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:8 tmp_ldXn = Rt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c004000/mask=xbffff000
+# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c804000/mask=xbfe0f000
+# CONSTRUCT x0c004000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.8B, Vt2.8B, Vt3.8B}, [Xn|SP] [, wback]
+
+:st3 {vVt^".8B", vVtt^".8B", vVttt^".8B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0100 & b_1011=0b00 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR64[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c004000/mask=xbffff000
+# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c804000/mask=xbfe0f000
+# CONSTRUCT x0c004400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.4H, Vt2.4H, Vt3.4H}, [Xn|SP] [, wback]
+
+:st3 {vVt^".4H", vVtt^".4H", vVttt^".4H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0100 & b_1011=0b01 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR64[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR64[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR64[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR64[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR64[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR64[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR64[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR64[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR64[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR64[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR64[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR64[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c004000/mask=xbffff000
+# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c804000/mask=xbfe0f000
+# CONSTRUCT x0c004800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.2S, Vt2.2S, Vt3.2S}, [Xn|SP] [, wback]
+
+:st3 {vVt^".2S", vVtt^".2S", vVttt^".2S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0100 & b_1011=0b10 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR64[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR64[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR64[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR64[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR64[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR64[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c004000/mask=xbffff000
+# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c804000/mask=xbfe0f000
+# CONSTRUCT x4c004000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.16B, Vt2.16B, Vt3.16B}, [Xn|SP] [, wback]
+
+:st3 {vVt^".16B", vVtt^".16B", vVttt^".16B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0100 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c004000/mask=xbffff000
+# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c804000/mask=xbfe0f000
+# CONSTRUCT x4c004400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.8H, Vt2.8H, Vt3.8H}, [Xn|SP] [, wback]
+
+:st3 {vVt^".8H", vVtt^".8H", vVttt^".8H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0100 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c004000/mask=xbffff000
+# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c804000/mask=xbfe0f000
+# CONSTRUCT x4c004800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.4S, Vt2.4S, Vt3.4S}, [Xn|SP] [, wback]
+
+:st3 {vVt^".4S", vVtt^".4S", vVttt^".4S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0100 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c004000/mask=xbffff000
+# C7.2.325 ST3 (multiple structures) page C7-2763 line 161283 MATCH x0c804000/mask=xbfe0f000
+# CONSTRUCT x4c004c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.2D, Vt2.2D, Vt3.2D}, [Xn|SP] [, wback]
+
+:st3 {vVt^".2D", vVtt^".2D", vVttt^".2D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0100 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:8 tmp_ldXn = Rt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rttt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rttt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x0d002000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.B, Vt2.B, Vt3.B}[0], [Xn|SP] [, wback]
+
+:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x0d002400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.B, Vt2.B, Vt3.B}[1], [Xn|SP] [, wback]
+
+:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x0d002800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.B, Vt2.B, Vt3.B}[2], [Xn|SP] [, wback]
+
+:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[2], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x0d002c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.B, Vt2.B, Vt3.B}[3], [Xn|SP] [, wback]
+
+:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[3], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x0d003000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.B, Vt2.B, Vt3.B}[4], [Xn|SP] [, wback]
+
+:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[4], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x0d003400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.B, Vt2.B, Vt3.B}[5], [Xn|SP] [, wback]
+
+:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[5], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x0d003800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.B, Vt2.B, Vt3.B}[6], [Xn|SP] [, wback]
+
+:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[6], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x0d003c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.B, Vt2.B, Vt3.B}[7], [Xn|SP] [, wback]
+
+:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[7], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x4d002000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.B, Vt2.B, Vt3.B}[8], [Xn|SP] [, wback]
+
+:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[8], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x4d002400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.B, Vt2.B, Vt3.B}[9], [Xn|SP] [, wback]
+
+:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[9], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x4d002800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.B, Vt2.B, Vt3.B}[10], [Xn|SP] [, wback]
+
+:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[10], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x4d002c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.B, Vt2.B, Vt3.B}[11], [Xn|SP] [, wback]
+
+:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[11], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x4d003000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.B, Vt2.B, Vt3.B}[12], [Xn|SP] [, wback]
+
+:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[12], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x4d003400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.B, Vt2.B, Vt3.B}[13], [Xn|SP] [, wback]
+
+:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[13], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x4d003800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.B, Vt2.B, Vt3.B}[14], [Xn|SP] [, wback]
+
+:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[14], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x4d003c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.B, Vt2.B, Vt3.B}[15], [Xn|SP] [, wback]
+
+:st3 {vVt^".B", vVtt^".B", vVttt^".B"}[15], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b001 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x0d006000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.H, Vt2.H, Vt3.H}[0], [Xn|SP] [, wback]
+
+:st3 {vVt^".H", vVtt^".H", vVttt^".H"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b011 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x0d006800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.H, Vt2.H, Vt3.H}[1], [Xn|SP] [, wback]
+
+:st3 {vVt^".H", vVtt^".H", vVttt^".H"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b011 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x0d007000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.H, Vt2.H, Vt3.H}[2], [Xn|SP] [, wback]
+
+:st3 {vVt^".H", vVtt^".H", vVttt^".H"}[2], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b011 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x0d007800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.H, Vt2.H, Vt3.H}[3], [Xn|SP] [, wback]
+
+:st3 {vVt^".H", vVtt^".H", vVttt^".H"}[3], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b011 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x4d006000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.H, Vt2.H, Vt3.H}[4], [Xn|SP] [, wback]
+
+:st3 {vVt^".H", vVtt^".H", vVttt^".H"}[4], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b011 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x4d006800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.H, Vt2.H, Vt3.H}[5], [Xn|SP] [, wback]
+
+:st3 {vVt^".H", vVtt^".H", vVttt^".H"}[5], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b011 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x4d007000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.H, Vt2.H, Vt3.H}[6], [Xn|SP] [, wback]
+
+:st3 {vVt^".H", vVtt^".H", vVttt^".H"}[6], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b011 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x4d007800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.H, Vt2.H, Vt3.H}[7], [Xn|SP] [, wback]
+
+:st3 {vVt^".H", vVtt^".H", vVttt^".H"}[7], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b011 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x0d00a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.S, Vt2.S, Vt3.S}[0], [Xn|SP] [, wback]
+
+:st3 {vVt^".S", vVtt^".S", vVttt^".S"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b101 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x0d00b000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.S, Vt2.S, Vt3.S}[1], [Xn|SP] [, wback]
+
+:st3 {vVt^".S", vVtt^".S", vVttt^".S"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b101 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x4d00a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.S, Vt2.S, Vt3.S}[2], [Xn|SP] [, wback]
+
+:st3 {vVt^".S", vVtt^".S", vVttt^".S"}[2], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b101 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x4d00b000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.S, Vt2.S, Vt3.S}[3], [Xn|SP] [, wback]
+
+:st3 {vVt^".S", vVtt^".S", vVttt^".S"}[3], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b101 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x0d00a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.D, Vt2.D, Vt3.D}[0], [Xn|SP] [, wback]
+
+:st3 {vVt^".D", vVtt^".D", vVttt^".D"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b101 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:8 tmp_ldXn = Rt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rttt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d002000/mask=xbfff2000
+# C7.2.326 ST3 (single structure) page C7-2766 line 161466 MATCH x0d802000/mask=xbfe02000
+# CONSTRUCT x4d00a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st3 {Vt.D, Vt2.D, Vt3.D}[1], [Xn|SP] [, wback]
+
+:st3 {vVt^".D", vVtt^".D", vVttt^".D"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=0 & b_1315=0b101 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:8 tmp_ldXn = Rt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rttt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c000000/mask=xbffff000
+# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c800000/mask=xbfe0f000
+# CONSTRUCT x0c000000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.8B, Vt2.8B, Vt3.8B, Vt4.8B}, [Xn|SP] [, wback]
+
+:st4 {vVt^".8B", vVtt^".8B", vVttt^".8B", vVtttt^".8B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0000 & b_1011=0b00 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & vVtttt & Rtttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR64[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR64[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR64[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR64[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR64[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR64[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR64[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR64[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR64[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR64[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR64[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR64[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c000000/mask=xbffff000
+# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c800000/mask=xbfe0f000
+# CONSTRUCT x0c000400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.4H, Vt2.4H, Vt3.4H, Vt4.4H}, [Xn|SP] [, wback]
+
+:st4 {vVt^".4H", vVtt^".4H", vVttt^".4H", vVtttt^".4H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0000 & b_1011=0b01 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & vVtttt & Rtttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR64[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR64[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR64[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR64[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR64[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR64[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR64[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR64[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR64[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR64[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR64[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR64[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR64[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR64[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR64[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR64[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c000000/mask=xbffff000
+# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c800000/mask=xbfe0f000
+# CONSTRUCT x0c000800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.2S, Vt2.2S, Vt3.2S, Vt4.2S}, [Xn|SP] [, wback]
+
+:st4 {vVt^".2S", vVtt^".2S", vVttt^".2S", vVtttt^".2S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0000 & b_1011=0b10 & vVt & Rt_VPR64 & vVtt & Rtt_VPR64 & vVttt & Rttt_VPR64 & vVtttt & Rtttt_VPR64 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR64[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR64[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR64[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtttt_VPR64[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR64[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR64[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR64[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtttt_VPR64[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c000000/mask=xbffff000
+# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c800000/mask=xbfe0f000
+# CONSTRUCT x4c000000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.16B, Vt2.16B, Vt3.16B, Vt4.16B}, [Xn|SP] [, wback]
+
+:st4 {vVt^".16B", vVtt^".16B", vVttt^".16B", vVtttt^".16B"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0000 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c000000/mask=xbffff000
+# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c800000/mask=xbfe0f000
+# CONSTRUCT x4c000400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.8H, Vt2.8H, Vt3.8H, Vt4.8H}, [Xn|SP] [, wback]
+
+:st4 {vVt^".8H", vVtt^".8H", vVttt^".8H", vVtttt^".8H"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0000 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c000000/mask=xbffff000
+# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c800000/mask=xbfe0f000
+# CONSTRUCT x4c000800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.4S, Vt2.4S, Vt3.4S, Vt4.4S}, [Xn|SP] [, wback]
+
+:st4 {vVt^".4S", vVtt^".4S", vVttt^".4S", vVtttt^".4S"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0000 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtttt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtttt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtttt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtttt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c000000/mask=xbffff000
+# C7.2.327 ST4 (multiple structures) page C7-2770 line 161722 MATCH x0c800000/mask=xbfe0f000
+# CONSTRUCT x4c000c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.2D, Vt2.2D, Vt3.2D, Vt4.2D}, [Xn|SP] [, wback]
+
+:st4 {vVt^".2D", vVtt^".2D", vVttt^".2D", vVtttt^".2D"}, [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001100 & b_22=0 & b_21=0 & b_1215=0b0000 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:8 tmp_ldXn = Rt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rttt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtttt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rttt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtttt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x0d202000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[0], [Xn|SP] [, wback]
+
+:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[0,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x0d202400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[1], [Xn|SP] [, wback]
+
+:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[8,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x0d202800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[2], [Xn|SP] [, wback]
+
+:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[2], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[16,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x0d202c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[3], [Xn|SP] [, wback]
+
+:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[3], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[24,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x0d203000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[4], [Xn|SP] [, wback]
+
+:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[4], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[32,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x0d203400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[5], [Xn|SP] [, wback]
+
+:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[5], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[40,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x0d203800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[6], [Xn|SP] [, wback]
+
+:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[6], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[48,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x0d203c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[7], [Xn|SP] [, wback]
+
+:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[7], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[56,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x4d202000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[8], [Xn|SP] [, wback]
+
+:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[8], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[64,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x4d202400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[9], [Xn|SP] [, wback]
+
+:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[9], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[72,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x4d202800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[10], [Xn|SP] [, wback]
+
+:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[10], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[80,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x4d202c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[11], [Xn|SP] [, wback]
+
+:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[11], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=0 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[88,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x4d203000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[12], [Xn|SP] [, wback]
+
+:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[12], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[96,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x4d203400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[13], [Xn|SP] [, wback]
+
+:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[13], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[104,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x4d203800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[14], [Xn|SP] [, wback]
+
+:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[14], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[112,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x4d203c00/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.B, Vt2.B, Vt3.B, Vt4.B}[15], [Xn|SP] [, wback]
+
+:st4 {vVt^".B", vVtt^".B", vVttt^".B", vVtttt^".B"}[15], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b001 & b_12=1 & b_1011=0b11 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:1 tmp_ldXn = Rt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rttt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ *:1 tmp_ldXn = Rtttt_VPR128[120,8];
+ tmp_ldXn = tmp_ldXn + 1;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x0d206000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[0], [Xn|SP] [, wback]
+
+:st4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b011 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR128[0,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x0d206800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[1], [Xn|SP] [, wback]
+
+:st4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b011 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR128[16,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x0d207000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[2], [Xn|SP] [, wback]
+
+:st4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[2], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b011 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR128[32,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x0d207800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[3], [Xn|SP] [, wback]
+
+:st4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[3], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b011 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR128[48,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x4d206000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[4], [Xn|SP] [, wback]
+
+:st4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[4], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b011 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR128[64,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x4d206800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[5], [Xn|SP] [, wback]
+
+:st4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[5], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b011 & b_12=0 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR128[80,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x4d207000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[6], [Xn|SP] [, wback]
+
+:st4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[6], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b011 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR128[96,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x4d207800/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.H, Vt2.H, Vt3.H, Vt4.H}[7], [Xn|SP] [, wback]
+
+:st4 {vVt^".H", vVtt^".H", vVttt^".H", vVtttt^".H"}[7], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b011 & b_12=1 & b_1011=0b10 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:2 tmp_ldXn = Rt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rttt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ *:2 tmp_ldXn = Rtttt_VPR128[112,16];
+ tmp_ldXn = tmp_ldXn + 2;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x0d20a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.S, Vt2.S, Vt3.S, Vt4.S}[0], [Xn|SP] [, wback]
+
+:st4 {vVt^".S", vVtt^".S", vVttt^".S", vVtttt^".S"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b101 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtttt_VPR128[0,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x0d20b000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.S, Vt2.S, Vt3.S, Vt4.S}[1], [Xn|SP] [, wback]
+
+:st4 {vVt^".S", vVtt^".S", vVttt^".S", vVtttt^".S"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b101 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtttt_VPR128[32,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x4d20a000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.S, Vt2.S, Vt3.S, Vt4.S}[2], [Xn|SP] [, wback]
+
+:st4 {vVt^".S", vVtt^".S", vVttt^".S", vVtttt^".S"}[2], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b101 & b_12=0 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtttt_VPR128[64,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x4d20b000/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.S, Vt2.S, Vt3.S, Vt4.S}[3], [Xn|SP] [, wback]
+
+:st4 {vVt^".S", vVtt^".S", vVttt^".S", vVtttt^".S"}[3], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b101 & b_12=1 & b_1011=0b00 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:4 tmp_ldXn = Rt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rttt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ *:4 tmp_ldXn = Rtttt_VPR128[96,32];
+ tmp_ldXn = tmp_ldXn + 4;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x0d20a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.D, Vt2.D, Vt3.D, Vt4.D}[0], [Xn|SP] [, wback]
+
+:st4 {vVt^".D", vVtt^".D", vVttt^".D", vVtttt^".D"}[0], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=0 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b101 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:8 tmp_ldXn = Rt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rttt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtttt_VPR128[0,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
+
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0d202000/mask=xbfff2000
+# C7.2.328 ST4 (single structure) page C7-2773 line 161907 MATCH x0da02000/mask=xbfe02000
+# CONSTRUCT x4d20a400/mask=xff60fc00 MATCHED 2 DOCUMENTED OPCODES
+# st4 {Vt.D, Vt2.D, Vt3.D, Vt4.D}[1], [Xn|SP] [, wback]
+
+:st4 {vVt^".D", vVtt^".D", vVttt^".D", vVtttt^".D"}[1], [Rn_GPR64xsp]^ldst_wback
+is b_31=0 & b_30=1 & b_2429=0b001101 & b_22=0 & b_21=1 & b_1315=0b101 & b_12=0 & b_1011=0b01 & vVt & Rt_VPR128 & vVtt & Rtt_VPR128 & vVttt & Rttt_VPR128 & vVtttt & Rtttt_VPR128 & Rn_GPR64xsp & ldst_wback & Rm_GPR64
+{
+ tmp_ldXn = Rn_GPR64xsp;
+ *:8 tmp_ldXn = Rt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rttt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ *:8 tmp_ldXn = Rtttt_VPR128[64,64];
+ tmp_ldXn = tmp_ldXn + 8;
+ # neglected zexts
+ build ldst_wback;
+}
diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64neon.sinc b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64neon.sinc
new file mode 100644
index 0000000..58f6137
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64neon.sinc
@@ -0,0 +1,29911 @@
+# C7.2.1 ABS page C7-1009 line 58362 KEEPWITH
+#
+# The semantics in this file are auto-generated with armit.py script
+# in the andre directory (capture output and replace file):
+#
+# python ../../../ProcessorTest/test/andre/scrape/armit.py --arch a64 --sort --refurb --smacro primitive --sinc languages/AARCH64neon.sinc
+#
+# The AUNIT tests are run using the command line options from the
+# comment with the python script aunit.py in the cunit directory:
+#
+# (cd ../../../ProcessorTest/test/cunit; python aunit.py OPTIONS)
+#
+# (aunit.py may require a local copy of a current andre exhaust).
+
+# C7.2.1 ABS page C7-2017 line 117868 MATCH x5e20b800/mask=xff3ffc00
+# CONSTRUCT x5ee0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =abs
+# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1
+# AUNIT --inst x5ee0b800/mask=xfffffc00 --status pass
+# ABS Scalar
+
+:abs Rd_FPR64, Rn_FPR64
+is b_2431=0b01011110 & b_2223=0b11 & b_1021=0b100000101110 & Rd_FPR64 & Rn_FPR64 & Zd
+{
+ Rd_FPR64 = MP_INT_ABS(Rn_FPR64);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.1 ABS page C7-2017 line 117868 MATCH x0e20b800/mask=xbf3ffc00
+# CONSTRUCT x0e20b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$abs@1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@1
+# AUNIT --inst x0e20b800/mask=xfffffc00 --status pass
+# ABS Vector 8B when size = 00 , Q = 0
+
+:abs Rd_VPR64.8B, Rn_VPR64.8B
+is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000101110 & Rd_VPR64.8B & Rn_VPR64.8B & Zd
+{
+ # simd unary Rd_VPR64.8B = MP_INT_ABS(Rn_VPR64.8B) on lane size 1
+ Rd_VPR64.8B[0,8] = MP_INT_ABS(Rn_VPR64.8B[0,8]);
+ Rd_VPR64.8B[8,8] = MP_INT_ABS(Rn_VPR64.8B[8,8]);
+ Rd_VPR64.8B[16,8] = MP_INT_ABS(Rn_VPR64.8B[16,8]);
+ Rd_VPR64.8B[24,8] = MP_INT_ABS(Rn_VPR64.8B[24,8]);
+ Rd_VPR64.8B[32,8] = MP_INT_ABS(Rn_VPR64.8B[32,8]);
+ Rd_VPR64.8B[40,8] = MP_INT_ABS(Rn_VPR64.8B[40,8]);
+ Rd_VPR64.8B[48,8] = MP_INT_ABS(Rn_VPR64.8B[48,8]);
+ Rd_VPR64.8B[56,8] = MP_INT_ABS(Rn_VPR64.8B[56,8]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.1 ABS page C7-2017 line 117868 MATCH x0e20b800/mask=xbf3ffc00
+# CONSTRUCT x4e20b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$abs@1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@1
+# AUNIT --inst x4e20b800/mask=xfffffc00 --status pass
+# ABS Vector SIMD 16B when size = 00 , Q = 1
+
+:abs Rd_VPR128.16B, Rn_VPR128.16B
+is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000101110 & Rd_VPR128.16B & Rn_VPR128.16B & Zd
+{
+ # simd unary Rd_VPR128.16B = MP_INT_ABS(Rn_VPR128.16B) on lane size 1
+ Rd_VPR128.16B[0,8] = MP_INT_ABS(Rn_VPR128.16B[0,8]);
+ Rd_VPR128.16B[8,8] = MP_INT_ABS(Rn_VPR128.16B[8,8]);
+ Rd_VPR128.16B[16,8] = MP_INT_ABS(Rn_VPR128.16B[16,8]);
+ Rd_VPR128.16B[24,8] = MP_INT_ABS(Rn_VPR128.16B[24,8]);
+ Rd_VPR128.16B[32,8] = MP_INT_ABS(Rn_VPR128.16B[32,8]);
+ Rd_VPR128.16B[40,8] = MP_INT_ABS(Rn_VPR128.16B[40,8]);
+ Rd_VPR128.16B[48,8] = MP_INT_ABS(Rn_VPR128.16B[48,8]);
+ Rd_VPR128.16B[56,8] = MP_INT_ABS(Rn_VPR128.16B[56,8]);
+ Rd_VPR128.16B[64,8] = MP_INT_ABS(Rn_VPR128.16B[64,8]);
+ Rd_VPR128.16B[72,8] = MP_INT_ABS(Rn_VPR128.16B[72,8]);
+ Rd_VPR128.16B[80,8] = MP_INT_ABS(Rn_VPR128.16B[80,8]);
+ Rd_VPR128.16B[88,8] = MP_INT_ABS(Rn_VPR128.16B[88,8]);
+ Rd_VPR128.16B[96,8] = MP_INT_ABS(Rn_VPR128.16B[96,8]);
+ Rd_VPR128.16B[104,8] = MP_INT_ABS(Rn_VPR128.16B[104,8]);
+ Rd_VPR128.16B[112,8] = MP_INT_ABS(Rn_VPR128.16B[112,8]);
+ Rd_VPR128.16B[120,8] = MP_INT_ABS(Rn_VPR128.16B[120,8]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.1 ABS page C7-2017 line 117868 MATCH x0e20b800/mask=xbf3ffc00
+# CONSTRUCT x0e60b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$abs@2
+# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@2
+# AUNIT --inst x0e60b800/mask=xfffffc00 --status pass
+# ABS Vector SIMD 4H when size = 01 , Q = 0
+
+:abs Rd_VPR64.4H, Rn_VPR64.4H
+is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000101110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
+{
+ # simd unary Rd_VPR64.4H = MP_INT_ABS(Rn_VPR64.4H) on lane size 2
+ Rd_VPR64.4H[0,16] = MP_INT_ABS(Rn_VPR64.4H[0,16]);
+ Rd_VPR64.4H[16,16] = MP_INT_ABS(Rn_VPR64.4H[16,16]);
+ Rd_VPR64.4H[32,16] = MP_INT_ABS(Rn_VPR64.4H[32,16]);
+ Rd_VPR64.4H[48,16] = MP_INT_ABS(Rn_VPR64.4H[48,16]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.1 ABS page C7-2017 line 117868 MATCH x0e20b800/mask=xbf3ffc00
+# CONSTRUCT x4e60b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$abs@2
+# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@2
+# AUNIT --inst x4e60b800/mask=xfffffc00 --status pass
+# ABS Vector SIMD 8H when size = 01 , Q = 1
+
+:abs Rd_VPR128.8H, Rn_VPR128.8H
+is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000101110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
+{
+ # simd unary Rd_VPR128.8H = MP_INT_ABS(Rn_VPR128.8H) on lane size 2
+ Rd_VPR128.8H[0,16] = MP_INT_ABS(Rn_VPR128.8H[0,16]);
+ Rd_VPR128.8H[16,16] = MP_INT_ABS(Rn_VPR128.8H[16,16]);
+ Rd_VPR128.8H[32,16] = MP_INT_ABS(Rn_VPR128.8H[32,16]);
+ Rd_VPR128.8H[48,16] = MP_INT_ABS(Rn_VPR128.8H[48,16]);
+ Rd_VPR128.8H[64,16] = MP_INT_ABS(Rn_VPR128.8H[64,16]);
+ Rd_VPR128.8H[80,16] = MP_INT_ABS(Rn_VPR128.8H[80,16]);
+ Rd_VPR128.8H[96,16] = MP_INT_ABS(Rn_VPR128.8H[96,16]);
+ Rd_VPR128.8H[112,16] = MP_INT_ABS(Rn_VPR128.8H[112,16]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.1 ABS page C7-2017 line 117868 MATCH x0e20b800/mask=xbf3ffc00
+# CONSTRUCT x0ea0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$abs@4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@4
+# AUNIT --inst x0ea0b800/mask=xfffffc00 --status pass
+# ABS Vector SIMD 2S when size = 10 , Q = 0
+
+:abs Rd_VPR64.2S, Rn_VPR64.2S
+is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000101110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd
+{
+ # simd unary Rd_VPR64.2S = MP_INT_ABS(Rn_VPR64.2S) on lane size 4
+ Rd_VPR64.2S[0,32] = MP_INT_ABS(Rn_VPR64.2S[0,32]);
+ Rd_VPR64.2S[32,32] = MP_INT_ABS(Rn_VPR64.2S[32,32]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.1 ABS page C7-2017 line 117868 MATCH x0e20b800/mask=xbf3ffc00
+# CONSTRUCT x4ea0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$abs@4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@4
+# AUNIT --inst x4ea0b800/mask=xfffffc00 --status pass
+# ABS Vector SIMD 4S when size = 10 , Q = 1
+
+:abs Rd_VPR128.4S, Rn_VPR128.4S
+is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000101110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
+{
+ # simd unary Rd_VPR128.4S = MP_INT_ABS(Rn_VPR128.4S) on lane size 4
+ Rd_VPR128.4S[0,32] = MP_INT_ABS(Rn_VPR128.4S[0,32]);
+ Rd_VPR128.4S[32,32] = MP_INT_ABS(Rn_VPR128.4S[32,32]);
+ Rd_VPR128.4S[64,32] = MP_INT_ABS(Rn_VPR128.4S[64,32]);
+ Rd_VPR128.4S[96,32] = MP_INT_ABS(Rn_VPR128.4S[96,32]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.1 ABS page C7-2017 line 117868 MATCH x0e20b800/mask=xbf3ffc00
+# CONSTRUCT x4ee0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$abs@8
+# SMACRO(pseudo) ARG1 ARG2 =NEON_abs/1@8
+# AUNIT --inst x4ee0b800/mask=xfffffc00 --status pass
+# ABS Vector SIMD 2D when size = 11 , Q = 1
+
+:abs Rd_VPR128.2D, Rn_VPR128.2D
+is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b11 & b_1021=0b100000101110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd
+{
+ # simd unary Rd_VPR128.2D = MP_INT_ABS(Rn_VPR128.2D) on lane size 8
+ Rd_VPR128.2D[0,64] = MP_INT_ABS(Rn_VPR128.2D[0,64]);
+ Rd_VPR128.2D[64,64] = MP_INT_ABS(Rn_VPR128.2D[64,64]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.2 ADD (vector) page C7-2019 line 118000 MATCH x5e208400/mask=xff20fc00
+# CONSTRUCT x5ee08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =+
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2
+# AUNIT --inst x5ee08400/mask=xffe0fc00 --status pass
+
+:add Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x10 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = Rn_FPR64 + Rm_FPR64;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.2 ADD (vector) page C7-2019 line 118000 MATCH x0e208400/mask=xbf20fc00
+# CONSTRUCT x4e208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(force-primitive) ARG1 ARG2 ARG3 =$+@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@1
+# AUNIT --inst x4e208400/mask=xffe0fc00 --status pass
+
+:add Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x10 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ # simd infix Rd_VPR128.16B = Rn_VPR128.16B + Rm_VPR128.16B on lane size 1
+ Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] + Rm_VPR128.16B[0,8];
+ Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] + Rm_VPR128.16B[8,8];
+ Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] + Rm_VPR128.16B[16,8];
+ Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] + Rm_VPR128.16B[24,8];
+ Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] + Rm_VPR128.16B[32,8];
+ Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] + Rm_VPR128.16B[40,8];
+ Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] + Rm_VPR128.16B[48,8];
+ Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] + Rm_VPR128.16B[56,8];
+ Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] + Rm_VPR128.16B[64,8];
+ Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] + Rm_VPR128.16B[72,8];
+ Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] + Rm_VPR128.16B[80,8];
+ Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] + Rm_VPR128.16B[88,8];
+ Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] + Rm_VPR128.16B[96,8];
+ Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] + Rm_VPR128.16B[104,8];
+ Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] + Rm_VPR128.16B[112,8];
+ Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] + Rm_VPR128.16B[120,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.2 ADD (vector) page C7-2019 line 118000 MATCH x0e208400/mask=xbf20fc00
+# CONSTRUCT x4e608400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@2
+# AUNIT --inst x4e608400/mask=xffe0fc00 --status pass
+
+:add Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x10 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ # simd infix Rd_VPR128.8H = Rn_VPR128.8H + Rm_VPR128.8H on lane size 2
+ Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] + Rm_VPR128.8H[0,16];
+ Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] + Rm_VPR128.8H[16,16];
+ Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] + Rm_VPR128.8H[32,16];
+ Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] + Rm_VPR128.8H[48,16];
+ Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] + Rm_VPR128.8H[64,16];
+ Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] + Rm_VPR128.8H[80,16];
+ Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] + Rm_VPR128.8H[96,16];
+ Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] + Rm_VPR128.8H[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.2 ADD (vector) page C7-2019 line 118000 MATCH x0e208400/mask=xbf20fc00
+# CONSTRUCT x4ea08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(force-primitive) ARG1 ARG2 ARG3 =$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@4
+# AUNIT --inst x4ea08400/mask=xffe0fc00 --status pass
+
+:add Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x10 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd infix Rd_VPR128.4S = Rn_VPR128.4S + Rm_VPR128.4S on lane size 4
+ Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] + Rm_VPR128.4S[0,32];
+ Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] + Rm_VPR128.4S[32,32];
+ Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] + Rm_VPR128.4S[64,32];
+ Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] + Rm_VPR128.4S[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.2 ADD (vector) page C7-2019 line 118000 MATCH x0e208400/mask=xbf20fc00
+# CONSTRUCT x4ee08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@8
+# AUNIT --inst x4ee08400/mask=xffe0fc00 --status pass
+
+:add Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x10 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ # simd infix Rd_VPR128.2D = Rn_VPR128.2D + Rm_VPR128.2D on lane size 8
+ Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] + Rm_VPR128.2D[0,64];
+ Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] + Rm_VPR128.2D[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.2 ADD (vector) page C7-2019 line 118000 MATCH x0e208400/mask=xbf20fc00
+# CONSTRUCT x0e208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$+@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@1
+# AUNIT --inst x0e208400/mask=xffe0fc00 --status pass
+
+:add Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x10 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ # simd infix Rd_VPR64.8B = Rn_VPR64.8B + Rm_VPR64.8B on lane size 1
+ Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] + Rm_VPR64.8B[0,8];
+ Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] + Rm_VPR64.8B[8,8];
+ Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] + Rm_VPR64.8B[16,8];
+ Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] + Rm_VPR64.8B[24,8];
+ Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] + Rm_VPR64.8B[32,8];
+ Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] + Rm_VPR64.8B[40,8];
+ Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] + Rm_VPR64.8B[48,8];
+ Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] + Rm_VPR64.8B[56,8];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.2 ADD (vector) page C7-2019 line 118000 MATCH x0e208400/mask=xbf20fc00
+# CONSTRUCT x0e608400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@2
+# AUNIT --inst x0e608400/mask=xffe0fc00 --status pass
+
+:add Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x10 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ # simd infix Rd_VPR64.4H = Rn_VPR64.4H + Rm_VPR64.4H on lane size 2
+ Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] + Rm_VPR64.4H[0,16];
+ Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] + Rm_VPR64.4H[16,16];
+ Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] + Rm_VPR64.4H[32,16];
+ Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] + Rm_VPR64.4H[48,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.2 ADD (vector) page C7-2019 line 118000 MATCH x0e208400/mask=xbf20fc00
+# CONSTRUCT x0ea08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(force-primitive) ARG1 ARG2 ARG3 =$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_add/2@4
+# AUNIT --inst x0ea08400/mask=xffe0fc00 --status pass
+
+:add Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x10 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ # simd infix Rd_VPR64.2S = Rn_VPR64.2S + Rm_VPR64.2S on lane size 4
+ Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] + Rm_VPR64.2S[0,32];
+ Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] + Rm_VPR64.2S[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.3 ADDHN, ADDHN2 page C7-2021 line 118138 MATCH x0e204000/mask=xbf20fc00
+# CONSTRUCT x0ea04000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $+@8 &=$shuffle@1-0@3-1:4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_addhn/3@8
+# AUNIT --inst x0ea04000/mask=xffe0fc00 --status pass
+
+:addhn Rd_VPR64.2S, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x4 & b_1011=0 & Rn_VPR128.2D & Rd_VPR64.2S & Rd_VPR128 & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.2D + Rm_VPR128.2D on lane size 8
+ TMPQ1[0,64] = Rn_VPR128.2D[0,64] + Rm_VPR128.2D[0,64];
+ TMPQ1[64,64] = Rn_VPR128.2D[64,64] + Rm_VPR128.2D[64,64];
+ # simd shuffle Rd_VPR64.2S = TMPQ1 (@1-0@3-1) lane size 4
+ Rd_VPR64.2S[0,32] = TMPQ1[32,32];
+ Rd_VPR64.2S[32,32] = TMPQ1[96,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.3 ADDHN, ADDHN2 page C7-2021 line 118138 MATCH x0e204000/mask=xbf20fc00
+# CONSTRUCT x0e604000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $+@4 &=$shuffle@1-0@3-1@5-2@7-3:2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_addhn/3@4
+# AUNIT --inst x0e604000/mask=xffe0fc00 --status pass
+
+:addhn Rd_VPR64.4H, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x4 & b_1011=0 & Rn_VPR128.4S & Rd_VPR64.4H & Rd_VPR128 & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.4S + Rm_VPR128.4S on lane size 4
+ TMPQ1[0,32] = Rn_VPR128.4S[0,32] + Rm_VPR128.4S[0,32];
+ TMPQ1[32,32] = Rn_VPR128.4S[32,32] + Rm_VPR128.4S[32,32];
+ TMPQ1[64,32] = Rn_VPR128.4S[64,32] + Rm_VPR128.4S[64,32];
+ TMPQ1[96,32] = Rn_VPR128.4S[96,32] + Rm_VPR128.4S[96,32];
+ # simd shuffle Rd_VPR64.4H = TMPQ1 (@1-0@3-1@5-2@7-3) lane size 2
+ Rd_VPR64.4H[0,16] = TMPQ1[16,16];
+ Rd_VPR64.4H[16,16] = TMPQ1[48,16];
+ Rd_VPR64.4H[32,16] = TMPQ1[80,16];
+ Rd_VPR64.4H[48,16] = TMPQ1[112,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.3 ADDHN, ADDHN2 page C7-2021 line 118138 MATCH x0e204000/mask=xbf20fc00
+# CONSTRUCT x0e204000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $+@2 &=$shuffle@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7:1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_addhn/3@2
+# AUNIT --inst x0e204000/mask=xffe0fc00 --status pass
+
+:addhn Rd_VPR64.8B, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x4 & b_1011=0 & Rn_VPR128.8H & Rd_VPR64.8B & Rd_VPR128 & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.8H + Rm_VPR128.8H on lane size 2
+ TMPQ1[0,16] = Rn_VPR128.8H[0,16] + Rm_VPR128.8H[0,16];
+ TMPQ1[16,16] = Rn_VPR128.8H[16,16] + Rm_VPR128.8H[16,16];
+ TMPQ1[32,16] = Rn_VPR128.8H[32,16] + Rm_VPR128.8H[32,16];
+ TMPQ1[48,16] = Rn_VPR128.8H[48,16] + Rm_VPR128.8H[48,16];
+ TMPQ1[64,16] = Rn_VPR128.8H[64,16] + Rm_VPR128.8H[64,16];
+ TMPQ1[80,16] = Rn_VPR128.8H[80,16] + Rm_VPR128.8H[80,16];
+ TMPQ1[96,16] = Rn_VPR128.8H[96,16] + Rm_VPR128.8H[96,16];
+ TMPQ1[112,16] = Rn_VPR128.8H[112,16] + Rm_VPR128.8H[112,16];
+ # simd shuffle Rd_VPR64.8B = TMPQ1 (@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7) lane size 1
+ Rd_VPR64.8B[0,8] = TMPQ1[8,8];
+ Rd_VPR64.8B[8,8] = TMPQ1[24,8];
+ Rd_VPR64.8B[16,8] = TMPQ1[40,8];
+ Rd_VPR64.8B[24,8] = TMPQ1[56,8];
+ Rd_VPR64.8B[32,8] = TMPQ1[72,8];
+ Rd_VPR64.8B[40,8] = TMPQ1[88,8];
+ Rd_VPR64.8B[48,8] = TMPQ1[104,8];
+ Rd_VPR64.8B[56,8] = TMPQ1[120,8];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.3 ADDHN, ADDHN2 page C7-2021 line 118138 MATCH x0e204000/mask=xbf20fc00
+# CONSTRUCT x4e204000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $+@2 &=$shuffle@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15:1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_addhn2/3@2
+# AUNIT --inst x4e204000/mask=xffe0fc00 --status pass
+
+:addhn2 Rd_VPR128.16B, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x4 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.16B & Rd_VPR128 & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.8H + Rm_VPR128.8H on lane size 2
+ TMPQ1[0,16] = Rn_VPR128.8H[0,16] + Rm_VPR128.8H[0,16];
+ TMPQ1[16,16] = Rn_VPR128.8H[16,16] + Rm_VPR128.8H[16,16];
+ TMPQ1[32,16] = Rn_VPR128.8H[32,16] + Rm_VPR128.8H[32,16];
+ TMPQ1[48,16] = Rn_VPR128.8H[48,16] + Rm_VPR128.8H[48,16];
+ TMPQ1[64,16] = Rn_VPR128.8H[64,16] + Rm_VPR128.8H[64,16];
+ TMPQ1[80,16] = Rn_VPR128.8H[80,16] + Rm_VPR128.8H[80,16];
+ TMPQ1[96,16] = Rn_VPR128.8H[96,16] + Rm_VPR128.8H[96,16];
+ TMPQ1[112,16] = Rn_VPR128.8H[112,16] + Rm_VPR128.8H[112,16];
+ # simd shuffle Rd_VPR128.16B = TMPQ1 (@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15) lane size 1
+ Rd_VPR128.16B[64,8] = TMPQ1[8,8];
+ Rd_VPR128.16B[72,8] = TMPQ1[24,8];
+ Rd_VPR128.16B[80,8] = TMPQ1[40,8];
+ Rd_VPR128.16B[88,8] = TMPQ1[56,8];
+ Rd_VPR128.16B[96,8] = TMPQ1[72,8];
+ Rd_VPR128.16B[104,8] = TMPQ1[88,8];
+ Rd_VPR128.16B[112,8] = TMPQ1[104,8];
+ Rd_VPR128.16B[120,8] = TMPQ1[120,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.3 ADDHN, ADDHN2 page C7-2021 line 118138 MATCH x0e204000/mask=xbf20fc00
+# CONSTRUCT x4ea04000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $+@8 &=$shuffle@1-2@3-3:4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_addhn2/3@8
+# AUNIT --inst x4ea04000/mask=xffe0fc00 --status pass
+
+:addhn2 Rd_VPR128.4S, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x4 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.4S & Rd_VPR128 & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.2D + Rm_VPR128.2D on lane size 8
+ TMPQ1[0,64] = Rn_VPR128.2D[0,64] + Rm_VPR128.2D[0,64];
+ TMPQ1[64,64] = Rn_VPR128.2D[64,64] + Rm_VPR128.2D[64,64];
+ # simd shuffle Rd_VPR128.4S = TMPQ1 (@1-2@3-3) lane size 4
+ Rd_VPR128.4S[64,32] = TMPQ1[32,32];
+ Rd_VPR128.4S[96,32] = TMPQ1[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.3 ADDHN, ADDHN2 page C7-2021 line 118138 MATCH x0e204000/mask=xbf20fc00
+# CONSTRUCT x4e604000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $+@4 &=$shuffle@1-4@3-5@5-6@7-7:2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_addhn2/3@4
+# AUNIT --inst x4e604000/mask=xffe0fc00 --status pass
+
+:addhn2 Rd_VPR128.8H, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x4 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.8H & Rd_VPR128 & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.4S + Rm_VPR128.4S on lane size 4
+ TMPQ1[0,32] = Rn_VPR128.4S[0,32] + Rm_VPR128.4S[0,32];
+ TMPQ1[32,32] = Rn_VPR128.4S[32,32] + Rm_VPR128.4S[32,32];
+ TMPQ1[64,32] = Rn_VPR128.4S[64,32] + Rm_VPR128.4S[64,32];
+ TMPQ1[96,32] = Rn_VPR128.4S[96,32] + Rm_VPR128.4S[96,32];
+ # simd shuffle Rd_VPR128.8H = TMPQ1 (@1-4@3-5@5-6@7-7) lane size 2
+ Rd_VPR128.8H[64,16] = TMPQ1[16,16];
+ Rd_VPR128.8H[80,16] = TMPQ1[48,16];
+ Rd_VPR128.8H[96,16] = TMPQ1[80,16];
+ Rd_VPR128.8H[112,16] = TMPQ1[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.4 ADDP (scalar) page C7-2023 line 118265 MATCH x5e31b800/mask=xff3ffc00
+# CONSTRUCT x5ef1b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =#+
+# SMACRO(pseudo) ARG1 ARG2 =NEON_addp/1@8
+# AUNIT --inst x5ef1b800/mask=xfffffc00 --status pass
+
+:addp Rd_FPR64, Rn_VPR128.2D
+is b_3031=1 & u=0 & b_2428=0x1e & b_23=1 & b_1722=0x38 & b_1216=0x1b & b_1011=2 & Rn_VPR128.2D & Rd_FPR64 & Zd
+{
+ # sipd infix Rd_FPR64 = +(Rn_VPR128.2D) on pairs lane size (8 to 8)
+ local tmp1 = Rn_VPR128.2D[0,64];
+ local tmp2 = Rn_VPR128.2D[64,64];
+ Rd_FPR64 = tmp1 + tmp2;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.5 ADDP (vector) page C7-2025 line 118351 MATCH x0e20bc00/mask=xbf20fc00
+# CONSTRUCT x4e20bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 var:16 ARG2 ARG3 =#+/2 =
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@1
+# AUNIT --inst x4e20bc00/mask=xffe0fc00 --status pass
+
+:addp Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x17 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ TMPQ1 = 0;
+ # sipd infix TMPQ1 = +(Rn_VPR128.16B,Rm_VPR128.16B) on pairs lane size (1 to 1)
+ local tmp2 = Rn_VPR128.16B[0,8];
+ local tmp3 = Rn_VPR128.16B[8,8];
+ TMPQ1[0,8] = tmp2 + tmp3;
+ tmp2 = Rn_VPR128.16B[16,8];
+ tmp3 = Rn_VPR128.16B[24,8];
+ TMPQ1[8,8] = tmp2 + tmp3;
+ tmp2 = Rn_VPR128.16B[32,8];
+ tmp3 = Rn_VPR128.16B[40,8];
+ TMPQ1[16,8] = tmp2 + tmp3;
+ tmp2 = Rn_VPR128.16B[48,8];
+ tmp3 = Rn_VPR128.16B[56,8];
+ TMPQ1[24,8] = tmp2 + tmp3;
+ tmp2 = Rn_VPR128.16B[64,8];
+ tmp3 = Rn_VPR128.16B[72,8];
+ TMPQ1[32,8] = tmp2 + tmp3;
+ tmp2 = Rn_VPR128.16B[80,8];
+ tmp3 = Rn_VPR128.16B[88,8];
+ TMPQ1[40,8] = tmp2 + tmp3;
+ tmp2 = Rn_VPR128.16B[96,8];
+ tmp3 = Rn_VPR128.16B[104,8];
+ TMPQ1[48,8] = tmp2 + tmp3;
+ tmp2 = Rn_VPR128.16B[112,8];
+ tmp3 = Rn_VPR128.16B[120,8];
+ TMPQ1[56,8] = tmp2 + tmp3;
+ tmp2 = Rm_VPR128.16B[0,8];
+ tmp3 = Rm_VPR128.16B[8,8];
+ TMPQ1[64,8] = tmp2 + tmp3;
+ tmp2 = Rm_VPR128.16B[16,8];
+ tmp3 = Rm_VPR128.16B[24,8];
+ TMPQ1[72,8] = tmp2 + tmp3;
+ tmp2 = Rm_VPR128.16B[32,8];
+ tmp3 = Rm_VPR128.16B[40,8];
+ TMPQ1[80,8] = tmp2 + tmp3;
+ tmp2 = Rm_VPR128.16B[48,8];
+ tmp3 = Rm_VPR128.16B[56,8];
+ TMPQ1[88,8] = tmp2 + tmp3;
+ tmp2 = Rm_VPR128.16B[64,8];
+ tmp3 = Rm_VPR128.16B[72,8];
+ TMPQ1[96,8] = tmp2 + tmp3;
+ tmp2 = Rm_VPR128.16B[80,8];
+ tmp3 = Rm_VPR128.16B[88,8];
+ TMPQ1[104,8] = tmp2 + tmp3;
+ tmp2 = Rm_VPR128.16B[96,8];
+ tmp3 = Rm_VPR128.16B[104,8];
+ TMPQ1[112,8] = tmp2 + tmp3;
+ tmp2 = Rm_VPR128.16B[112,8];
+ tmp3 = Rm_VPR128.16B[120,8];
+ TMPQ1[120,8] = tmp2 + tmp3;
+ Rd_VPR128.16B = TMPQ1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.5 ADDP (vector) page C7-2025 line 118351 MATCH x0e20bc00/mask=xbf20fc00
+# CONSTRUCT x4ee0bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 var:16 ARG2 ARG3 =#+/2 =
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@8
+# AUNIT --inst x4ee0bc00/mask=xffe0fc00 --status pass
+
+:addp Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x17 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ TMPQ1 = 0;
+ # sipd infix TMPQ1 = +(Rn_VPR128.2D,Rm_VPR128.2D) on pairs lane size (8 to 8)
+ local tmp2 = Rn_VPR128.2D[0,64];
+ local tmp3 = Rn_VPR128.2D[64,64];
+ TMPQ1[0,64] = tmp2 + tmp3;
+ tmp2 = Rm_VPR128.2D[0,64];
+ tmp3 = Rm_VPR128.2D[64,64];
+ TMPQ1[64,64] = tmp2 + tmp3;
+ Rd_VPR128.2D = TMPQ1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.5 ADDP (vector) page C7-2025 line 118351 MATCH x0e20bc00/mask=xbf20fc00
+# CONSTRUCT x0ea0bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 var:8 ARG2 ARG3 =#+/2 =
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@4
+# AUNIT --inst x0ea0bc00/mask=xffe0fc00 --status pass
+
+:addp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x17 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ TMPD1 = 0;
+ # sipd infix TMPD1 = +(Rn_VPR64.2S,Rm_VPR64.2S) on pairs lane size (4 to 4)
+ local tmp2 = Rn_VPR64.2S[0,32];
+ local tmp3 = Rn_VPR64.2S[32,32];
+ TMPD1[0,32] = tmp2 + tmp3;
+ tmp2 = Rm_VPR64.2S[0,32];
+ tmp3 = Rm_VPR64.2S[32,32];
+ TMPD1[32,32] = tmp2 + tmp3;
+ Rd_VPR64.2S = TMPD1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.5 ADDP (vector) page C7-2025 line 118351 MATCH x0e20bc00/mask=xbf20fc00
+# CONSTRUCT x0e60bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 var:8 ARG2 ARG3 =#+/2 =
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@2
+# AUNIT --inst x0e60bc00/mask=xffe0fc00 --status pass
+
+:addp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x17 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ TMPD1 = 0;
+ # sipd infix TMPD1 = +(Rn_VPR64.4H,Rm_VPR64.4H) on pairs lane size (2 to 2)
+ local tmp2 = Rn_VPR64.4H[0,16];
+ local tmp3 = Rn_VPR64.4H[16,16];
+ TMPD1[0,16] = tmp2 + tmp3;
+ tmp2 = Rn_VPR64.4H[32,16];
+ tmp3 = Rn_VPR64.4H[48,16];
+ TMPD1[16,16] = tmp2 + tmp3;
+ tmp2 = Rm_VPR64.4H[0,16];
+ tmp3 = Rm_VPR64.4H[16,16];
+ TMPD1[32,16] = tmp2 + tmp3;
+ tmp2 = Rm_VPR64.4H[32,16];
+ tmp3 = Rm_VPR64.4H[48,16];
+ TMPD1[48,16] = tmp2 + tmp3;
+ Rd_VPR64.4H = TMPD1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.5 ADDP (vector) page C7-2025 line 118351 MATCH x0e20bc00/mask=xbf20fc00
+# CONSTRUCT x4ea0bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 var:16 ARG2 ARG3 =#+/2 =
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@4
+# AUNIT --inst x4ea0bc00/mask=xffe0fc00 --status pass
+
+:addp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x17 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ TMPQ1 = 0;
+ # sipd infix TMPQ1 = +(Rn_VPR128.4S,Rm_VPR128.4S) on pairs lane size (4 to 4)
+ local tmp2 = Rn_VPR128.4S[0,32];
+ local tmp3 = Rn_VPR128.4S[32,32];
+ TMPQ1[0,32] = tmp2 + tmp3;
+ tmp2 = Rn_VPR128.4S[64,32];
+ tmp3 = Rn_VPR128.4S[96,32];
+ TMPQ1[32,32] = tmp2 + tmp3;
+ tmp2 = Rm_VPR128.4S[0,32];
+ tmp3 = Rm_VPR128.4S[32,32];
+ TMPQ1[64,32] = tmp2 + tmp3;
+ tmp2 = Rm_VPR128.4S[64,32];
+ tmp3 = Rm_VPR128.4S[96,32];
+ TMPQ1[96,32] = tmp2 + tmp3;
+ Rd_VPR128.4S = TMPQ1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.5 ADDP (vector) page C7-2025 line 118351 MATCH x0e20bc00/mask=xbf20fc00
+# CONSTRUCT x0e20bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 var:8 ARG2 ARG3 =#+/2 =
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@1
+# AUNIT --inst x0e20bc00/mask=xffe0fc00 --status pass
+
+:addp Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x17 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ TMPD1 = 0;
+ # sipd infix TMPD1 = +(Rn_VPR64.8B,Rm_VPR64.8B) on pairs lane size (1 to 1)
+ local tmp2 = Rn_VPR64.8B[0,8];
+ local tmp3 = Rn_VPR64.8B[8,8];
+ TMPD1[0,8] = tmp2 + tmp3;
+ tmp2 = Rn_VPR64.8B[16,8];
+ tmp3 = Rn_VPR64.8B[24,8];
+ TMPD1[8,8] = tmp2 + tmp3;
+ tmp2 = Rn_VPR64.8B[32,8];
+ tmp3 = Rn_VPR64.8B[40,8];
+ TMPD1[16,8] = tmp2 + tmp3;
+ tmp2 = Rn_VPR64.8B[48,8];
+ tmp3 = Rn_VPR64.8B[56,8];
+ TMPD1[24,8] = tmp2 + tmp3;
+ tmp2 = Rm_VPR64.8B[0,8];
+ tmp3 = Rm_VPR64.8B[8,8];
+ TMPD1[32,8] = tmp2 + tmp3;
+ tmp2 = Rm_VPR64.8B[16,8];
+ tmp3 = Rm_VPR64.8B[24,8];
+ TMPD1[40,8] = tmp2 + tmp3;
+ tmp2 = Rm_VPR64.8B[32,8];
+ tmp3 = Rm_VPR64.8B[40,8];
+ TMPD1[48,8] = tmp2 + tmp3;
+ tmp2 = Rm_VPR64.8B[48,8];
+ tmp3 = Rm_VPR64.8B[56,8];
+ TMPD1[56,8] = tmp2 + tmp3;
+ Rd_VPR64.8B = TMPD1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.5 ADDP (vector) page C7-2025 line 118351 MATCH x0e20bc00/mask=xbf20fc00
+# CONSTRUCT x4e60bc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 var:16 ARG2 ARG3 =#+/2 =
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_addp/2@2
+# AUNIT --inst x4e60bc00/mask=xffe0fc00 --status pass
+
+:addp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x17 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ TMPQ1 = 0;
+ # sipd infix TMPQ1 = +(Rn_VPR128.8H,Rm_VPR128.8H) on pairs lane size (2 to 2)
+ local tmp2 = Rn_VPR128.8H[0,16];
+ local tmp3 = Rn_VPR128.8H[16,16];
+ TMPQ1[0,16] = tmp2 + tmp3;
+ tmp2 = Rn_VPR128.8H[32,16];
+ tmp3 = Rn_VPR128.8H[48,16];
+ TMPQ1[16,16] = tmp2 + tmp3;
+ tmp2 = Rn_VPR128.8H[64,16];
+ tmp3 = Rn_VPR128.8H[80,16];
+ TMPQ1[32,16] = tmp2 + tmp3;
+ tmp2 = Rn_VPR128.8H[96,16];
+ tmp3 = Rn_VPR128.8H[112,16];
+ TMPQ1[48,16] = tmp2 + tmp3;
+ tmp2 = Rm_VPR128.8H[0,16];
+ tmp3 = Rm_VPR128.8H[16,16];
+ TMPQ1[64,16] = tmp2 + tmp3;
+ tmp2 = Rm_VPR128.8H[32,16];
+ tmp3 = Rm_VPR128.8H[48,16];
+ TMPQ1[80,16] = tmp2 + tmp3;
+ tmp2 = Rm_VPR128.8H[64,16];
+ tmp3 = Rm_VPR128.8H[80,16];
+ TMPQ1[96,16] = tmp2 + tmp3;
+ tmp2 = Rm_VPR128.8H[96,16];
+ tmp3 = Rm_VPR128.8H[112,16];
+ TMPQ1[112,16] = tmp2 + tmp3;
+ Rd_VPR128.8H = TMPQ1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.6 ADDV page C7-2027 line 118452 MATCH x0e31b800/mask=xbf3ffc00
+# CONSTRUCT x4e31b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_addv/1@1
+# AUNIT --inst x4e31b800/mask=xfffffc00 --status nopcodeop
+
+:addv Rd_FPR8, Rn_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1b & b_1011=2 & Rn_VPR128.16B & Rd_FPR8 & Zd
+{
+ Rd_FPR8 = NEON_addv(Rn_VPR128.16B, 1:1);
+}
+
+# C7.2.6 ADDV page C7-2027 line 118452 MATCH x0e31b800/mask=xbf3ffc00
+# CONSTRUCT x0e31b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_addv/1@1
+# AUNIT --inst x0e31b800/mask=xfffffc00 --status nopcodeop
+
+:addv Rd_FPR8, Rn_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1b & b_1011=2 & Rn_VPR64.8B & Rd_FPR8 & Zd
+{
+ Rd_FPR8 = NEON_addv(Rn_VPR64.8B, 1:1);
+}
+
+# C7.2.6 ADDV page C7-2027 line 118452 MATCH x0e31b800/mask=xbf3ffc00
+# CONSTRUCT x0e71b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_addv/1@2
+# AUNIT --inst x0e71b800/mask=xfffffc00 --status nopcodeop
+
+:addv Rd_FPR16, Rn_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1b & b_1011=2 & Rn_VPR64.4H & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_addv(Rn_VPR64.4H, 2:1);
+}
+
+# C7.2.6 ADDV page C7-2027 line 118452 MATCH x0e31b800/mask=xbf3ffc00
+# CONSTRUCT x4e71b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_addv/1@2
+# AUNIT --inst x4e71b800/mask=xfffffc00 --status nopcodeop
+
+:addv Rd_FPR16, Rn_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1b & b_1011=2 & Rn_VPR128.8H & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_addv(Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.6 ADDV page C7-2027 line 118452 MATCH x0e31b800/mask=xbf3ffc00
+# CONSTRUCT x4eb1b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(force-primitive) ARG1 ARG2[0]:4 ARG2[1]:4 + ARG2[2]:4 ARG2[3]:4 + =+
+# SMACRO(pseudo) ARG1 ARG2 =NEON_addv/1@4
+# AUNIT --inst x4eb1b800/mask=xfffffc00 --status pass
+
+:addv Rd_FPR32, Rn_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x1b & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd
+{
+ local tmp1:4 = Rn_VPR128.4S[0,32];
+ local tmp2:4 = Rn_VPR128.4S[32,32];
+ local tmp3:4 = tmp1 + tmp2;
+ local tmp4:4 = Rn_VPR128.4S[64,32];
+ local tmp5:4 = Rn_VPR128.4S[96,32];
+ local tmp6:4 = tmp4 + tmp5;
+ Rd_FPR32 = tmp3 + tmp6;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.7 AESD page C7-2029 line 118544 MATCH x4e285800/mask=xfffffc00
+# CONSTRUCT x4e285800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_aesd/2
+# AUNIT --inst x4e285800/mask=xfffffc00 --status noqemu
+
+:aesd Rd_VPR128.16B, Rn_VPR128.16B
+is b_2431=0b01001110 & b_2223=0b00 & b_1721=0b10100 & b_1216=5 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_aesd(Rd_VPR128.16B, Rn_VPR128.16B);
+}
+
+# C7.2.8 AESE page C7-2030 line 118606 MATCH x4e284800/mask=xfffffc00
+# CONSTRUCT x4e284800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_aese/2
+# AUNIT --inst x4e284800/mask=xfffffc00 --status noqemu
+
+:aese Rd_VPR128.16B, Rn_VPR128.16B
+is b_2431=0b01001110 & b_2223=0b00 & b_1721=0b10100 & b_1216=4 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_aese(Rd_VPR128.16B, Rn_VPR128.16B);
+}
+
+# C7.2.9 AESIMC page C7-2031 line 118669 MATCH x4e287800/mask=xfffffc00
+# CONSTRUCT x4e287800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_aesimc/2
+# AUNIT --inst x4e287800/mask=xfffffc00 --status noqemu
+
+:aesimc Rd_VPR128.16B, Rn_VPR128.16B
+is b_2431=0b01001110 & b_2223=0b00 & b_1721=0b10100 & b_1216=7 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Rd_VPR128 & Zd
+{
+ Rd_VPR128.16B = NEON_aesimc(Rd_VPR128.16B, Rn_VPR128.16B);
+}
+
+# C7.2.10 AESMC page C7-2032 line 118729 MATCH x4e286800/mask=xfffffc00
+# CONSTRUCT x4e286800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_aesmc/2
+# AUNIT --inst x4e286800/mask=xfffffc00 --status noqemu
+
+:aesmc Rd_VPR128.16B, Rn_VPR128.16B
+is b_2431=0b01001110 & b_2223=0b00 & b_1721=0b10100 & b_1216=6 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Rd_VPR128 & Zd
+{
+ Rd_VPR128.16B = NEON_aesmc(Rd_VPR128.16B, Rn_VPR128.16B);
+}
+
+# C7.2.11 AND (vector) page C7-2033 line 118789 MATCH x0e201c00/mask=xbfe0fc00
+# CONSTRUCT x4e201c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$&@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_and/2@1
+# AUNIT --inst x4e201c00/mask=xffe0fc00 --status pass
+
+:and Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ # simd infix Rd_VPR128.16B = Rn_VPR128.16B & Rm_VPR128.16B on lane size 1
+ Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] & Rm_VPR128.16B[0,8];
+ Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] & Rm_VPR128.16B[8,8];
+ Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] & Rm_VPR128.16B[16,8];
+ Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] & Rm_VPR128.16B[24,8];
+ Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] & Rm_VPR128.16B[32,8];
+ Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] & Rm_VPR128.16B[40,8];
+ Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] & Rm_VPR128.16B[48,8];
+ Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] & Rm_VPR128.16B[56,8];
+ Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] & Rm_VPR128.16B[64,8];
+ Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] & Rm_VPR128.16B[72,8];
+ Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] & Rm_VPR128.16B[80,8];
+ Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] & Rm_VPR128.16B[88,8];
+ Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] & Rm_VPR128.16B[96,8];
+ Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] & Rm_VPR128.16B[104,8];
+ Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] & Rm_VPR128.16B[112,8];
+ Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] & Rm_VPR128.16B[120,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.11 AND (vector) page C7-2033 line 118789 MATCH x0e201c00/mask=xbfe0fc00
+# CONSTRUCT x0e201c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =&
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_and/2@1
+# AUNIT --inst x0e201c00/mask=xffe0fc00 --status pass
+
+:and Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = Rn_VPR64.8B & Rm_VPR64.8B;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.12 BCAX page C7-2035 line 118871 MATCH xce200000/mask=xffe08000
+# CONSTRUCT xce200000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 ARG4 $~@1 $&@1 =$|@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG3 =NEON_bcax/3@1
+# AUNIT --inst xce200000/mask=xffe08000 --status noqemu
+
+:bcax Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, Ra_VPR128.16B
+is b_2131=0b11001110001 & b_15=0 & Rd_VPR128.16B & Rn_VPR128.16B & Rm_VPR128.16B & Ra_VPR128.16B & Zd
+{
+ # simd unary TMPQ1 = ~(Ra_VPR128.16B) on lane size 1
+ TMPQ1[0,8] = ~(Ra_VPR128.16B[0,8]);
+ TMPQ1[8,8] = ~(Ra_VPR128.16B[8,8]);
+ TMPQ1[16,8] = ~(Ra_VPR128.16B[16,8]);
+ TMPQ1[24,8] = ~(Ra_VPR128.16B[24,8]);
+ TMPQ1[32,8] = ~(Ra_VPR128.16B[32,8]);
+ TMPQ1[40,8] = ~(Ra_VPR128.16B[40,8]);
+ TMPQ1[48,8] = ~(Ra_VPR128.16B[48,8]);
+ TMPQ1[56,8] = ~(Ra_VPR128.16B[56,8]);
+ TMPQ1[64,8] = ~(Ra_VPR128.16B[64,8]);
+ TMPQ1[72,8] = ~(Ra_VPR128.16B[72,8]);
+ TMPQ1[80,8] = ~(Ra_VPR128.16B[80,8]);
+ TMPQ1[88,8] = ~(Ra_VPR128.16B[88,8]);
+ TMPQ1[96,8] = ~(Ra_VPR128.16B[96,8]);
+ TMPQ1[104,8] = ~(Ra_VPR128.16B[104,8]);
+ TMPQ1[112,8] = ~(Ra_VPR128.16B[112,8]);
+ TMPQ1[120,8] = ~(Ra_VPR128.16B[120,8]);
+ # simd infix TMPQ2 = Rm_VPR128.16B & TMPQ1 on lane size 1
+ TMPQ2[0,8] = Rm_VPR128.16B[0,8] & TMPQ1[0,8];
+ TMPQ2[8,8] = Rm_VPR128.16B[8,8] & TMPQ1[8,8];
+ TMPQ2[16,8] = Rm_VPR128.16B[16,8] & TMPQ1[16,8];
+ TMPQ2[24,8] = Rm_VPR128.16B[24,8] & TMPQ1[24,8];
+ TMPQ2[32,8] = Rm_VPR128.16B[32,8] & TMPQ1[32,8];
+ TMPQ2[40,8] = Rm_VPR128.16B[40,8] & TMPQ1[40,8];
+ TMPQ2[48,8] = Rm_VPR128.16B[48,8] & TMPQ1[48,8];
+ TMPQ2[56,8] = Rm_VPR128.16B[56,8] & TMPQ1[56,8];
+ TMPQ2[64,8] = Rm_VPR128.16B[64,8] & TMPQ1[64,8];
+ TMPQ2[72,8] = Rm_VPR128.16B[72,8] & TMPQ1[72,8];
+ TMPQ2[80,8] = Rm_VPR128.16B[80,8] & TMPQ1[80,8];
+ TMPQ2[88,8] = Rm_VPR128.16B[88,8] & TMPQ1[88,8];
+ TMPQ2[96,8] = Rm_VPR128.16B[96,8] & TMPQ1[96,8];
+ TMPQ2[104,8] = Rm_VPR128.16B[104,8] & TMPQ1[104,8];
+ TMPQ2[112,8] = Rm_VPR128.16B[112,8] & TMPQ1[112,8];
+ TMPQ2[120,8] = Rm_VPR128.16B[120,8] & TMPQ1[120,8];
+ # simd infix Rd_VPR128.16B = Rn_VPR128.16B | TMPQ2 on lane size 1
+ Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] | TMPQ2[0,8];
+ Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] | TMPQ2[8,8];
+ Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] | TMPQ2[16,8];
+ Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] | TMPQ2[24,8];
+ Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] | TMPQ2[32,8];
+ Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] | TMPQ2[40,8];
+ Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] | TMPQ2[48,8];
+ Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] | TMPQ2[56,8];
+ Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] | TMPQ2[64,8];
+ Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] | TMPQ2[72,8];
+ Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] | TMPQ2[80,8];
+ Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] | TMPQ2[88,8];
+ Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] | TMPQ2[96,8];
+ Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] | TMPQ2[104,8];
+ Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] | TMPQ2[112,8];
+ Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] | TMPQ2[120,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.20 BIC (vector, immediate) page C7-2048 line 119572 MATCH x2f001400/mask=xbff81c00
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00
+# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00
+# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00
+# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00
+# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00
+# CONSTRUCT x2f001400/mask=xfff89c00 MATCHED 7 DOCUMENTED OPCODES
+# SMACRO ARG1 Imm_neon_uimm8Shift:4 ~ &=$&
+# SMACRO(pseudo) ARG1 Imm_neon_uimm8Shift:4 &=NEON_bic/2@4
+# AUNIT --inst x2f001400/mask=xfff89c00 --status pass
+
+:bic Rd_VPR64.2S, abcdefgh
+is b_3131=0 & q=0 & b_29=1 & b_2428=0xf & b_1923=0x0 & b_1515=0 & abcdefgh & Imm_neon_uimm8Shift & b_1012=5 & Rd_VPR64.2S & Zd
+{
+ local tmp1:4 = ~ Imm_neon_uimm8Shift:4;
+ # simd infix Rd_VPR64.2S = Rd_VPR64.2S & tmp1 on lane size 4
+ Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] & tmp1;
+ Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] & tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.20 BIC (vector, immediate) page C7-2048 line 119572 MATCH x2f001400/mask=xbff81c00
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00
+# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x2f009400/mask=xbf80fc00
+# CONSTRUCT x2f009400/mask=xfff8dc00 MATCHED 4 DOCUMENTED OPCODES
+# SMACRO ARG1 Imm_neon_uimm8Shift:2 ~ &=$&
+# SMACRO(pseudo) ARG1 Imm_neon_uimm8Shift:2 &=NEON_bic/2@2
+# AUNIT --inst x2f009400/mask=xfff8dc00 --status pass
+
+:bic Rd_VPR64.4H, abcdefgh
+is b_3131=0 & q=0 & b_29=1 & b_2428=0xf & abcdefgh & b_1923=0x0 & b_1415=2 & Imm_neon_uimm8Shift & b_1012=5 & Rd_VPR64.4H & Zd
+{
+ local tmp1:2 = ~ Imm_neon_uimm8Shift:2;
+ # simd infix Rd_VPR64.4H = Rd_VPR64.4H & tmp1 on lane size 2
+ Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] & tmp1;
+ Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] & tmp1;
+ Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] & tmp1;
+ Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] & tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.20 BIC (vector, immediate) page C7-2048 line 119572 MATCH x2f001400/mask=xbff81c00
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00
+# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00
+# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00
+# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00
+# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00
+# CONSTRUCT x6f001400/mask=xfff89c00 MATCHED 7 DOCUMENTED OPCODES
+# SMACRO ARG1 Imm_neon_uimm8Shift:4 ~ &=$&
+# SMACRO(pseudo) ARG1 Imm_neon_uimm8Shift:4 &=NEON_bic/2@4
+# AUNIT --inst x6f001400/mask=xfff89c00 --status pass
+
+:bic Rd_VPR128.4S, abcdefgh
+is b_3131=0 & q=1 & b_29=1 & b_2428=0xf & b_1923=0x0 & b_1515=0 & abcdefgh & Imm_neon_uimm8Shift & b_1012=5 & Rd_VPR128.4S & Zd
+{
+ local tmp1:4 = ~ Imm_neon_uimm8Shift:4;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S & tmp1 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] & tmp1;
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] & tmp1;
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] & tmp1;
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] & tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.20 BIC (vector, immediate) page C7-2048 line 119572 MATCH x2f001400/mask=xbff81c00
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00
+# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x2f009400/mask=xbf80fc00
+# CONSTRUCT x6f009400/mask=xfff8dc00 MATCHED 4 DOCUMENTED OPCODES
+# SMACRO ARG1 Imm_neon_uimm8Shift:2 ~ &=$&
+# SMACRO(pseudo) ARG1 Imm_neon_uimm8Shift:2 &=NEON_bic/2@2
+# AUNIT --inst x6f009400/mask=xfff8dc00 --status pass
+
+:bic Rd_VPR128.8H, abcdefgh
+is b_3131=0 & q=1 & b_29=1 & b_2428=0xf & b_1923=0x0 & abcdefgh & b_1415=2 & Imm_neon_uimm8Shift & b_1012=5 & Rd_VPR128.8H & Zd
+{
+ local tmp1:2 = ~ Imm_neon_uimm8Shift:2;
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H & tmp1 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] & tmp1;
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] & tmp1;
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] & tmp1;
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] & tmp1;
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] & tmp1;
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] & tmp1;
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] & tmp1;
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] & tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.21 BIC (vector, register) page C7-2050 line 119707 MATCH x0e601c00/mask=xbfe0fc00
+# CONSTRUCT x4e601c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $~@1 =$&@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_bic/2@1
+# AUNIT --inst x4e601c00/mask=xffe0fc00 --status pass
+
+:bic Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ # simd unary TMPQ1 = ~(Rm_VPR128.16B) on lane size 1
+ TMPQ1[0,8] = ~(Rm_VPR128.16B[0,8]);
+ TMPQ1[8,8] = ~(Rm_VPR128.16B[8,8]);
+ TMPQ1[16,8] = ~(Rm_VPR128.16B[16,8]);
+ TMPQ1[24,8] = ~(Rm_VPR128.16B[24,8]);
+ TMPQ1[32,8] = ~(Rm_VPR128.16B[32,8]);
+ TMPQ1[40,8] = ~(Rm_VPR128.16B[40,8]);
+ TMPQ1[48,8] = ~(Rm_VPR128.16B[48,8]);
+ TMPQ1[56,8] = ~(Rm_VPR128.16B[56,8]);
+ TMPQ1[64,8] = ~(Rm_VPR128.16B[64,8]);
+ TMPQ1[72,8] = ~(Rm_VPR128.16B[72,8]);
+ TMPQ1[80,8] = ~(Rm_VPR128.16B[80,8]);
+ TMPQ1[88,8] = ~(Rm_VPR128.16B[88,8]);
+ TMPQ1[96,8] = ~(Rm_VPR128.16B[96,8]);
+ TMPQ1[104,8] = ~(Rm_VPR128.16B[104,8]);
+ TMPQ1[112,8] = ~(Rm_VPR128.16B[112,8]);
+ TMPQ1[120,8] = ~(Rm_VPR128.16B[120,8]);
+ # simd infix Rd_VPR128.16B = Rn_VPR128.16B & TMPQ1 on lane size 1
+ Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] & TMPQ1[0,8];
+ Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] & TMPQ1[8,8];
+ Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] & TMPQ1[16,8];
+ Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] & TMPQ1[24,8];
+ Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] & TMPQ1[32,8];
+ Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] & TMPQ1[40,8];
+ Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] & TMPQ1[48,8];
+ Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] & TMPQ1[56,8];
+ Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] & TMPQ1[64,8];
+ Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] & TMPQ1[72,8];
+ Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] & TMPQ1[80,8];
+ Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] & TMPQ1[88,8];
+ Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] & TMPQ1[96,8];
+ Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] & TMPQ1[104,8];
+ Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] & TMPQ1[112,8];
+ Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] & TMPQ1[120,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.21 BIC (vector, register) page C7-2050 line 119707 MATCH x0e601c00/mask=xbfe0fc00
+# CONSTRUCT x0e601c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $~@1 =$&@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_bic/2@1
+# AUNIT --inst x0e601c00/mask=xffe0fc00 --status pass
+
+:bic Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ # simd unary TMPD1 = ~(Rm_VPR64.8B) on lane size 1
+ TMPD1[0,8] = ~(Rm_VPR64.8B[0,8]);
+ TMPD1[8,8] = ~(Rm_VPR64.8B[8,8]);
+ TMPD1[16,8] = ~(Rm_VPR64.8B[16,8]);
+ TMPD1[24,8] = ~(Rm_VPR64.8B[24,8]);
+ TMPD1[32,8] = ~(Rm_VPR64.8B[32,8]);
+ TMPD1[40,8] = ~(Rm_VPR64.8B[40,8]);
+ TMPD1[48,8] = ~(Rm_VPR64.8B[48,8]);
+ TMPD1[56,8] = ~(Rm_VPR64.8B[56,8]);
+ # simd infix Rd_VPR64.8B = Rn_VPR64.8B & TMPD1 on lane size 1
+ Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] & TMPD1[0,8];
+ Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] & TMPD1[8,8];
+ Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] & TMPD1[16,8];
+ Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] & TMPD1[24,8];
+ Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] & TMPD1[32,8];
+ Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] & TMPD1[40,8];
+ Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] & TMPD1[48,8];
+ Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] & TMPD1[56,8];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.22 BIF page C7-2052 line 119791 MATCH x2ee01c00/mask=xbfe0fc00
+# CONSTRUCT x6ee01c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_bif/3@1
+# AUNIT --inst x6ee01c00/mask=xffe0fc00 --status nopcodeop
+
+:bif Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_bif(Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.22 BIF page C7-2052 line 119791 MATCH x2ee01c00/mask=xbfe0fc00
+# CONSTRUCT x2ee01c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_bif/3@1
+# AUNIT --inst x2ee01c00/mask=xffe0fc00 --status nopcodeop
+
+:bif Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_bif(Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.23 BIT page C7-2054 line 119875 MATCH x2ea01c00/mask=xbfe0fc00
+# CONSTRUCT x6ea01c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_bit/3@1
+# AUNIT --inst x6ea01c00/mask=xffe0fc00 --status nopcodeop
+
+:bit Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_bit(Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.23 BIT page C7-2054 line 119875 MATCH x2ea01c00/mask=xbfe0fc00
+# CONSTRUCT x2ea01c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_bit/3@1
+# AUNIT --inst x2ea01c00/mask=xffe0fc00 --status nopcodeop
+
+:bit Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_bit(Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.24 BSL page C7-2056 line 119959 MATCH x2e601c00/mask=xbfe0fc00
+# CONSTRUCT x6e601c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_bsl/3@1
+# AUNIT --inst x6e601c00/mask=xffe0fc00 --status nopcodeop
+
+:bsl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_bsl(Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.24 BSL page C7-2056 line 119959 MATCH x2e601c00/mask=xbfe0fc00
+# CONSTRUCT x2e601c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_bsl/3@1
+# AUNIT --inst x2e601c00/mask=xffe0fc00 --status nopcodeop
+
+:bsl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_bsl(Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.25 CLS (vector) page C7-2058 line 120043 MATCH x0e204800/mask=xbf3ffc00
+# CONSTRUCT x0e204800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_cls/1@1
+# AUNIT --inst x0e204800/mask=xfffffc00 --status nopcodeop
+# CLS (vector) SIMD 8B when size = 00 , Q = 0
+
+:cls Rd_VPR64.8B, Rn_VPR64.8B
+is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000010010 & Rd_VPR64.8B & Rn_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_cls(Rn_VPR64.8B, 1:1);
+}
+
+# C7.2.25 CLS (vector) page C7-2058 line 120043 MATCH x0e204800/mask=xbf3ffc00
+# CONSTRUCT x4e204800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_cls/1@1
+# AUNIT --inst x4e204800/mask=xfffffc00 --status nopcodeop
+# CLS (vector) SIMD 16B when size = 00 , Q = 1
+
+:cls Rd_VPR128.16B, Rn_VPR128.16B
+is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000010010 & Rd_VPR128.16B & Rn_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_cls(Rn_VPR128.16B, 1:1);
+}
+
+# C7.2.25 CLS (vector) page C7-2058 line 120043 MATCH x0e204800/mask=xbf3ffc00
+# CONSTRUCT x0e604800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_cls/1@2
+# AUNIT --inst x0e604800/mask=xfffffc00 --status nopcodeop
+# CLS (vector) SIMD 4H when size = 01 , Q = 0
+
+:cls Rd_VPR64.4H, Rn_VPR64.4H
+is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000010010 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_cls(Rn_VPR64.4H, 2:1);
+}
+
+# C7.2.25 CLS (vector) page C7-2058 line 120043 MATCH x0e204800/mask=xbf3ffc00
+# CONSTRUCT x4e604800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_cls/1@2
+# AUNIT --inst x4e604800/mask=xfffffc00 --status nopcodeop
+# CLS (vector) SIMD 8H when size = 01 , Q = 1
+
+:cls Rd_VPR128.8H, Rn_VPR128.8H
+is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000010010 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_cls(Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.25 CLS (vector) page C7-2058 line 120043 MATCH x0e204800/mask=xbf3ffc00
+# CONSTRUCT x0ea04800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_cls/1@4
+# AUNIT --inst x0ea04800/mask=xfffffc00 --status nopcodeop
+# CLS (vector) SIMD 2S when size = 10 , Q = 0
+
+:cls Rd_VPR64.2S, Rn_VPR64.2S
+is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000010010 & Rd_VPR64.2S & Rn_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_cls(Rn_VPR64.2S, 4:1);
+}
+
+# C7.2.25 CLS (vector) page C7-2058 line 120043 MATCH x0e204800/mask=xbf3ffc00
+# CONSTRUCT x4ea04800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_cls/1@4
+# AUNIT --inst x4ea04800/mask=xfffffc00 --status nopcodeop
+# CLS (vector) SIMD 4S when size = 10 , Q = 1
+
+:cls Rd_VPR128.4S, Rn_VPR128.4S
+is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000010010 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_cls(Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.26 CLZ (vector) page C7-2060 line 120140 MATCH x2e204800/mask=xbf3ffc00
+# CONSTRUCT x2e204800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_clz/1@1
+# AUNIT --inst x2e204800/mask=xfffffc00 --status nopcodeop
+# CLZ (vector) SIMD 8B when size = 00 , Q = 0
+
+:clz Rd_VPR64.8B, Rn_VPR64.8B
+is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000010010 & Rd_VPR64.8B & Rn_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_clz(Rn_VPR64.8B, 1:1);
+}
+
+# C7.2.26 CLZ (vector) page C7-2060 line 120140 MATCH x2e204800/mask=xbf3ffc00
+# CONSTRUCT x6e204800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_clz/1@1
+# AUNIT --inst x6e204800/mask=xfffffc00 --status nopcodeop
+# CLZ (vector) SIMD 16B when size = 00 , Q = 1
+
+:clz Rd_VPR128.16B, Rn_VPR128.16B
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000010010 & Rd_VPR128.16B & Rn_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_clz(Rn_VPR128.16B, 1:1);
+}
+
+# C7.2.26 CLZ (vector) page C7-2060 line 120140 MATCH x2e204800/mask=xbf3ffc00
+# CONSTRUCT x2e604800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_clz/1@2
+# AUNIT --inst x2e604800/mask=xfffffc00 --status nopcodeop
+# CLZ (vector) SIMD 4H when size = 01 , Q = 0
+
+:clz Rd_VPR64.4H, Rn_VPR64.4H
+is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000010010 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_clz(Rn_VPR64.4H, 2:1);
+}
+
+# C7.2.26 CLZ (vector) page C7-2060 line 120140 MATCH x2e204800/mask=xbf3ffc00
+# CONSTRUCT x6e604800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_clz/1@2
+# AUNIT --inst x6e604800/mask=xfffffc00 --status nopcodeop
+# CLZ (vector) SIMD 8H when size = 01 , Q = 1
+
+:clz Rd_VPR128.8H, Rn_VPR128.8H
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000010010 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_clz(Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.26 CLZ (vector) page C7-2060 line 120140 MATCH x2e204800/mask=xbf3ffc00
+# CONSTRUCT x2ea04800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_clz/1@4
+# AUNIT --inst x2ea04800/mask=xfffffc00 --status nopcodeop
+# CLZ (vector) SIMD 2S when size = 10 , Q = 0
+
+:clz Rd_VPR64.2S, Rn_VPR64.2S
+is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000010010 & Rd_VPR64.2S & Rn_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_clz(Rn_VPR64.2S, 4:1);
+}
+
+# C7.2.26 CLZ (vector) page C7-2060 line 120140 MATCH x2e204800/mask=xbf3ffc00
+# CONSTRUCT x6ea04800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_clz/1@4
+# AUNIT --inst x6ea04800/mask=xfffffc00 --status nopcodeop
+# CLZ (vector) SIMD 4S when size = 10 , Q = 1
+
+:clz Rd_VPR128.4S, Rn_VPR128.4S
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000010010 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_clz(Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.27 CMEQ (register) page C7-2062 line 120236 MATCH x7e208c00/mask=xff20fc00
+# CONSTRUCT x7ee08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 dup dup dup ARG2 ARG3 equal:1 zext:8 0:8 ~ =*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2
+# AUNIT --inst x7ee08c00/mask=xffe0fc00 --status pass
+# CMEQ (register) Scalar
+
+:cmeq Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_2431=0b01111110 & b_2223=0b11 & b_21=1 & b_1015=0b100011 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
+{
+ local tmp1:1 = Rn_FPR64 == Rm_FPR64;
+ local tmp2:8 = zext(tmp1);
+ local tmp3:8 = ~ 0:8;
+ Rd_FPR64 = tmp2 * tmp3;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.27 CMEQ (register) page C7-2062 line 120236 MATCH x2e208c00/mask=xbf20fc00
+# CONSTRUCT x2e208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@1
+# AUNIT --inst x2e208c00/mask=xffe0fc00 --status nopcodeop
+# CMEQ (register) SIMD 8B when size = 00 , Q = 0
+
+:cmeq Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b00 & b_21=1 & b_1015=0b100011 & Rd_VPR64.8B & Rn_VPR64.8B & Rm_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_cmeq(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.27 CMEQ (register) page C7-2062 line 120236 MATCH x2e208c00/mask=xbf20fc00
+# CONSTRUCT x6e208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@1
+# AUNIT --inst x6e208c00/mask=xffe0fc00 --status nopcodeop
+# CMEQ (register) SIMD 16B when size = 00 , Q = 1
+
+:cmeq Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b00 & b_21=1 & b_1015=0b100011 & Rd_VPR128.16B & Rn_VPR128.16B & Rm_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_cmeq(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.27 CMEQ (register) page C7-2062 line 120236 MATCH x2e208c00/mask=xbf20fc00
+# CONSTRUCT x2e608c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@2
+# AUNIT --inst x2e608c00/mask=xffe0fc00 --status nopcodeop
+# CMEQ (register) SIMD 4H when size = 01 , Q = 0
+
+:cmeq Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_21=1 & b_1015=0b100011 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_cmeq(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.27 CMEQ (register) page C7-2062 line 120236 MATCH x2e208c00/mask=xbf20fc00
+# CONSTRUCT x6e608c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@2
+# AUNIT --inst x6e608c00/mask=xffe0fc00 --status nopcodeop
+# CMEQ (register) SIMD 8H when size = 01 , Q = 1
+
+:cmeq Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_21=1 & b_1015=0b100011 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_cmeq(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.27 CMEQ (register) page C7-2062 line 120236 MATCH x2e208c00/mask=xbf20fc00
+# CONSTRUCT x2ea08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@4
+# AUNIT --inst x2ea08c00/mask=xffe0fc00 --status nopcodeop
+# CMEQ (register) SIMD 2S when size = 10 , Q = 0
+
+:cmeq Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_21=1 & b_1015=0b100011 & Rd_VPR64.2S & Rn_VPR64.2S & Rm_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_cmeq(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.27 CMEQ (register) page C7-2062 line 120236 MATCH x2e208c00/mask=xbf20fc00
+# CONSTRUCT x6ea08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@4
+# AUNIT --inst x6ea08c00/mask=xffe0fc00 --status nopcodeop
+# CMEQ (register) SIMD 4S when size = 10 , Q = 1
+
+:cmeq Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_21=1 & b_1015=0b100011 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_cmeq(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.27 CMEQ (register) page C7-2062 line 120236 MATCH x2e208c00/mask=xbf20fc00
+# CONSTRUCT x6ee08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmeq/2@8
+# AUNIT --inst x6ee08c00/mask=xffe0fc00 --status nopcodeop
+# CMEQ (register) SIMD 2D when size = 11 , Q = 1
+
+:cmeq Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b11 & b_21=1 & b_1015=0b100011 & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_cmeq(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.28 CMEQ (zero) page C7-2064 line 120376 MATCH x0e209800/mask=xbf3ffc00
+# CONSTRUCT x4e209800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmeq/2@1
+# AUNIT --inst x4e209800/mask=xfffffc00 --status nopcodeop
+
+:cmeq Rd_VPR128.16B, Rn_VPR128.16B, "#0"
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_cmeq(Rn_VPR128.16B, 0:1, 1:1);
+}
+
+# C7.2.28 CMEQ (zero) page C7-2064 line 120376 MATCH x0e209800/mask=xbf3ffc00
+# CONSTRUCT x4ee09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmeq/2@8
+# AUNIT --inst x4ee09800/mask=xfffffc00 --status nopcodeop
+
+:cmeq Rd_VPR128.2D, Rn_VPR128.2D, "#0"
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_cmeq(Rn_VPR128.2D, 0:8, 8:1);
+}
+
+# C7.2.28 CMEQ (zero) page C7-2064 line 120376 MATCH x0e209800/mask=xbf3ffc00
+# CONSTRUCT x0ea09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmeq/2@4
+# AUNIT --inst x0ea09800/mask=xfffffc00 --status nopcodeop
+
+:cmeq Rd_VPR64.2S, Rn_VPR64.2S, "#0"
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_cmeq(Rn_VPR64.2S, 0:4, 4:1);
+}
+
+# C7.2.28 CMEQ (zero) page C7-2064 line 120376 MATCH x0e209800/mask=xbf3ffc00
+# CONSTRUCT x0e609800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmeq/2@2
+# AUNIT --inst x0e609800/mask=xfffffc00 --status nopcodeop
+
+:cmeq Rd_VPR64.4H, Rn_VPR64.4H, "#0"
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_cmeq(Rn_VPR64.4H, 0:2, 2:1);
+}
+
+# C7.2.28 CMEQ (zero) page C7-2064 line 120376 MATCH x0e209800/mask=xbf3ffc00
+# CONSTRUCT x4ea09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmeq/2@2
+# AUNIT --inst x4ea09800/mask=xfffffc00 --status nopcodeop
+
+:cmeq Rd_VPR128.4S, Rn_VPR128.4S, "#0"
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_cmeq(Rn_VPR128.4S, 0:4, 2:1);
+}
+
+# C7.2.28 CMEQ (zero) page C7-2064 line 120376 MATCH x0e209800/mask=xbf3ffc00
+# CONSTRUCT x0e209800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmeq/2@1
+# AUNIT --inst x0e209800/mask=xfffffc00 --status nopcodeop
+
+:cmeq Rd_VPR64.8B, Rn_VPR64.8B, "#0"
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_cmeq(Rn_VPR64.8B, 0:1, 1:1);
+}
+
+# C7.2.28 CMEQ (zero) page C7-2064 line 120376 MATCH x0e209800/mask=xbf3ffc00
+# CONSTRUCT x4e609800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmeq/2@2
+# AUNIT --inst x4e609800/mask=xfffffc00 --status nopcodeop
+
+:cmeq Rd_VPR128.8H, Rn_VPR128.8H, "#0"
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_cmeq(Rn_VPR128.8H, 0:2, 2:1);
+}
+
+# C7.2.28 CMEQ (zero) page C7-2064 line 120376 MATCH x5e209800/mask=xff3ffc00
+# CONSTRUCT x5ee09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmeq/2
+# AUNIT --inst x5ee09800/mask=xfffffc00 --status nopcodeop
+
+:cmeq Rd_FPR64, Rn_FPR64, "#0"
+is b_2431=0b01011110 & b_2223=0b11 & b_1021=0b100000100110 & Rd_FPR64 & Rn_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_cmeq(Rn_FPR64, 0:4);
+}
+
+# C7.2.29 CMGE (register) page C7-2067 line 120534 MATCH x0e203c00/mask=xbf20fc00
+# CONSTRUCT x4e203c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@1
+# AUNIT --inst x4e203c00/mask=xffe0fc00 --status nopcodeop
+
+:cmge Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x7 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_cmge(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.29 CMGE (register) page C7-2067 line 120534 MATCH x0e203c00/mask=xbf20fc00
+# CONSTRUCT x4ee03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@8
+# AUNIT --inst x4ee03c00/mask=xffe0fc00 --status nopcodeop
+
+:cmge Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x7 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_cmge(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.29 CMGE (register) page C7-2067 line 120534 MATCH x0e203c00/mask=xbf20fc00
+# CONSTRUCT x0ea03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@4
+# AUNIT --inst x0ea03c00/mask=xffe0fc00 --status nopcodeop
+
+:cmge Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x7 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_cmge(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.29 CMGE (register) page C7-2067 line 120534 MATCH x0e203c00/mask=xbf20fc00
+# CONSTRUCT x0e603c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@2
+# AUNIT --inst x0e603c00/mask=xffe0fc00 --status nopcodeop
+
+:cmge Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x7 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_cmge(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.29 CMGE (register) page C7-2067 line 120534 MATCH x0e203c00/mask=xbf20fc00
+# CONSTRUCT x4ea03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@4
+# AUNIT --inst x4ea03c00/mask=xffe0fc00 --status nopcodeop
+
+:cmge Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x7 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_cmge(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.29 CMGE (register) page C7-2067 line 120534 MATCH x0e203c00/mask=xbf20fc00
+# CONSTRUCT x0e203c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@1
+# AUNIT --inst x0e203c00/mask=xffe0fc00 --status nopcodeop
+
+:cmge Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x7 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_cmge(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.29 CMGE (register) page C7-2067 line 120534 MATCH x0e203c00/mask=xbf20fc00
+# CONSTRUCT x4e603c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2@2
+# AUNIT --inst x4e603c00/mask=xffe0fc00 --status nopcodeop
+
+:cmge Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x7 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_cmge(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.29 CMGE (register) page C7-2067 line 120534 MATCH x5e203c00/mask=xff20fc00
+# CONSTRUCT x5ee03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmge/2
+# AUNIT --inst x5ee03c00/mask=xffe0fc00 --status nopcodeop
+
+:cmge Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_2431=0b01011110 & b_2223=0b11 & b_21=1 & b_1015=0b001111 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_cmge(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.30 CMGE (zero) page C7-2070 line 120683 MATCH x2e208800/mask=xbf3ffc00
+# CONSTRUCT x6e208800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmge/2@1
+# AUNIT --inst x6e208800/mask=xfffffc00 --status nopcodeop
+
+:cmge Rd_VPR128.16B, Rn_VPR128.16B, "#0"
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_cmge(Rn_VPR128.16B, 0:1, 1:1);
+}
+
+# C7.2.30 CMGE (zero) page C7-2070 line 120683 MATCH x2e208800/mask=xbf3ffc00
+# CONSTRUCT x6ee08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmge/2@8
+# AUNIT --inst x6ee08800/mask=xfffffc00 --status nopcodeop
+
+:cmge Rd_VPR128.2D, Rn_VPR128.2D, "#0"
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_cmge(Rn_VPR128.2D, 0:8, 8:1);
+}
+
+# C7.2.30 CMGE (zero) page C7-2070 line 120683 MATCH x2e208800/mask=xbf3ffc00
+# CONSTRUCT x2ea08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmge/2@4
+# AUNIT --inst x2ea08800/mask=xfffffc00 --status nopcodeop
+
+:cmge Rd_VPR64.2S, Rn_VPR64.2S, "#0"
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_cmge(Rn_VPR64.2S, 0:4, 4:1);
+}
+
+# C7.2.30 CMGE (zero) page C7-2070 line 120683 MATCH x2e208800/mask=xbf3ffc00
+# CONSTRUCT x2e608800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmge/2@2
+# AUNIT --inst x2e608800/mask=xfffffc00 --status nopcodeop
+
+:cmge Rd_VPR64.4H, Rn_VPR64.4H, "#0"
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_cmge(Rn_VPR64.4H, 0:2, 2:1);
+}
+
+# C7.2.30 CMGE (zero) page C7-2070 line 120683 MATCH x2e208800/mask=xbf3ffc00
+# CONSTRUCT x6ea08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmge/2@4
+# AUNIT --inst x6ea08800/mask=xfffffc00 --status nopcodeop
+
+:cmge Rd_VPR128.4S, Rn_VPR128.4S, "#0"
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_cmge(Rn_VPR128.4S, 0:4, 4:1);
+}
+
+# C7.2.30 CMGE (zero) page C7-2070 line 120683 MATCH x2e208800/mask=xbf3ffc00
+# CONSTRUCT x2e208800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmge/2@1
+# AUNIT --inst x2e208800/mask=xfffffc00 --status nopcodeop
+
+:cmge Rd_VPR64.8B, Rn_VPR64.8B, "#0"
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_cmge(Rn_VPR64.8B, 0:1, 1:1);
+}
+
+# C7.2.30 CMGE (zero) page C7-2070 line 120683 MATCH x2e208800/mask=xbf3ffc00
+# CONSTRUCT x6e608800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmge/2@2
+# AUNIT --inst x6e608800/mask=xfffffc00 --status nopcodeop
+
+:cmge Rd_VPR128.8H, Rn_VPR128.8H, "#0"
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_cmge(Rn_VPR128.8H, 0:2, 2:1);
+}
+
+# C7.2.30 CMGE (zero) page C7-2070 line 120683 MATCH x7e208800/mask=xff3ffc00
+# CONSTRUCT x7ee08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmge/2
+# AUNIT --inst x7ee08800/mask=xfffffc00 --status nopcodeop
+
+:cmge Rd_FPR64, Rn_FPR64, "#0"
+is b_2431=0b01111110 & b_2223=0b11 & b_1021=0b100000100010 & Rd_FPR64 & Rn_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_cmge(Rn_FPR64, 0:4);
+}
+
+# C7.2.31 CMGT (register) page C7-2073 line 120841 MATCH x0e203400/mask=xbf20fc00
+# CONSTRUCT x4e203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@1
+# AUNIT --inst x4e203400/mask=xffe0fc00 --status nopcodeop
+
+:cmgt Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x6 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_cmgt(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.31 CMGT (register) page C7-2073 line 120841 MATCH x0e203400/mask=xbf20fc00
+# CONSTRUCT x4ee03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@8
+# AUNIT --inst x4ee03400/mask=xffe0fc00 --status nopcodeop
+
+:cmgt Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x6 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_cmgt(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.31 CMGT (register) page C7-2073 line 120841 MATCH x0e203400/mask=xbf20fc00
+# CONSTRUCT x0ea03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@4
+# AUNIT --inst x0ea03400/mask=xffe0fc00 --status nopcodeop
+
+:cmgt Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x6 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_cmgt(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.31 CMGT (register) page C7-2073 line 120841 MATCH x0e203400/mask=xbf20fc00
+# CONSTRUCT x0e603400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@2
+# AUNIT --inst x0e603400/mask=xffe0fc00 --status nopcodeop
+
+:cmgt Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x6 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_cmgt(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.31 CMGT (register) page C7-2073 line 120841 MATCH x0e203400/mask=xbf20fc00
+# CONSTRUCT x4ea03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@4
+# AUNIT --inst x4ea03400/mask=xffe0fc00 --status nopcodeop
+
+:cmgt Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x6 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_cmgt(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.31 CMGT (register) page C7-2073 line 120841 MATCH x0e203400/mask=xbf20fc00
+# CONSTRUCT x0e203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@1
+# AUNIT --inst x0e203400/mask=xffe0fc00 --status nopcodeop
+
+:cmgt Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x6 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_cmgt(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.31 CMGT (register) page C7-2073 line 120841 MATCH x0e203400/mask=xbf20fc00
+# CONSTRUCT x4e603400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2@2
+# AUNIT --inst x4e603400/mask=xffe0fc00 --status nopcodeop
+
+:cmgt Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x6 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_cmgt(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.31 CMGT (register) page C7-2073 line 120841 MATCH x5e203400/mask=xff20fc00
+# CONSTRUCT x5ee03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmgt/2
+# AUNIT --inst x5ee03400/mask=xffe0fc00 --status nopcodeop
+
+:cmgt Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_2431=0b01011110 & b_2223=0b11 & b_21=1 & b_1015=0b001101 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_cmgt(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.32 CMGT (zero) page C7-2076 line 120990 MATCH x0e208800/mask=xbf3ffc00
+# CONSTRUCT x4e208800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmgt/2@1
+# AUNIT --inst x4e208800/mask=xfffffc00 --status nopcodeop
+
+:cmgt Rd_VPR128.16B, Rn_VPR128.16B, "#0"
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_cmgt(Rn_VPR128.16B, 0:1, 1:1);
+}
+
+# C7.2.32 CMGT (zero) page C7-2076 line 120990 MATCH x0e208800/mask=xbf3ffc00
+# CONSTRUCT x4ee08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmgt/2@8
+# AUNIT --inst x4ee08800/mask=xfffffc00 --status nopcodeop
+
+:cmgt Rd_VPR128.2D, Rn_VPR128.2D, "#0"
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_cmgt(Rn_VPR128.2D, 0:8, 8:1);
+}
+
+# C7.2.32 CMGT (zero) page C7-2076 line 120990 MATCH x0e208800/mask=xbf3ffc00
+# CONSTRUCT x0ea08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmgt/2@4
+# AUNIT --inst x0ea08800/mask=xfffffc00 --status nopcodeop
+
+:cmgt Rd_VPR64.2S, Rn_VPR64.2S, "#0"
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_cmgt(Rn_VPR64.2S, 0:4, 4:1);
+}
+
+# C7.2.32 CMGT (zero) page C7-2076 line 120990 MATCH x0e208800/mask=xbf3ffc00
+# CONSTRUCT x0e608800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmgt/2@2
+# AUNIT --inst x0e608800/mask=xfffffc00 --status nopcodeop
+
+:cmgt Rd_VPR64.4H, Rn_VPR64.4H, "#0"
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_cmgt(Rn_VPR64.4H, 0:2, 2:1);
+}
+
+# C7.2.32 CMGT (zero) page C7-2076 line 120990 MATCH x0e208800/mask=xbf3ffc00
+# CONSTRUCT x4ea08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmgt/2@4
+# AUNIT --inst x4ea08800/mask=xfffffc00 --status nopcodeop
+
+:cmgt Rd_VPR128.4S, Rn_VPR128.4S, "#0"
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_cmgt(Rn_VPR128.4S, 0:4, 4:1);
+}
+
+# C7.2.32 CMGT (zero) page C7-2076 line 120990 MATCH x0e208800/mask=xbf3ffc00
+# CONSTRUCT x0e208800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmgt/2@1
+# AUNIT --inst x0e208800/mask=xfffffc00 --status nopcodeop
+
+:cmgt Rd_VPR64.8B, Rn_VPR64.8B, "#0"
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_cmgt(Rn_VPR64.8B, 0:1, 1:1);
+}
+
+# C7.2.32 CMGT (zero) page C7-2076 line 120990 MATCH x0e208800/mask=xbf3ffc00
+# CONSTRUCT x4e608800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmgt/2@2
+# AUNIT --inst x4e608800/mask=xfffffc00 --status nopcodeop
+
+:cmgt Rd_VPR128.8H, Rn_VPR128.8H, "#0"
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x8 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_cmgt(Rn_VPR128.8H, 0:2, 2:1);
+}
+
+# C7.2.32 CMGT (zero) page C7-2076 line 120990 MATCH x5e208800/mask=xff3ffc00
+# CONSTRUCT x5ee08800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmgt/2
+# AUNIT --inst x5ee08800/mask=xfffffc00 --status nopcodeop
+
+:cmgt Rd_FPR64, Rn_FPR64, "#0"
+is b_2431=0b01011110 & b_2223=0b11 & b_1021=0b100000100010 & Rd_FPR64 & Rn_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_cmgt(Rn_FPR64, 0:8);
+}
+
+# C7.2.33 CMHI (register) page C7-2079 line 121148 MATCH x2e203400/mask=xbf20fc00
+# CONSTRUCT x6e203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@1
+# AUNIT --inst x6e203400/mask=xffe0fc00 --status nopcodeop
+
+:cmhi Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x6 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_cmhi(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.33 CMHI (register) page C7-2079 line 121148 MATCH x2e203400/mask=xbf20fc00
+# CONSTRUCT x6ee03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@8
+# AUNIT --inst x6ee03400/mask=xffe0fc00 --status nopcodeop
+
+:cmhi Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x6 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_cmhi(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.33 CMHI (register) page C7-2079 line 121148 MATCH x2e203400/mask=xbf20fc00
+# CONSTRUCT x2ea03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@4
+# AUNIT --inst x2ea03400/mask=xffe0fc00 --status nopcodeop
+
+:cmhi Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x6 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_cmhi(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.33 CMHI (register) page C7-2079 line 121148 MATCH x2e203400/mask=xbf20fc00
+# CONSTRUCT x2e603400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@2
+# AUNIT --inst x2e603400/mask=xffe0fc00 --status nopcodeop
+
+:cmhi Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x6 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_cmhi(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.33 CMHI (register) page C7-2079 line 121148 MATCH x2e203400/mask=xbf20fc00
+# CONSTRUCT x6ea03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@4
+# AUNIT --inst x6ea03400/mask=xffe0fc00 --status nopcodeop
+
+:cmhi Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x6 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_cmhi(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.33 CMHI (register) page C7-2079 line 121148 MATCH x2e203400/mask=xbf20fc00
+# CONSTRUCT x2e203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@1
+# AUNIT --inst x2e203400/mask=xffe0fc00 --status nopcodeop
+
+:cmhi Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x6 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_cmhi(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.33 CMHI (register) page C7-2079 line 121148 MATCH x2e203400/mask=xbf20fc00
+# CONSTRUCT x6e603400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2@2
+# AUNIT --inst x6e603400/mask=xffe0fc00 --status nopcodeop
+
+:cmhi Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x6 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_cmhi(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.33 CMHI (register) page C7-2079 line 121148 MATCH x7e203400/mask=xff20fc00
+# CONSTRUCT x7ee03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhi/2
+# AUNIT --inst x7ee03400/mask=xffe0fc00 --status nopcodeop
+
+:cmhi Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_2431=0b01111110 & b_2223=0b11 & b_21=1 & b_1015=0b001101 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_cmhi(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.34 CMHS (register) page C7-2082 line 121297 MATCH x2e203c00/mask=xbf20fc00
+# CONSTRUCT x6e203c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@1
+# AUNIT --inst x6e203c00/mask=xffe0fc00 --status nopcodeop
+
+:cmhs Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x7 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_cmhs(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.34 CMHS (register) page C7-2082 line 121297 MATCH x2e203c00/mask=xbf20fc00
+# CONSTRUCT x6ee03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@8
+# AUNIT --inst x6ee03c00/mask=xffe0fc00 --status nopcodeop
+
+:cmhs Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x7 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_cmhs(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.34 CMHS (register) page C7-2082 line 121297 MATCH x2e203c00/mask=xbf20fc00
+# CONSTRUCT x2ea03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@4
+# AUNIT --inst x2ea03c00/mask=xffe0fc00 --status nopcodeop
+
+:cmhs Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x7 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_cmhs(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.34 CMHS (register) page C7-2082 line 121297 MATCH x2e203c00/mask=xbf20fc00
+# CONSTRUCT x2e603c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@2
+# AUNIT --inst x2e603c00/mask=xffe0fc00 --status nopcodeop
+
+:cmhs Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x7 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_cmhs(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.34 CMHS (register) page C7-2082 line 121297 MATCH x2e203c00/mask=xbf20fc00
+# CONSTRUCT x6ea03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@4
+# AUNIT --inst x6ea03c00/mask=xffe0fc00 --status nopcodeop
+
+:cmhs Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x7 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_cmhs(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.34 CMHS (register) page C7-2082 line 121297 MATCH x2e203c00/mask=xbf20fc00
+# CONSTRUCT x2e203c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@1
+# AUNIT --inst x2e203c00/mask=xffe0fc00 --status nopcodeop
+
+:cmhs Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x7 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_cmhs(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.34 CMHS (register) page C7-2082 line 121297 MATCH x2e203c00/mask=xbf20fc00
+# CONSTRUCT x6e603c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2@2
+# AUNIT --inst x6e603c00/mask=xffe0fc00 --status nopcodeop
+
+:cmhs Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x7 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_cmhs(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.34 CMHS (register) page C7-2082 line 121297 MATCH x7e203c00/mask=xff20fc00
+# CONSTRUCT x7ee03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmhs/2
+# AUNIT --inst x7ee03c00/mask=xffe0fc00 --status nopcodeop
+
+:cmhs Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_2431=0b01111110 & b_2223=0b11 & b_21=1 & b_1015=0b001111 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_cmhs(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.35 CMLE (zero) page C7-2085 line 121446 MATCH x2e209800/mask=xbf3ffc00
+# CONSTRUCT x6e209800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmle/2@1
+# AUNIT --inst x6e209800/mask=xfffffc00 --status nopcodeop
+
+:cmle Rd_VPR128.16B, Rn_VPR128.16B, "#0"
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_cmle(Rn_VPR128.16B, 0:1, 1:1);
+}
+
+# C7.2.35 CMLE (zero) page C7-2085 line 121446 MATCH x2e209800/mask=xbf3ffc00
+# CONSTRUCT x6ee09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmle/2@8
+# AUNIT --inst x6ee09800/mask=xfffffc00 --status nopcodeop
+
+:cmle Rd_VPR128.2D, Rn_VPR128.2D, "#0"
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_cmle(Rn_VPR128.2D, 0:8, 8:1);
+}
+
+# C7.2.35 CMLE (zero) page C7-2085 line 121446 MATCH x2e209800/mask=xbf3ffc00
+# CONSTRUCT x2ea09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmle/2@4
+# AUNIT --inst x2ea09800/mask=xfffffc00 --status nopcodeop
+
+:cmle Rd_VPR64.2S, Rn_VPR64.2S, "#0"
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_cmle(Rn_VPR64.2S, 0:4, 4:1);
+}
+
+# C7.2.35 CMLE (zero) page C7-2085 line 121446 MATCH x2e209800/mask=xbf3ffc00
+# CONSTRUCT x2e609800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmle/2@2
+# AUNIT --inst x2e609800/mask=xfffffc00 --status nopcodeop
+
+:cmle Rd_VPR64.4H, Rn_VPR64.4H, "#0"
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_cmle(Rn_VPR64.4H, 0:2, 2:1);
+}
+
+# C7.2.35 CMLE (zero) page C7-2085 line 121446 MATCH x2e209800/mask=xbf3ffc00
+# CONSTRUCT x6ea09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmle/2@4
+# AUNIT --inst x6ea09800/mask=xfffffc00 --status nopcodeop
+
+:cmle Rd_VPR128.4S, Rn_VPR128.4S, "#0"
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_cmle(Rn_VPR128.4S, 0:4, 4:1);
+}
+
+# C7.2.35 CMLE (zero) page C7-2085 line 121446 MATCH x2e209800/mask=xbf3ffc00
+# CONSTRUCT x2e209800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmle/2@1
+# AUNIT --inst x2e209800/mask=xfffffc00 --status nopcodeop
+
+:cmle Rd_VPR64.8B, Rn_VPR64.8B, "#0"
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_cmle(Rn_VPR64.8B, 0:1, 1:1);
+}
+
+# C7.2.35 CMLE (zero) page C7-2085 line 121446 MATCH x2e209800/mask=xbf3ffc00
+# CONSTRUCT x6e609800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmle/2@2
+# AUNIT --inst x6e609800/mask=xfffffc00 --status nopcodeop
+
+:cmle Rd_VPR128.8H, Rn_VPR128.8H, "#0"
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x9 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_cmle(Rn_VPR128.8H, 0:2, 2:1);
+}
+
+# C7.2.35 CMLE (zero) page C7-2085 line 121446 MATCH x7e209800/mask=xff3ffc00
+# CONSTRUCT x7ee09800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmle/2
+# AUNIT --inst x7ee09800/mask=xfffffc00 --status nopcodeop
+
+:cmle Rd_FPR64, Rn_FPR64, "#0"
+is b_2431=0b01111110 & b_2223=0b11 & b_1021=0b100000100110 & Rd_FPR64 & Rn_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_cmle(Rn_FPR64, 0:8);
+}
+
+# C7.2.36 CMLT (zero) page C7-2088 line 121604 MATCH x0e20a800/mask=xbf3ffc00
+# CONSTRUCT x4e20a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmlt/2@1
+# AUNIT --inst x4e20a800/mask=xfffffc00 --status nopcodeop
+
+:cmlt Rd_VPR128.16B, Rn_VPR128.16B, "#0"
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_cmlt(Rn_VPR128.16B, 0:1, 1:1);
+}
+
+# C7.2.36 CMLT (zero) page C7-2088 line 121604 MATCH x0e20a800/mask=xbf3ffc00
+# CONSTRUCT x4ee0a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmlt/2@8
+# AUNIT --inst x4ee0a800/mask=xfffffc00 --status nopcodeop
+
+:cmlt Rd_VPR128.2D, Rn_VPR128.2D, "#0"
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_cmlt(Rn_VPR128.2D, 0:8, 8:1);
+}
+
+# C7.2.36 CMLT (zero) page C7-2088 line 121604 MATCH x0e20a800/mask=xbf3ffc00
+# CONSTRUCT x0ea0a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmlt/2@4
+# AUNIT --inst x0ea0a800/mask=xfffffc00 --status nopcodeop
+
+:cmlt Rd_VPR64.2S, Rn_VPR64.2S, "#0"
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_cmlt(Rn_VPR64.2S, 0:4, 4:1);
+}
+
+# C7.2.36 CMLT (zero) page C7-2088 line 121604 MATCH x0e20a800/mask=xbf3ffc00
+# CONSTRUCT x0e60a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmlt/2@2
+# AUNIT --inst x0e60a800/mask=xfffffc00 --status nopcodeop
+
+:cmlt Rd_VPR64.4H, Rn_VPR64.4H, "#0"
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_cmlt(Rn_VPR64.4H, 0:2, 2:1);
+}
+
+# C7.2.36 CMLT (zero) page C7-2088 line 121604 MATCH x0e20a800/mask=xbf3ffc00
+# CONSTRUCT x4ea0a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_cmlt/2@4
+# AUNIT --inst x4ea0a800/mask=xfffffc00 --status nopcodeop
+
+:cmlt Rd_VPR128.4S, Rn_VPR128.4S, "#0"
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_cmlt(Rn_VPR128.4S, 0:4, 4:1);
+}
+
+# C7.2.36 CMLT (zero) page C7-2088 line 121604 MATCH x0e20a800/mask=xbf3ffc00
+# CONSTRUCT x0e20a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:1 =NEON_cmlt/2@1
+# AUNIT --inst x0e20a800/mask=xfffffc00 --status nopcodeop
+
+:cmlt Rd_VPR64.8B, Rn_VPR64.8B, "#0"
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_cmlt(Rn_VPR64.8B, 0:1, 1:1);
+}
+
+# C7.2.36 CMLT (zero) page C7-2088 line 121604 MATCH x0e20a800/mask=xbf3ffc00
+# CONSTRUCT x4e60a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_cmlt/2@2
+# AUNIT --inst x4e60a800/mask=xfffffc00 --status nopcodeop
+
+:cmlt Rd_VPR128.8H, Rn_VPR128.8H, "#0"
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0xa & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_cmlt(Rn_VPR128.8H, 0:2, 2:1);
+}
+
+# C7.2.36 CMLT (zero) page C7-2088 line 121604 MATCH x5e20a800/mask=xff3ffc00
+# CONSTRUCT x5ee0a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_cmlt/2
+# AUNIT --inst x5ee0a800/mask=xfffffc00 --status nopcodeop
+
+:cmlt Rd_FPR64, Rn_FPR64, "#0"
+is b_2431=0b01011110 & b_2223=0b11 & b_1021=0b100000101010 & Rd_FPR64 & Rn_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_cmlt(Rn_FPR64, 0:8);
+}
+
+# C7.2.37 CMTST page C7-2090 line 121743 MATCH x0e208c00/mask=xbf20fc00
+# CONSTRUCT x4e208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@1
+# AUNIT --inst x4e208c00/mask=xffe0fc00 --status nopcodeop
+
+:cmtst Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x11 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_cmtst(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.37 CMTST page C7-2090 line 121743 MATCH x0e208c00/mask=xbf20fc00
+# CONSTRUCT x4ee08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@8
+# AUNIT --inst x4ee08c00/mask=xffe0fc00 --status nopcodeop
+
+:cmtst Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x11 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_cmtst(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.37 CMTST page C7-2090 line 121743 MATCH x0e208c00/mask=xbf20fc00
+# CONSTRUCT x0ea08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@4
+# AUNIT --inst x0ea08c00/mask=xffe0fc00 --status nopcodeop
+
+:cmtst Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x11 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_cmtst(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.37 CMTST page C7-2090 line 121743 MATCH x0e208c00/mask=xbf20fc00
+# CONSTRUCT x0e608c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@2
+# AUNIT --inst x0e608c00/mask=xffe0fc00 --status nopcodeop
+
+:cmtst Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x11 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_cmtst(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.37 CMTST page C7-2090 line 121743 MATCH x0e208c00/mask=xbf20fc00
+# CONSTRUCT x4ea08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@4
+# AUNIT --inst x4ea08c00/mask=xffe0fc00 --status nopcodeop
+
+:cmtst Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x11 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_cmtst(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.37 CMTST page C7-2090 line 121743 MATCH x0e208c00/mask=xbf20fc00
+# CONSTRUCT x0e208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@1
+# AUNIT --inst x0e208c00/mask=xffe0fc00 --status nopcodeop
+
+:cmtst Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x11 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_cmtst(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.37 CMTST page C7-2090 line 121743 MATCH x0e208c00/mask=xbf20fc00
+# CONSTRUCT x4e608c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2@2
+# AUNIT --inst x4e608c00/mask=xffe0fc00 --status nopcodeop
+
+:cmtst Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x11 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_cmtst(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.37 CMTST page C7-2090 line 121743 MATCH x5e208c00/mask=xff20fc00
+# CONSTRUCT x5ee08c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_cmtst/2
+# AUNIT --inst x5ee08c00/mask=xffe0fc00 --status nopcodeop
+
+:cmtst Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_2431=0b01011110 & b_2223=0b11 & b_21=1 & b_1015=0b100011 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_cmtst(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.38 CNT page C7-2092 line 121883 MATCH x0e205800/mask=xbf3ffc00
+# CONSTRUCT x4e205800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_cnt/1@1
+# AUNIT --inst x4e205800/mask=xfffffc00 --status nopcodeop
+
+:cnt Rd_VPR128.16B, Rn_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x5 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_cnt(Rn_VPR128.16B, 1:1);
+}
+
+# C7.2.38 CNT page C7-2092 line 121883 MATCH x0e205800/mask=xbf3ffc00
+# CONSTRUCT x0e205800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_cnt/1@1
+# AUNIT --inst x0e205800/mask=xfffffc00 --status nopcodeop
+
+:cnt Rd_VPR64.8B, Rn_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x5 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_cnt(Rn_VPR64.8B, 1:1);
+}
+
+# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x0e000400/mask=xbfe0fc00
+# CONSTRUCT x4e010400/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 &=$dup
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@1
+# AUNIT --inst x4e010400/mask=xffe1fc00 --status pass
+
+:dup Rd_VPR128.16B, Rn_VPR128.B.imm_neon_uimm4
+is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR128.16B & Zd
+{
+ # simd element Rn_VPR128[imm_neon_uimm4] lane size 1
+ local tmp1:1 = Rn_VPR128.B.imm_neon_uimm4;
+ # simd duplicate Rd_VPR128.16B = all elements tmp1 (lane size 1)
+ Rd_VPR128.16B[0,8] = tmp1;
+ Rd_VPR128.16B[8,8] = tmp1;
+ Rd_VPR128.16B[16,8] = tmp1;
+ Rd_VPR128.16B[24,8] = tmp1;
+ Rd_VPR128.16B[32,8] = tmp1;
+ Rd_VPR128.16B[40,8] = tmp1;
+ Rd_VPR128.16B[48,8] = tmp1;
+ Rd_VPR128.16B[56,8] = tmp1;
+ Rd_VPR128.16B[64,8] = tmp1;
+ Rd_VPR128.16B[72,8] = tmp1;
+ Rd_VPR128.16B[80,8] = tmp1;
+ Rd_VPR128.16B[88,8] = tmp1;
+ Rd_VPR128.16B[96,8] = tmp1;
+ Rd_VPR128.16B[104,8] = tmp1;
+ Rd_VPR128.16B[112,8] = tmp1;
+ Rd_VPR128.16B[120,8] = tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x0e000400/mask=xbfe0fc00
+# CONSTRUCT x4e080400/mask=xffeffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 &=$dup
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@8
+# AUNIT --inst x4e080400/mask=xffeffc00 --status pass
+
+:dup Rd_VPR128.2D, Rn_VPR128.D.imm_neon_uimm1
+is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.D.imm_neon_uimm1 & b_1619=0x8 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR128.2D & Zd
+{
+ # simd element Rn_VPR128[imm_neon_uimm1] lane size 8
+ local tmp1:8 = Rn_VPR128.D.imm_neon_uimm1;
+ # simd duplicate Rd_VPR128.2D = all elements tmp1 (lane size 8)
+ Rd_VPR128.2D[0,64] = tmp1;
+ Rd_VPR128.2D[64,64] = tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x0e000400/mask=xbfe0fc00
+# CONSTRUCT x0e040400/mask=xffe7fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 &=$dup
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@4
+# AUNIT --inst x0e040400/mask=xffe7fc00 --status pass
+
+:dup Rd_VPR64.2S, Rn_VPR128.S.imm_neon_uimm2
+is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR64.2S & Zd
+{
+ # simd element Rn_VPR128[imm_neon_uimm2] lane size 4
+ local tmp1:4 = Rn_VPR128.S.imm_neon_uimm2;
+ # simd duplicate Rd_VPR64.2S = all elements tmp1 (lane size 4)
+ Rd_VPR64.2S[0,32] = tmp1;
+ Rd_VPR64.2S[32,32] = tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x0e000400/mask=xbfe0fc00
+# CONSTRUCT x0e020400/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 &=$dup
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@2
+# AUNIT --inst x0e020400/mask=xffe3fc00 --status pass
+
+:dup Rd_VPR64.4H, Rn_VPR128.H.imm_neon_uimm3
+is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR64.4H & Zd
+{
+ # simd element Rn_VPR128[imm_neon_uimm3] lane size 2
+ local tmp1:2 = Rn_VPR128.H.imm_neon_uimm3;
+ # simd duplicate Rd_VPR64.4H = all elements tmp1 (lane size 2)
+ Rd_VPR64.4H[0,16] = tmp1;
+ Rd_VPR64.4H[16,16] = tmp1;
+ Rd_VPR64.4H[32,16] = tmp1;
+ Rd_VPR64.4H[48,16] = tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x0e000400/mask=xbfe0fc00
+# CONSTRUCT x4e040400/mask=xffe7fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 &=$dup
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@4
+# AUNIT --inst x4e040400/mask=xffe7fc00 --status pass
+
+:dup Rd_VPR128.4S, Rn_VPR128.S.imm_neon_uimm2
+is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR128.4S & Zd
+{
+ # simd element Rn_VPR128[imm_neon_uimm2] lane size 4
+ local tmp1:4 = Rn_VPR128.S.imm_neon_uimm2;
+ # simd duplicate Rd_VPR128.4S = all elements tmp1 (lane size 4)
+ Rd_VPR128.4S[0,32] = tmp1;
+ Rd_VPR128.4S[32,32] = tmp1;
+ Rd_VPR128.4S[64,32] = tmp1;
+ Rd_VPR128.4S[96,32] = tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x0e000400/mask=xbfe0fc00
+# CONSTRUCT x0e010400/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 &=$dup
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@1
+# AUNIT --inst x0e010400/mask=xffe1fc00 --status pass
+
+:dup Rd_VPR64.8B, Rn_VPR128.B.imm_neon_uimm4
+is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR64.8B & Zd
+{
+ # simd element Rn_VPR128[imm_neon_uimm4] lane size 1
+ local tmp1:1 = Rn_VPR128.B.imm_neon_uimm4;
+ # simd duplicate Rd_VPR64.8B = all elements tmp1 (lane size 1)
+ Rd_VPR64.8B[0,8] = tmp1;
+ Rd_VPR64.8B[8,8] = tmp1;
+ Rd_VPR64.8B[16,8] = tmp1;
+ Rd_VPR64.8B[24,8] = tmp1;
+ Rd_VPR64.8B[32,8] = tmp1;
+ Rd_VPR64.8B[40,8] = tmp1;
+ Rd_VPR64.8B[48,8] = tmp1;
+ Rd_VPR64.8B[56,8] = tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x0e000400/mask=xbfe0fc00
+# CONSTRUCT x4e020400/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 &=$dup
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@2
+# AUNIT --inst x4e020400/mask=xffe3fc00 --status pass
+
+:dup Rd_VPR128.8H, Rn_VPR128.H.imm_neon_uimm3
+is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_VPR128.8H & Zd
+{
+ # simd element Rn_VPR128[imm_neon_uimm3] lane size 2
+ local tmp1:2 = Rn_VPR128.H.imm_neon_uimm3;
+ # simd duplicate Rd_VPR128.8H = all elements tmp1 (lane size 2)
+ Rd_VPR128.8H[0,16] = tmp1;
+ Rd_VPR128.8H[16,16] = tmp1;
+ Rd_VPR128.8H[32,16] = tmp1;
+ Rd_VPR128.8H[48,16] = tmp1;
+ Rd_VPR128.8H[64,16] = tmp1;
+ Rd_VPR128.8H[80,16] = tmp1;
+ Rd_VPR128.8H[96,16] = tmp1;
+ Rd_VPR128.8H[112,16] = tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x5e000400/mask=xffe0fc00
+# C7.2.199 MOV (scalar) page C7-2481 line 145318 MATCH x5e000400/mask=xffe0fc00
+# CONSTRUCT x5e010400/mask=xffe1fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 =ARG2
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@1
+# AUNIT --inst x5e010400/mask=xffe1fc00 --status pass
+
+:dup Rd_FPR8, Rn_VPR128.B.imm_neon_uimm4
+is b_3131=0 & q=1 & b_29=0 & b_2428=0x1e & b_2123=0 & Rn_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_FPR8 & Zd
+{
+ # simd element Rn_VPR128[imm_neon_uimm4] lane size 1
+ Rd_FPR8 = Rn_VPR128.B.imm_neon_uimm4;
+ zext_zb(Zd); # zero upper 31 bytes of Zd
+}
+
+# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x5e000400/mask=xffe0fc00
+# C7.2.199 MOV (scalar) page C7-2481 line 145318 MATCH x5e000400/mask=xffe0fc00
+# CONSTRUCT x5e080400/mask=xffeffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 =ARG2
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@8
+# AUNIT --inst x5e080400/mask=xffeffc00 --status pass
+
+:dup Rd_FPR64, Rn_VPR128.D.imm_neon_uimm1
+is b_3131=0 & q=1 & b_29=0 & b_2428=0x1e & b_2123=0 & Rn_VPR128.D.imm_neon_uimm1 & b_1619=0x8 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_FPR64 & Zd
+{
+ # simd element Rn_VPR128[imm_neon_uimm1] lane size 8
+ Rd_FPR64 = Rn_VPR128.D.imm_neon_uimm1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x5e000400/mask=xffe0fc00
+# C7.2.199 MOV (scalar) page C7-2481 line 145318 MATCH x5e000400/mask=xffe0fc00
+# CONSTRUCT x5e020400/mask=xffe3fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 =ARG2
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@2
+# AUNIT --inst x5e020400/mask=xffe3fc00 --status pass
+
+:dup Rd_FPR16, Rn_VPR128.H.imm_neon_uimm3
+is b_3131=0 & q=1 & b_29=0 & b_2428=0x1e & b_2123=0 & Rn_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_FPR16 & Zd
+{
+ # simd element Rn_VPR128[imm_neon_uimm3] lane size 2
+ Rd_FPR16 = Rn_VPR128.H.imm_neon_uimm3;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.39 DUP (element) page C7-2094 line 121971 MATCH x5e000400/mask=xffe0fc00
+# C7.2.199 MOV (scalar) page C7-2481 line 145318 MATCH x5e000400/mask=xffe0fc00
+# CONSTRUCT x5e040400/mask=xffe7fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 =ARG2
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@4
+# AUNIT --inst x5e040400/mask=xffe7fc00 --status pass
+
+:dup Rd_FPR32, Rn_VPR128.S.imm_neon_uimm2
+is b_3131=0 & q=1 & b_29=0 & b_2428=0x1e & b_2123=0 & Rn_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & imm4=0x0 & b_1010=1 & Rn_VPR128 & Rd_FPR32 & Zd
+{
+ # simd element Rn_VPR128[imm_neon_uimm2] lane size 4
+ Rd_FPR32 = Rn_VPR128.S.imm_neon_uimm2;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.40 DUP (general) page C7-2097 line 122143 MATCH x0e000c00/mask=xbfe0fc00
+# CONSTRUCT x4e010c00/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(force-primitive) ARG1 ARG2[0]:1 &=$dup
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@1
+# AUNIT --inst x4e010c00/mask=xffe1fc00 --status pass
+
+:dup Rd_VPR128.16B, Rn_GPR32
+is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & b_16=1 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR32 & Rd_VPR128.16B & Zd
+{
+ local tmp1:1 = Rn_GPR32[0,8];
+ # simd duplicate Rd_VPR128.16B = all elements tmp1 (lane size 1)
+ Rd_VPR128.16B[0,8] = tmp1;
+ Rd_VPR128.16B[8,8] = tmp1;
+ Rd_VPR128.16B[16,8] = tmp1;
+ Rd_VPR128.16B[24,8] = tmp1;
+ Rd_VPR128.16B[32,8] = tmp1;
+ Rd_VPR128.16B[40,8] = tmp1;
+ Rd_VPR128.16B[48,8] = tmp1;
+ Rd_VPR128.16B[56,8] = tmp1;
+ Rd_VPR128.16B[64,8] = tmp1;
+ Rd_VPR128.16B[72,8] = tmp1;
+ Rd_VPR128.16B[80,8] = tmp1;
+ Rd_VPR128.16B[88,8] = tmp1;
+ Rd_VPR128.16B[96,8] = tmp1;
+ Rd_VPR128.16B[104,8] = tmp1;
+ Rd_VPR128.16B[112,8] = tmp1;
+ Rd_VPR128.16B[120,8] = tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.40 DUP (general) page C7-2097 line 122143 MATCH x0e000c00/mask=xbfe0fc00
+# CONSTRUCT x4e080c00/mask=xffeffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 &=$dup
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@8
+# AUNIT --inst x4e080c00/mask=xffeffc00 --status pass
+
+:dup Rd_VPR128.2D, Rn_GPR64
+is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & b_1619=0b1000 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR64 & Rd_VPR128.2D & Zd
+{
+ # simd duplicate Rd_VPR128.2D = all elements Rn_GPR64 (lane size 8)
+ Rd_VPR128.2D[0,64] = Rn_GPR64;
+ Rd_VPR128.2D[64,64] = Rn_GPR64;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.40 DUP (general) page C7-2097 line 122143 MATCH x0e000c00/mask=xbfe0fc00
+# CONSTRUCT x0e040c00/mask=xffe7fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 &=$dup
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@4
+# AUNIT --inst x0e040c00/mask=xffe7fc00 --status pass
+
+:dup Rd_VPR64.2S, Rn_GPR32
+is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & b_1618=0b100 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR32 & Rd_VPR64.2S & Zd
+{
+ # simd duplicate Rd_VPR64.2S = all elements Rn_GPR32 (lane size 4)
+ Rd_VPR64.2S[0,32] = Rn_GPR32;
+ Rd_VPR64.2S[32,32] = Rn_GPR32;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.40 DUP (general) page C7-2097 line 122143 MATCH x0e000c00/mask=xbfe0fc00
+# CONSTRUCT x0e020c00/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[0]:2 &=$dup
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@2
+# AUNIT --inst x0e020c00/mask=xffe3fc00 --status pass
+
+:dup Rd_VPR64.4H, Rn_GPR32
+is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & b_1617=0b10 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR32 & Rd_VPR64.4H & Zd
+{
+ local tmp1:2 = Rn_GPR32[0,16];
+ # simd duplicate Rd_VPR64.4H = all elements tmp1 (lane size 2)
+ Rd_VPR64.4H[0,16] = tmp1;
+ Rd_VPR64.4H[16,16] = tmp1;
+ Rd_VPR64.4H[32,16] = tmp1;
+ Rd_VPR64.4H[48,16] = tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.40 DUP (general) page C7-2097 line 122143 MATCH x0e000c00/mask=xbfe0fc00
+# CONSTRUCT x4e040c00/mask=xffe7fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 &=$dup
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@4
+# AUNIT --inst x4e040c00/mask=xffe7fc00 --status pass
+
+:dup Rd_VPR128.4S, Rn_GPR32
+is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & b_1618=0b100 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR32 & Rd_VPR128.4S & Zd
+{
+ # simd duplicate Rd_VPR128.4S = all elements Rn_GPR32 (lane size 4)
+ Rd_VPR128.4S[0,32] = Rn_GPR32;
+ Rd_VPR128.4S[32,32] = Rn_GPR32;
+ Rd_VPR128.4S[64,32] = Rn_GPR32;
+ Rd_VPR128.4S[96,32] = Rn_GPR32;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.40 DUP (general) page C7-2097 line 122143 MATCH x0e000c00/mask=xbfe0fc00
+# CONSTRUCT x0e010c00/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[0]:1 &=$dup
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@1
+# AUNIT --inst x0e010c00/mask=xffe1fc00 --status pass
+
+:dup Rd_VPR64.8B, Rn_GPR32
+is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & b_16=1 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR32 & Rd_VPR64.8B & Zd
+{
+ local tmp1:1 = Rn_GPR32[0,8];
+ # simd duplicate Rd_VPR64.8B = all elements tmp1 (lane size 1)
+ Rd_VPR64.8B[0,8] = tmp1;
+ Rd_VPR64.8B[8,8] = tmp1;
+ Rd_VPR64.8B[16,8] = tmp1;
+ Rd_VPR64.8B[24,8] = tmp1;
+ Rd_VPR64.8B[32,8] = tmp1;
+ Rd_VPR64.8B[40,8] = tmp1;
+ Rd_VPR64.8B[48,8] = tmp1;
+ Rd_VPR64.8B[56,8] = tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.40 DUP (general) page C7-2097 line 122143 MATCH x0e000c00/mask=xbfe0fc00
+# CONSTRUCT x4e020c00/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[0]:2 &=$dup
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_dup/2@2
+# AUNIT --inst x4e020c00/mask=xffe3fc00 --status pass
+
+:dup Rd_VPR128.8H, Rn_GPR32
+is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & b_1617=0b10 & b_1515=0 & imm4=0x1 & b_1010=1 & Rn_GPR32 & Rd_VPR128.8H & Zd
+{
+ local tmp1:2 = Rn_GPR32[0,16];
+ # simd duplicate Rd_VPR128.8H = all elements tmp1 (lane size 2)
+ Rd_VPR128.8H[0,16] = tmp1;
+ Rd_VPR128.8H[16,16] = tmp1;
+ Rd_VPR128.8H[32,16] = tmp1;
+ Rd_VPR128.8H[48,16] = tmp1;
+ Rd_VPR128.8H[64,16] = tmp1;
+ Rd_VPR128.8H[80,16] = tmp1;
+ Rd_VPR128.8H[96,16] = tmp1;
+ Rd_VPR128.8H[112,16] = tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.41 EOR (vector) page C7-2099 line 122248 MATCH x2e201c00/mask=xbfe0fc00
+# CONSTRUCT x6e201c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$^@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_eor/2@1
+# AUNIT --inst x6e201c00/mask=xffe0fc00 --status pass
+
+:eor Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ # simd infix Rd_VPR128.16B = Rn_VPR128.16B ^ Rm_VPR128.16B on lane size 1
+ Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] ^ Rm_VPR128.16B[0,8];
+ Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] ^ Rm_VPR128.16B[8,8];
+ Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] ^ Rm_VPR128.16B[16,8];
+ Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] ^ Rm_VPR128.16B[24,8];
+ Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] ^ Rm_VPR128.16B[32,8];
+ Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] ^ Rm_VPR128.16B[40,8];
+ Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] ^ Rm_VPR128.16B[48,8];
+ Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] ^ Rm_VPR128.16B[56,8];
+ Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] ^ Rm_VPR128.16B[64,8];
+ Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] ^ Rm_VPR128.16B[72,8];
+ Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] ^ Rm_VPR128.16B[80,8];
+ Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] ^ Rm_VPR128.16B[88,8];
+ Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] ^ Rm_VPR128.16B[96,8];
+ Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] ^ Rm_VPR128.16B[104,8];
+ Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] ^ Rm_VPR128.16B[112,8];
+ Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] ^ Rm_VPR128.16B[120,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.41 EOR (vector) page C7-2099 line 122248 MATCH x2e201c00/mask=xbfe0fc00
+# CONSTRUCT x2e201c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$^@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_eor/2@1
+# AUNIT --inst x2e201c00/mask=xffe0fc00 --status pass
+
+:eor Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ # simd infix Rd_VPR64.8B = Rn_VPR64.8B ^ Rm_VPR64.8B on lane size 1
+ Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] ^ Rm_VPR64.8B[0,8];
+ Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] ^ Rm_VPR64.8B[8,8];
+ Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] ^ Rm_VPR64.8B[16,8];
+ Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] ^ Rm_VPR64.8B[24,8];
+ Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] ^ Rm_VPR64.8B[32,8];
+ Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] ^ Rm_VPR64.8B[40,8];
+ Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] ^ Rm_VPR64.8B[48,8];
+ Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] ^ Rm_VPR64.8B[56,8];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.42 EOR3 page C7-2101 line 122332 MATCH xce000000/mask=xffe08000
+# CONSTRUCT xce000000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 ARG4 $|@1 =$|@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_eor3/3@1
+# AUNIT --inst xce000000/mask=xffe08000 --status noqemu
+
+:eor3 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, Ra_VPR128.16B
+is b_2131=0b11001110000 & b_15=0 & Rd_VPR128.16B & Rn_VPR128.16B & Rm_VPR128.16B & Ra_VPR128.16B & Zd
+{
+ # simd infix TMPQ1 = Rm_VPR128.16B | Ra_VPR128.16B on lane size 1
+ TMPQ1[0,8] = Rm_VPR128.16B[0,8] | Ra_VPR128.16B[0,8];
+ TMPQ1[8,8] = Rm_VPR128.16B[8,8] | Ra_VPR128.16B[8,8];
+ TMPQ1[16,8] = Rm_VPR128.16B[16,8] | Ra_VPR128.16B[16,8];
+ TMPQ1[24,8] = Rm_VPR128.16B[24,8] | Ra_VPR128.16B[24,8];
+ TMPQ1[32,8] = Rm_VPR128.16B[32,8] | Ra_VPR128.16B[32,8];
+ TMPQ1[40,8] = Rm_VPR128.16B[40,8] | Ra_VPR128.16B[40,8];
+ TMPQ1[48,8] = Rm_VPR128.16B[48,8] | Ra_VPR128.16B[48,8];
+ TMPQ1[56,8] = Rm_VPR128.16B[56,8] | Ra_VPR128.16B[56,8];
+ TMPQ1[64,8] = Rm_VPR128.16B[64,8] | Ra_VPR128.16B[64,8];
+ TMPQ1[72,8] = Rm_VPR128.16B[72,8] | Ra_VPR128.16B[72,8];
+ TMPQ1[80,8] = Rm_VPR128.16B[80,8] | Ra_VPR128.16B[80,8];
+ TMPQ1[88,8] = Rm_VPR128.16B[88,8] | Ra_VPR128.16B[88,8];
+ TMPQ1[96,8] = Rm_VPR128.16B[96,8] | Ra_VPR128.16B[96,8];
+ TMPQ1[104,8] = Rm_VPR128.16B[104,8] | Ra_VPR128.16B[104,8];
+ TMPQ1[112,8] = Rm_VPR128.16B[112,8] | Ra_VPR128.16B[112,8];
+ TMPQ1[120,8] = Rm_VPR128.16B[120,8] | Ra_VPR128.16B[120,8];
+ # simd infix Rd_VPR128.16B = Rn_VPR128.16B | TMPQ1 on lane size 1
+ Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] | TMPQ1[0,8];
+ Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] | TMPQ1[8,8];
+ Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] | TMPQ1[16,8];
+ Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] | TMPQ1[24,8];
+ Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] | TMPQ1[32,8];
+ Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] | TMPQ1[40,8];
+ Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] | TMPQ1[48,8];
+ Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] | TMPQ1[56,8];
+ Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] | TMPQ1[64,8];
+ Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] | TMPQ1[72,8];
+ Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] | TMPQ1[80,8];
+ Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] | TMPQ1[88,8];
+ Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] | TMPQ1[96,8];
+ Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] | TMPQ1[104,8];
+ Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] | TMPQ1[112,8];
+ Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] | TMPQ1[120,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.43 EXT page C7-2102 line 122403 MATCH x2e000000/mask=xbfe08400
+# CONSTRUCT x6e000000/mask=xffe08400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 imm4:1 =NEON_ext/3@1
+# AUNIT --inst x6e000000/mask=xffe08400 --status nopcodeop
+
+:ext Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, imm4
+is b_3131=0 & q=1 & b_2429=0x2e & b_2223=0b00 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & imm4 & b_1010=0 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_ext(Rn_VPR128.16B, Rm_VPR128.16B, imm4:1, 1:1);
+}
+
+# C7.2.43 EXT page C7-2102 line 122403 MATCH x2e000000/mask=xbfe08400
+# CONSTRUCT x2e000000/mask=xffe0c400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 imm4:1 =NEON_ext/3@1
+# AUNIT --inst x2e000000/mask=xffe0c400 --status nopcodeop
+
+:ext Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B, imm4
+is b_3131=0 & q=0 & b_2429=0x2e & b_2223=0b00 & b_2121=0 & Rm_VPR64.8B & b_1415=0 & imm4 & b_1010=0 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_ext(Rn_VPR64.8B, Rm_VPR64.8B, imm4:1, 1:1);
+}
+
+# C7.2.44 FABD page C7-2104 line 122507 MATCH x2ec01400/mask=xbfe0fc00
+# CONSTRUCT x2ec01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $f-@2 =$fabs@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2@2
+# AUNIT --inst x2ec01400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Vector half precision variant when Q=0 sz=1 bb=0 cc=00 F=VPR64.4H
+
+:fabd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=1 & b_21=0 & b_1015=0b000101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ # simd infix TMPD1 = Rn_VPR64.4H f- Rm_VPR64.4H on lane size 2
+ TMPD1[0,16] = Rn_VPR64.4H[0,16] f- Rm_VPR64.4H[0,16];
+ TMPD1[16,16] = Rn_VPR64.4H[16,16] f- Rm_VPR64.4H[16,16];
+ TMPD1[32,16] = Rn_VPR64.4H[32,16] f- Rm_VPR64.4H[32,16];
+ TMPD1[48,16] = Rn_VPR64.4H[48,16] f- Rm_VPR64.4H[48,16];
+ # simd unary Rd_VPR64.4H = abs(TMPD1) on lane size 2
+ Rd_VPR64.4H[0,16] = abs(TMPD1[0,16]);
+ Rd_VPR64.4H[16,16] = abs(TMPD1[16,16]);
+ Rd_VPR64.4H[32,16] = abs(TMPD1[32,16]);
+ Rd_VPR64.4H[48,16] = abs(TMPD1[48,16]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.44 FABD page C7-2104 line 122507 MATCH x2ec01400/mask=xbfe0fc00
+# CONSTRUCT x6ec01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $f-@2 =$fabs@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2@2
+# AUNIT --inst x6ec01400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Vector half precision variant when Q=1 sz=1 bb=0 cc=00 F=VPR128.8H
+
+:fabd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=1 & b_21=0 & b_1015=0b000101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.8H f- Rm_VPR128.8H on lane size 2
+ TMPQ1[0,16] = Rn_VPR128.8H[0,16] f- Rm_VPR128.8H[0,16];
+ TMPQ1[16,16] = Rn_VPR128.8H[16,16] f- Rm_VPR128.8H[16,16];
+ TMPQ1[32,16] = Rn_VPR128.8H[32,16] f- Rm_VPR128.8H[32,16];
+ TMPQ1[48,16] = Rn_VPR128.8H[48,16] f- Rm_VPR128.8H[48,16];
+ TMPQ1[64,16] = Rn_VPR128.8H[64,16] f- Rm_VPR128.8H[64,16];
+ TMPQ1[80,16] = Rn_VPR128.8H[80,16] f- Rm_VPR128.8H[80,16];
+ TMPQ1[96,16] = Rn_VPR128.8H[96,16] f- Rm_VPR128.8H[96,16];
+ TMPQ1[112,16] = Rn_VPR128.8H[112,16] f- Rm_VPR128.8H[112,16];
+ # simd unary Rd_VPR128.8H = abs(TMPQ1) on lane size 2
+ Rd_VPR128.8H[0,16] = abs(TMPQ1[0,16]);
+ Rd_VPR128.8H[16,16] = abs(TMPQ1[16,16]);
+ Rd_VPR128.8H[32,16] = abs(TMPQ1[32,16]);
+ Rd_VPR128.8H[48,16] = abs(TMPQ1[48,16]);
+ Rd_VPR128.8H[64,16] = abs(TMPQ1[64,16]);
+ Rd_VPR128.8H[80,16] = abs(TMPQ1[80,16]);
+ Rd_VPR128.8H[96,16] = abs(TMPQ1[96,16]);
+ Rd_VPR128.8H[112,16] = abs(TMPQ1[112,16]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.44 FABD page C7-2104 line 122507 MATCH x2ea0d400/mask=xbfa0fc00
+# CONSTRUCT x2ea0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $f-@4 =$fabs@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2@4
+# AUNIT --inst x2ea0d400/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround"
+# Vector half precision variant when Q=0 sz=0 bb=1 cc=11 F=VPR64.2S
+
+:fabd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=0 & b_21=1 & b_1015=0b110101 & Rd_VPR64.2S & Rn_VPR64.2S & Rm_VPR64.2S & Zd
+{
+ # simd infix TMPD1 = Rn_VPR64.2S f- Rm_VPR64.2S on lane size 4
+ TMPD1[0,32] = Rn_VPR64.2S[0,32] f- Rm_VPR64.2S[0,32];
+ TMPD1[32,32] = Rn_VPR64.2S[32,32] f- Rm_VPR64.2S[32,32];
+ # simd unary Rd_VPR64.2S = abs(TMPD1) on lane size 4
+ Rd_VPR64.2S[0,32] = abs(TMPD1[0,32]);
+ Rd_VPR64.2S[32,32] = abs(TMPD1[32,32]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.44 FABD page C7-2104 line 122507 MATCH x2ea0d400/mask=xbfa0fc00
+# CONSTRUCT x6ea0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $f-@4 =$fabs@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2@4
+# AUNIT --inst x6ea0d400/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround"
+# Vector half precision variant when Q=1 sz=0 bb=1 cc=11 F=VPR128.4S
+
+:fabd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=0 & b_21=1 & b_1015=0b110101 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.4S f- Rm_VPR128.4S on lane size 4
+ TMPQ1[0,32] = Rn_VPR128.4S[0,32] f- Rm_VPR128.4S[0,32];
+ TMPQ1[32,32] = Rn_VPR128.4S[32,32] f- Rm_VPR128.4S[32,32];
+ TMPQ1[64,32] = Rn_VPR128.4S[64,32] f- Rm_VPR128.4S[64,32];
+ TMPQ1[96,32] = Rn_VPR128.4S[96,32] f- Rm_VPR128.4S[96,32];
+ # simd unary Rd_VPR128.4S = abs(TMPQ1) on lane size 4
+ Rd_VPR128.4S[0,32] = abs(TMPQ1[0,32]);
+ Rd_VPR128.4S[32,32] = abs(TMPQ1[32,32]);
+ Rd_VPR128.4S[64,32] = abs(TMPQ1[64,32]);
+ Rd_VPR128.4S[96,32] = abs(TMPQ1[96,32]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.44 FABD page C7-2104 line 122507 MATCH x2ea0d400/mask=xbfa0fc00
+# CONSTRUCT x6ee0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $f-@8 =$fabs@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2@8
+# AUNIT --inst x6ee0d400/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
+# Vector half precision variant when Q=1 sz=1 bb=1 cc=11 F=VPR128.2D
+
+:fabd Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=1 & b_21=1 & b_1015=0b110101 & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.2D f- Rm_VPR128.2D on lane size 8
+ TMPQ1[0,64] = Rn_VPR128.2D[0,64] f- Rm_VPR128.2D[0,64];
+ TMPQ1[64,64] = Rn_VPR128.2D[64,64] f- Rm_VPR128.2D[64,64];
+ # simd unary Rd_VPR128.2D = abs(TMPQ1) on lane size 8
+ Rd_VPR128.2D[0,64] = abs(TMPQ1[0,64]);
+ Rd_VPR128.2D[64,64] = abs(TMPQ1[64,64]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.44 FABD page C7-2104 line 122507 MATCH x7ec01400/mask=xffe0fc00
+# CONSTRUCT x7ec01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 f- =fabs
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2
+# AUNIT --inst x7ec01400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Scalar half precision variant when sz=1 bb=0 cc=00 F=FPR16
+
+:fabd Rd_FPR16, Rn_FPR16, Rm_FPR16
+is b_2131=0b01111110110 & b_1015=0b000101 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd
+{
+ local tmp1:2 = Rn_FPR16 f- Rm_FPR16;
+ Rd_FPR16 = abs(tmp1);
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.44 FABD page C7-2104 line 122507 MATCH x7ea0d400/mask=xffa0fc00
+# CONSTRUCT x7ea0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 f- =fabs
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2
+# AUNIT --inst x7ea0d400/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround"
+# Scalar half precision variant when sz=0 bb=1 cc=11 F=FPR32
+
+:fabd Rd_FPR32, Rn_FPR32, Rm_FPR32
+is b_2131=0b01111110101 & b_1015=0b110101 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd
+{
+ local tmp1:4 = Rn_FPR32 f- Rm_FPR32;
+ Rd_FPR32 = abs(tmp1);
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.44 FABD page C7-2104 line 122507 MATCH x7ea0d400/mask=xffa0fc00
+# CONSTRUCT x7ee0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 f- =fabs
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fabd/2
+# AUNIT --inst x7ee0d400/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
+# Scalar half precision variant when sz=1 bb=1 cc=11 F=FPR64
+
+:fabd Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_2131=0b01111110111 & b_1015=0b110101 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
+{
+ local tmp1:8 = Rn_FPR64 f- Rm_FPR64;
+ Rd_FPR64 = abs(tmp1);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.45 FABS (vector) page C7-2107 line 122704 MATCH x0ea0f800/mask=xbfbffc00
+# CONSTRUCT x4ee0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$fabs@8
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1@8
+# AUNIT --inst x4ee0f800/mask=xfffffc00 --rand dfp --status pass
+
+:fabs Rd_VPR128.2D, Rn_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0xf & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ # simd unary Rd_VPR128.2D = abs(Rn_VPR128.2D) on lane size 8
+ Rd_VPR128.2D[0,64] = abs(Rn_VPR128.2D[0,64]);
+ Rd_VPR128.2D[64,64] = abs(Rn_VPR128.2D[64,64]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.45 FABS (vector) page C7-2107 line 122704 MATCH x0ea0f800/mask=xbfbffc00
+# CONSTRUCT x0ea0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$fabs@4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1@4
+# AUNIT --inst x0ea0f800/mask=xfffffc00 --rand sfp --status pass
+
+:fabs Rd_VPR64.2S, Rn_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xf & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ # simd unary Rd_VPR64.2S = abs(Rn_VPR64.2S) on lane size 4
+ Rd_VPR64.2S[0,32] = abs(Rn_VPR64.2S[0,32]);
+ Rd_VPR64.2S[32,32] = abs(Rn_VPR64.2S[32,32]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.45 FABS (vector) page C7-2107 line 122704 MATCH x0ea0f800/mask=xbfbffc00
+# CONSTRUCT x4ea0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$fabs@4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1@4
+# AUNIT --inst x4ea0f800/mask=xfffffc00 --rand sfp --status pass
+
+:fabs Rd_VPR128.4S, Rn_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xf & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd unary Rd_VPR128.4S = abs(Rn_VPR128.4S) on lane size 4
+ Rd_VPR128.4S[0,32] = abs(Rn_VPR128.4S[0,32]);
+ Rd_VPR128.4S[32,32] = abs(Rn_VPR128.4S[32,32]);
+ Rd_VPR128.4S[64,32] = abs(Rn_VPR128.4S[64,32]);
+ Rd_VPR128.4S[96,32] = abs(Rn_VPR128.4S[96,32]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.45 FABS (vector) page C7-2107 line 122704 MATCH x0ef8f800/mask=xbffffc00
+# CONSTRUCT x0ef8f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$fabs@2
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1@2
+# AUNIT --inst x0ef8f800/mask=xfffffc00 --rand hfp --status noqemu
+# FABS (vector) SIMD 4H when size=0 Q=0
+
+:fabs Rd_VPR64.4H, Rn_VPR64.4H
+is b_31=0 & b_30=0 & b_1029=0b00111011111000111110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
+{
+ # simd unary Rd_VPR64.4H = abs(Rn_VPR64.4H) on lane size 2
+ Rd_VPR64.4H[0,16] = abs(Rn_VPR64.4H[0,16]);
+ Rd_VPR64.4H[16,16] = abs(Rn_VPR64.4H[16,16]);
+ Rd_VPR64.4H[32,16] = abs(Rn_VPR64.4H[32,16]);
+ Rd_VPR64.4H[48,16] = abs(Rn_VPR64.4H[48,16]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.45 FABS (vector) page C7-2107 line 122704 MATCH x0ef8f800/mask=xbffffc00
+# CONSTRUCT x4ef8f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$fabs@2
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1@2
+# AUNIT --inst x4ef8f800/mask=xfffffc00 --rand hfp --status noqemu
+# FABS (vector) SIMD 8H when size=0 Q=1
+
+:fabs Rd_VPR128.8H, Rn_VPR128.8H
+is b_31=0 & b_30=1 & b_1029=0b00111011111000111110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
+{
+ # simd unary Rd_VPR128.8H = abs(Rn_VPR128.8H) on lane size 2
+ Rd_VPR128.8H[0,16] = abs(Rn_VPR128.8H[0,16]);
+ Rd_VPR128.8H[16,16] = abs(Rn_VPR128.8H[16,16]);
+ Rd_VPR128.8H[32,16] = abs(Rn_VPR128.8H[32,16]);
+ Rd_VPR128.8H[48,16] = abs(Rn_VPR128.8H[48,16]);
+ Rd_VPR128.8H[64,16] = abs(Rn_VPR128.8H[64,16]);
+ Rd_VPR128.8H[80,16] = abs(Rn_VPR128.8H[80,16]);
+ Rd_VPR128.8H[96,16] = abs(Rn_VPR128.8H[96,16]);
+ Rd_VPR128.8H[112,16] = abs(Rn_VPR128.8H[112,16]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.46 FABS (scalar) page C7-2109 line 122815 MATCH x1e20c000/mask=xff3ffc00
+# CONSTRUCT x1ee0c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =fabs
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1
+# AUNIT --inst x1ee0c000/mask=xfffffc00 --rand hfp --status noqemu
+
+:fabs Rd_FPR16, Rn_FPR16
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & fpDpOpcode=0x1 & b_1014=0x10 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = abs(Rn_FPR16);
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.46 FABS (scalar) page C7-2109 line 122815 MATCH x1e20c000/mask=xff3ffc00
+# CONSTRUCT x1e60c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =fabs
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1
+# AUNIT --inst x1e60c000/mask=xfffffc00 --rand dfp --status pass
+
+:fabs Rd_FPR64, Rn_FPR64
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & fpDpOpcode=0x1 & b_1014=0x10 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = abs(Rn_FPR64);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.46 FABS (scalar) page C7-2109 line 122815 MATCH x1e20c000/mask=xff3ffc00
+# CONSTRUCT x1e20c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =fabs
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fabs/1
+# AUNIT --inst x1e20c000/mask=xfffffc00 --rand sfp --status pass
+
+:fabs Rd_FPR32, Rn_FPR32
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & fpDpOpcode=0x1 & b_1014=0x10 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = abs(Rn_FPR32);
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.47 FACGE page C7-2111 line 122911 MATCH x2e20ec00/mask=xbfa0fc00
+# CONSTRUCT x6e60ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2@8
+# AUNIT --inst x6e60ec00/mask=xffe0fc00 --rand dfp --status nopcodeop
+
+:facge Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1d & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_facge(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.47 FACGE page C7-2111 line 122911 MATCH x2e20ec00/mask=xbfa0fc00
+# CONSTRUCT x2e20ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2@4
+# AUNIT --inst x2e20ec00/mask=xffe0fc00 --rand sfp --status nopcodeop
+
+:facge Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1d & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_facge(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.47 FACGE page C7-2111 line 122911 MATCH x2e20ec00/mask=xbfa0fc00
+# CONSTRUCT x6e20ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2@4
+# AUNIT --inst x6e20ec00/mask=xffe0fc00 --rand sfp --status nopcodeop
+
+:facge Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1d & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_facge(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.47 FACGE page C7-2111 line 122911 MATCH x7e402c00/mask=xffe0fc00
+# CONSTRUCT x7e402c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2
+# AUNIT --inst x7e402c00/mask=xffe0fc00 --rand hfp --status noqemu
+# Scalar half precision
+
+:facge Rd_FPR16, Rn_FPR16, Rm_FPR16
+is b_2131=0b01111110010 & b_1015=0b001011 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_facge(Rn_FPR16, Rm_FPR16);
+}
+
+# C7.2.47 FACGE page C7-2111 line 122911 MATCH x7e20ec00/mask=xffa0fc00
+# CONSTRUCT x7e20ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2
+# AUNIT --inst x7e20ec00/mask=xffe0fc00 --rand sfp --status nopcodeop
+# Scalar single-precision and double-precision sz=0
+
+:facge Rd_FPR32, Rn_FPR32, Rm_FPR32
+is b_2331=0b011111100 & b_22=0 & b_21=1 & b_1015=0b111011 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_facge(Rn_FPR32, Rm_FPR32);
+}
+
+# C7.2.47 FACGE page C7-2111 line 122911 MATCH x7e20ec00/mask=xffa0fc00
+# CONSTRUCT x7e60ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2
+# AUNIT --inst x7e60ec00/mask=xffe0fc00 --rand dfp --status nopcodeop
+# Scalar single-precision and double-precision sz=1
+
+:facge Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_2331=0b011111100 & b_22=1 & b_21=1 & b_1015=0b111011 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_facge(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.47 FACGE page C7-2111 line 122911 MATCH x2e402c00/mask=xbfe0fc00
+# CONSTRUCT x2e402c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2@2
+# AUNIT --inst x2e402c00/mask=xffe0fc00 --rand hfp --status noqemu
+# FACGE SIMD 4H when size=0 Q=0
+
+:facge Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b001011 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_facge(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.47 FACGE page C7-2111 line 122911 MATCH x2e402c00/mask=xbfe0fc00
+# CONSTRUCT x6e402c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facge/2@2
+# AUNIT --inst x6e402c00/mask=xffe0fc00 --rand hfp --status noqemu
+# FACGE SIMD 8H when size=0 Q=1
+
+:facge Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b001011 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_facge(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.48 FACGT page C7-2115 line 123160 MATCH x2ea0ec00/mask=xbfa0fc00
+# CONSTRUCT x6ee0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2@8
+# AUNIT --inst x6ee0ec00/mask=xffe0fc00 --rand dfp --status nopcodeop
+
+:facgt Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x1d & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_facgt(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.48 FACGT page C7-2115 line 123160 MATCH x2ea0ec00/mask=xbfa0fc00
+# CONSTRUCT x2ea0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2@4
+# AUNIT --inst x2ea0ec00/mask=xffe0fc00 --rand sfp --status nopcodeop
+
+:facgt Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x1d & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_facgt(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.48 FACGT page C7-2115 line 123160 MATCH x2ea0ec00/mask=xbfa0fc00
+# CONSTRUCT x6ea0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2@4
+# AUNIT --inst x6ea0ec00/mask=xffe0fc00 --rand sfp --status nopcodeop
+
+:facgt Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x1d & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_facgt(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.48 FACGT page C7-2115 line 123160 MATCH x7ec02c00/mask=xffe0fc00
+# CONSTRUCT x7ec02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2
+# AUNIT --inst x7ec02c00/mask=xffe0fc00 --rand hfp --status noqemu
+# Scalar half precision
+
+:facgt Rd_FPR16, Rn_FPR16, Rm_FPR16
+is b_2131=0b01111110110 & b_1015=0b001011 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_facgt(Rn_FPR16, Rm_FPR16);
+}
+
+# C7.2.48 FACGT page C7-2115 line 123160 MATCH x7ea0ec00/mask=xffa0fc00
+# CONSTRUCT x7ea0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2
+# AUNIT --inst x7ea0ec00/mask=xffe0fc00 --rand sfp --status nopcodeop
+# Scalar single-precision and double-precision sz=0
+
+:facgt Rd_FPR32, Rn_FPR32, Rm_FPR32
+is b_2331=0b011111101 & b_22=0 & b_21=1 & b_1015=0b111011 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_facgt(Rn_FPR32, Rm_FPR32);
+}
+
+# C7.2.48 FACGT page C7-2115 line 123160 MATCH x7ea0ec00/mask=xffa0fc00
+# CONSTRUCT x7ee0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2
+# AUNIT --inst x7ee0ec00/mask=xffe0fc00 --rand dfp --status nopcodeop
+# Scalar single-precision and double-precision sz=1
+
+:facgt Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_2331=0b011111101 & b_22=1 & b_21=1 & b_1015=0b111011 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_facgt(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.48 FACGT page C7-2115 line 123160 MATCH x2ec02c00/mask=xbfe0fc00
+# CONSTRUCT x2ec02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2@2
+# AUNIT --inst x2ec02c00/mask=xffe0fc00 --rand hfp --status noqemu
+# Vector half-precision SIMD 4H when Q=0
+
+:facgt Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2129=0b101110110 & b_1015=0b001011 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_facgt(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.48 FACGT page C7-2115 line 123160 MATCH x2ec02c00/mask=xbfe0fc00
+# CONSTRUCT x6ec02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_facgt/2@2
+# AUNIT --inst x6ec02c00/mask=xffe0fc00 --rand hfp --status noqemu
+# Vector half-precision SIMD 8H when Q=1
+
+:facgt Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2129=0b101110110 & b_1015=0b001011 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_facgt(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.49 FADD (vector) page C7-2119 line 123409 MATCH x0e20d400/mask=xbfa0fc00
+# CONSTRUCT x4e60d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2@8
+# AUNIT --inst x4e60d400/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
+
+:fadd Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1a & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ # simd infix Rd_VPR128.2D = Rn_VPR128.2D f+ Rm_VPR128.2D on lane size 8
+ Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] f+ Rm_VPR128.2D[0,64];
+ Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] f+ Rm_VPR128.2D[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.49 FADD (vector) page C7-2119 line 123409 MATCH x0e20d400/mask=xbfa0fc00
+# CONSTRUCT x0e20d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2@4
+# AUNIT --inst x0e20d400/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround"
+
+:fadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1a & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ # simd infix Rd_VPR64.2S = Rn_VPR64.2S f+ Rm_VPR64.2S on lane size 4
+ Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] f+ Rm_VPR64.2S[0,32];
+ Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] f+ Rm_VPR64.2S[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.49 FADD (vector) page C7-2119 line 123409 MATCH x0e20d400/mask=xbfa0fc00
+# CONSTRUCT x4e20d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2@4
+# AUNIT --inst x4e20d400/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround"
+
+:fadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1a & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd infix Rd_VPR128.4S = Rn_VPR128.4S f+ Rm_VPR128.4S on lane size 4
+ Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] f+ Rm_VPR128.4S[0,32];
+ Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] f+ Rm_VPR128.4S[32,32];
+ Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] f+ Rm_VPR128.4S[64,32];
+ Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] f+ Rm_VPR128.4S[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.49 FADD (vector) page C7-2119 line 123409 MATCH x0e401400/mask=xbfe0fc00
+# CONSTRUCT x0e401400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2@2
+# AUNIT --inst x0e401400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision SIMD 4H when Q=0
+
+:fadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b000101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ # simd infix Rd_VPR64.4H = Rn_VPR64.4H f+ Rm_VPR64.4H on lane size 2
+ Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f+ Rm_VPR64.4H[0,16];
+ Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f+ Rm_VPR64.4H[16,16];
+ Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f+ Rm_VPR64.4H[32,16];
+ Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f+ Rm_VPR64.4H[48,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.49 FADD (vector) page C7-2119 line 123409 MATCH x0e401400/mask=xbfe0fc00
+# CONSTRUCT x4e401400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2@2
+# AUNIT --inst x4e401400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision SIMD 8H when Q=1
+
+:fadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b000101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ # simd infix Rd_VPR128.8H = Rn_VPR128.8H f+ Rm_VPR128.8H on lane size 2
+ Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f+ Rm_VPR128.8H[0,16];
+ Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f+ Rm_VPR128.8H[16,16];
+ Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f+ Rm_VPR128.8H[32,16];
+ Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f+ Rm_VPR128.8H[48,16];
+ Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f+ Rm_VPR128.8H[64,16];
+ Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f+ Rm_VPR128.8H[80,16];
+ Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f+ Rm_VPR128.8H[96,16];
+ Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f+ Rm_VPR128.8H[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.50 FADD (scalar) page C7-2121 line 123531 MATCH x1e202800/mask=xff20fc00
+# CONSTRUCT x1e602800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =f+
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2
+# AUNIT --inst x1e602800/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
+
+:fadd Rd_FPR64, Rn_FPR64, Rm_FPR64
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x2 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = Rn_FPR64 f+ Rm_FPR64;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.50 FADD (scalar) page C7-2121 line 123531 MATCH x1e202800/mask=xff20fc00
+# CONSTRUCT x1ee02800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =f+
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2
+# AUNIT --inst x1ee02800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+
+:fadd Rd_FPR16, Rn_FPR16, Rm_FPR16
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x2 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = Rn_FPR16 f+ Rm_FPR16;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.50 FADD (scalar) page C7-2121 line 123531 MATCH x1e202800/mask=xff20fc00
+# CONSTRUCT x1e202800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =f+
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fadd/2
+# AUNIT --inst x1e202800/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround"
+
+:fadd Rd_FPR32, Rn_FPR32, Rm_FPR32
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x2 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = Rn_FPR32 f+ Rm_FPR32;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.51 FADDP (scalar) page C7-2123 line 123639 MATCH x7e30d800/mask=xffbffc00
+# CONSTRUCT x7e70d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =#f+
+# SMACRO(pseudo) ARG1 ARG2 =NEON_faddp/1@8
+# AUNIT --inst x7e70d800/mask=xfffffc00 --rand dfp --status pass --comment "nofpround"
+
+:faddp Rd_FPR64, Rn_VPR128.2D
+is b_3031=1 & u=1 & b_2428=0x1e & b_23=0 & b_1722=0x38 & b_1216=0xd & b_1011=2 & Rn_VPR128.2D & Rd_FPR64 & Zd
+{
+ # sipd infix Rd_FPR64 = f+(Rn_VPR128.2D) on pairs lane size (8 to 8)
+ local tmp1 = Rn_VPR128.2D[0,64];
+ local tmp2 = Rn_VPR128.2D[64,64];
+ Rd_FPR64 = tmp1 f+ tmp2;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.51 FADDP (scalar) page C7-2123 line 123639 MATCH x7e30d800/mask=xffbffc00
+# CONSTRUCT x7e30d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =#f+
+# SMACRO(pseudo) ARG1 ARG2 =NEON_faddp/1@4
+# AUNIT --inst x7e30d800/mask=xfffffc00 --rand sfp --status pass --comment "nofpround"
+
+:faddp Rd_FPR32, Rn_VPR64.2S
+is b_3031=1 & u=1 & b_2428=0x1e & b_23=0 & b_1722=0x18 & b_1216=0xd & b_1011=2 & Rn_VPR64.2S & Rd_FPR32 & Zd
+{
+ # sipd infix Rd_FPR32 = f+(Rn_VPR64.2S) on pairs lane size (4 to 4)
+ local tmp1 = Rn_VPR64.2S[0,32];
+ local tmp2 = Rn_VPR64.2S[32,32];
+ Rd_FPR32 = tmp1 f+ tmp2;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.51 FADDP (scalar) page C7-2123 line 123639 MATCH x5e30d800/mask=xffbffc00
+# CONSTRUCT x5e30d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 Rn_FPR32 =#f+@2
+# SMACRO(pseudo) ARG1 Rn_FPR32 =NEON_faddp/1@2
+# AUNIT --inst x5e30d800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant
+
+:faddp Rd_FPR16, vRn_VPR128^".2H"
+is b_1031=0b0101111000110000110110 & Rd_FPR16 & vRn_VPR128 & Rn_FPR32 & Zd
+{
+ # sipd infix Rd_FPR16 = f+(Rn_FPR32) on pairs lane size (2 to 2)
+ local tmp1 = Rn_FPR32[0,16];
+ local tmp2 = Rn_FPR32[16,16];
+ Rd_FPR16 = tmp1 f+ tmp2;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.52 FADDP (vector) page C7-2125 line 123747 MATCH x2e20d400/mask=xbfa0fc00
+# CONSTRUCT x6e60d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 var:16 ARG2 ARG3 =#f+/2 =
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_faddp/2@8
+# AUNIT --inst x6e60d400/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
+
+:faddp Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1a & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ TMPQ1 = 0;
+ # sipd infix TMPQ1 = f+(Rn_VPR128.2D,Rm_VPR128.2D) on pairs lane size (8 to 8)
+ local tmp2 = Rn_VPR128.2D[0,64];
+ local tmp3 = Rn_VPR128.2D[64,64];
+ TMPQ1[0,64] = tmp2 f+ tmp3;
+ tmp2 = Rm_VPR128.2D[0,64];
+ tmp3 = Rm_VPR128.2D[64,64];
+ TMPQ1[64,64] = tmp2 f+ tmp3;
+ Rd_VPR128.2D = TMPQ1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.52 FADDP (vector) page C7-2125 line 123747 MATCH x2e20d400/mask=xbfa0fc00
+# CONSTRUCT x2e20d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 var:8 ARG2 ARG3 =#f+/2 =
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_faddp/2@4
+# AUNIT --inst x2e20d400/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround"
+
+:faddp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1a & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ TMPD1 = 0;
+ # sipd infix TMPD1 = f+(Rn_VPR64.2S,Rm_VPR64.2S) on pairs lane size (4 to 4)
+ local tmp2 = Rn_VPR64.2S[0,32];
+ local tmp3 = Rn_VPR64.2S[32,32];
+ TMPD1[0,32] = tmp2 f+ tmp3;
+ tmp2 = Rm_VPR64.2S[0,32];
+ tmp3 = Rm_VPR64.2S[32,32];
+ TMPD1[32,32] = tmp2 f+ tmp3;
+ Rd_VPR64.2S = TMPD1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.52 FADDP (vector) page C7-2125 line 123747 MATCH x2e20d400/mask=xbfa0fc00
+# CONSTRUCT x6e20d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 var:16 ARG2 ARG3 =#f+/2 =
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_faddp/2@4
+# AUNIT --inst x6e20d400/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround"
+
+:faddp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1a & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ TMPQ1 = 0;
+ # sipd infix TMPQ1 = f+(Rn_VPR128.4S,Rm_VPR128.4S) on pairs lane size (4 to 4)
+ local tmp2 = Rn_VPR128.4S[0,32];
+ local tmp3 = Rn_VPR128.4S[32,32];
+ TMPQ1[0,32] = tmp2 f+ tmp3;
+ tmp2 = Rn_VPR128.4S[64,32];
+ tmp3 = Rn_VPR128.4S[96,32];
+ TMPQ1[32,32] = tmp2 f+ tmp3;
+ tmp2 = Rm_VPR128.4S[0,32];
+ tmp3 = Rm_VPR128.4S[32,32];
+ TMPQ1[64,32] = tmp2 f+ tmp3;
+ tmp2 = Rm_VPR128.4S[64,32];
+ tmp3 = Rm_VPR128.4S[96,32];
+ TMPQ1[96,32] = tmp2 f+ tmp3;
+ Rd_VPR128.4S = TMPQ1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.52 FADDP (vector) page C7-2125 line 123747 MATCH x2e401400/mask=xbfe0fc00
+# CONSTRUCT x2e401400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 var:8 ARG3 ARG2 =#f+/2 =
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_faddp/2@2
+# AUNIT --inst x2e401400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision SIMD 4H when Q = 0
+
+:faddp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b000101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ TMPD1 = 0;
+ # sipd infix TMPD1 = f+(Rm_VPR64.4H,Rn_VPR64.4H) on pairs lane size (2 to 2)
+ local tmp2 = Rm_VPR64.4H[0,16];
+ local tmp3 = Rm_VPR64.4H[16,16];
+ TMPD1[0,16] = tmp2 f+ tmp3;
+ tmp2 = Rm_VPR64.4H[32,16];
+ tmp3 = Rm_VPR64.4H[48,16];
+ TMPD1[16,16] = tmp2 f+ tmp3;
+ tmp2 = Rn_VPR64.4H[0,16];
+ tmp3 = Rn_VPR64.4H[16,16];
+ TMPD1[32,16] = tmp2 f+ tmp3;
+ tmp2 = Rn_VPR64.4H[32,16];
+ tmp3 = Rn_VPR64.4H[48,16];
+ TMPD1[48,16] = tmp2 f+ tmp3;
+ Rd_VPR64.4H = TMPD1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.52 FADDP (vector) page C7-2125 line 123747 MATCH x2e401400/mask=xbfe0fc00
+# CONSTRUCT x6e401400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 var:16 ARG2 ARG3 =#f+/2 =
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_faddp/2@2
+# AUNIT --inst x6e401400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision SIMD 8H when Q = 1
+
+:faddp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b000101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ TMPQ1 = 0;
+ # sipd infix TMPQ1 = f+(Rn_VPR128.8H,Rm_VPR128.8H) on pairs lane size (2 to 2)
+ local tmp2 = Rn_VPR128.8H[0,16];
+ local tmp3 = Rn_VPR128.8H[16,16];
+ TMPQ1[0,16] = tmp2 f+ tmp3;
+ tmp2 = Rn_VPR128.8H[32,16];
+ tmp3 = Rn_VPR128.8H[48,16];
+ TMPQ1[16,16] = tmp2 f+ tmp3;
+ tmp2 = Rn_VPR128.8H[64,16];
+ tmp3 = Rn_VPR128.8H[80,16];
+ TMPQ1[32,16] = tmp2 f+ tmp3;
+ tmp2 = Rn_VPR128.8H[96,16];
+ tmp3 = Rn_VPR128.8H[112,16];
+ TMPQ1[48,16] = tmp2 f+ tmp3;
+ tmp2 = Rm_VPR128.8H[0,16];
+ tmp3 = Rm_VPR128.8H[16,16];
+ TMPQ1[64,16] = tmp2 f+ tmp3;
+ tmp2 = Rm_VPR128.8H[32,16];
+ tmp3 = Rm_VPR128.8H[48,16];
+ TMPQ1[80,16] = tmp2 f+ tmp3;
+ tmp2 = Rm_VPR128.8H[64,16];
+ tmp3 = Rm_VPR128.8H[80,16];
+ TMPQ1[96,16] = tmp2 f+ tmp3;
+ tmp2 = Rm_VPR128.8H[96,16];
+ tmp3 = Rm_VPR128.8H[112,16];
+ TMPQ1[112,16] = tmp2 f+ tmp3;
+ Rd_VPR128.8H = TMPQ1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.46 FCADD page C7-1090 line 63037 KEEPWITH
+
+fcadd_rotate: #90 is b_12=0 { export 90:1; }
+fcadd_rotate: #270 is b_12=1 { export 270:1; }
+
+# C7.2.53 FCADD page C7-2127 line 123874 MATCH x2e00e400/mask=xbf20ec00
+# CONSTRUCT x2e40e400/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcadd/3@2
+# AUNIT --inst x2e40e400/mask=xffe0ec00 --rand hfp --status noqemu --comment "nofpround"
+# FCADD SIMD 4H when size = 01 , Q = 0
+
+:fcadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H, fcadd_rotate
+is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_21=0 & b_1315=0b111 & b_1011=0b01 & fcadd_rotate & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_fcadd(Rn_VPR64.4H, Rm_VPR64.4H, fcadd_rotate, 2:1);
+}
+
+# C7.2.53 FCADD page C7-2127 line 123874 MATCH x2e00e400/mask=xbf20ec00
+# CONSTRUCT x6e40e400/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcadd/3@2
+# AUNIT --inst x6e40e400/mask=xffe0ec00 --rand hfp --status noqemu --comment "nofpround"
+# FCADD SIMD 8H when size = 01 , Q = 1
+
+:fcadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H, fcadd_rotate
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_21=0 & b_1315=0b111 & b_1011=0b01 & fcadd_rotate & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_fcadd(Rn_VPR128.8H, Rm_VPR128.8H, fcadd_rotate, 2:1);
+}
+
+# C7.2.53 FCADD page C7-2127 line 123874 MATCH x2e00e400/mask=xbf20ec00
+# CONSTRUCT x2e80e400/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcadd/3@4
+# AUNIT --inst x2e80e400/mask=xffe0ec00 --rand sfp --status noqemu --comment "nofpround"
+# FCADD SIMD 2S when size = 10 , Q = 0
+
+:fcadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S, fcadd_rotate
+is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_21=0 & b_1315=0b111 & b_1011=0b01 & fcadd_rotate & Rd_VPR64.2S & Rn_VPR64.2S & Rm_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_fcadd(Rn_VPR64.2S, Rm_VPR64.2S, fcadd_rotate, 4:1);
+}
+
+# C7.2.53 FCADD page C7-2127 line 123874 MATCH x2e00e400/mask=xbf20ec00
+# CONSTRUCT x6e80e400/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcadd/3@4
+# AUNIT --inst x6e80e400/mask=xffe0ec00 --rand sfp --status noqemu --comment "nofpround"
+# FCADD SIMD 4S when size = 10 , Q = 1
+
+:fcadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, fcadd_rotate
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_21=0 & b_1315=0b111 & b_1011=0b01 & fcadd_rotate & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_fcadd(Rn_VPR128.4S, Rm_VPR128.4S, fcadd_rotate, 4:1);
+}
+
+# C7.2.53 FCADD page C7-2127 line 123874 MATCH x2e00e400/mask=xbf20ec00
+# CONSTRUCT x6ec0e400/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcadd/3@8
+# AUNIT --inst x6ec0e400/mask=xffe0ec00 --rand dfp --status noqemu --comment "nofpround"
+# FCADD SIMD 2D when size = 11 , Q = 1
+
+:fcadd Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D, fcadd_rotate
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b11 & b_21=0 & b_1315=0b111 & b_1011=0b01 & fcadd_rotate & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_fcadd(Rn_VPR128.2D, Rm_VPR128.2D, fcadd_rotate, 8:1);
+}
+
+# C7.2.54 FCCMP page C7-2129 line 123987 MATCH x1e200400/mask=xff200c10
+# CONSTRUCT x1e600400/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO null ARG3:1 =setCC_NZCV/1 ARG4:1 ! inst_next goto null ARG1 ARG2 =fcomp/2
+# SMACRO(pseudo) null ARG1 ARG2 ARG3:1 ARG4:1 =NEON_fccmp/4
+# AUNIT --inst x1e600400/mask=xffe00c10 --rand dfp --status nodest --comment "flags"
+
+:fccmp Rn_FPR64, Rm_FPR64, NZCVImm_uimm4, CondOp
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & CondOp & b_1011=1 & Rn_FPR64 & fpccmp.op=0 & NZCVImm_uimm4
+{
+ setCC_NZCV(NZCVImm_uimm4:1);
+ local tmp1:1 = ! CondOp:1;
+ if (tmp1) goto inst_next;
+ fcomp(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.54 FCCMP page C7-2129 line 123987 MATCH x1e200400/mask=xff200c10
+# CONSTRUCT x1e200400/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO null ARG3:1 =setCC_NZCV/1 ARG4:1 ! inst_next goto null ARG1 ARG2 =fcomp/2
+# SMACRO(pseudo) null ARG1 ARG2 ARG3:1 ARG4:1 =NEON_fccmp/4
+# AUNIT --inst x1e200400/mask=xffe00c10 --rand sfp --status nodest --comment "flags"
+
+:fccmp Rn_FPR32, Rm_FPR32, NZCVImm_uimm4, CondOp
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & CondOp & b_1011=1 & Rn_FPR32 & fpccmp.op=0 & NZCVImm_uimm4
+{
+ setCC_NZCV(NZCVImm_uimm4:1);
+ local tmp1:1 = ! CondOp:1;
+ if (tmp1) goto inst_next;
+ fcomp(Rn_FPR32, Rm_FPR32);
+}
+
+# C7.2.54 FCCMP page C7-2129 line 123987 MATCH x1e200400/mask=xff200c10
+# CONSTRUCT x1ee00400/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO null ARG3:1 =setCC_NZCV/1 ARG4:1 ! inst_next goto null ARG1 ARG2 =fcomp/2
+# SMACRO(pseudo) null ARG1 ARG2 ARG3:1 ARG4:1 =NEON_fccmp/4
+# AUNIT --inst x1ee00400/mask=xffe00c10 --rand hfp --status nodest --comment "flags"
+
+:fccmp Rn_FPR16, Rm_FPR16, NZCVImm_uimm4, CondOp
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & CondOp & b_1011=1 & Rn_FPR16 & fpccmp.op=0 & NZCVImm_uimm4
+{
+ setCC_NZCV(NZCVImm_uimm4:1);
+ local tmp1:1 = ! CondOp:1;
+ if (tmp1) goto inst_next;
+ fcomp(Rn_FPR16, Rm_FPR16);
+}
+
+# C7.2.55 FCCMPE page C7-2131 line 124107 MATCH x1e200410/mask=xff200c10
+# CONSTRUCT x1e600410/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO null ARG3:1 =setCC_NZCV/1 ARG4:1 ! inst_next goto null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2
+# SMACRO(pseudo) null ARG1 ARG2 ARG3:1 ARG4:1 =NEON_fccmpe/4
+# AUNIT --inst x1e600410/mask=xffe00c10 --rand dfp --status nodest --comment "flags"
+
+:fccmpe Rn_FPR64, Rm_FPR64, NZCVImm_uimm4, CondOp
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & CondOp & b_1011=1 & Rn_FPR64 & fpccmp.op=1 & NZCVImm_uimm4
+{
+ setCC_NZCV(NZCVImm_uimm4:1);
+ local tmp1:1 = ! CondOp:1;
+ if (tmp1) goto inst_next;
+ ftestNAN(Rn_FPR64, Rm_FPR64);
+ fcomp(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.55 FCCMPE page C7-2131 line 124107 MATCH x1e200410/mask=xff200c10
+# CONSTRUCT x1e200410/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO null ARG3:1 =setCC_NZCV/1 ARG4:1 ! inst_next goto null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2
+# SMACRO(pseudo) null ARG1 ARG2 ARG3:1 ARG4:1 =NEON_fccmpe/4
+# AUNIT --inst x1e200410/mask=xffe00c10 --rand sfp --status nodest --comment "flags"
+
+:fccmpe Rn_FPR32, Rm_FPR32, NZCVImm_uimm4, CondOp
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & CondOp & b_1011=1 & Rn_FPR32 & fpccmp.op=1 & NZCVImm_uimm4
+{
+ setCC_NZCV(NZCVImm_uimm4:1);
+ local tmp1:1 = ! CondOp:1;
+ if (tmp1) goto inst_next;
+ ftestNAN(Rn_FPR32, Rm_FPR32);
+ fcomp(Rn_FPR32, Rm_FPR32);
+}
+
+# C7.2.55 FCCMPE page C7-2131 line 124107 MATCH x1e200410/mask=xff200c10
+# CONSTRUCT x1ee00410/mask=xffe00c10 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO null ARG3:1 =setCC_NZCV/1 ARG4:1 ! inst_next goto null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2
+# SMACRO(pseudo) null ARG1 ARG2 ARG3:1 ARG4:1 =NEON_fccmpe/4
+# AUNIT --inst x1ee00410/mask=xffe00c10 --rand hfp --status nodest --comment "flags"
+
+:fccmpe Rn_FPR16, Rm_FPR16, NZCVImm_uimm4, CondOp
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & CondOp & b_1011=1 & Rn_FPR16 & fpccmp.op=1 & NZCVImm_uimm4
+{
+ setCC_NZCV(NZCVImm_uimm4:1);
+ local tmp1:1 = ! CondOp:1;
+ if (tmp1) goto inst_next;
+ ftestNAN(Rn_FPR16, Rm_FPR16);
+ fcomp(Rn_FPR16, Rm_FPR16);
+}
+
+# C7.2.56 FCMEQ (register) page C7-2133 line 124227 MATCH x0e20e400/mask=xbfa0fc00
+# CONSTRUCT x4e60e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2@8
+# AUNIT --inst x4e60e400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "noflags"
+
+:fcmeq Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1c & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_fcmeq(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.56 FCMEQ (register) page C7-2133 line 124227 MATCH x0e20e400/mask=xbfa0fc00
+# CONSTRUCT x0e20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2@4
+# AUNIT --inst x0e20e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags"
+
+:fcmeq Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1c & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_fcmeq(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.56 FCMEQ (register) page C7-2133 line 124227 MATCH x0e20e400/mask=xbfa0fc00
+# CONSTRUCT x4e20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2@4
+# AUNIT --inst x4e20e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags"
+
+:fcmeq Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1c & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_fcmeq(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.56 FCMEQ (register) page C7-2133 line 124227 MATCH x5e402400/mask=xffe0fc00
+# CONSTRUCT x5e402400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2
+# AUNIT --inst x5e402400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags"
+# Scalar half precision variant
+
+:fcmeq Rd_FPR16, Rn_FPR16, Rm_FPR16
+is b_2131=0b01011110010 & b_1015=0b001001 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_fcmeq(Rn_FPR16, Rm_FPR16);
+}
+
+# C7.2.56 FCMEQ (register) page C7-2133 line 124227 MATCH x5e20e400/mask=xffa0fc00
+# CONSTRUCT x5e20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2
+# AUNIT --inst x5e20e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags"
+# Scalar single-precision and double-precision variant sz=0
+
+:fcmeq Rd_FPR32, Rn_FPR32, Rm_FPR32
+is b_2331=0b010111100 & b_22=0 & b_21=1 & b_1015=0b111001 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_fcmeq(Rn_FPR32, Rm_FPR32);
+}
+
+# C7.2.56 FCMEQ (register) page C7-2133 line 124227 MATCH x5e20e400/mask=xffa0fc00
+# CONSTRUCT x5e60e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2
+# AUNIT --inst x5e60e400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "noflags"
+# Scalar single-precision and double-precision variant sz=1
+
+:fcmeq Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_2331=0b010111100 & b_22=1 & b_21=1 & b_1015=0b111001 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_fcmeq(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.56 FCMEQ (register) page C7-2133 line 124227 MATCH x0e402400/mask=xbfe0fc00
+# CONSTRUCT x0e402400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2@2
+# AUNIT --inst x0e402400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags"
+# Vector half precision variant SIMD 4H when Q=0
+
+:fcmeq Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b001001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_fcmeq(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.56 FCMEQ (register) page C7-2133 line 124227 MATCH x0e402400/mask=xbfe0fc00
+# CONSTRUCT x4e402400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmeq/2@2
+# AUNIT --inst x4e402400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags"
+# Vector half precision variant SIMD 8H when Q=1
+
+:fcmeq Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b001001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_fcmeq(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.57 FCMEQ (zero) page C7-2137 line 124475 MATCH x0ea0d800/mask=xbfbffc00
+# CONSTRUCT x4ee0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmeq/2@8
+# AUNIT --inst x4ee0d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags"
+
+:fcmeq Rd_VPR128.2D, Rn_VPR128.2D, "#0"
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x30 & b_1216=0xd & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_fcmeq(Rn_VPR128.2D, 0:8, 8:1);
+}
+
+# C7.2.57 FCMEQ (zero) page C7-2137 line 124475 MATCH x0ea0d800/mask=xbfbffc00
+# CONSTRUCT x0ea0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmeq/2@4
+# AUNIT --inst x0ea0d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
+
+:fcmeq Rd_VPR64.2S, Rn_VPR64.2S, "#0"
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xd & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_fcmeq(Rn_VPR64.2S, 0:4, 4:1);
+}
+
+# C7.2.57 FCMEQ (zero) page C7-2137 line 124475 MATCH x0ea0d800/mask=xbfbffc00
+# CONSTRUCT x4ea0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmeq/2@4
+# AUNIT --inst x4ea0d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
+
+:fcmeq Rd_VPR128.4S, Rn_VPR128.4S, "#0"
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xd & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_fcmeq(Rn_VPR128.4S, 0:4, 4:1);
+}
+
+# C7.2.57 FCMEQ (zero) page C7-2137 line 124475 MATCH x5ef8d800/mask=xfffffc00
+# CONSTRUCT x5ef8d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmeq/2
+# AUNIT --inst x5ef8d800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
+# Scalar half precision variant
+
+:fcmeq Rd_FPR16, Rn_FPR16, "#0.0"
+is b_1031=0b0101111011111000110110 & Rd_FPR16 & Rn_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_fcmeq(Rn_FPR16, 0:2);
+}
+
+# C7.2.57 FCMEQ (zero) page C7-2137 line 124475 MATCH x5ea0d800/mask=xffbffc00
+# CONSTRUCT x5ea0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmeq/2
+# AUNIT --inst x5ea0d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
+# Scalar single-precision and double-precision sz=0
+
+:fcmeq Rd_FPR32, Rn_FPR32, "#0.0"
+is b_2331=0b010111101 & b_22=0 & b_1021=0b100000110110 & Rd_FPR32 & Rn_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_fcmeq(Rn_FPR32, 0:4);
+}
+
+# C7.2.57 FCMEQ (zero) page C7-2137 line 124475 MATCH x5ea0d800/mask=xffbffc00
+# CONSTRUCT x5ee0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmeq/2
+# AUNIT --inst x5ee0d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags"
+# Scalar single-precision and double-precision sz=1
+
+:fcmeq Rd_FPR64, Rn_FPR64, "#0.0"
+is b_2331=0b010111101 & b_22=1 & b_1021=0b100000110110 & Rd_FPR64 & Rn_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_fcmeq(Rn_FPR64, 0:8);
+}
+
+# C7.2.57 FCMEQ (zero) page C7-2137 line 124475 MATCH x0ef8d800/mask=xbffffc00
+# CONSTRUCT x0ef8d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmeq/2@2
+# AUNIT --inst x0ef8d800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
+# Vector half precision variant SIMD 4H when Q = 0
+
+:fcmeq Rd_VPR64.4H, Rn_VPR64.4H, "#0.0"
+is b_31=0 & b_30=0 & b_1029=0b00111011111000110110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_fcmeq(Rn_VPR64.4H, 0:2, 2:1);
+}
+
+# C7.2.57 FCMEQ (zero) page C7-2137 line 124475 MATCH x0ef8d800/mask=xbffffc00
+# CONSTRUCT x4ef8d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmeq/2@2
+# AUNIT --inst x4ef8d800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
+# Vector half precision variant SIMD 8H when Q = 1
+
+:fcmeq Rd_VPR128.8H, Rn_VPR128.8H, "#0.0"
+is b_31=0 & b_30=1 & b_1029=0b00111011111000110110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_fcmeq(Rn_VPR128.8H, 0:2, 2:1);
+}
+
+# C7.2.58 FCMGE (register) page C7-2140 line 124691 MATCH x2e20e400/mask=xbfa0fc00
+# CONSTRUCT x6e60e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2@8
+# AUNIT --inst x6e60e400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "noflags"
+
+:fcmge Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1c & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_fcmge(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.58 FCMGE (register) page C7-2140 line 124691 MATCH x2e20e400/mask=xbfa0fc00
+# CONSTRUCT x2e20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2@4
+# AUNIT --inst x2e20e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags"
+
+:fcmge Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1c & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_fcmge(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.58 FCMGE (register) page C7-2140 line 124691 MATCH x2e20e400/mask=xbfa0fc00
+# CONSTRUCT x6e20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2@4
+# AUNIT --inst x6e20e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags"
+
+:fcmge Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1c & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_fcmge(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.58 FCMGE (register) page C7-2140 line 124691 MATCH x7e402400/mask=xffe0fc00
+# CONSTRUCT x7e402400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2
+# AUNIT --inst x7e402400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags"
+# Scalar half precision variant
+
+:fcmge Rd_FPR16, Rn_FPR16, Rm_FPR16
+is b_2131=0b01111110010 & b_1015=0b001001 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_fcmge(Rn_FPR16, Rm_FPR16);
+}
+
+# C7.2.58 FCMGE (register) page C7-2140 line 124691 MATCH x7e20e400/mask=xffa0fc00
+# CONSTRUCT x7e20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2
+# AUNIT --inst x7e20e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags"
+# Scalar single-precision and double-precision variant sz=0
+
+:fcmge Rd_FPR32, Rn_FPR32, Rm_FPR32
+is b_2331=0b011111100 & b_22=0 & b_21=1 & b_1015=0b111001 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_fcmge(Rn_FPR32, Rm_FPR32);
+}
+
+# C7.2.58 FCMGE (register) page C7-2140 line 124691 MATCH x7e20e400/mask=xffa0fc00
+# CONSTRUCT x7e60e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2
+# AUNIT --inst x7e60e400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "noflags"
+# Scalar single-precision and double-precision variant sz=1
+
+:fcmge Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_2331=0b011111100 & b_22=1 & b_21=1 & b_1015=0b111001 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_fcmge(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.58 FCMGE (register) page C7-2140 line 124691 MATCH x2e402400/mask=xbfe0fc00
+# CONSTRUCT x2e402400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2@2
+# AUNIT --inst x2e402400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags"
+# Vector half precision variant SIMD 4H when Q = 0
+
+:fcmge Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b001001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_fcmge(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.58 FCMGE (register) page C7-2140 line 124691 MATCH x2e402400/mask=xbfe0fc00
+# CONSTRUCT x6e402400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmge/2@2
+# AUNIT --inst x6e402400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags"
+# Vector half precision variant SIMD 8H when Q = 1
+
+:fcmge Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b001001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_fcmge(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.59 FCMGE (zero) page C7-2144 line 124940 MATCH x2ea0c800/mask=xbfbffc00
+# CONSTRUCT x6ee0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmge/2@8
+# AUNIT --inst x6ee0c800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags"
+
+:fcmge Rd_VPR128.2D, Rn_VPR128.2D, "#0"
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & b_23=1 & b_1722=0x30 & b_1216=0xc & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_fcmge(Rn_VPR128.2D, 0:8, 8:1);
+}
+
+# C7.2.59 FCMGE (zero) page C7-2144 line 124940 MATCH x2ea0c800/mask=xbfbffc00
+# CONSTRUCT x2ea0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmge/2@4
+# AUNIT --inst x2ea0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
+
+:fcmge Rd_VPR64.2S, Rn_VPR64.2S, "#0"
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xc & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_fcmge(Rn_VPR64.2S, 0:4, 4:1);
+}
+
+# C7.2.59 FCMGE (zero) page C7-2144 line 124940 MATCH x2ea0c800/mask=xbfbffc00
+# CONSTRUCT x6ea0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmge/2@4
+# AUNIT --inst x6ea0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
+
+:fcmge Rd_VPR128.4S, Rn_VPR128.4S, "#0"
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xc & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_fcmge(Rn_VPR128.4S, 0:4, 4:1);
+}
+
+# C7.2.59 FCMGE (zero) page C7-2144 line 124940 MATCH x7ef8c800/mask=xfffffc00
+# CONSTRUCT x7ef8c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmge/2
+# AUNIT --inst x7ef8c800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
+# Scalar half precision variant
+
+:fcmge Rd_FPR16, Rn_FPR16, "#0.0"
+is b_1031=0b0111111011111000110010 & Rd_FPR16 & Rn_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_fcmge(Rn_FPR16, 0:2);
+}
+
+# C7.2.59 FCMGE (zero) page C7-2144 line 124940 MATCH x7ea0c800/mask=xffbffc00
+# CONSTRUCT x7ea0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmge/2
+# AUNIT --inst x7ea0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
+# Scalar single-precision and double-precision sz=0
+
+:fcmge Rd_FPR32, Rn_FPR32, "#0.0"
+is b_2331=0b011111101 & b_22=0 & b_1021=0b100000110010 & Rd_FPR32 & Rn_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_fcmge(Rn_FPR32, 0:4);
+}
+
+# C7.2.59 FCMGE (zero) page C7-2144 line 124940 MATCH x7ea0c800/mask=xffbffc00
+# CONSTRUCT x7ee0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmge/2
+# AUNIT --inst x7ee0c800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags"
+# Scalar single-precision and double-precision sz=1
+
+:fcmge Rd_FPR64, Rn_FPR64, "#0.0"
+is b_2331=0b011111101 & b_22=1 & b_1021=0b100000110010 & Rd_FPR64 & Rn_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_fcmge(Rn_FPR64, 0:8);
+}
+
+# C7.2.59 FCMGE (zero) page C7-2144 line 124940 MATCH x2ef8c800/mask=xbffffc00
+# CONSTRUCT x2ef8c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmge/2@2
+# AUNIT --inst x2ef8c800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
+# Vector half precision variant SIMD 4H when Q = 0
+
+:fcmge Rd_VPR64.4H, Rn_VPR64.4H, "#0.0"
+is b_31=0 & b_30=0 & b_1029=0b10111011111000110010 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_fcmge(Rn_VPR64.4H, 0:2, 2:1);
+}
+
+# C7.2.59 FCMGE (zero) page C7-2144 line 124940 MATCH x2ef8c800/mask=xbffffc00
+# CONSTRUCT x6ef8c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmge/2@2
+# AUNIT --inst x6ef8c800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
+# Vector half precision variant SIMD 8H when Q = 1
+
+:fcmge Rd_VPR128.8H, Rn_VPR128.8H, "#0.0"
+is b_31=0 & b_30=1 & b_1029=0b10111011111000110010 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_fcmge(Rn_VPR128.8H, 0:2, 2:1);
+}
+
+# C7.2.60 FCMGT (register) page C7-2147 line 125156 MATCH x2ea0e400/mask=xbfa0fc00
+# CONSTRUCT x6ee0e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2@8
+# AUNIT --inst x6ee0e400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "noflags"
+
+:fcmgt Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x1c & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_fcmgt(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.60 FCMGT (register) page C7-2147 line 125156 MATCH x2ea0e400/mask=xbfa0fc00
+# CONSTRUCT x2ea0e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2@4
+# AUNIT --inst x2ea0e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags"
+
+:fcmgt Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x1c & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_fcmgt(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.60 FCMGT (register) page C7-2147 line 125156 MATCH x2ea0e400/mask=xbfa0fc00
+# CONSTRUCT x6ea0e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2@4
+# AUNIT --inst x6ea0e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags"
+
+:fcmgt Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x1c & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_fcmgt(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.60 FCMGT (register) page C7-2147 line 125156 MATCH x7ec02400/mask=xffe0fc00
+# CONSTRUCT x7ec02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2
+# AUNIT --inst x7ec02400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags"
+# Scalar half precision variant
+
+:fcmgt Rd_FPR16, Rn_FPR16, Rm_FPR16
+is b_2131=0b01111110110 & b_1015=0b001001 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_fcmgt(Rn_FPR16, Rm_FPR16);
+}
+
+# C7.2.60 FCMGT (register) page C7-2147 line 125156 MATCH x7ea0e400/mask=xffa0fc00
+# CONSTRUCT x7ea0e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2
+# AUNIT --inst x7ea0e400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "noflags"
+# Scalar single-precision and double-precision variant sz=0
+
+:fcmgt Rd_FPR32, Rn_FPR32, Rm_FPR32
+is b_2331=0b011111101 & b_22=0 & b_21=1 & b_1015=0b111001 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_fcmgt(Rn_FPR32, Rm_FPR32);
+}
+
+# C7.2.60 FCMGT (register) page C7-2147 line 125156 MATCH x7ea0e400/mask=xffa0fc00
+# CONSTRUCT x7ee0e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2
+# AUNIT --inst x7ee0e400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "noflags"
+# Scalar single-precision and double-precision variant sz=1
+
+:fcmgt Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_2331=0b011111101 & b_22=1 & b_21=1 & b_1015=0b111001 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_fcmgt(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.60 FCMGT (register) page C7-2147 line 125156 MATCH x2ec02400/mask=xbfe0fc00
+# CONSTRUCT x2ec02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2@2
+# AUNIT --inst x2ec02400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags"
+# Vector half precision variant SIMD 4H when Q = 0
+
+:fcmgt Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2129=0b101110110 & b_1015=0b001001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_fcmgt(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.60 FCMGT (register) page C7-2147 line 125156 MATCH x2ec02400/mask=xbfe0fc00
+# CONSTRUCT x6ec02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcmgt/2@2
+# AUNIT --inst x6ec02400/mask=xffe0fc00 --rand hfp --status noqemu --comment "noflags"
+# Vector half precision variant SIMD 8H when Q = 1
+
+:fcmgt Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2129=0b101110110 & b_1015=0b001001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_fcmgt(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.61 FCMGT (zero) page C7-2151 line 125404 MATCH x0ea0c800/mask=xbfbffc00
+# CONSTRUCT x4ee0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmgt/2@8
+# AUNIT --inst x4ee0c800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags"
+
+:fcmgt Rd_VPR128.2D, Rn_VPR128.2D, "#0"
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x30 & b_1216=0xc & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_fcmgt(Rn_VPR128.2D, 0:8, 8:1);
+}
+
+# C7.2.61 FCMGT (zero) page C7-2151 line 125404 MATCH x0ea0c800/mask=xbfbffc00
+# CONSTRUCT x0ea0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmgt/2@4
+# AUNIT --inst x0ea0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
+
+:fcmgt Rd_VPR64.2S, Rn_VPR64.2S, "#0"
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xc & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_fcmgt(Rn_VPR64.2S, 0:4, 4:1);
+}
+
+# C7.2.61 FCMGT (zero) page C7-2151 line 125404 MATCH x0ea0c800/mask=xbfbffc00
+# CONSTRUCT x4ea0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmgt/2@4
+# AUNIT --inst x4ea0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
+
+:fcmgt Rd_VPR128.4S, Rn_VPR128.4S, "#0"
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xc & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_fcmgt(Rn_VPR128.4S, 0:4, 4:1);
+}
+
+# C7.2.61 FCMGT (zero) page C7-2151 line 125404 MATCH x5ef8c800/mask=xfffffc00
+# CONSTRUCT x5ef8c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmgt/2
+# AUNIT --inst x5ef8c800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
+# Scalar half precision variant
+
+:fcmgt Rd_FPR16, Rn_FPR16, "#0.0"
+is b_1031=0b0101111011111000110010 & Rd_FPR16 & Rn_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_fcmgt(Rn_FPR16, 0:2);
+}
+
+# C7.2.61 FCMGT (zero) page C7-2151 line 125404 MATCH x5ea0c800/mask=xffbffc00
+# CONSTRUCT x5ea0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmgt/2
+# AUNIT --inst x5ea0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
+# Scalar single-precision and double-precision sz=0
+
+:fcmgt Rd_FPR32, Rn_FPR32, "#0.0"
+is b_2331=0b010111101 & b_22=0 & b_1021=0b100000110010 & Rd_FPR32 & Rn_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_fcmgt(Rn_FPR32, 0:4);
+}
+
+# C7.2.61 FCMGT (zero) page C7-2151 line 125404 MATCH x5ea0c800/mask=xffbffc00
+# CONSTRUCT x5ee0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmgt/2
+# AUNIT --inst x5ee0c800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags"
+# Scalar single-precision and double-precision sz=1
+
+:fcmgt Rd_FPR64, Rn_FPR64, "#0.0"
+is b_2331=0b010111101 & b_22=1 & b_1021=0b100000110010 & Rd_FPR64 & Rn_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_fcmgt(Rn_FPR64, 0:8);
+}
+
+# C7.2.61 FCMGT (zero) page C7-2151 line 125404 MATCH x0ef8c800/mask=xbffffc00
+# CONSTRUCT x0ef8c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmgt/2@2
+# AUNIT --inst x0ef8c800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
+# Vector half precision variant SIMD 4H when Q = 0
+
+:fcmgt Rd_VPR64.4H, Rn_VPR64.4H, "#0.0"
+is b_31=0 & b_30=0 & b_1029=0b00111011111000110010 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_fcmgt(Rn_VPR64.4H, 0:2, 2:1);
+}
+
+# C7.2.61 FCMGT (zero) page C7-2151 line 125404 MATCH x0ef8c800/mask=xbffffc00
+# CONSTRUCT x4ef8c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmgt/2@2
+# AUNIT --inst x4ef8c800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
+# Vector half precision variant SIMD 8H when Q = 1
+
+:fcmgt Rd_VPR128.8H, Rn_VPR128.8H, "#0.0"
+is b_31=0 & b_30=1 & b_1029=0b00111011111000110010 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_fcmgt(Rn_VPR128.8H, 0:2, 2:1);
+}
+
+# C7.2.55 FCMLA (by element) page C7-1117 line 64749 KEEPWITH
+
+fcmla_rotate: #0 is b_15=0 & b_1314=0b00 { export 0:1; }
+fcmla_rotate: #90 is b_15=0 & b_1314=0b01 { export 90:1; }
+fcmla_rotate: #180 is b_15=0 & b_1314=0b10 { export 180:1; }
+fcmla_rotate: #270 is b_15=0 & b_1314=0b11 { export 270:1; }
+fcmla_rotate: #0 is b_15=1 & b_1112=0b00 { export 0:1; }
+fcmla_rotate: #90 is b_15=1 & b_1112=0b01 { export 90:1; }
+fcmla_rotate: #180 is b_15=1 & b_1112=0b10 { export 180:1; }
+fcmla_rotate: #270 is b_15=1 & b_1112=0b11 { export 270:1; }
+
+# C7.2.62 FCMLA (by element) page C7-2154 line 125620 MATCH x2f001000/mask=xbf009400
+# CONSTRUCT x2f401000/mask=xffc09c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@2
+# AUNIT --inst x2f401000/mask=xffc09c00 --rand hfp --status noqemu --comment "noflags"
+# The representation of Rm in the documentation as a 4 bit field
+# extended by M actually makes it a standard 5 bit field.
+# 4H variant when size = 01 , Q = 0 T=VPR64.4H imm=Re_VPR128.H.vIndexHL i1=Re_VPR128.H i2=vIndexHL
+# NOTE: if size == '01' and H == '1' && Q == '0' then ReservedValue();
+
+:fcmla Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128.H.vIndexHL, fcmla_rotate
+is b_31=0 & b_30=0 & b_2429=0b101111 & b_2223=0b01 & b_15=0 & b_12=1 & b_11=0 & b_10=0 & fcmla_rotate & Rd_VPR64.4H & Rn_VPR64.4H & Re_VPR128.H.vIndexHL & Re_VPR128.H & vIndexHL & Zd
+{
+ local tmp1:2 = SIMD_PIECE(Re_VPR128.H, vIndexHL:1);
+ Rd_VPR64.4H = NEON_fcmla(Rn_VPR64.4H, tmp1, fcmla_rotate, 2:1);
+}
+
+# C7.2.62 FCMLA (by element) page C7-2154 line 125620 MATCH x2f001000/mask=xbf009400
+# CONSTRUCT x6f401000/mask=xffc09400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@2
+# AUNIT --inst x6f401000/mask=xffc09400 --rand hfp --status noqemu --comment "noflags"
+# 8H variant when size = 01 , Q = 1 T=VPR128.8H imm=Re_VPR128.H.vIndexHL i1=Re_VPR128.H i2=vIndexHL
+
+:fcmla Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128.H.vIndexHL, fcmla_rotate
+is b_31=0 & b_30=1 & b_2429=0b101111 & b_2223=0b01 & b_15=0 & b_12=1 & b_10=0 & fcmla_rotate & Rd_VPR128.8H & Rn_VPR128.8H & Re_VPR128.H.vIndexHL & Re_VPR128.H & vIndexHL & Zd
+{
+ local tmp1:2 = SIMD_PIECE(Re_VPR128.H, vIndexHL:1);
+ Rd_VPR128.8H = NEON_fcmla(Rn_VPR128.8H, tmp1, fcmla_rotate, 2:1);
+}
+
+# C7.2.62 FCMLA (by element) page C7-2154 line 125620 MATCH x2f001000/mask=xbf009400
+# CONSTRUCT x6f801000/mask=xffe09400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@4
+# AUNIT --inst x6f801000/mask=xffe09400 --rand sfp --status noqemu --comment "noflags"
+# 4S variant when size = 10 , Q = 1 T=VPR128.4S imm=Re_VPR128.S.vIndex i1=Re_VPR128.S i2=vIndex
+# NOTE: if size == '10' and (L == '1' || Q == '0') then ReservedValue();
+
+:fcmla Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex, fcmla_rotate
+is b_31=0 & b_30=1 & b_2429=0b101111 & b_2223=0b10 & b_21=0 & b_15=0 & b_12=1 & b_10=0 & fcmla_rotate & Rd_VPR128.4S & Rn_VPR128.4S & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Zd
+{
+ local tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1);
+ Rd_VPR128.4S = NEON_fcmla(Rn_VPR128.4S, tmp1, fcmla_rotate, 4:1);
+}
+
+# C7.2.63 FCMLA page C7-2157 line 125798 MATCH x2e00c400/mask=xbf20e400
+# CONSTRUCT x2e40c400/mask=xffe0e400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@4
+# AUNIT --inst x2e40c400/mask=xffe0e400 --rand hfp --status noqemu --comment "noflags"
+# FCMLA SIMD 4H when size = 01 , Q = 0
+
+:fcmla Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H, fcmla_rotate
+is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_21=0 & b_1315=0b110 & b_10=1 & fcmla_rotate & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_fcmla(Rn_VPR64.4H, Rm_VPR64.4H, fcmla_rotate, 4:1);
+}
+
+# C7.2.63 FCMLA page C7-2157 line 125798 MATCH x2e00c400/mask=xbf20e400
+# CONSTRUCT x6e40c400/mask=xffe0e400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@4
+# AUNIT --inst x6e40c400/mask=xffe0e400 --rand hfp --status noqemu --comment "noflags"
+# FCMLA SIMD 8H when size = 01 , Q = 1
+
+:fcmla Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H, fcmla_rotate
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_21=0 & b_1315=0b110 & b_10=1 & fcmla_rotate & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_fcmla(Rn_VPR128.8H, Rm_VPR128.8H, fcmla_rotate, 4:1);
+}
+
+# C7.2.63 FCMLA page C7-2157 line 125798 MATCH x2e00c400/mask=xbf20e400
+# CONSTRUCT x2e80c400/mask=xffe0e400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@4
+# AUNIT --inst x2e80c400/mask=xffe0e400 --rand sfp --status noqemu --comment "noflags"
+# FCMLA SIMD 2S when size = 10 , Q = 0
+
+:fcmla Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S, fcmla_rotate
+is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_21=0 & b_1315=0b110 & b_10=1 & fcmla_rotate & Rd_VPR64.2S & Rn_VPR64.2S & Rm_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_fcmla(Rn_VPR64.2S, Rm_VPR64.2S, fcmla_rotate, 4:1);
+}
+
+# C7.2.63 FCMLA page C7-2157 line 125798 MATCH x2e00c400/mask=xbf20e400
+# CONSTRUCT x6e80c400/mask=xffe0e400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@4
+# AUNIT --inst x6e80c400/mask=xffe0e400 --rand sfp --status noqemu --comment "noflags"
+# FCMLA SIMD 4S when size = 10 , Q = 1
+
+:fcmla Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, fcmla_rotate
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_21=0 & b_1315=0b110 & b_10=1 & fcmla_rotate & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_fcmla(Rn_VPR128.4S, Rm_VPR128.4S, fcmla_rotate, 4:1);
+}
+
+# C7.2.63 FCMLA page C7-2157 line 125798 MATCH x2e00c400/mask=xbf20e400
+# CONSTRUCT x6ec0c400/mask=xffe0e400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fcmla/3@4
+# AUNIT --inst x6ec0c400/mask=xffe0e400 --rand dfp --status noqemu --comment "noflags"
+# FCMLA SIMD 2D when size = 11 , Q = 1
+
+:fcmla Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D, fcmla_rotate
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b11 & b_21=0 & b_1315=0b110 & b_10=1 & fcmla_rotate & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_fcmla(Rn_VPR128.2D, Rm_VPR128.2D, fcmla_rotate, 4:1);
+}
+
+# C7.2.64 FCMLE (zero) page C7-2160 line 125952 MATCH x2ea0d800/mask=xbfbffc00
+# CONSTRUCT x6ee0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmle/2@8
+# AUNIT --inst x6ee0d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags"
+
+:fcmle Rd_VPR128.2D, Rn_VPR128.2D, "#0"
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & b_23=1 & b_1722=0x30 & b_1216=0xd & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_fcmle(Rn_VPR128.2D, 0:8, 8:1);
+}
+
+# C7.2.64 FCMLE (zero) page C7-2160 line 125952 MATCH x2ea0d800/mask=xbfbffc00
+# CONSTRUCT x2ea0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmle/2@2
+# AUNIT --inst x2ea0d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
+
+:fcmle Rd_VPR64.2S, Rn_VPR64.2S, "#0"
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xd & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_fcmle(Rn_VPR64.2S, 0:2, 2:1);
+}
+
+# C7.2.64 FCMLE (zero) page C7-2160 line 125952 MATCH x2ea0d800/mask=xbfbffc00
+# CONSTRUCT x6ea0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmle/2@4
+# AUNIT --inst x6ea0d800/mask=xfffffc00 --rand sfp --status nopcodeop
+
+:fcmle Rd_VPR128.4S, Rn_VPR128.4S, "#0"
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xd & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_fcmle(Rn_VPR128.4S, 0:4, 4:1);
+}
+
+# C7.2.64 FCMLE (zero) page C7-2160 line 125952 MATCH x7ef8d800/mask=xfffffc00
+# CONSTRUCT x7ef8d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmle/2
+# AUNIT --inst x7ef8d800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
+# Scalar half precision variant
+
+:fcmle Rd_FPR16, Rn_FPR16, "#0.0"
+is b_1031=0b0111111011111000110110 & Rd_FPR16 & Rn_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_fcmle(Rn_FPR16, 0:2);
+}
+
+# C7.2.64 FCMLE (zero) page C7-2160 line 125952 MATCH x7ea0d800/mask=xffbffc00
+# CONSTRUCT x7ea0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmle/2
+# AUNIT --inst x7ea0d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
+# Scalar single-precision and double-precision sz=0
+
+:fcmle Rd_FPR32, Rn_FPR32, "#0.0"
+is b_2331=0b011111101 & b_22=0 & b_1021=0b100000110110 & Rd_FPR32 & Rn_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_fcmle(Rn_FPR32, 0:4);
+}
+
+# C7.2.64 FCMLE (zero) page C7-2160 line 125952 MATCH x7ea0d800/mask=xffbffc00
+# CONSTRUCT x7ee0d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmle/2
+# AUNIT --inst x7ee0d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags"
+# Scalar single-precision and double-precision sz=1
+
+:fcmle Rd_FPR64, Rn_FPR64, "#0.0"
+is b_2331=0b011111101 & b_22=1 & b_1021=0b100000110110 & Rd_FPR64 & Rn_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_fcmle(Rn_FPR64, 0:8);
+}
+
+# C7.2.64 FCMLE (zero) page C7-2160 line 125952 MATCH x2ef8d800/mask=xbffffc00
+# CONSTRUCT x2ef8d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmle/2@2
+# AUNIT --inst x2ef8d800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
+# Vector half precision variant SIMD 4H when Q = 0
+
+:fcmle Rd_VPR64.4H, Rn_VPR64.4H, "#0.0"
+is b_31=0 & b_30=0 & b_1029=0b10111011111000110110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_fcmle(Rn_VPR64.4H, 0:2, 2:1);
+}
+
+# C7.2.64 FCMLE (zero) page C7-2160 line 125952 MATCH x2ef8d800/mask=xbffffc00
+# CONSTRUCT x6ef8d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmle/2@2
+# AUNIT --inst x6ef8d800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
+# Vector half precision variant SIMD 8H when Q = 1
+
+:fcmle Rd_VPR128.8H, Rn_VPR128.8H, "#0.0"
+is b_31=0 & b_30=1 & b_1029=0b10111011111000110110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_fcmle(Rn_VPR128.8H, 0:2, 2:1);
+}
+
+# C7.2.65 FCMLT (zero) page C7-2163 line 126168 MATCH x0ea0e800/mask=xbfbffc00
+# CONSTRUCT x4ee0e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmlt/2@8
+# AUNIT --inst x4ee0e800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags"
+
+:fcmlt Rd_VPR128.2D, Rn_VPR128.2D, "#0"
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x30 & b_1216=0xe & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_fcmlt(Rn_VPR128.2D, 0:8, 8:1);
+}
+
+# C7.2.65 FCMLT (zero) page C7-2163 line 126168 MATCH x0ea0e800/mask=xbfbffc00
+# CONSTRUCT x0ea0e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmlt/2@4
+# AUNIT --inst x0ea0e800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
+
+:fcmlt Rd_VPR64.2S, Rn_VPR64.2S, "#0"
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xe & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_fcmlt(Rn_VPR64.2S, 0:4, 4:1);
+}
+
+# C7.2.65 FCMLT (zero) page C7-2163 line 126168 MATCH x0ea0e800/mask=xbfbffc00
+# CONSTRUCT x4ea0e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmlt/2@4
+# AUNIT --inst x4ea0e800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
+
+:fcmlt Rd_VPR128.4S, Rn_VPR128.4S, "#0"
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & b_23=1 & b_1722=0x10 & b_1216=0xe & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_fcmlt(Rn_VPR128.4S, 0:4, 4:1);
+}
+
+# C7.2.65 FCMLT (zero) page C7-2163 line 126168 MATCH x5ef8e800/mask=xfffffc00
+# CONSTRUCT x5ef8e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmlt/2
+# AUNIT --inst x5ef8e800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
+# Scalar half precision variant
+
+:fcmlt Rd_FPR16, Rn_FPR16, "#0.0"
+is b_1031=0b0101111011111000111010 & Rd_FPR16 & Rn_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_fcmlt(Rn_FPR16, 0:2);
+}
+
+# C7.2.65 FCMLT (zero) page C7-2163 line 126168 MATCH x5ea0e800/mask=xffbffc00
+# CONSTRUCT x5ea0e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:4 =NEON_fcmlt/2
+# AUNIT --inst x5ea0e800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "noflags"
+# Scalar single-precision and double-precision sz=0
+
+:fcmlt Rd_FPR32, Rn_FPR32, "#0.0"
+is b_2331=0b010111101 & b_22=0 & b_1021=0b100000111010 & Rd_FPR32 & Rn_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_fcmlt(Rn_FPR32, 0:4);
+}
+
+# C7.2.65 FCMLT (zero) page C7-2163 line 126168 MATCH x5ea0e800/mask=xffbffc00
+# CONSTRUCT x5ee0e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:8 =NEON_fcmlt/2
+# AUNIT --inst x5ee0e800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "noflags"
+# Scalar single-precision and double-precision sz=1
+
+:fcmlt Rd_FPR64, Rn_FPR64, "#0.0"
+is b_2331=0b010111101 & b_22=1 & b_1021=0b100000111010 & Rd_FPR64 & Rn_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_fcmlt(Rn_FPR64, 0:8);
+}
+
+# C7.2.65 FCMLT (zero) page C7-2163 line 126168 MATCH x0ef8e800/mask=xbffffc00
+# CONSTRUCT x0ef8e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmlt/2@2
+# AUNIT --inst x0ef8e800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
+# Vector half precision variant SIMD 4H when Q = 0
+
+:fcmlt Rd_VPR64.4H, Rn_VPR64.4H, "#0.0"
+is b_31=0 & b_30=0 & b_1029=0b00111011111000111010 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_fcmlt(Rn_VPR64.4H, 0:2, 2:1);
+}
+
+# C7.2.65 FCMLT (zero) page C7-2163 line 126168 MATCH x0ef8e800/mask=xbffffc00
+# CONSTRUCT x4ef8e800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 0:2 =NEON_fcmlt/2@2
+# AUNIT --inst x4ef8e800/mask=xfffffc00 --rand hfp --status noqemu --comment "noflags"
+# Vector half precision variant SIMD 8H when Q = 1
+
+:fcmlt Rd_VPR128.8H, Rn_VPR128.8H, "#0.0"
+is b_31=0 & b_30=1 & b_1029=0b00111011111000111010 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_fcmlt(Rn_VPR128.8H, 0:2, 2:1);
+}
+
+# C7.2.66 FCMP page C7-2166 line 126365 MATCH x1e202000/mask=xff20fc17
+# CONSTRUCT x1e602000/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES
+# SMACRO null ARG1 ARG2 =fcomp/2
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmp/2
+# AUNIT --inst x1e602000/mask=xffe0fc1f --rand dfp --status nodest --comment "flags"
+
+:fcmp Rn_FPR64, Rm_FPR64
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR64 & fpcmp.opcode2=0x0
+{
+ fcomp(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.66 FCMP page C7-2166 line 126365 MATCH x1e202000/mask=xff20fc17
+# CONSTRUCT x1e602008/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES
+# SMACRO null ARG1 ARG2 =fcomp/2
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmp/2
+# AUNIT --inst x1e602008/mask=xffe0fc1f --rand dfp --status nodest --comment "flags"
+
+:fcmp Rn_FPR64, Rm_fpz64
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_fpz64 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR64 & fpcmp.opcode2=0x8
+{
+ fcomp(Rn_FPR64, Rm_fpz64);
+}
+
+# C7.2.66 FCMP page C7-2166 line 126365 MATCH x1e202000/mask=xff20fc17
+# CONSTRUCT x1e202008/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES
+# SMACRO null ARG1 ARG2 =fcomp/2
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmp/2
+# AUNIT --inst x1e202008/mask=xffe0fc1f --rand sfp --status nodest --comment "flags"
+
+:fcmp Rn_FPR32, Rm_fpz32
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_fpz32 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR32 & fpcmp.opcode2=0x8
+{
+ fcomp(Rn_FPR32, Rm_fpz32);
+}
+
+# C7.2.66 FCMP page C7-2166 line 126365 MATCH x1e202000/mask=xff20fc17
+# CONSTRUCT x1e202000/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES
+# SMACRO null ARG1 ARG2 =fcomp/2
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmp/2
+# AUNIT --inst x1e202000/mask=xffe0fc1f --rand sfp --status nodest --comment "flags"
+
+:fcmp Rn_FPR32, Rm_FPR32
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR32 & fpcmp.opcode2=0x0
+{
+ fcomp(Rn_FPR32, Rm_FPR32);
+}
+
+# C7.2.66 FCMP page C7-2166 line 126365 MATCH x1e202000/mask=xff20fc17
+# CONSTRUCT x1ee02008/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES
+# SMACRO null ARG1 ARG2 =fcomp/2
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmp/2
+# AUNIT --inst x1ee02008/mask=xffe0fc1f --rand hfp --status nodest --comment "flags"
+
+:fcmp Rn_FPR16, Rm_fpz16
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_fpz16 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR16 & fpcmp.opcode2=0x8
+{
+ fcomp(Rn_FPR16, Rm_fpz16);
+}
+
+# C7.2.66 FCMP page C7-2166 line 126365 MATCH x1e202000/mask=xff20fc17
+# CONSTRUCT x1ee02000/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES
+# SMACRO null ARG1 ARG2 =fcomp/2
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmp/2
+# AUNIT --inst x1ee02000/mask=xffe0fc1f --rand hfp --status nodest --comment "flags"
+
+:fcmp Rn_FPR16, Rm_FPR16
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR16 & fpcmp.opcode2=0x0
+{
+ fcomp(Rn_FPR16, Rm_FPR16);
+}
+
+# C7.2.67 FCMPE page C7-2168 line 126506 MATCH x1e202010/mask=xff20fc17
+# CONSTRUCT x1e602010/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES
+# SMACRO null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmpe/2
+# AUNIT --inst x1e602010/mask=xffe0fc1f --rand dfp --status nodest --comment "flags"
+
+:fcmpe Rn_FPR64, Rm_FPR64
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR64 & fpcmp.opcode2=0x10
+{
+ ftestNAN(Rn_FPR64, Rm_FPR64);
+ fcomp(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.67 FCMPE page C7-2168 line 126506 MATCH x1e202010/mask=xff20fc17
+# CONSTRUCT x1e602018/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES
+# SMACRO null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmpe/2
+# AUNIT --inst x1e602018/mask=xffe0fc1f --rand dfp --status nodest --comment "flags"
+
+:fcmpe Rn_FPR64, Rm_fpz64
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_fpz64 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR64 & fpcmp.opcode2=0x18
+{
+ ftestNAN(Rn_FPR64, Rm_fpz64);
+ fcomp(Rn_FPR64, Rm_fpz64);
+}
+
+# C7.2.67 FCMPE page C7-2168 line 126506 MATCH x1e202010/mask=xff20fc17
+# CONSTRUCT x1e202018/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES
+# SMACRO null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmpe/2
+# AUNIT --inst x1e202018/mask=xffe0fc1f --rand sfp --status nodest --comment "flags"
+
+:fcmpe Rn_FPR32, Rm_fpz32
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_fpz32 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR32 & fpcmp.opcode2=0x18
+{
+ ftestNAN(Rn_FPR32, Rm_fpz32);
+ fcomp(Rn_FPR32, Rm_fpz32);
+}
+
+# C7.2.67 FCMPE page C7-2168 line 126506 MATCH x1e202010/mask=xff20fc17
+# CONSTRUCT x1e202010/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES
+# SMACRO null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmpe/2
+# AUNIT --inst x1e202010/mask=xffe0fc1f --rand sfp --status nodest --comment "flags"
+
+:fcmpe Rn_FPR32, Rm_FPR32
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR32 & fpcmp.opcode2=0x10
+{
+ ftestNAN(Rn_FPR32, Rm_FPR32);
+ fcomp(Rn_FPR32, Rm_FPR32);
+}
+
+# C7.2.67 FCMPE page C7-2168 line 126506 MATCH x1e202010/mask=xff20fc17
+# CONSTRUCT x1ee02018/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES
+# SMACRO null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmpe/2
+# AUNIT --inst x1ee02018/mask=xffe0fc1f --rand hfp --status nodest --comment "flags"
+
+:fcmpe Rn_FPR16, Rm_fpz16
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_fpz16 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR16 & fpcmp.opcode2=0x18
+{
+ ftestNAN(Rn_FPR16, Rm_fpz16);
+ fcomp(Rn_FPR16, Rm_fpz16);
+}
+
+# C7.2.67 FCMPE page C7-2168 line 126506 MATCH x1e202010/mask=xff20fc17
+# CONSTRUCT x1ee02010/mask=xffe0fc1f MATCHED 1 DOCUMENTED OPCODES
+# SMACRO null ARG1 ARG2 =ftestNAN/2 null ARG1 ARG2 =fcomp/2
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_fcmpe/2
+# AUNIT --inst x1ee02010/mask=xffe0fc1f --rand hfp --status nodest --comment "flags"
+
+:fcmpe Rn_FPR16, Rm_FPR16
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & fpcmp.op=0 & b_1013=0x8 & Rn_FPR16 & fpcmp.opcode2=0x10
+{
+ ftestNAN(Rn_FPR16, Rm_FPR16);
+ fcomp(Rn_FPR16, Rm_FPR16);
+}
+
+# C7.2.68 FCSEL page C7-2170 line 126647 MATCH x1e200c00/mask=xff200c00
+# CONSTRUCT x1e600c00/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 = dup ext swap ARG4:1 inst_next goto =
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4:1 =NEON_fcsel/3
+# AUNIT --inst x1e600c00/mask=xffe00c00 --rand dfp --status pass --comment "flags"
+# Rm may be the same register as Rd, so it needs to be saved
+
+:fcsel Rd_FPR64, Rn_FPR64, Rm_FPR64, CondOp
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & CondOp & b_1011=3 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ local tmp1:8 = Rm_FPR64;
+ Rd_FPR64 = Rn_FPR64;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+ if (CondOp:1) goto inst_next;
+ Rd_FPR64 = tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.68 FCSEL page C7-2170 line 126647 MATCH x1e200c00/mask=xff200c00
+# CONSTRUCT x1e200c00/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 = dup ext swap ARG4:1 inst_next goto =
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4:1 =NEON_fcsel/3
+# AUNIT --inst x1e200c00/mask=xffe00c00 --rand sfp --status pass --comment "flags"
+
+:fcsel Rd_FPR32, Rn_FPR32, Rm_FPR32, CondOp
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & CondOp & b_1011=3 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ local tmp1:4 = Rm_FPR32;
+ Rd_FPR32 = Rn_FPR32;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+ if (CondOp:1) goto inst_next;
+ Rd_FPR32 = tmp1;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.68 FCSEL page C7-2170 line 126647 MATCH x1e200c00/mask=xff200c00
+# CONSTRUCT x1ee00c00/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 = dup ext swap ARG4:1 inst_next goto =
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4:1 =NEON_fcsel/3
+# AUNIT --inst x1ee00c00/mask=xffe00c00 --rand hfp --status noqemu --comment "flags"
+
+:fcsel Rd_FPR16, Rn_FPR16, Rm_FPR16, CondOp
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & CondOp & b_1011=3 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ local tmp1:2 = Rm_FPR16;
+ Rd_FPR16 = Rn_FPR16;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+ if (CondOp:1) goto inst_next;
+ Rd_FPR16 = tmp1;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.69 FCVT page C7-2172 line 126762 MATCH x1e224000/mask=xff3e7c00
+# CONSTRUCT x1ee2c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =float2float/1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt/1
+# AUNIT --inst x1ee2c000/mask=xfffffc00 --rand hfp --status pass --comment "nofpround"
+
+:fcvt Rd_FPR64, Rn_FPR16
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & fpDpOpcode=0x5 & b_1014=0x10 & Rn_FPR16 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = float2float(Rn_FPR16);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.69 FCVT page C7-2172 line 126762 MATCH x1e224000/mask=xff3e7c00
+# CONSTRUCT x1e22c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =float2float/1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt/1
+# AUNIT --inst x1e22c000/mask=xfffffc00 --rand sfp --status pass --comment "nofpround"
+
+:fcvt Rd_FPR64, Rn_FPR32
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & fpDpOpcode=0x5 & b_1014=0x10 & Rn_FPR32 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = float2float(Rn_FPR32);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.69 FCVT page C7-2172 line 126762 MATCH x1e224000/mask=xff3e7c00
+# CONSTRUCT x1e63c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =float2float/1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt/1
+# AUNIT --inst x1e63c000/mask=xfffffc00 --rand hfp --status pass --comment "nofpround"
+
+:fcvt Rd_FPR16, Rn_FPR64
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & fpDpOpcode=0x7 & b_1014=0x10 & Rn_FPR64 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = float2float(Rn_FPR64);
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.69 FCVT page C7-2172 line 126762 MATCH x1e224000/mask=xff3e7c00
+# CONSTRUCT x1e23c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =float2float/1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt/1
+# AUNIT --inst x1e23c000/mask=xfffffc00 --rand hfp --status fail --comment "nofpround"
+
+:fcvt Rd_FPR16, Rn_FPR32
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & fpDpOpcode=0x7 & b_1014=0x10 & Rn_FPR32 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = float2float(Rn_FPR32);
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.69 FCVT page C7-2172 line 126762 MATCH x1e224000/mask=xff3e7c00
+# CONSTRUCT x1e624000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =float2float/1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt/1
+# AUNIT --inst x1e624000/mask=xfffffc00 --rand sfp --status fail --comment "nofpround"
+
+:fcvt Rd_FPR32, Rn_FPR64
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & fpDpOpcode=0x4 & b_1014=0x10 & Rn_FPR64 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = float2float(Rn_FPR64);
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.69 FCVT page C7-2172 line 126762 MATCH x1e224000/mask=xff3e7c00
+# CONSTRUCT x1ee24000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =float2float/1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt/1
+# AUNIT --inst x1ee24000/mask=xfffffc00 --rand hfp --status pass --comment "nofpround"
+
+:fcvt Rd_FPR32, Rn_FPR16
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & fpDpOpcode=0x4 & b_1014=0x10 & Rn_FPR16 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = float2float(Rn_FPR16);
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.63 FCVTAS (vector) page C7-1136 line 65961 KEEPWITH
+
+fcvt_vmnemonic: "fcvtas" is b_29=0 & b_23=0 & b_1314=0b10 & b_12=0 { }
+fcvt_vmnemonic: "fcvtau" is b_29=1 & b_23=0 & b_1314=0b10 & b_12=0 { }
+fcvt_vmnemonic: "fcvtms" is b_29=0 & b_23=0 & b_1314=0b01 & b_12=1 { }
+fcvt_vmnemonic: "fcvtmu" is b_29=1 & b_23=0 & b_1314=0b01 & b_12=1 { }
+fcvt_vmnemonic: "fcvtns" is b_29=0 & b_23=0 & b_1314=0b01 & b_12=0 { }
+fcvt_vmnemonic: "fcvtnu" is b_29=1 & b_23=0 & b_1314=0b01 & b_12=0 { }
+fcvt_vmnemonic: "fcvtps" is b_29=0 & b_23=1 & b_1314=0b01 & b_12=0 { }
+fcvt_vmnemonic: "fcvtpu" is b_29=1 & b_23=1 & b_1314=0b01 & b_12=0 { }
+fcvt_vmnemonic: "fcvtzs" is b_29=0 & b_23=1 & b_1314=0b01 & b_12=1 { }
+fcvt_vmnemonic: "fcvtzu" is b_29=1 & b_23=1 & b_1314=0b01 & b_12=1 { }
+
+fcvt_smnemonic: "fcvtas" is b_1920=0b00 & b_1618=0b100 { }
+fcvt_smnemonic: "fcvtau" is b_1920=0b00 & b_1618=0b101 { }
+fcvt_smnemonic: "fcvtms" is b_1920=0b10 & b_1618=0b000 { }
+fcvt_smnemonic: "fcvtmu" is b_1920=0b10 & b_1618=0b001 { }
+fcvt_smnemonic: "fcvtns" is b_1920=0b00 & b_1618=0b000 { }
+fcvt_smnemonic: "fcvtnu" is b_1920=0b00 & b_1618=0b001 { }
+fcvt_smnemonic: "fcvtps" is b_1920=0b01 & b_1618=0b000 { }
+fcvt_smnemonic: "fcvtpu" is b_1920=0b01 & b_1618=0b001 { }
+fcvt_smnemonic: "fcvtzs" is b_1920=0b11 & b_1618=0b000 { }
+fcvt_smnemonic: "fcvtzu" is b_1920=0b11 & b_1618=0b001 { }
+
+# C7.2.70 FCVTAS (vector) page C7-2174 line 126882 MATCH x5e79c800/mask=xfffffc00
+# C7.2.72 FCVTAU (vector) page C7-2179 line 127203 MATCH x7e79c800/mask=xfffffc00
+# CONSTRUCT x5e79c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =trunc
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
+# AUNIT --inst x5e79c800/mask=xdffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Scalar half precision
+
+:^fcvt_vmnemonic Rd_FPR16, Rn_FPR16
+is b_3031=0b01 & b_1028=0b1111001111001110010 & fcvt_vmnemonic & Rd_FPR16 & Rn_FPR16 & Zd
+{
+ Rd_FPR16 = trunc(Rn_FPR16);
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.70 FCVTAS (vector) page C7-2174 line 126882 MATCH x5e21c800/mask=xffbffc00
+# C7.2.72 FCVTAU (vector) page C7-2179 line 127203 MATCH x7e21c800/mask=xffbffc00
+# CONSTRUCT x5e21c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =trunc
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
+# AUNIT --inst x5e21c800/mask=xdffffc00 --rand sfp --status fail --comment "nofpround"
+# Scalar single-precision and double-precision variant sz=0
+
+:^fcvt_vmnemonic Rd_FPR32, Rn_FPR32
+is b_3031=0b01 & b_2328=0b111100 & b_22=0 & b_1021=0b100001110010 & fcvt_vmnemonic & Rd_FPR32 & Rn_FPR32 & Zd
+{
+ Rd_FPR32 = trunc(Rn_FPR32);
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.70 FCVTAS (vector) page C7-2174 line 126882 MATCH x5e21c800/mask=xffbffc00
+# C7.2.72 FCVTAU (vector) page C7-2179 line 127203 MATCH x7e21c800/mask=xffbffc00
+# CONSTRUCT x5e61c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =trunc
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
+# AUNIT --inst x5e61c800/mask=xdffffc00 --rand dfp --status fail --comment "nofpround"
+# Scalar single-precision and double-precision variant sz=1
+
+:^fcvt_vmnemonic Rd_FPR64, Rn_FPR64
+is b_3031=0b01 & b_2328=0b111100 & b_22=1 & b_1021=0b100001110010 & fcvt_vmnemonic & Rd_FPR64 & Rn_FPR64 & Zd
+{
+ Rd_FPR64 = trunc(Rn_FPR64);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.70 FCVTAS (vector) page C7-2174 line 126882 MATCH x0e79c800/mask=xbffffc00
+# C7.2.72 FCVTAU (vector) page C7-2179 line 127203 MATCH x2e79c800/mask=xbffffc00
+# CONSTRUCT x0e79c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$trunc@2
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@2
+# AUNIT --inst x0e79c800/mask=xdffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Vector half precision variant Q=0
+
+:^fcvt_vmnemonic Rd_VPR64.4H, Rn_VPR64.4H
+is b_31=0 & b_30=0 & b_2328=0b011100 & b_1022=0b1111001110010 & fcvt_vmnemonic & Rd_VPR64.4H & Rn_VPR64.4H & Zd
+{
+ # simd unary Rd_VPR64.4H = trunc(Rn_VPR64.4H) on lane size 2
+ Rd_VPR64.4H[0,16] = trunc(Rn_VPR64.4H[0,16]);
+ Rd_VPR64.4H[16,16] = trunc(Rn_VPR64.4H[16,16]);
+ Rd_VPR64.4H[32,16] = trunc(Rn_VPR64.4H[32,16]);
+ Rd_VPR64.4H[48,16] = trunc(Rn_VPR64.4H[48,16]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.70 FCVTAS (vector) page C7-2174 line 126882 MATCH x0e79c800/mask=xbffffc00
+# C7.2.72 FCVTAU (vector) page C7-2179 line 127203 MATCH x2e79c800/mask=xbffffc00
+# CONSTRUCT x4e79c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$trunc@2
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@2
+# AUNIT --inst x4e79c800/mask=xdffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Vector half precision variant Q=1
+
+:^fcvt_vmnemonic Rd_VPR128.8H, Rn_VPR128.8H
+is b_31=0 & b_30=1 & b_2328=0b011100 & b_1022=0b1111001110010 & fcvt_vmnemonic & Rd_VPR128.8H & Rn_VPR128.8H & Zd
+{
+ # simd unary Rd_VPR128.8H = trunc(Rn_VPR128.8H) on lane size 2
+ Rd_VPR128.8H[0,16] = trunc(Rn_VPR128.8H[0,16]);
+ Rd_VPR128.8H[16,16] = trunc(Rn_VPR128.8H[16,16]);
+ Rd_VPR128.8H[32,16] = trunc(Rn_VPR128.8H[32,16]);
+ Rd_VPR128.8H[48,16] = trunc(Rn_VPR128.8H[48,16]);
+ Rd_VPR128.8H[64,16] = trunc(Rn_VPR128.8H[64,16]);
+ Rd_VPR128.8H[80,16] = trunc(Rn_VPR128.8H[80,16]);
+ Rd_VPR128.8H[96,16] = trunc(Rn_VPR128.8H[96,16]);
+ Rd_VPR128.8H[112,16] = trunc(Rn_VPR128.8H[112,16]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.70 FCVTAS (vector) page C7-2174 line 126882 MATCH x0e21c800/mask=xbfbffc00
+# C7.2.72 FCVTAU (vector) page C7-2179 line 127203 MATCH x2e21c800/mask=xbfbffc00
+# CONSTRUCT x0e21c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$trunc@4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@4
+# AUNIT --inst x0e21c800/mask=xdffffc00 --rand sfp --status fail --comment "nofpround"
+# Vector single-precision and double-precision variant SIMD 2S when sz = 0 , Q = 0
+
+:^fcvt_vmnemonic Rd_VPR64.2S, Rn_VPR64.2S
+is b_31=0 & b_30=0 & b_2328=0b011100 & b_22=0 & b_1021=0b100001110010 & fcvt_vmnemonic & Rd_VPR64.2S & Rn_VPR64.2S & Zd
+{
+ # simd unary Rd_VPR64.2S = trunc(Rn_VPR64.2S) on lane size 4
+ Rd_VPR64.2S[0,32] = trunc(Rn_VPR64.2S[0,32]);
+ Rd_VPR64.2S[32,32] = trunc(Rn_VPR64.2S[32,32]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.70 FCVTAS (vector) page C7-2174 line 126882 MATCH x0e21c800/mask=xbfbffc00
+# C7.2.72 FCVTAU (vector) page C7-2179 line 127203 MATCH x2e21c800/mask=xbfbffc00
+# CONSTRUCT x4e21c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$trunc@4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@4
+# AUNIT --inst x4e21c800/mask=xdffffc00 --rand sfp --status fail --comment "nofpround"
+# Vector single-precision and double-precision variant SIMD 4S when sz = 0 , Q = 1
+
+:^fcvt_vmnemonic Rd_VPR128.4S, Rn_VPR128.4S
+is b_31=0 & b_30=1 & b_2328=0b011100 & b_22=0 & b_1021=0b100001110010 & fcvt_vmnemonic & Rd_VPR128.4S & Rn_VPR128.4S & Zd
+{
+ # simd unary Rd_VPR128.4S = trunc(Rn_VPR128.4S) on lane size 4
+ Rd_VPR128.4S[0,32] = trunc(Rn_VPR128.4S[0,32]);
+ Rd_VPR128.4S[32,32] = trunc(Rn_VPR128.4S[32,32]);
+ Rd_VPR128.4S[64,32] = trunc(Rn_VPR128.4S[64,32]);
+ Rd_VPR128.4S[96,32] = trunc(Rn_VPR128.4S[96,32]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.70 FCVTAS (vector) page C7-2174 line 126882 MATCH x0e21c800/mask=xbfbffc00
+# C7.2.72 FCVTAU (vector) page C7-2179 line 127203 MATCH x2e21c800/mask=xbfbffc00
+# CONSTRUCT x4e61c800/mask=xdffffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$trunc@8
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@8
+# AUNIT --inst x4e61c800/mask=xdffffc00 --rand dfp --status fail --comment "nofpround"
+# Vector single-precision and double-precision variant SIMD 2D when sz = 1 , Q = 1
+
+:^fcvt_vmnemonic Rd_VPR128.2D, Rn_VPR128.2D
+is b_31=0 & b_30=1 & b_2328=0b011100 & b_22=1 & b_1021=0b100001110010 & fcvt_vmnemonic & Rd_VPR128.2D & Rn_VPR128.2D & Zd
+{
+ # simd unary Rd_VPR128.2D = trunc(Rn_VPR128.2D) on lane size 8
+ Rd_VPR128.2D[0,64] = trunc(Rn_VPR128.2D[0,64]);
+ Rd_VPR128.2D[64,64] = trunc(Rn_VPR128.2D[64,64]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.71 FCVTAS (scalar) page C7-2177 line 127075 MATCH x1e240000/mask=x7f3ffc00
+# C7.2.73 FCVTAU (scalar) page C7-2182 line 127396 MATCH x1e250000/mask=x7f3ffc00
+# CONSTRUCT x1ee40000/mask=xfffefc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =trunc
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
+# AUNIT --inst x1ee40000/mask=xfffefc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision to 32-bit variant when sf == 0 && type == 11
+
+:^fcvt_smnemonic Rd_GPR32, Rn_FPR16
+is b_31=0 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1720=0b0010 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR32 & Rn_FPR16 & Rd_GPR64
+{
+ Rd_GPR32 = trunc(Rn_FPR16);
+ zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
+}
+
+# C7.2.71 FCVTAS (scalar) page C7-2177 line 127075 MATCH x1e240000/mask=x7f3ffc00
+# C7.2.73 FCVTAU (scalar) page C7-2182 line 127396 MATCH x1e250000/mask=x7f3ffc00
+# CONSTRUCT x9ee40000/mask=xfffefc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =trunc
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
+# AUNIT --inst x9ee40000/mask=xfffefc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision to 64-bit variant when sf == 1 && type == 11
+
+:^fcvt_smnemonic Rd_GPR64, Rn_FPR16
+is b_31=1 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1720=0b0010 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR64 & Rn_FPR16
+{
+ Rd_GPR64 = trunc(Rn_FPR16);
+}
+
+# C7.2.71 FCVTAS (scalar) page C7-2177 line 127075 MATCH x1e240000/mask=x7f3ffc00
+# C7.2.73 FCVTAU (scalar) page C7-2182 line 127396 MATCH x1e250000/mask=x7f3ffc00
+# CONSTRUCT x1e240000/mask=xfffefc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =trunc
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
+# AUNIT --inst x1e240000/mask=xfffefc00 --rand sfp --status fail --comment "nofpround"
+# Single-precision to 32-bit variant when sf == 0 && type == 00
+
+:^fcvt_smnemonic Rd_GPR32, Rn_FPR32
+is b_31=0 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1720=0b0010 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR32 & Rn_FPR32 & Rd_GPR64
+{
+ Rd_GPR32 = trunc(Rn_FPR32);
+ zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
+}
+
+# C7.2.71 FCVTAS (scalar) page C7-2177 line 127075 MATCH x1e240000/mask=x7f3ffc00
+# C7.2.73 FCVTAU (scalar) page C7-2182 line 127396 MATCH x1e250000/mask=x7f3ffc00
+# CONSTRUCT x9e240000/mask=xfffefc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =trunc
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
+# AUNIT --inst x9e240000/mask=xfffefc00 --rand sfp --status fail --comment "nofpround"
+# Single-precision to 64-bit variant when sf == 1 && type == 00
+
+:^fcvt_smnemonic Rd_GPR64, Rn_FPR32
+is b_31=1 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1720=0b0010 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR64 & Rn_FPR32
+{
+ Rd_GPR64 = trunc(Rn_FPR32);
+}
+
+# C7.2.71 FCVTAS (scalar) page C7-2177 line 127075 MATCH x1e240000/mask=x7f3ffc00
+# C7.2.73 FCVTAU (scalar) page C7-2182 line 127396 MATCH x1e250000/mask=x7f3ffc00
+# CONSTRUCT x1e640000/mask=xfffefc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =trunc
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
+# AUNIT --inst x1e640000/mask=xfffefc00 --rand dfp --status fail --comment "nofpround"
+# Double-precision to 32-bit variant when sf == 0 && type == 01
+
+:^fcvt_smnemonic Rd_GPR32, Rn_FPR64
+is b_31=0 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1720=0b0010 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR32 & Rn_FPR64 & Rd_GPR64
+{
+ Rd_GPR32 = trunc(Rn_FPR64);
+ zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
+}
+
+# C7.2.71 FCVTAS (scalar) page C7-2177 line 127075 MATCH x1e240000/mask=x7f3ffc00
+# C7.2.73 FCVTAU (scalar) page C7-2182 line 127396 MATCH x1e250000/mask=x7f3ffc00
+# CONSTRUCT x9e640000/mask=xfffefc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =trunc
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
+# AUNIT --inst x9e640000/mask=xfffefc00 --rand dfp --status fail --comment "nofpround"
+# Double-precision to 64-bit variant sf == 1 && type == 01
+
+:^fcvt_smnemonic Rd_GPR64, Rn_FPR64
+is b_31=1 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1720=0b0010 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR64 & Rn_FPR64
+{
+ Rd_GPR64 = trunc(Rn_FPR64);
+}
+
+# C7.2.74 FCVTL, FCVTL2 page C7-2184 line 127524 MATCH x0e217800/mask=xbfbffc00
+# CONSTRUCT x0e617800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =var =$float2float@4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvtl/1@4
+# AUNIT --inst x0e617800/mask=xfffffc00 --rand dfp --status fail --comment "ext nofpround"
+
+:fcvtl Rd_VPR128.2D, Rn_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x17 & b_1011=2 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR64.2S;
+ # simd resize Rd_VPR128.2D = float2float(TMPD1) (lane size 4 to 8)
+ Rd_VPR128.2D[0,64] = float2float(TMPD1[0,32]);
+ Rd_VPR128.2D[64,64] = float2float(TMPD1[32,32]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.74 FCVTL, FCVTL2 page C7-2184 line 127524 MATCH x0e217800/mask=xbfbffc00
+# CONSTRUCT x4e617800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 =$float2float@4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvtl2/1@8
+# AUNIT --inst x4e617800/mask=xfffffc00 --rand dfp --status fail --comment "ext nofpround"
+
+:fcvtl2 Rd_VPR128.2D, Rn_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x17 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize Rd_VPR128.2D = float2float(TMPD1) (lane size 4 to 8)
+ Rd_VPR128.2D[0,64] = float2float(TMPD1[0,32]);
+ Rd_VPR128.2D[64,64] = float2float(TMPD1[32,32]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.74 FCVTL, FCVTL2 page C7-2184 line 127524 MATCH x0e217800/mask=xbfbffc00
+# CONSTRUCT x0e217800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =var =$float2float@2
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvtl/1@4
+# AUNIT --inst x0e217800/mask=xfffffc00 --rand sfp --status fail --comment "ext nofpround"
+
+:fcvtl Rd_VPR128.4S, Rn_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x17 & b_1011=2 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR64.4H;
+ # simd resize Rd_VPR128.4S = float2float(TMPD1) (lane size 2 to 4)
+ Rd_VPR128.4S[0,32] = float2float(TMPD1[0,16]);
+ Rd_VPR128.4S[32,32] = float2float(TMPD1[16,16]);
+ Rd_VPR128.4S[64,32] = float2float(TMPD1[32,16]);
+ Rd_VPR128.4S[96,32] = float2float(TMPD1[48,16]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.74 FCVTL, FCVTL2 page C7-2184 line 127524 MATCH x0e217800/mask=xbfbffc00
+# CONSTRUCT x4e217800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 =$float2float@2
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvtl2/1@2
+# AUNIT --inst x4e217800/mask=xfffffc00 --rand sfp --status fail --comment "ext nofpround"
+
+:fcvtl2 Rd_VPR128.4S, Rn_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x17 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize Rd_VPR128.4S = float2float(TMPD1) (lane size 2 to 4)
+ Rd_VPR128.4S[0,32] = float2float(TMPD1[0,16]);
+ Rd_VPR128.4S[32,32] = float2float(TMPD1[16,16]);
+ Rd_VPR128.4S[64,32] = float2float(TMPD1[32,16]);
+ Rd_VPR128.4S[96,32] = float2float(TMPD1[48,16]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.75 FCVTMS (vector) page C7-2186 line 127614 MATCH x5e79b800/mask=xfffffc00
+# C7.2.77 FCVTMU (vector) page C7-2191 line 127938 MATCH x7e79b800/mask=xfffffc00
+# C7.2.80 FCVTNS (vector) page C7-2198 line 128355 MATCH x5e79a800/mask=xfffffc00
+# C7.2.82 FCVTNU (vector) page C7-2203 line 128679 MATCH x7e79a800/mask=xfffffc00
+# C7.2.84 FCVTPS (vector) page C7-2208 line 129003 MATCH x5ef9a800/mask=xfffffc00
+# C7.2.86 FCVTPU (vector) page C7-2213 line 129327 MATCH x7ef9a800/mask=xfffffc00
+# C7.2.90 FCVTZS (vector, integer) page C7-2224 line 129963 MATCH x5ef9b800/mask=xfffffc00
+# C7.2.94 FCVTZU (vector, integer) page C7-2234 line 130576 MATCH x7ef9b800/mask=xfffffc00
+# CONSTRUCT x5e79a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =trunc
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
+# AUNIT --inst x5e79a800/mask=xdf7fec00 --rand hfp --status noqemu --comment "nofpround"
+# Scalar half precision
+
+:^fcvt_vmnemonic Rd_FPR16, Rn_FPR16
+is b_3031=0b01 & b_2428=0b11110 & b_1322=0b1111001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_FPR16 & Rn_FPR16 & Zd
+{
+ Rd_FPR16 = trunc(Rn_FPR16);
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.75 FCVTMS (vector) page C7-2186 line 127614 MATCH x5e21b800/mask=xffbffc00
+# C7.2.77 FCVTMU (vector) page C7-2191 line 127938 MATCH x7e21b800/mask=xffbffc00
+# C7.2.80 FCVTNS (vector) page C7-2198 line 128355 MATCH x5e21a800/mask=xffbffc00
+# C7.2.82 FCVTNU (vector) page C7-2203 line 128679 MATCH x7e21a800/mask=xffbffc00
+# C7.2.84 FCVTPS (vector) page C7-2208 line 129003 MATCH x5ea1a800/mask=xffbffc00
+# C7.2.86 FCVTPU (vector) page C7-2213 line 129327 MATCH x7ea1a800/mask=xffbffc00
+# C7.2.90 FCVTZS (vector, integer) page C7-2224 line 129963 MATCH x5ea1b800/mask=xffbffc00
+# C7.2.94 FCVTZU (vector, integer) page C7-2234 line 130576 MATCH x7ea1b800/mask=xffbffc00
+# CONSTRUCT x5e21a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =trunc
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
+# AUNIT --inst x5e21a800/mask=xdf7fec00 --rand sfp --status fail --comment "nofpround"
+# Scalar single-precision and double-precision variant sz=0
+
+:^fcvt_vmnemonic Rd_FPR32, Rn_FPR32
+is b_3031=0b01 & b_2428=0b11110 & b_22=0 & b_1321=0b100001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_FPR32 & Rn_FPR32 & Zd
+{
+ Rd_FPR32 = trunc(Rn_FPR32);
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.75 FCVTMS (vector) page C7-2186 line 127614 MATCH x5e21b800/mask=xffbffc00
+# C7.2.77 FCVTMU (vector) page C7-2191 line 127938 MATCH x7e21b800/mask=xffbffc00
+# C7.2.80 FCVTNS (vector) page C7-2198 line 128355 MATCH x5e21a800/mask=xffbffc00
+# C7.2.82 FCVTNU (vector) page C7-2203 line 128679 MATCH x7e21a800/mask=xffbffc00
+# C7.2.84 FCVTPS (vector) page C7-2208 line 129003 MATCH x5ea1a800/mask=xffbffc00
+# C7.2.86 FCVTPU (vector) page C7-2213 line 129327 MATCH x7ea1a800/mask=xffbffc00
+# C7.2.90 FCVTZS (vector, integer) page C7-2224 line 129963 MATCH x5ea1b800/mask=xffbffc00
+# C7.2.94 FCVTZU (vector, integer) page C7-2234 line 130576 MATCH x7ea1b800/mask=xffbffc00
+# CONSTRUCT x5e61a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =trunc
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
+# AUNIT --inst x5e61a800/mask=xdf7fec00 --rand dfp --status fail --comment "nofpround"
+# Scalar single-precision and double-precision variant sz=1
+
+:^fcvt_vmnemonic Rd_FPR64, Rn_FPR64
+is b_3031=0b01 & b_2428=0b11110 & b_22=1 & b_1321=0b100001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_FPR64 & Rn_FPR64 & Zd
+{
+ Rd_FPR64 = trunc(Rn_FPR64);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.75 FCVTMS (vector) page C7-2186 line 127614 MATCH x0e79b800/mask=xbffffc00
+# C7.2.77 FCVTMU (vector) page C7-2191 line 127938 MATCH x2e79b800/mask=xbffffc00
+# C7.2.80 FCVTNS (vector) page C7-2198 line 128355 MATCH x0e79a800/mask=xbffffc00
+# C7.2.82 FCVTNU (vector) page C7-2203 line 128679 MATCH x2e79a800/mask=xbffffc00
+# C7.2.84 FCVTPS (vector) page C7-2208 line 129003 MATCH x0ef9a800/mask=xbffffc00
+# C7.2.86 FCVTPU (vector) page C7-2213 line 129327 MATCH x2ef9a800/mask=xbffffc00
+# C7.2.90 FCVTZS (vector, integer) page C7-2224 line 129963 MATCH x0ef9b800/mask=xbffffc00
+# C7.2.94 FCVTZU (vector, integer) page C7-2234 line 130576 MATCH x2ef9b800/mask=xbffffc00
+# CONSTRUCT x0e79a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$trunc@2
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@2
+# AUNIT --inst x0e79a800/mask=xdf7fec00 --rand hfp --status noqemu --comment "nofpround"
+# Vector half precision variant Q=0
+
+:^fcvt_vmnemonic Rd_VPR64.4H, Rn_VPR64.4H
+is b_31=0 & b_30=0 & b_2428=0b01110 & b_1322=0b1111001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_VPR64.4H & Rn_VPR64.4H & Zd
+{
+ # simd unary Rd_VPR64.4H = trunc(Rn_VPR64.4H) on lane size 2
+ Rd_VPR64.4H[0,16] = trunc(Rn_VPR64.4H[0,16]);
+ Rd_VPR64.4H[16,16] = trunc(Rn_VPR64.4H[16,16]);
+ Rd_VPR64.4H[32,16] = trunc(Rn_VPR64.4H[32,16]);
+ Rd_VPR64.4H[48,16] = trunc(Rn_VPR64.4H[48,16]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.75 FCVTMS (vector) page C7-2186 line 127614 MATCH x0e79b800/mask=xbffffc00
+# C7.2.77 FCVTMU (vector) page C7-2191 line 127938 MATCH x2e79b800/mask=xbffffc00
+# C7.2.80 FCVTNS (vector) page C7-2198 line 128355 MATCH x0e79a800/mask=xbffffc00
+# C7.2.82 FCVTNU (vector) page C7-2203 line 128679 MATCH x2e79a800/mask=xbffffc00
+# C7.2.84 FCVTPS (vector) page C7-2208 line 129003 MATCH x0ef9a800/mask=xbffffc00
+# C7.2.86 FCVTPU (vector) page C7-2213 line 129327 MATCH x2ef9a800/mask=xbffffc00
+# C7.2.90 FCVTZS (vector, integer) page C7-2224 line 129963 MATCH x0ef9b800/mask=xbffffc00
+# C7.2.94 FCVTZU (vector, integer) page C7-2234 line 130576 MATCH x2ef9b800/mask=xbffffc00
+# CONSTRUCT x4e79a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$trunc@2
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@2
+# AUNIT --inst x4e79a800/mask=xdf7fec00 --rand hfp --status noqemu --comment "nofpround"
+# Vector half precision variant Q=1
+
+:^fcvt_vmnemonic Rd_VPR128.8H, Rn_VPR128.8H
+is b_31=0 & b_30=1 & b_2428=0b01110 & b_1322=0b1111001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_VPR128.8H & Rn_VPR128.8H & Zd
+{
+ # simd unary Rd_VPR128.8H = trunc(Rn_VPR128.8H) on lane size 2
+ Rd_VPR128.8H[0,16] = trunc(Rn_VPR128.8H[0,16]);
+ Rd_VPR128.8H[16,16] = trunc(Rn_VPR128.8H[16,16]);
+ Rd_VPR128.8H[32,16] = trunc(Rn_VPR128.8H[32,16]);
+ Rd_VPR128.8H[48,16] = trunc(Rn_VPR128.8H[48,16]);
+ Rd_VPR128.8H[64,16] = trunc(Rn_VPR128.8H[64,16]);
+ Rd_VPR128.8H[80,16] = trunc(Rn_VPR128.8H[80,16]);
+ Rd_VPR128.8H[96,16] = trunc(Rn_VPR128.8H[96,16]);
+ Rd_VPR128.8H[112,16] = trunc(Rn_VPR128.8H[112,16]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.75 FCVTMS (vector) page C7-2186 line 127614 MATCH x0e21b800/mask=xbfbffc00
+# C7.2.77 FCVTMU (vector) page C7-2191 line 127938 MATCH x2e21b800/mask=xbfbffc00
+# C7.2.80 FCVTNS (vector) page C7-2198 line 128355 MATCH x0e21a800/mask=xbfbffc00
+# C7.2.82 FCVTNU (vector) page C7-2203 line 128679 MATCH x2e21a800/mask=xbfbffc00
+# C7.2.84 FCVTPS (vector) page C7-2208 line 129003 MATCH x0ea1a800/mask=xbfbffc00
+# C7.2.86 FCVTPU (vector) page C7-2213 line 129327 MATCH x2ea1a800/mask=xbfbffc00
+# C7.2.90 FCVTZS (vector, integer) page C7-2224 line 129963 MATCH x0ea1b800/mask=xbfbffc00
+# C7.2.94 FCVTZU (vector, integer) page C7-2234 line 130576 MATCH x2ea1b800/mask=xbfbffc00
+# CONSTRUCT x0e21a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$trunc@4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@4
+# AUNIT --inst x0e21a800/mask=xdf7fec00 --rand sfp --status fail --comment "nofpround"
+# Vector single-precision and double-precision variant SIMD 2S when sz = 0 , Q = 0
+
+:^fcvt_vmnemonic Rd_VPR64.2S, Rn_VPR64.2S
+is b_31=0 & b_30=0 & b_2428=0b01110 & b_22=0 & b_1321=0b100001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_VPR64.2S & Rn_VPR64.2S & Zd
+{
+ # simd unary Rd_VPR64.2S = trunc(Rn_VPR64.2S) on lane size 4
+ Rd_VPR64.2S[0,32] = trunc(Rn_VPR64.2S[0,32]);
+ Rd_VPR64.2S[32,32] = trunc(Rn_VPR64.2S[32,32]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.75 FCVTMS (vector) page C7-2186 line 127614 MATCH x0e21b800/mask=xbfbffc00
+# C7.2.77 FCVTMU (vector) page C7-2191 line 127938 MATCH x2e21b800/mask=xbfbffc00
+# C7.2.80 FCVTNS (vector) page C7-2198 line 128355 MATCH x0e21a800/mask=xbfbffc00
+# C7.2.82 FCVTNU (vector) page C7-2203 line 128679 MATCH x2e21a800/mask=xbfbffc00
+# C7.2.84 FCVTPS (vector) page C7-2208 line 129003 MATCH x0ea1a800/mask=xbfbffc00
+# C7.2.86 FCVTPU (vector) page C7-2213 line 129327 MATCH x2ea1a800/mask=xbfbffc00
+# C7.2.90 FCVTZS (vector, integer) page C7-2224 line 129963 MATCH x0ea1b800/mask=xbfbffc00
+# C7.2.94 FCVTZU (vector, integer) page C7-2234 line 130576 MATCH x2ea1b800/mask=xbfbffc00
+# CONSTRUCT x4e21a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$trunc@4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@4
+# AUNIT --inst x4e21a800/mask=xdf7fec00 --rand sfp --status fail --comment "nofpround"
+# Vector single-precision and double-precision variant SIMD 4S when sz = 0 , Q = 1
+
+:^fcvt_vmnemonic Rd_VPR128.4S, Rn_VPR128.4S
+is b_31=0 & b_30=1 & b_2428=0b01110 & b_22=0 & b_1321=0b100001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_VPR128.4S & Rn_VPR128.4S & Zd
+{
+ # simd unary Rd_VPR128.4S = trunc(Rn_VPR128.4S) on lane size 4
+ Rd_VPR128.4S[0,32] = trunc(Rn_VPR128.4S[0,32]);
+ Rd_VPR128.4S[32,32] = trunc(Rn_VPR128.4S[32,32]);
+ Rd_VPR128.4S[64,32] = trunc(Rn_VPR128.4S[64,32]);
+ Rd_VPR128.4S[96,32] = trunc(Rn_VPR128.4S[96,32]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.75 FCVTMS (vector) page C7-2186 line 127614 MATCH x0e21b800/mask=xbfbffc00
+# C7.2.77 FCVTMU (vector) page C7-2191 line 127938 MATCH x2e21b800/mask=xbfbffc00
+# C7.2.80 FCVTNS (vector) page C7-2198 line 128355 MATCH x0e21a800/mask=xbfbffc00
+# C7.2.82 FCVTNU (vector) page C7-2203 line 128679 MATCH x2e21a800/mask=xbfbffc00
+# C7.2.84 FCVTPS (vector) page C7-2208 line 129003 MATCH x0ea1a800/mask=xbfbffc00
+# C7.2.86 FCVTPU (vector) page C7-2213 line 129327 MATCH x2ea1a800/mask=xbfbffc00
+# C7.2.90 FCVTZS (vector, integer) page C7-2224 line 129963 MATCH x0ea1b800/mask=xbfbffc00
+# C7.2.94 FCVTZU (vector, integer) page C7-2234 line 130576 MATCH x2ea1b800/mask=xbfbffc00
+# CONSTRUCT x4e61a800/mask=xdf7fec00 MATCHED 8 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$trunc@8
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1@8
+# AUNIT --inst x4e61a800/mask=xdf7fec00 --rand dfp --status fail --comment "nofpround"
+# Vector single-precision and double-precision variant SIMD 2D when sz = 1 , Q = 1
+
+:^fcvt_vmnemonic Rd_VPR128.2D, Rn_VPR128.2D
+is b_31=0 & b_30=1 & b_2428=0b01110 & b_22=1 & b_1321=0b100001101 & b_1011=0b10 & fcvt_vmnemonic & Rd_VPR128.2D & Rn_VPR128.2D & Zd
+{
+ # simd unary Rd_VPR128.2D = trunc(Rn_VPR128.2D) on lane size 8
+ Rd_VPR128.2D[0,64] = trunc(Rn_VPR128.2D[0,64]);
+ Rd_VPR128.2D[64,64] = trunc(Rn_VPR128.2D[64,64]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.76 FCVTMS (scalar) page C7-2189 line 127807 MATCH x1e300000/mask=x7f3ffc00
+# C7.2.78 FCVTMU (scalar) page C7-2194 line 128131 MATCH x1e310000/mask=x7f3ffc00
+# C7.2.81 FCVTNS (scalar) page C7-2201 line 128548 MATCH x1e200000/mask=x7f3ffc00
+# C7.2.83 FCVTNU (scalar) page C7-2206 line 128872 MATCH x1e210000/mask=x7f3ffc00
+# C7.2.85 FCVTPS (scalar) page C7-2211 line 129196 MATCH x1e280000/mask=x7f3ffc00
+# C7.2.87 FCVTPU (scalar) page C7-2216 line 129520 MATCH x1e290000/mask=x7f3ffc00
+# C7.2.92 FCVTZS (scalar, integer) page C7-2229 line 130291 MATCH x1e380000/mask=x7f3ffc00
+# C7.2.96 FCVTZU (scalar, integer) page C7-2239 line 130904 MATCH x1e390000/mask=x7f3ffc00
+# CONSTRUCT x1ee00000/mask=xffe6fc00 MATCHED 8 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =trunc
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
+# AUNIT --inst x1ee00000/mask=xffe6fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision to 32-bit variant when sf == 0 && type == 11
+
+:^fcvt_smnemonic Rd_GPR32, Rn_FPR16
+is b_31=0 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1718=0b00 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR32 & Rn_FPR16 & Rd_GPR64
+{
+ Rd_GPR32 = trunc(Rn_FPR16);
+ zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
+}
+
+# C7.2.76 FCVTMS (scalar) page C7-2189 line 127807 MATCH x1e300000/mask=x7f3ffc00
+# C7.2.78 FCVTMU (scalar) page C7-2194 line 128131 MATCH x1e310000/mask=x7f3ffc00
+# C7.2.81 FCVTNS (scalar) page C7-2201 line 128548 MATCH x1e200000/mask=x7f3ffc00
+# C7.2.83 FCVTNU (scalar) page C7-2206 line 128872 MATCH x1e210000/mask=x7f3ffc00
+# C7.2.85 FCVTPS (scalar) page C7-2211 line 129196 MATCH x1e280000/mask=x7f3ffc00
+# C7.2.87 FCVTPU (scalar) page C7-2216 line 129520 MATCH x1e290000/mask=x7f3ffc00
+# C7.2.92 FCVTZS (scalar, integer) page C7-2229 line 130291 MATCH x1e380000/mask=x7f3ffc00
+# C7.2.96 FCVTZU (scalar, integer) page C7-2239 line 130904 MATCH x1e390000/mask=x7f3ffc00
+# CONSTRUCT x9ee00000/mask=xffe6fc00 MATCHED 8 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =trunc
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
+# AUNIT --inst x9ee00000/mask=xffe6fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision to 64-bit variant when sf == 1 && type == 11
+
+:^fcvt_smnemonic Rd_GPR64, Rn_FPR16
+is b_31=1 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1718=0b00 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR64 & Rn_FPR16
+{
+ Rd_GPR64 = trunc(Rn_FPR16);
+}
+
+# C7.2.76 FCVTMS (scalar) page C7-2189 line 127807 MATCH x1e300000/mask=x7f3ffc00
+# C7.2.78 FCVTMU (scalar) page C7-2194 line 128131 MATCH x1e310000/mask=x7f3ffc00
+# C7.2.81 FCVTNS (scalar) page C7-2201 line 128548 MATCH x1e200000/mask=x7f3ffc00
+# C7.2.83 FCVTNU (scalar) page C7-2206 line 128872 MATCH x1e210000/mask=x7f3ffc00
+# C7.2.85 FCVTPS (scalar) page C7-2211 line 129196 MATCH x1e280000/mask=x7f3ffc00
+# C7.2.87 FCVTPU (scalar) page C7-2216 line 129520 MATCH x1e290000/mask=x7f3ffc00
+# C7.2.92 FCVTZS (scalar, integer) page C7-2229 line 130291 MATCH x1e380000/mask=x7f3ffc00
+# C7.2.96 FCVTZU (scalar, integer) page C7-2239 line 130904 MATCH x1e390000/mask=x7f3ffc00
+# CONSTRUCT x1e200000/mask=xffe6fc00 MATCHED 8 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =trunc
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
+# AUNIT --inst x1e200000/mask=xffe6fc00 --rand sfp --status fail --comment "nofpround"
+# Single-precision to 32-bit variant when sf == 0 && type == 00
+
+:^fcvt_smnemonic Rd_GPR32, Rn_FPR32
+is b_31=0 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1718=0b00 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR32 & Rn_FPR32 & Rd_GPR64
+{
+ Rd_GPR32 = trunc(Rn_FPR32);
+ zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
+}
+
+# C7.2.76 FCVTMS (scalar) page C7-2189 line 127807 MATCH x1e300000/mask=x7f3ffc00
+# C7.2.78 FCVTMU (scalar) page C7-2194 line 128131 MATCH x1e310000/mask=x7f3ffc00
+# C7.2.81 FCVTNS (scalar) page C7-2201 line 128548 MATCH x1e200000/mask=x7f3ffc00
+# C7.2.83 FCVTNU (scalar) page C7-2206 line 128872 MATCH x1e210000/mask=x7f3ffc00
+# C7.2.85 FCVTPS (scalar) page C7-2211 line 129196 MATCH x1e280000/mask=x7f3ffc00
+# C7.2.87 FCVTPU (scalar) page C7-2216 line 129520 MATCH x1e290000/mask=x7f3ffc00
+# C7.2.92 FCVTZS (scalar, integer) page C7-2229 line 130291 MATCH x1e380000/mask=x7f3ffc00
+# C7.2.96 FCVTZU (scalar, integer) page C7-2239 line 130904 MATCH x1e390000/mask=x7f3ffc00
+# CONSTRUCT x9e200000/mask=xffe6fc00 MATCHED 8 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =trunc
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
+# AUNIT --inst x9e200000/mask=xffe6fc00 --rand sfp --status fail --comment "nofpround"
+# Single-precision to 64-bit variant when sf == 1 && type == 00
+
+:^fcvt_smnemonic Rd_GPR64, Rn_FPR32
+is b_31=1 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1718=0b00 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR64 & Rn_FPR32
+{
+ Rd_GPR64 = trunc(Rn_FPR32);
+}
+
+# C7.2.76 FCVTMS (scalar) page C7-2189 line 127807 MATCH x1e300000/mask=x7f3ffc00
+# C7.2.78 FCVTMU (scalar) page C7-2194 line 128131 MATCH x1e310000/mask=x7f3ffc00
+# C7.2.81 FCVTNS (scalar) page C7-2201 line 128548 MATCH x1e200000/mask=x7f3ffc00
+# C7.2.83 FCVTNU (scalar) page C7-2206 line 128872 MATCH x1e210000/mask=x7f3ffc00
+# C7.2.85 FCVTPS (scalar) page C7-2211 line 129196 MATCH x1e280000/mask=x7f3ffc00
+# C7.2.87 FCVTPU (scalar) page C7-2216 line 129520 MATCH x1e290000/mask=x7f3ffc00
+# C7.2.92 FCVTZS (scalar, integer) page C7-2229 line 130291 MATCH x1e380000/mask=x7f3ffc00
+# C7.2.96 FCVTZU (scalar, integer) page C7-2239 line 130904 MATCH x1e390000/mask=x7f3ffc00
+# CONSTRUCT x1e600000/mask=xffe6fc00 MATCHED 8 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =trunc
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
+# AUNIT --inst x1e600000/mask=xffe6fc00 --rand dfp --status fail --comment "nofpround"
+# Double-precision to 32-bit variant when sf == 0 && type == 01
+
+:^fcvt_smnemonic Rd_GPR32, Rn_FPR64
+is b_31=0 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1718=0b00 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR32 & Rn_FPR64 & Rd_GPR64
+{
+ Rd_GPR32 = trunc(Rn_FPR64);
+ zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
+}
+
+# C7.2.76 FCVTMS (scalar) page C7-2189 line 127807 MATCH x1e300000/mask=x7f3ffc00
+# C7.2.78 FCVTMU (scalar) page C7-2194 line 128131 MATCH x1e310000/mask=x7f3ffc00
+# C7.2.81 FCVTNS (scalar) page C7-2201 line 128548 MATCH x1e200000/mask=x7f3ffc00
+# C7.2.83 FCVTNU (scalar) page C7-2206 line 128872 MATCH x1e210000/mask=x7f3ffc00
+# C7.2.85 FCVTPS (scalar) page C7-2211 line 129196 MATCH x1e280000/mask=x7f3ffc00
+# C7.2.87 FCVTPU (scalar) page C7-2216 line 129520 MATCH x1e290000/mask=x7f3ffc00
+# C7.2.92 FCVTZS (scalar, integer) page C7-2229 line 130291 MATCH x1e380000/mask=x7f3ffc00
+# C7.2.96 FCVTZU (scalar, integer) page C7-2239 line 130904 MATCH x1e390000/mask=x7f3ffc00
+# CONSTRUCT x9e600000/mask=xffe6fc00 MATCHED 8 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =trunc
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fcvt_amnpz_su/1
+# AUNIT --inst x9e600000/mask=xffe6fc00 --rand dfp --status fail --comment "nofpround"
+# Double-precision to 64-bit variant sf == 1 && type == 01
+
+:^fcvt_smnemonic Rd_GPR64, Rn_FPR64
+is b_31=1 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1718=0b00 & b_1015=0b000000 & fcvt_smnemonic & Rd_GPR64 & Rn_FPR64
+{
+ Rd_GPR64 = trunc(Rn_FPR64);
+}
+
+# C7.2.79 FCVTN, FCVTN2 page C7-2196 line 128262 MATCH x0e216800/mask=xbfbffc00
+# CONSTRUCT x0e616800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =var =$float2float@8:8
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtn/2@8
+# AUNIT --inst x0e616800/mask=xfffffc00 --rand sfp --status fail --comment "ext nofpround"
+
+:fcvtn Rd_VPR64.2S, Rn_VPR128.2D
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x16 & b_1011=2 & Rn_VPR128.2D & Rd_VPR64.2S & Rd_VPR128 & Zd
+{
+ TMPQ1 = Rn_VPR128.2D;
+ # simd resize Rd_VPR64.2S = float2float(TMPQ1) (lane size 8 to 4)
+ Rd_VPR64.2S[0,32] = float2float(TMPQ1[0,64]);
+ Rd_VPR64.2S[32,32] = float2float(TMPQ1[64,64]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.79 FCVTN, FCVTN2 page C7-2196 line 128262 MATCH x0e216800/mask=xbfbffc00
+# CONSTRUCT x4e616800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $float2float@8:8 1:1 &=$copy
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtn2/2@8
+# AUNIT --inst x4e616800/mask=xfffffc00 --rand sfp --status pass --comment "ext nofpround"
+
+:fcvtn2 Rd_VPR128.4S, Rn_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x16 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPD1 = float2float(Rn_VPR128.2D) (lane size 8 to 4)
+ TMPD1[0,32] = float2float(Rn_VPR128.2D[0,64]);
+ TMPD1[32,32] = float2float(Rn_VPR128.2D[64,64]);
+ # simd copy Rd_VPR128.4S element 1:1 = TMPD1 (lane size 8)
+ Rd_VPR128.4S[64,64] = TMPD1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.79 FCVTN, FCVTN2 page C7-2196 line 128262 MATCH x0e216800/mask=xbfbffc00
+# CONSTRUCT x0e216800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =var =$float2float@4:8
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtn/2@4
+# AUNIT --inst x0e216800/mask=xfffffc00 --rand hfp --status fail --comment "ext nofpround"
+
+:fcvtn Rd_VPR64.4H, Rn_VPR128.4S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x16 & b_1011=2 & Rn_VPR128.4S & Rd_VPR64.4H & Rd_VPR128 & Zd
+{
+ TMPQ1 = Rn_VPR128.4S;
+ # simd resize Rd_VPR64.4H = float2float(TMPQ1) (lane size 4 to 2)
+ Rd_VPR64.4H[0,16] = float2float(TMPQ1[0,32]);
+ Rd_VPR64.4H[16,16] = float2float(TMPQ1[32,32]);
+ Rd_VPR64.4H[32,16] = float2float(TMPQ1[64,32]);
+ Rd_VPR64.4H[48,16] = float2float(TMPQ1[96,32]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.79 FCVTN, FCVTN2 page C7-2196 line 128262 MATCH x0e216800/mask=xbfbffc00
+# CONSTRUCT x4e216800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $float2float@4:8 1:1 &=$copy
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtn2/2@4
+# AUNIT --inst x4e216800/mask=xfffffc00 --rand hfp --status fail --comment "ext nofpround"
+
+:fcvtn2 Rd_VPR128.8H, Rn_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x16 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
+{
+ # simd resize TMPD1 = float2float(Rn_VPR128.4S) (lane size 4 to 2)
+ TMPD1[0,16] = float2float(Rn_VPR128.4S[0,32]);
+ TMPD1[16,16] = float2float(Rn_VPR128.4S[32,32]);
+ TMPD1[32,16] = float2float(Rn_VPR128.4S[64,32]);
+ TMPD1[48,16] = float2float(Rn_VPR128.4S[96,32]);
+ # simd copy Rd_VPR128.8H element 1:1 = TMPD1 (lane size 8)
+ Rd_VPR128.8H[64,64] = TMPD1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.88 FCVTXN, FCVTXN2 page C7-2218 line 129651 MATCH x7e216800/mask=xffbffc00
+# CONSTRUCT x7e616800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =float2float
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtxn/2
+# AUNIT --inst x7e616800/mask=xfffffc00 --rand sfp --status fail --comment "nofpround"
+
+:fcvtxn Rd_FPR32, Rn_FPR64
+is b_2331=0b011111100 & b_22=1 & b_1021=0b100001011010 & Rd_FPR32 & Rn_FPR64 & Zd
+{
+ Rd_FPR32 = float2float(Rn_FPR64);
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.88 FCVTXN, FCVTXN2 page C7-2218 line 129651 MATCH x2e216800/mask=xbfbffc00
+# CONSTRUCT x2e616800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =var =$float2float@8:8
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtxn/2@8
+# AUNIT --inst x2e616800/mask=xfffffc00 --rand sfp --status fail --comment "ext nofpround"
+# Vector Variant
+
+:fcvtxn Rd_VPR64.2S, Rn_VPR128.2D
+is b_31=0 & b_30=0 & b_2329=0b1011100 & b_22=1 & b_1021=0b100001011010 & Rd_VPR64.2S & Rd_VPR128 & Rn_VPR128.2D & Zd
+{
+ TMPQ1 = Rn_VPR128.2D;
+ # simd resize Rd_VPR64.2S = float2float(TMPQ1) (lane size 8 to 4)
+ Rd_VPR64.2S[0,32] = float2float(TMPQ1[0,64]);
+ Rd_VPR64.2S[32,32] = float2float(TMPQ1[64,64]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.88 FCVTXN, FCVTXN2 page C7-2218 line 129651 MATCH x2e216800/mask=xbfbffc00
+# CONSTRUCT x6e616800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $float2float@8:8 1:1 &=$copy
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtxn2/2@8
+# AUNIT --inst x6e616800/mask=xfffffc00 --rand sfp --status fail --comment "ext nofpround"
+# Vector Variant
+
+:fcvtxn2 Rd_VPR128.4S, Rn_VPR128.2D
+is b_31=0 & b_30=1 & b_2329=0b1011100 & b_22=1 & b_1021=0b100001011010 & Rd_VPR128.4S & Rn_VPR128.2D & Rd_VPR128 & Zd
+{
+ # simd resize TMPD1 = float2float(Rn_VPR128.2D) (lane size 8 to 4)
+ TMPD1[0,32] = float2float(Rn_VPR128.2D[0,64]);
+ TMPD1[32,32] = float2float(Rn_VPR128.2D[64,64]);
+ # simd copy Rd_VPR128.4S element 1:1 = TMPD1 (lane size 8)
+ Rd_VPR128.4S[64,64] = TMPD1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x5f00fc00/mask=xff80fc00
+# CONSTRUCT x5f40fc00/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 zext:8 =NEON_fcvtzs/2
+# AUNIT --inst x5f40fc00/mask=xffc0fc00 --rand dfp --status nopcodeop --comment "nofpround"
+# Scalar variant when immh=1xxx
+
+:fcvtzs Rd_FPR64, Rn_FPR64, Imm_shr_imm64
+is b_2331=0b010111110 & b_22=1 & b_1015=0b111111 & Imm_shr_imm64 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ local tmp1:8 = zext(Imm_shr_imm64);
+ Rd_FPR64 = NEON_fcvtzs(Rn_FPR64, tmp1);
+}
+
+# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x5f00fc00/mask=xff80fc00
+# CONSTRUCT x5f20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_fcvtzs/2
+# AUNIT --inst x5f20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+# Scalar variant when immh=01xx
+
+:fcvtzs Rd_FPR32, Rn_FPR32, Imm_shr_imm32
+is b_2331=0b010111110 & b_2122=0b01 & b_1015=0b111111 & Imm_shr_imm32 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_fcvtzs(Rn_FPR32, Imm_shr_imm32:4);
+}
+
+# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x5f00fc00/mask=xff80fc00
+# CONSTRUCT x5f10fc00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzs/2
+# AUNIT --inst x5f10fc00/mask=xfff0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Scalar variant when immh=001x
+
+:fcvtzs Rd_FPR16, Rn_FPR16, Imm_shr_imm16
+is b_2331=0b010111110 & b_2022=0b001 & b_1015=0b111111 & Imm_shr_imm16 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_fcvtzs(Rn_FPR16, Imm_shr_imm16);
+}
+
+# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x0f00fc00/mask=xbf80fc00
+# CONSTRUCT x4f40fc00/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 zext:8 =NEON_fcvtzs/2@8
+# AUNIT --inst x4f40fc00/mask=xffc0fc00 --rand dfp --status nopcodeop --comment "nofpround"
+# Vector 2D variant when immh=1xxx Q=1 bb=b_22 cc=1 V=VPR128.2D imm=Imm_shr_imm64
+
+:fcvtzs Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
+is b_31=0 & b_30=1 & b_2329=0b0011110 & b_22=1 & b_1015=0b111111 & Rd_VPR128.2D & Rn_VPR128.2D & Imm_shr_imm64 & Zd
+{
+ local tmp1:8 = zext(Imm_shr_imm64);
+ Rd_VPR128.2D = NEON_fcvtzs(Rn_VPR128.2D, tmp1, 8:1);
+}
+
+# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x0f00fc00/mask=xbf80fc00
+# CONSTRUCT x0f20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_fcvtzs/2@4
+# AUNIT --inst x0f20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+# Vector 2S variant when immh=01xx Q=0 bb=b_2122 cc=0b01 V=VPR64.2S imm=Imm_shr_imm32
+
+:fcvtzs Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
+is b_31=0 & b_30=0 & b_2329=0b0011110 & b_2122=0b01 & b_1015=0b111111 & Rd_VPR64.2S & Rn_VPR64.2S & Imm_shr_imm32 & Zd
+{
+ Rd_VPR64.2S = NEON_fcvtzs(Rn_VPR64.2S, Imm_shr_imm32:4, 4:1);
+}
+
+# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x0f00fc00/mask=xbf80fc00
+# CONSTRUCT x4f20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_fcvtzs/2@4
+# AUNIT --inst x4f20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+# Vector 4S variant when immh=01xx Q=1 bb=b_2122 cc=0b01 V=VPR128.4S imm=Imm_shr_imm32
+
+:fcvtzs Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
+is b_31=0 & b_30=1 & b_2329=0b0011110 & b_2122=0b01 & b_1015=0b111111 & Rd_VPR128.4S & Rn_VPR128.4S & Imm_shr_imm32 & Zd
+{
+ Rd_VPR128.4S = NEON_fcvtzs(Rn_VPR128.4S, Imm_shr_imm32:4, 4:1);
+}
+
+# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x0f00fc00/mask=xbf80fc00
+# CONSTRUCT x0f10fc00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzs/2@2
+# AUNIT --inst x0f10fc00/mask=xfff0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Vector 4H variant when immh=001x Q=0 bb=b_2022 cc=0b001 V=VPR64.4H imm=Imm_shr_imm16
+
+:fcvtzs Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16
+is b_31=0 & b_30=0 & b_2329=0b0011110 & b_2022=0b001 & b_1015=0b111111 & Rd_VPR64.4H & Rn_VPR64.4H & Imm_shr_imm16 & Zd
+{
+ Rd_VPR64.4H = NEON_fcvtzs(Rn_VPR64.4H, Imm_shr_imm16, 2:1);
+}
+
+# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x0f00fc00/mask=xbf80fc00
+# CONSTRUCT x4f10fc00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzs/2@2
+# AUNIT --inst x4f10fc00/mask=xfff0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Vector 8H variant when immh=001x Q=1 bb=b_2022 cc=0b001 V=VPR128.8H imm=Imm_shr_imm16
+
+:fcvtzs Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16
+is b_31=0 & b_30=1 & b_2329=0b0011110 & b_2022=0b001 & b_1015=0b111111 & Rd_VPR128.8H & Rn_VPR128.8H & Imm_shr_imm16 & Zd
+{
+ Rd_VPR128.8H = NEON_fcvtzs(Rn_VPR128.8H, Imm_shr_imm16, 2:1);
+}
+
+# C7.2.91 FCVTZS (scalar, fixed-point) page C7-2227 line 130156 MATCH x1e180000/mask=x7f3f0000
+# CONSTRUCT x1ed88000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 FBits16 f* =trunc
+# SMACRO(pseudo) ARG1 ARG2 FBits16 =NEON_fcvtzs/2
+# AUNIT --inst x1ed88000/mask=xffff8000 --rand hfp --status noqemu --comment "nofpround"
+# if sf == '0' && scale<5> == '0' then UnallocatedEncoding();
+# Half-precision to 32-bit variant when sf == 0 && type == 11 G=GPR32 V=FPR16 size=2 fbits=FBits16
+
+:fcvtzs Rd_GPR32, Rn_FPR16, FBitsOp
+is b_31=0 & b_2430=0b0011110 & b_2223=0b11 & b_1621=0b011000 & b_15=1 & Rd_GPR32 & Rn_FPR16 & FBitsOp & FBits16 & Rd_GPR64
+{
+ local tmp1:2 = Rn_FPR16 f* FBits16;
+ Rd_GPR32 = trunc(tmp1);
+ zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
+}
+
+# C7.2.91 FCVTZS (scalar, fixed-point) page C7-2227 line 130156 MATCH x1e180000/mask=x7f3f0000
+# CONSTRUCT x9ed80000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 f* =trunc
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzs/2
+# AUNIT --inst x9ed80000/mask=xffff0000 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision to 64-bit variant when sf == 1 && type == 11 G=GPR64 V=FPR16 size=2 fbits=FBits16
+
+:fcvtzs Rd_GPR64, Rn_FPR16, FBitsOp
+is b_31=1 & b_2430=0b0011110 & b_2223=0b11 & b_1621=0b011000 & Rd_GPR64 & Rn_FPR16 & FBitsOp & FBits16
+{
+ local tmp1:2 = Rn_FPR16 f* FBitsOp;
+ Rd_GPR64 = trunc(tmp1);
+}
+
+# C7.2.91 FCVTZS (scalar, fixed-point) page C7-2227 line 130156 MATCH x1e180000/mask=x7f3f0000
+# CONSTRUCT x1e188000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 FBits32 f* =trunc
+# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_fcvtzs/2
+# AUNIT --inst x1e188000/mask=xffff8000 --rand sfp --status fail --comment "nofpround"
+# Single-precision to 32-bit variant when sf == 0 && type == 00 G=GPR32 V=FPR32 size=4 fbits=FBits32
+
+:fcvtzs Rd_GPR32, Rn_FPR32, FBitsOp
+is b_31=0 & b_2430=0b0011110 & b_2223=0b00 & b_1621=0b011000 & b_15=1 & Rd_GPR32 & Rn_FPR32 & FBitsOp & FBits32 & Rd_GPR64
+{
+ local tmp1:4 = Rn_FPR32 f* FBits32;
+ Rd_GPR32 = trunc(tmp1);
+ zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
+}
+
+# C7.2.91 FCVTZS (scalar, fixed-point) page C7-2227 line 130156 MATCH x1e180000/mask=x7f3f0000
+# CONSTRUCT x9e180000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 FBits32 f* =trunc
+# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_fcvtzs/2
+# AUNIT --inst x9e180000/mask=xffff0000 --rand sfp --status pass --comment "nofpround"
+# Single-precision to 64-bit variant when sf == 1 && type == 00 G=GPR64 V=FPR32 size=4 fbits=FBits32
+
+:fcvtzs Rd_GPR64, Rn_FPR32, FBitsOp
+is b_31=1 & b_2430=0b0011110 & b_2223=0b00 & b_1621=0b011000 & Rd_GPR64 & Rn_FPR32 & FBitsOp & FBits32
+{
+ local tmp1:4 = Rn_FPR32 f* FBits32;
+ Rd_GPR64 = trunc(tmp1);
+}
+
+# C7.2.91 FCVTZS (scalar, fixed-point) page C7-2227 line 130156 MATCH x1e180000/mask=x7f3f0000
+# CONSTRUCT x1e588000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 FBits64 f* =trunc
+# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_fcvtzs/2
+# AUNIT --inst x1e588000/mask=xffff8000 --rand dfp --status fail --comment "nofpround"
+# Double-precision to 32-bit variant when sf == 0 && type == 01 G=GPR32 V=FPR64 size=8 fbits=FBits64
+
+:fcvtzs Rd_GPR32, Rn_FPR64, FBitsOp
+is b_31=0 & b_2430=0b0011110 & b_2223=0b01 & b_1621=0b011000 & b_15=1 & Rd_GPR32 & Rn_FPR64 & FBitsOp & FBits64 & Rd_GPR64
+{
+ local tmp1:8 = Rn_FPR64 f* FBits64;
+ Rd_GPR32 = trunc(tmp1);
+ zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
+}
+
+# C7.2.91 FCVTZS (scalar, fixed-point) page C7-2227 line 130156 MATCH x1e180000/mask=x7f3f0000
+# CONSTRUCT x9e580000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 FBits64 f* =trunc
+# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_fcvtzs/2
+# AUNIT --inst x9e580000/mask=xffff0000 --rand dfp --status pass --comment "nofpround"
+# Double-precision to 64-bit variant when sf == 1 && type == 01 G=GPR64 V=FPR64 size=8 fbits=FBits64
+
+:fcvtzs Rd_GPR64, Rn_FPR64, FBitsOp
+is b_31=1 & b_2430=0b0011110 & b_2223=0b01 & b_1621=0b011000 & Rd_GPR64 & Rn_FPR64 & FBitsOp & FBits64
+{
+ local tmp1:8 = Rn_FPR64 f* FBits64;
+ Rd_GPR64 = trunc(tmp1);
+}
+
+# C7.2.93 FCVTZU (vector, fixed-point) page C7-2231 line 130422 MATCH x2f00fc00/mask=xbf80fc00
+# CONSTRUCT x6f40fc00/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 zext:8 =NEON_fcvtzu/2@8
+# AUNIT --inst x6f40fc00/mask=xffc0fc00 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fcvtzu Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x1f & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ local tmp1:8 = zext(Imm_shr_imm64);
+ Rd_VPR128.2D = NEON_fcvtzu(Rn_VPR128.2D, tmp1, 8:1);
+}
+
+# C7.2.93 FCVTZU (vector, fixed-point) page C7-2231 line 130422 MATCH x2f00fc00/mask=xbf80fc00
+# CONSTRUCT x2f20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_fcvtzu/2@4
+# AUNIT --inst x2f20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fcvtzu Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x1f & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_fcvtzu(Rn_VPR64.2S, Imm_shr_imm32:4, 4:1);
+}
+
+# C7.2.93 FCVTZU (vector, fixed-point) page C7-2231 line 130422 MATCH x2f00fc00/mask=xbf80fc00
+# CONSTRUCT x6f20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_fcvtzu/2@4
+# AUNIT --inst x6f20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fcvtzu Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x1f & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_fcvtzu(Rn_VPR128.4S, Imm_shr_imm32:4, 4:1);
+}
+
+# C7.2.93 FCVTZU (vector, fixed-point) page C7-2231 line 130422 MATCH x2f00fc00/mask=xbf80fc00
+# CONSTRUCT x2f10fc00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2@2
+# AUNIT --inst x2f10fc00/mask=xfff0fc00 --rand hfp --status noqemu --comment "nofpround"
+
+:fcvtzu Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=1 & Imm_shr_imm16 & b_1115=0x1f & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_fcvtzu(Rn_VPR64.4H, Imm_shr_imm16, 2:1);
+}
+
+# C7.2.93 FCVTZU (vector, fixed-point) page C7-2231 line 130422 MATCH x2f00fc00/mask=xbf80fc00
+# CONSTRUCT x6f10fc00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2@2
+# AUNIT --inst x6f10fc00/mask=xfff0fc00 --rand hfp --status noqemu --comment "nofpround"
+
+:fcvtzu Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=1 & Imm_shr_imm16 & b_1115=0x1f & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_fcvtzu(Rn_VPR128.8H, Imm_shr_imm16, 2:1);
+}
+
+# C7.2.93 FCVTZU (vector, fixed-point) page C7-2231 line 130422 MATCH x7f00fc00/mask=xff80fc00
+# CONSTRUCT x7f10fc00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 1:2 ARG3 << int2float:2 f* fabs =trunc
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2
+# AUNIT --inst x7f10fc00/mask=xfff0fc00 --rand hfp --status noqemu --comment "nofpround"
+# FCVTZU (vector, fixed-point) Scalar immh=001x
+
+:fcvtzu Rd_FPR16, Rn_FPR16, Imm_shr_imm32
+is b_2331=0b011111110 & b_2022=0b001 & b_1015=0b111111 & Imm_shr_imm32 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ local tmp1:2 = 1:2 << Imm_shr_imm32;
+ local tmp2:2 = int2float(tmp1);
+ local tmp3:2 = Rn_FPR16 f* tmp2;
+ local tmp4:2 = abs(tmp3);
+ Rd_FPR16 = trunc(tmp4);
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.93 FCVTZU (vector, fixed-point) page C7-2231 line 130422 MATCH x7f00fc00/mask=xff80fc00
+# CONSTRUCT x7f20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 1:4 ARG3:4 << int2float:4 f* fabs =trunc
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2
+# AUNIT --inst x7f20fc00/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround"
+# FCVTZU (vector, fixed-point) Scalar immh=01xx
+
+:fcvtzu Rd_FPR32, Rn_FPR32, Imm_shr_imm32
+is b_2331=0b011111110 & b_2122=0b01 & b_1015=0b111111 & Imm_shr_imm32 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ local tmp1:4 = 1:4 << Imm_shr_imm32:4;
+ local tmp2:4 = int2float(tmp1);
+ local tmp3:4 = Rn_FPR32 f* tmp2;
+ local tmp4:4 = abs(tmp3);
+ Rd_FPR32 = trunc(tmp4);
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.93 FCVTZU (vector, fixed-point) page C7-2231 line 130422 MATCH x7f00fc00/mask=xff80fc00
+# CONSTRUCT x7f40fc00/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 1:8 ARG3 zext:8 << int2float:8 f* fabs =trunc
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2
+# AUNIT --inst x7f40fc00/mask=xffc0fc00 --rand dfp --status fail --comment "nofpround"
+# FCVTZU (vector, fixed-point) Scalar immh=1xxx
+
+:fcvtzu Rd_FPR64, Rn_FPR64, Imm_shr_imm32
+is b_2331=0b011111110 & b_22=1 & b_1015=0b111111 & Imm_shr_imm32 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ local tmp1:8 = zext(Imm_shr_imm32);
+ local tmp2:8 = 1:8 << tmp1;
+ local tmp3:8 = int2float(tmp2);
+ local tmp4:8 = Rn_FPR64 f* tmp3;
+ local tmp5:8 = abs(tmp4);
+ Rd_FPR64 = trunc(tmp5);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.95 FCVTZU (scalar, fixed-point) page C7-2237 line 130769 MATCH x1e190000/mask=x7f3f0000
+# CONSTRUCT x1ed98000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 f* =trunc
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2
+# AUNIT --inst x1ed98000/mask=xffff8000 --rand hfp --status noqemu --comment "nofpround"
+
+:fcvtzu Rd_GPR32, Rn_FPR16, FBitsOp
+is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=0 & mode=3 & fpOpcode=1 & b_15=1 & FBitsOp & FBits16 & Rn_FPR16 & Rd_GPR32 & Rd_GPR64
+{
+ local tmp1:2 = Rn_FPR16 f* FBitsOp;
+ Rd_GPR32 = trunc(tmp1);
+ zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
+}
+
+# C7.2.95 FCVTZU (scalar, fixed-point) page C7-2237 line 130769 MATCH x1e190000/mask=x7f3f0000
+# CONSTRUCT x9ed90000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 f* =trunc
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2
+# AUNIT --inst x9ed90000/mask=xffff0000 --rand hfp --status noqemu --comment "nofpround"
+
+:fcvtzu Rd_GPR64, Rn_FPR16, FBitsOp
+is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=0 & mode=3 & fpOpcode=1 & FBitsOp & FBits16 & Rn_FPR16 & Rd_GPR64
+{
+ local tmp1:2 = Rn_FPR16 f* FBitsOp;
+ Rd_GPR64 = trunc(tmp1);
+}
+
+# C7.2.95 FCVTZU (scalar, fixed-point) page C7-2237 line 130769 MATCH x1e190000/mask=x7f3f0000
+# CONSTRUCT x1e598000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 FBits64 f* =trunc
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fcvtzu/2
+# AUNIT --inst x1e598000/mask=xffff8000 --rand dfp --status fail --comment "nofpround"
+
+:fcvtzu Rd_GPR32, Rn_FPR64, FBitsOp
+is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=0 & mode=3 & fpOpcode=1 & b_15=1 & FBitsOp & FBits64 & Rn_FPR64 & Rd_GPR32 & Rd_GPR64
+{
+ local tmp1:8 = Rn_FPR64 f* FBits64;
+ Rd_GPR32 = trunc(tmp1);
+ zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
+}
+
+# C7.2.95 FCVTZU (scalar, fixed-point) page C7-2237 line 130769 MATCH x1e190000/mask=x7f3f0000
+# CONSTRUCT x1e198000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 FBits32 f* =trunc
+# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_fcvtzu/2
+# AUNIT --inst x1e198000/mask=xffff8000 --rand sfp --status fail --comment "nofpround"
+
+:fcvtzu Rd_GPR32, Rn_FPR32, FBitsOp
+is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=0 & mode=3 & fpOpcode=1 & b_15=1 & FBitsOp & FBits32 & Rn_FPR32 & Rd_GPR32 & Rd_GPR64
+{
+ local tmp1:4 = Rn_FPR32 f* FBits32;
+ Rd_GPR32 = trunc(tmp1);
+ zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
+}
+
+# C7.2.95 FCVTZU (scalar, fixed-point) page C7-2237 line 130769 MATCH x1e190000/mask=x7f3f0000
+# CONSTRUCT x9e590000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 FBits64 f* =trunc
+# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_fcvtzu/2
+# AUNIT --inst x9e590000/mask=xffff0000 --rand dfp --status fail --comment "nofpround"
+
+:fcvtzu Rd_GPR64, Rn_FPR64, FBitsOp
+is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=0 & mode=3 & fpOpcode=1 & FBitsOp & FBits64 & Rn_FPR64 & Rd_GPR64
+{
+ local tmp1:8 = Rn_FPR64 f* FBits64;
+ Rd_GPR64 = trunc(tmp1);
+}
+
+# C7.2.95 FCVTZU (scalar, fixed-point) page C7-2237 line 130769 MATCH x1e190000/mask=x7f3f0000
+# CONSTRUCT x9e190000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 FBits32 f* =trunc
+# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_fcvtzu/2
+# AUNIT --inst x9e190000/mask=xffff0000 --rand sfp --status fail --comment "nofpround"
+
+:fcvtzu Rd_GPR64, Rn_FPR32, FBitsOp
+is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=0 & mode=3 & fpOpcode=1 & FBitsOp & FBits32 & Rn_FPR32 & Rd_GPR64
+{
+ local tmp1:4 = Rn_FPR32 f* FBits32;
+ Rd_GPR64 = trunc(tmp1);
+}
+
+# C7.2.97 FDIV (vector) page C7-2241 line 131035 MATCH x2e20fc00/mask=xbfa0fc00
+# CONSTRUCT x6e60fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f/@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2@8
+# AUNIT --inst x6e60fc00/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
+
+:fdiv Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1f & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ # simd infix Rd_VPR128.2D = Rn_VPR128.2D f/ Rm_VPR128.2D on lane size 8
+ Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] f/ Rm_VPR128.2D[0,64];
+ Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] f/ Rm_VPR128.2D[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.97 FDIV (vector) page C7-2241 line 131035 MATCH x2e20fc00/mask=xbfa0fc00
+# CONSTRUCT x2e20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f/@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2@4
+# AUNIT --inst x2e20fc00/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround"
+
+:fdiv Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1f & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ # simd infix Rd_VPR64.2S = Rn_VPR64.2S f/ Rm_VPR64.2S on lane size 4
+ Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] f/ Rm_VPR64.2S[0,32];
+ Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] f/ Rm_VPR64.2S[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.97 FDIV (vector) page C7-2241 line 131035 MATCH x2e20fc00/mask=xbfa0fc00
+# CONSTRUCT x6e20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f/@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2@4
+# AUNIT --inst x6e20fc00/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround"
+
+:fdiv Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1f & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd infix Rd_VPR128.4S = Rn_VPR128.4S f/ Rm_VPR128.4S on lane size 4
+ Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] f/ Rm_VPR128.4S[0,32];
+ Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] f/ Rm_VPR128.4S[32,32];
+ Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] f/ Rm_VPR128.4S[64,32];
+ Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] f/ Rm_VPR128.4S[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.97 FDIV (vector) page C7-2241 line 131035 MATCH x2e403c00/mask=xbfe0fc00
+# CONSTRUCT x2e403c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f/@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2@2
+# AUNIT --inst x2e403c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 4H when Q = 0
+
+:fdiv Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b001111 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ # simd infix Rd_VPR64.4H = Rn_VPR64.4H f/ Rm_VPR64.4H on lane size 2
+ Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f/ Rm_VPR64.4H[0,16];
+ Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f/ Rm_VPR64.4H[16,16];
+ Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f/ Rm_VPR64.4H[32,16];
+ Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f/ Rm_VPR64.4H[48,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.97 FDIV (vector) page C7-2241 line 131035 MATCH x2e403c00/mask=xbfe0fc00
+# CONSTRUCT x6e403c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f/@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2@2
+# AUNIT --inst x6e403c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 8H when Q = 1
+
+:fdiv Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b001111 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ # simd infix Rd_VPR128.8H = Rn_VPR128.8H f/ Rm_VPR128.8H on lane size 2
+ Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f/ Rm_VPR128.8H[0,16];
+ Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f/ Rm_VPR128.8H[16,16];
+ Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f/ Rm_VPR128.8H[32,16];
+ Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f/ Rm_VPR128.8H[48,16];
+ Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f/ Rm_VPR128.8H[64,16];
+ Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f/ Rm_VPR128.8H[80,16];
+ Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f/ Rm_VPR128.8H[96,16];
+ Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f/ Rm_VPR128.8H[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.98 FDIV (scalar) page C7-2243 line 131150 MATCH x1e201800/mask=xff20fc00
+# CONSTRUCT x1e601800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =f/
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2
+# AUNIT --inst x1e601800/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
+
+:fdiv Rd_FPR64, Rn_FPR64, Rm_FPR64
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x1 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = Rn_FPR64 f/ Rm_FPR64;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.98 FDIV (scalar) page C7-2243 line 131150 MATCH x1e201800/mask=xff20fc00
+# CONSTRUCT x1e201800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =f/
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2
+# AUNIT --inst x1e201800/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround"
+
+:fdiv Rd_FPR32, Rn_FPR32, Rm_FPR32
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x1 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = Rn_FPR32 f/ Rm_FPR32;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.98 FDIV (scalar) page C7-2243 line 131150 MATCH x1e201800/mask=xff20fc00
+# CONSTRUCT x1ee01800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =f/
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fdiv/2
+# AUNIT --inst x1ee01800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+
+:fdiv Rd_FPR16, Rn_FPR16, Rm_FPR16
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x1 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = Rn_FPR16 f/ Rm_FPR16;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.99 FJCVTZS page C7-2245 line 131259 MATCH x1e7e0000/mask=xfffffc00
+# CONSTRUCT x1e7e0000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =trunc
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fjcvtzs/1
+# AUNIT --inst x1e7e0000/mask=xfffffc00 --rand dfp --status noqemu --comment "nofpround"
+
+:fjcvtzs Rd_GPR32, Rn_FPR64
+is b_1031=0b0001111001111110000000 & Rd_GPR32 & Rn_FPR64 & Rd_GPR64
+{
+ Rd_GPR32 = trunc(Rn_FPR64);
+ zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
+}
+
+# C7.2.100 FMADD page C7-2246 line 131323 MATCH x1f000000/mask=xff208000
+# CONSTRUCT x1f400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fmadd/3
+# AUNIT --inst x1f400000/mask=xffe08000 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fmadd Rd_FPR64, Rn_FPR64, Rm_FPR64, Ra_FPR64
+is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=1 & b_21=0 & Rm_FPR64 & b_15=0 & Ra_FPR64 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_fmadd(Rn_FPR64, Rm_FPR64, Ra_FPR64);
+}
+
+# C7.2.100 FMADD page C7-2246 line 131323 MATCH x1f000000/mask=xff208000
+# CONSTRUCT x1f000000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fmadd/3
+# AUNIT --inst x1f000000/mask=xffe08000 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fmadd Rd_FPR32, Rn_FPR32, Rm_FPR32, Ra_FPR32
+is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=0 & b_21=0 & Rm_FPR32 & b_15=0 & Ra_FPR32 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_fmadd(Rn_FPR32, Rm_FPR32, Ra_FPR32);
+}
+
+# C7.2.100 FMADD page C7-2246 line 131323 MATCH x1f000000/mask=xff208000
+# CONSTRUCT x1fc00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fmadd/3
+# AUNIT --inst x1fc00000/mask=xffe08000 --rand hfp --status noqemu --comment "nofpround"
+
+:fmadd Rd_FPR16, Rn_FPR16, Rm_FPR16, Ra_FPR16
+is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=3 & b_21=0 & Rm_FPR16 & b_15=0 & Ra_FPR16 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_fmadd(Rn_FPR16, Rm_FPR16, Ra_FPR16);
+}
+
+# C7.2.101 FMAX (vector) page C7-2248 line 131451 MATCH x0e20f400/mask=xbfa0fc00
+# CONSTRUCT x4e60f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2@8
+# AUNIT --inst x4e60f400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fmax Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1e & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_fmax(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.101 FMAX (vector) page C7-2248 line 131451 MATCH x0e20f400/mask=xbfa0fc00
+# CONSTRUCT x0e20f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2@4
+# AUNIT --inst x0e20f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fmax Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1e & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_fmax(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.101 FMAX (vector) page C7-2248 line 131451 MATCH x0e20f400/mask=xbfa0fc00
+# CONSTRUCT x4e20f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2@4
+# AUNIT --inst x4e20f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fmax Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1e & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_fmax(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.101 FMAX (vector) page C7-2248 line 131451 MATCH x0e403400/mask=xbfe0fc00
+# CONSTRUCT x0e403400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2@2
+# AUNIT --inst x0e403400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 4H when Q = 0
+
+:fmax Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b001101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_fmax(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.101 FMAX (vector) page C7-2248 line 131451 MATCH x0e403400/mask=xbfe0fc00
+# CONSTRUCT x4e403400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2@2
+# AUNIT --inst x4e403400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 8H when Q = 1
+
+:fmax Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b001101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_fmax(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.102 FMAX (scalar) page C7-2250 line 131581 MATCH x1e204800/mask=xff20fc00
+# CONSTRUCT x1e604800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 = ext ARG2 ARG3 f>:1 inst_next goto ARG1 ARG3 =
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2
+# AUNIT --inst x1e604800/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fmax Rd_FPR64, Rn_FPR64, Rm_FPR64
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x4 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = Rn_FPR64;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+ local tmp1:1 = Rn_FPR64 f> Rm_FPR64;
+ if (tmp1) goto inst_next;
+ Rd_FPR64 = Rm_FPR64;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.102 FMAX (scalar) page C7-2250 line 131581 MATCH x1e204800/mask=xff20fc00
+# CONSTRUCT x1e204800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 = ext ARG2 ARG3 f>:1 inst_next goto ARG1 ARG3 =
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2
+# AUNIT --inst x1e204800/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fmax Rd_FPR32, Rn_FPR32, Rm_FPR32
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x4 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = Rn_FPR32;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+ local tmp1:1 = Rn_FPR32 f> Rm_FPR32;
+ if (tmp1) goto inst_next;
+ Rd_FPR32 = Rm_FPR32;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.102 FMAX (scalar) page C7-2250 line 131581 MATCH x1e204800/mask=xff20fc00
+# CONSTRUCT x1ee04800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmax/2
+# AUNIT --inst x1ee04800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+
+:fmax Rd_FPR16, Rn_FPR16, Rm_FPR16
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x4 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_fmax(Rn_FPR16, Rm_FPR16);
+}
+
+# C7.2.103 FMAXNM (vector) page C7-2252 line 131688 MATCH x0e20c400/mask=xbfa0fc00
+# CONSTRUCT x4e60c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2@8
+# AUNIT --inst x4e60c400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fmaxnm Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x18 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_fmaxnm(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.103 FMAXNM (vector) page C7-2252 line 131688 MATCH x0e20c400/mask=xbfa0fc00
+# CONSTRUCT x0e20c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2@4
+# AUNIT --inst x0e20c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fmaxnm Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x18 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_fmaxnm(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.103 FMAXNM (vector) page C7-2252 line 131688 MATCH x0e20c400/mask=xbfa0fc00
+# CONSTRUCT x4e20c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2@4
+# AUNIT --inst x4e20c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fmaxnm Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x18 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_fmaxnm(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.103 FMAXNM (vector) page C7-2252 line 131688 MATCH x0e400400/mask=xbfe0fc00
+# CONSTRUCT x0e400400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2@2
+# AUNIT --inst x0e400400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision SIMD 4H when Q = 0
+
+:fmaxnm Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b000001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_fmaxnm(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.103 FMAXNM (vector) page C7-2252 line 131688 MATCH x0e400400/mask=xbfe0fc00
+# CONSTRUCT x4e400400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2@2
+# AUNIT --inst x4e400400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision SIMD 8H when Q = 1
+
+:fmaxnm Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b000001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_fmaxnm(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.104 FMAXNM (scalar) page C7-2254 line 131821 MATCH x1e206800/mask=xff20fc00
+# CONSTRUCT x1e606800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 = ext ARG2 ARG3 f>:1 inst_next goto ARG1 ARG3 =
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2
+# AUNIT --inst x1e606800/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fmaxnm Rd_FPR64, Rn_FPR64, Rm_FPR64
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x6 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = Rn_FPR64;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+ local tmp1:1 = Rn_FPR64 f> Rm_FPR64;
+ if (tmp1) goto inst_next;
+ Rd_FPR64 = Rm_FPR64;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.104 FMAXNM (scalar) page C7-2254 line 131821 MATCH x1e206800/mask=xff20fc00
+# CONSTRUCT x1e206800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 = ext ARG2 ARG3 f>:1 inst_next goto ARG1 ARG3 =
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2
+# AUNIT --inst x1e206800/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fmaxnm Rd_FPR32, Rn_FPR32, Rm_FPR32
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x6 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = Rn_FPR32;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+ local tmp1:1 = Rn_FPR32 f> Rm_FPR32;
+ if (tmp1) goto inst_next;
+ Rd_FPR32 = Rm_FPR32;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.104 FMAXNM (scalar) page C7-2254 line 131821 MATCH x1e206800/mask=xff20fc00
+# CONSTRUCT x1ee06800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 = ext ARG2 ARG3 f>:1 inst_next goto ARG1 ARG3 =
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnm/2
+# AUNIT --inst x1ee06800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+
+:fmaxnm Rd_FPR16, Rn_FPR16, Rm_FPR16
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x6 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = Rn_FPR16;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+ local tmp1:1 = Rn_FPR16 f> Rm_FPR16;
+ if (tmp1) goto inst_next;
+ Rd_FPR16 = Rm_FPR16;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.105 FMAXNMP (scalar) page C7-2256 line 131930 MATCH x7e30c800/mask=xffbffc00
+# CONSTRUCT x7e70c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxnmp/1@8
+# AUNIT --inst x7e70c800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fmaxnmp Rd_FPR64, Rn_VPR128.2D
+is b_3031=1 & u=1 & b_2428=0x1e & b_23=0 & b_1722=0x38 & b_1216=0xc & b_1011=2 & Rn_VPR128.2D & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_fmaxnmp(Rn_VPR128.2D, 8:1);
+}
+
+# C7.2.105 FMAXNMP (scalar) page C7-2256 line 131930 MATCH x7e30c800/mask=xffbffc00
+# CONSTRUCT x7e30c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxnmp/1@4
+# AUNIT --inst x7e30c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fmaxnmp Rd_FPR32, Rn_VPR64.2S
+is b_3031=1 & u=1 & b_2428=0x1e & b_23=0 & b_1722=0x18 & b_1216=0xc & b_1011=2 & Rn_VPR64.2S & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_fmaxnmp(Rn_VPR64.2S, 4:1);
+}
+
+# C7.2.105 FMAXNMP (scalar) page C7-2256 line 131930 MATCH x5e30c800/mask=xffbffc00
+# CONSTRUCT x5e30c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 Rn_FPR32 =NEON_fmaxnmp/1@2
+# AUNIT --inst x5e30c800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant
+
+:fmaxnmp Rd_FPR16, vRn_VPR128^".2H"
+is b_1031=0b0101111000110000110010 & Rd_FPR16 & vRn_VPR128 & Rn_FPR32 & Zd
+{
+ Rd_FPR16 = NEON_fmaxnmp(Rn_FPR32, 2:1);
+}
+
+# C7.2.106 FMAXNMP (vector) page C7-2258 line 132036 MATCH x2e20c400/mask=xbfa0fc00
+# CONSTRUCT x6e60c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnmp/2@8
+# AUNIT --inst x6e60c400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fmaxnmp Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x18 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_fmaxnmp(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.106 FMAXNMP (vector) page C7-2258 line 132036 MATCH x2e20c400/mask=xbfa0fc00
+# CONSTRUCT x2e20c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnmp/2@4
+# AUNIT --inst x2e20c400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fmaxnmp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x18 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_fmaxnmp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.106 FMAXNMP (vector) page C7-2258 line 132036 MATCH x2e20c400/mask=xbfa0fc00
+# CONSTRUCT x6e20c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnmp/2@4
+# AUNIT --inst x6e20c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fmaxnmp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x18 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_fmaxnmp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.106 FMAXNMP (vector) page C7-2258 line 132036 MATCH x2e400400/mask=xbfe0fc00
+# CONSTRUCT x2e400400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnmp/2@2
+# AUNIT --inst x2e400400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 4H when Q = 0
+
+:fmaxnmp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b000001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_fmaxnmp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.106 FMAXNMP (vector) page C7-2258 line 132036 MATCH x2e400400/mask=xbfe0fc00
+# CONSTRUCT x6e400400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxnmp/2@2
+# AUNIT --inst x6e400400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 8H when Q = 1
+
+:fmaxnmp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b000001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_fmaxnmp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.107 FMAXNMV page C7-2260 line 132171 MATCH x2e30c800/mask=xbfbffc00
+# CONSTRUCT x6e30c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxnmv/1@4
+# AUNIT --inst x6e30c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fmaxnmv Rd_FPR32, Rn_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xc & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_fmaxnmv(Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.107 FMAXNMV page C7-2260 line 132171 MATCH x0e30c800/mask=xbffffc00
+# CONSTRUCT x0e30c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxnmv/1@2
+# AUNIT --inst x0e30c800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 4H when Q = 0
+
+:fmaxnmv Rd_FPR16, Rn_VPR64.4H
+is b_31=0 & b_30=0 & b_1029=0b00111000110000110010 & Rd_FPR16 & Rn_VPR64.4H & Zd
+{
+ Rd_FPR16 = NEON_fmaxnmv(Rn_VPR64.4H, 2:1);
+}
+
+# C7.2.107 FMAXNMV page C7-2260 line 132171 MATCH x0e30c800/mask=xbffffc00
+# CONSTRUCT x4e30c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxnmv/1@2
+# AUNIT --inst x4e30c800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 8H when Q = 1
+
+:fmaxnmv Rd_FPR16, Rn_VPR128.8H
+is b_31=0 & b_30=1 & b_1029=0b00111000110000110010 & Rd_FPR16 & Rn_VPR128.8H & Zd
+{
+ Rd_FPR16 = NEON_fmaxnmv(Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.108 FMAXP (scalar) page C7-2262 line 132280 MATCH x7e30f800/mask=xffbffc00
+# CONSTRUCT x7e70f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxnmv/1@8
+# AUNIT --inst x7e70f800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fmaxp Rd_FPR64, Rn_VPR128.2D
+is b_3031=1 & u=1 & b_2428=0x1e & b_23=0 & b_1722=0x38 & b_1216=0xf & b_1011=2 & Rn_VPR128.2D & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_fmaxnmv(Rn_VPR128.2D, 8:1);
+}
+
+# C7.2.108 FMAXP (scalar) page C7-2262 line 132280 MATCH x7e30f800/mask=xffbffc00
+# CONSTRUCT x7e30f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxp/1@4
+# AUNIT --inst x7e30f800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fmaxp Rd_FPR32, Rn_VPR64.2S
+is b_3031=1 & u=1 & b_2428=0x1e & b_23=0 & b_1722=0x18 & b_1216=0xf & b_1011=2 & Rn_VPR64.2S & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_fmaxp(Rn_VPR64.2S, 4:1);
+}
+
+# C7.2.108 FMAXP (scalar) page C7-2262 line 132280 MATCH x5e30f800/mask=xffbffc00
+# CONSTRUCT x5e30f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 Rn_FPR32 =NEON_fmaxp/1@2
+# AUNIT --inst x5e30f800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant
+
+:fmaxp Rd_FPR16, vRn_VPR128^".2H"
+is b_1031=0b0101111000110000111110 & Rd_FPR16 & vRn_VPR128 & Rn_FPR32 & Zd
+{
+ Rd_FPR16 = NEON_fmaxp(Rn_FPR32, 2:1);
+}
+
+# C7.2.109 FMAXP (vector) page C7-2264 line 132387 MATCH x2e20f400/mask=xbfa0fc00
+# CONSTRUCT x6e60f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxp/2@8
+# AUNIT --inst x6e60f400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fmaxp Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1e & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_fmaxp(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.109 FMAXP (vector) page C7-2264 line 132387 MATCH x2e20f400/mask=xbfa0fc00
+# CONSTRUCT x2e20f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxp/2@4
+# AUNIT --inst x2e20f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fmaxp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1e & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_fmaxp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.109 FMAXP (vector) page C7-2264 line 132387 MATCH x2e20f400/mask=xbfa0fc00
+# CONSTRUCT x6e20f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxp/2@4
+# AUNIT --inst x6e20f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fmaxp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1e & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_fmaxp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.109 FMAXP (vector) page C7-2264 line 132387 MATCH x2e403400/mask=xbfe0fc00
+# CONSTRUCT x2e403400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxp/2@2
+# AUNIT --inst x2e403400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 4H when Q = 0
+
+:fmaxp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b001101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_fmaxp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.109 FMAXP (vector) page C7-2264 line 132387 MATCH x2e403400/mask=xbfe0fc00
+# CONSTRUCT x6e403400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmaxp/2@2
+# AUNIT --inst x6e403400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 8H when Q = 1
+
+:fmaxp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b001101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_fmaxp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.110 FMAXV page C7-2266 line 132519 MATCH x2e30f800/mask=xbfbffc00
+# CONSTRUCT x6e30f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxv/1@4
+# AUNIT --inst x6e30f800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fmaxv Rd_FPR32, Rn_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xf & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_fmaxv(Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.110 FMAXV page C7-2266 line 132519 MATCH x0e30f800/mask=xbffffc00
+# CONSTRUCT x0e30f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxv/1@2
+# AUNIT --inst x0e30f800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 4H when Q = 0
+
+:fmaxv Rd_FPR16, Rn_VPR64.4H
+is b_31=0 & b_30=0 & b_1029=0b00111000110000111110 & Rd_FPR16 & Rn_VPR64.4H & Zd
+{
+ Rd_FPR16 = NEON_fmaxv(Rn_VPR64.4H, 2:1);
+}
+
+# C7.2.110 FMAXV page C7-2266 line 132519 MATCH x0e30f800/mask=xbffffc00
+# CONSTRUCT x4e30f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmaxv/1@2
+# AUNIT --inst x4e30f800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 8H when Q = 1
+
+:fmaxv Rd_FPR16, Rn_VPR128.8H
+is b_31=0 & b_30=1 & b_1029=0b00111000110000111110 & Rd_FPR16 & Rn_VPR128.8H & Zd
+{
+ Rd_FPR16 = NEON_fmaxv(Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.111 FMIN (vector) page C7-2268 line 132628 MATCH x0ea0f400/mask=xbfa0fc00
+# CONSTRUCT x4ee0f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2@8
+# AUNIT --inst x4ee0f400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fmin Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x1e & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_fmin(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.111 FMIN (vector) page C7-2268 line 132628 MATCH x0ea0f400/mask=xbfa0fc00
+# CONSTRUCT x0ea0f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2@4
+# AUNIT --inst x0ea0f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fmin Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x1e & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_fmin(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.111 FMIN (vector) page C7-2268 line 132628 MATCH x0ea0f400/mask=xbfa0fc00
+# CONSTRUCT x4ea0f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2@4
+# AUNIT --inst x4ea0f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fmin Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x1e & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_fmin(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.111 FMIN (vector) page C7-2268 line 132628 MATCH x0ec03400/mask=xbfe0fc00
+# CONSTRUCT x0ec03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2@2
+# AUNIT --inst x0ec03400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 4H when Q = 0
+
+:fmin Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2129=0b001110110 & b_1015=0b001101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_fmin(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.111 FMIN (vector) page C7-2268 line 132628 MATCH x0ec03400/mask=xbfe0fc00
+# CONSTRUCT x4ec03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2@2
+# AUNIT --inst x4ec03400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 8H when Q = 1
+
+:fmin Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2129=0b001110110 & b_1015=0b001101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_fmin(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.112 FMIN (scalar) page C7-2270 line 132758 MATCH x1e205800/mask=xff20fc00
+# CONSTRUCT x1e605800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2
+# AUNIT --inst x1e605800/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fmin Rd_FPR64, Rn_FPR64, Rm_FPR64
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x5 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_fmin(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.112 FMIN (scalar) page C7-2270 line 132758 MATCH x1e205800/mask=xff20fc00
+# CONSTRUCT x1e205800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2
+# AUNIT --inst x1e205800/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fmin Rd_FPR32, Rn_FPR32, Rm_FPR32
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x5 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_fmin(Rn_FPR32, Rm_FPR32);
+}
+
+# C7.2.112 FMIN (scalar) page C7-2270 line 132758 MATCH x1e205800/mask=xff20fc00
+# CONSTRUCT x1ee05800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmin/2
+# AUNIT --inst x1ee05800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+
+:fmin Rd_FPR16, Rn_FPR16, Rm_FPR16
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x5 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_fmin(Rn_FPR16, Rm_FPR16);
+}
+
+# C7.2.113 FMINNM (vector) page C7-2272 line 132865 MATCH x0ea0c400/mask=xbfa0fc00
+# CONSTRUCT x4ee0c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2@8
+# AUNIT --inst x4ee0c400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fminnm Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x18 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_fminnm(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.113 FMINNM (vector) page C7-2272 line 132865 MATCH x0ea0c400/mask=xbfa0fc00
+# CONSTRUCT x0ea0c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2@4
+# AUNIT --inst x0ea0c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fminnm Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x18 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_fminnm(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.113 FMINNM (vector) page C7-2272 line 132865 MATCH x0ea0c400/mask=xbfa0fc00
+# CONSTRUCT x4ea0c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2@4
+# AUNIT --inst x4ea0c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fminnm Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x18 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_fminnm(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.113 FMINNM (vector) page C7-2272 line 132865 MATCH x0ec00400/mask=xbfe0fc00
+# CONSTRUCT x0ec00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2@2
+# AUNIT --inst x0ec00400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 4H when Q = 0
+
+:fminnm Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2129=0b001110110 & b_1015=0b000001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_fminnm(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.113 FMINNM (vector) page C7-2272 line 132865 MATCH x0ec00400/mask=xbfe0fc00
+# CONSTRUCT x4ec00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2@2
+# AUNIT --inst x4ec00400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 8H when Q = 1
+
+:fminnm Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2129=0b001110110 & b_1015=0b000001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_fminnm(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.114 FMINNM (scalar) page C7-2274 line 132998 MATCH x1e207800/mask=xff20fc00
+# CONSTRUCT x1e607800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2
+# AUNIT --inst x1e607800/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fminnm Rd_FPR64, Rn_FPR64, Rm_FPR64
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x7 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_fminnm(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.114 FMINNM (scalar) page C7-2274 line 132998 MATCH x1e207800/mask=xff20fc00
+# CONSTRUCT x1e207800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2
+# AUNIT --inst x1e207800/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fminnm Rd_FPR32, Rn_FPR32, Rm_FPR32
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x7 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_fminnm(Rn_FPR32, Rm_FPR32);
+}
+
+# C7.2.114 FMINNM (scalar) page C7-2274 line 132998 MATCH x1e207800/mask=xff20fc00
+# CONSTRUCT x1ee07800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnm/2
+# AUNIT --inst x1ee07800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+
+:fminnm Rd_FPR16, Rn_FPR16, Rm_FPR16
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x7 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_fminnm(Rn_FPR16, Rm_FPR16);
+}
+
+# C7.2.115 FMINNMP (scalar) page C7-2276 line 133108 MATCH x7eb0c800/mask=xffbffc00
+# CONSTRUCT x7ef0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fminnmp/1@8
+# AUNIT --inst x7ef0c800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fminnmp Rd_FPR64, Rn_VPR128.2D
+is b_3031=1 & u=1 & b_2428=0x1e & b_23=1 & b_1722=0x38 & b_1216=0xc & b_1011=2 & Rn_VPR128.2D & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_fminnmp(Rn_VPR128.2D, 8:1);
+}
+
+# C7.2.115 FMINNMP (scalar) page C7-2276 line 133108 MATCH x7eb0c800/mask=xffbffc00
+# CONSTRUCT x7eb0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fminnmp/1@4
+# AUNIT --inst x7eb0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fminnmp Rd_FPR32, Rn_VPR64.2S
+is b_3031=1 & u=1 & b_2428=0x1e & b_23=1 & b_1722=0x18 & b_1216=0xc & b_1011=2 & Rn_VPR64.2S & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_fminnmp(Rn_VPR64.2S, 4:1);
+}
+
+# C7.2.115 FMINNMP (scalar) page C7-2276 line 133108 MATCH x5eb0c800/mask=xffbffc00
+# CONSTRUCT x5eb0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 Rn_FPR32 =NEON_fminnmp/1@2
+# AUNIT --inst x5eb0c800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant
+
+:fminnmp Rd_FPR16, vRn_VPR128^".2H"
+is b_1031=0b0101111010110000110010 & Rd_FPR16 & vRn_VPR128 & Rn_FPR32 & Zd
+{
+ Rd_FPR16 = NEON_fminnmp(Rn_FPR32, 2:1);
+}
+
+# C7.2.116 FMINNMP (vector) page C7-2278 line 133214 MATCH x2ea0c400/mask=xbfa0fc00
+# CONSTRUCT x6ee0c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnmp/2@8
+# AUNIT --inst x6ee0c400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fminnmp Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x18 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_fminnmp(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.116 FMINNMP (vector) page C7-2278 line 133214 MATCH x2ea0c400/mask=xbfa0fc00
+# CONSTRUCT x2ea0c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnmp/2@4
+# AUNIT --inst x2ea0c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fminnmp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x18 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_fminnmp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.116 FMINNMP (vector) page C7-2278 line 133214 MATCH x2ea0c400/mask=xbfa0fc00
+# CONSTRUCT x6ea0c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnmp/2@4
+# AUNIT --inst x6ea0c400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fminnmp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x18 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_fminnmp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.116 FMINNMP (vector) page C7-2278 line 133214 MATCH x2ec00400/mask=xbfe0fc00
+# CONSTRUCT x2ec00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnmp/2@2
+# AUNIT --inst x2ec00400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 4H when Q = 0
+
+:fminnmp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2129=0b101110110 & b_1015=0b000001 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_fminnmp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.116 FMINNMP (vector) page C7-2278 line 133214 MATCH x2ec00400/mask=xbfe0fc00
+# CONSTRUCT x6ec00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminnmp/2@2
+# AUNIT --inst x6ec00400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 8H when Q = 1
+
+:fminnmp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2129=0b101110110 & b_1015=0b000001 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_fminnmp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.117 FMINNMV page C7-2280 line 133349 MATCH x2eb0c800/mask=xbfbffc00
+# CONSTRUCT x6eb0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fminnmv/1@4
+# AUNIT --inst x6eb0c800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fminnmv Rd_FPR32, Rn_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0xc & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_fminnmv(Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.117 FMINNMV page C7-2280 line 133349 MATCH x0eb0c800/mask=xbffffc00
+# CONSTRUCT x0eb0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fminnmv/1@2
+# AUNIT --inst x0eb0c800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 4H when Q = 0
+
+:fminnmv Rd_FPR16, Rn_VPR64.4H
+is b_31=0 & b_30=0 & b_1029=0b00111010110000110010 & Rd_FPR16 & Rn_VPR64.4H & Zd
+{
+ Rd_FPR16 = NEON_fminnmv(Rn_VPR64.4H, 2:1);
+}
+
+# C7.2.117 FMINNMV page C7-2280 line 133349 MATCH x0eb0c800/mask=xbffffc00
+# CONSTRUCT x4eb0c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fminnmv/1@2
+# AUNIT --inst x4eb0c800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 8H when Q = 1
+
+:fminnmv Rd_FPR16, Rn_VPR128.8H
+is b_31=0 & b_30=1 & b_1029=0b00111010110000110010 & Rd_FPR16 & Rn_VPR128.8H & Zd
+{
+ Rd_FPR16 = NEON_fminnmv(Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.118 FMINP (scalar) page C7-2282 line 133458 MATCH x7eb0f800/mask=xffbffc00
+# CONSTRUCT x7ef0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fminp/1@8
+# AUNIT --inst x7ef0f800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fminp Rd_FPR64, Rn_VPR128.2D
+is b_3031=1 & u=1 & b_2428=0x1e & b_23=1 & b_1722=0x38 & b_1216=0xf & b_1011=2 & Rn_VPR128.2D & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_fminp(Rn_VPR128.2D, 8:1);
+}
+
+# C7.2.118 FMINP (scalar) page C7-2282 line 133458 MATCH x7eb0f800/mask=xffbffc00
+# CONSTRUCT x7eb0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fminp/1@4
+# AUNIT --inst x7eb0f800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fminp Rd_FPR32, Rn_VPR64.2S
+is b_3031=1 & u=1 & b_2428=0x1e & b_23=1 & b_1722=0x18 & b_1216=0xf & b_1011=2 & Rn_VPR64.2S & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_fminp(Rn_VPR64.2S, 4:1);
+}
+
+# C7.2.118 FMINP (scalar) page C7-2282 line 133458 MATCH x5eb0f800/mask=xffbffc00
+# CONSTRUCT x5eb0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 Rn_FPR32 =NEON_fminp/1@2
+# AUNIT --inst x5eb0f800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant
+
+:fminp Rd_FPR16, vRn_VPR128^".2H"
+is b_1031=0b0101111010110000111110 & Rd_FPR16 & vRn_VPR128 & Rn_FPR32 & Zd
+{
+ Rd_FPR16 = NEON_fminp(Rn_FPR32, 2:1);
+}
+
+# C7.2.119 FMINP (vector) page C7-2284 line 133565 MATCH x2ea0f400/mask=xbfa0fc00
+# CONSTRUCT x6ee0f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminp/2@8
+# AUNIT --inst x6ee0f400/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fminp Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x1e & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_fminp(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.119 FMINP (vector) page C7-2284 line 133565 MATCH x2ea0f400/mask=xbfa0fc00
+# CONSTRUCT x2ea0f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminp/2@4
+# AUNIT --inst x2ea0f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fminp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x1e & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_fminp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.119 FMINP (vector) page C7-2284 line 133565 MATCH x2ea0f400/mask=xbfa0fc00
+# CONSTRUCT x6ea0f400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminp/2@4
+# AUNIT --inst x6ea0f400/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fminp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x1e & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_fminp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.119 FMINP (vector) page C7-2284 line 133565 MATCH x2ec03400/mask=xbfe0fc00
+# CONSTRUCT x2ec03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminp/2@2
+# AUNIT --inst x2ec03400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 4H when Q = 0
+
+:fminp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2129=0b101110110 & b_1015=0b001101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_fminp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.119 FMINP (vector) page C7-2284 line 133565 MATCH x2ec03400/mask=xbfe0fc00
+# CONSTRUCT x6ec03400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fminp/2@2
+# AUNIT --inst x6ec03400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 8H when Q = 1
+
+:fminp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2129=0b101110110 & b_1015=0b001101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_fminp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.120 FMINV page C7-2286 line 133697 MATCH x2eb0f800/mask=xbfbffc00
+# CONSTRUCT x6eb0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fminv/1@4
+# AUNIT --inst x6eb0f800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fminv Rd_FPR32, Rn_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0xf & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_fminv(Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.120 FMINV page C7-2286 line 133697 MATCH x0eb0f800/mask=xbffffc00
+# CONSTRUCT x0eb0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fminv/1@2
+# AUNIT --inst x0eb0f800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 4H when Q = 0
+
+:fminv Rd_FPR16, Rn_VPR64.4H
+is b_31=0 & b_30=0 & b_1029=0b00111010110000111110 & Rd_FPR16 & Rn_VPR64.4H & Zd
+{
+ Rd_FPR16 = NEON_fminv(Rn_VPR64.4H, 2:1);
+}
+
+# C7.2.120 FMINV page C7-2286 line 133697 MATCH x0eb0f800/mask=xbffffc00
+# CONSTRUCT x4eb0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fminv/1@2
+# AUNIT --inst x4eb0f800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 8H when Q = 1
+
+:fminv Rd_FPR16, Rn_VPR128.8H
+is b_31=0 & b_30=1 & b_1029=0b00111010110000111110 & Rd_FPR16 & Rn_VPR128.8H & Zd
+{
+ Rd_FPR16 = NEON_fminv(Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.121 FMLA (by element) page C7-2288 line 133806 MATCH x0f801000/mask=xbf80f400
+# CONSTRUCT x4fc01000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $f* &=$f+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@8
+# AUNIT --inst x4fc01000/mask=xffe0f400 --rand dfp --status pass --comment "nofpround"
+
+:fmla Rd_VPR128.2D, Rn_VPR128.2D, Re_VPR128.D.vIndex
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=3 & b_2121=0 & Re_VPR128.D.vIndex & vIndex & Re_VPR128.D & b_1215=0x1 & b_1010=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ # simd element Re_VPR128.D[vIndex] lane size 8
+ local tmp1:8 = Re_VPR128.D.vIndex;
+ # simd infix TMPQ1 = Rn_VPR128.2D f* tmp1 on lane size 8
+ TMPQ1[0,64] = Rn_VPR128.2D[0,64] f* tmp1;
+ TMPQ1[64,64] = Rn_VPR128.2D[64,64] f* tmp1;
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D f+ TMPQ1 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] f+ TMPQ1[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] f+ TMPQ1[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.121 FMLA (by element) page C7-2288 line 133806 MATCH x0f801000/mask=xbf80f400
+# CONSTRUCT x0f801000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $f* &=$f+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@4
+# AUNIT --inst x0f801000/mask=xffc0f400 --rand sfp --status pass --comment "nofpround"
+
+:fmla Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x1 & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp1:4 = Re_VPR128.S.vIndex;
+ # simd infix TMPD1 = Rn_VPR64.2S f* tmp1 on lane size 4
+ TMPD1[0,32] = Rn_VPR64.2S[0,32] f* tmp1;
+ TMPD1[32,32] = Rn_VPR64.2S[32,32] f* tmp1;
+ # simd infix Rd_VPR64.2S = Rd_VPR64.2S f+ TMPD1 on lane size 4
+ Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] f+ TMPD1[0,32];
+ Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] f+ TMPD1[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.121 FMLA (by element) page C7-2288 line 133806 MATCH x0f801000/mask=xbf80f400
+# CONSTRUCT x4f801000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $f* &=$f+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@4
+# AUNIT --inst x4f801000/mask=xffc0f400 --rand sfp --status fail --comment "nofpround"
+
+:fmla Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x1 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp1:4 = Re_VPR128.S.vIndex;
+ # simd infix TMPQ1 = Rn_VPR128.4S f* tmp1 on lane size 4
+ TMPQ1[0,32] = Rn_VPR128.4S[0,32] f* tmp1;
+ TMPQ1[32,32] = Rn_VPR128.4S[32,32] f* tmp1;
+ TMPQ1[64,32] = Rn_VPR128.4S[64,32] f* tmp1;
+ TMPQ1[96,32] = Rn_VPR128.4S[96,32] f* tmp1;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S f+ TMPQ1 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] f+ TMPQ1[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] f+ TMPQ1[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] f+ TMPQ1[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] f+ TMPQ1[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.121 FMLA (by element) page C7-2288 line 133806 MATCH x5f001000/mask=xffc0f400
+# CONSTRUCT x5f001000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 f* &=f+
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@2
+# AUNIT --inst x5f001000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround"
+# Scalar half-precision variant
+
+:fmla Rd_FPR16, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM
+is b_2231=0b0101111100 & b_1215=0b0001 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_FPR16 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Zd
+{
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp2:2 = Rn_FPR16 f* tmp1;
+ Rd_FPR16 = Rd_FPR16 f+ tmp2;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.121 FMLA (by element) page C7-2288 line 133806 MATCH x5f801000/mask=xff80f400
+# CONSTRUCT x5f801000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 f* &=f+
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@4
+# AUNIT --inst x5f801000/mask=xffc0f400 --rand sfp --status pass --comment "nofpround"
+# Scalar, single-precision and double-precision variant, sz=0
+
+:fmla Rd_FPR32, Rn_FPR32, Re_VPR128.S.vIndex
+is b_2331=0b010111111 & b_22=0 & b_1215=0b0001 & b_10=0 & Re_VPR128.S & vIndex & Rd_FPR32 & Rn_FPR32 & Re_VPR128.S.vIndex & Zd
+{
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp1:4 = Re_VPR128.S.vIndex;
+ local tmp2:4 = Rn_FPR32 f* tmp1;
+ Rd_FPR32 = Rd_FPR32 f+ tmp2;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.121 FMLA (by element) page C7-2288 line 133806 MATCH x5f801000/mask=xff80f400
+# CONSTRUCT x5fc01000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 f* &=f+
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@8
+# AUNIT --inst x5fc01000/mask=xffe0f400 --rand dfp --status pass --comment "nofpround"
+# Scalar, single-precision and double-precision variant, sz=1
+
+:fmla Rd_FPR64, Rn_FPR64, Re_VPR128.D.vIndex
+is b_2331=0b010111111 & b_22=1 & b_21=0 & b_1215=0b0001 & b_10=0 & Re_VPR128.D & vIndex & Rd_FPR64 & Rn_FPR64 & Re_VPR128.D.vIndex & Zd
+{
+ # simd element Re_VPR128.D[vIndex] lane size 8
+ local tmp1:8 = Re_VPR128.D.vIndex;
+ local tmp2:8 = Rn_FPR64 f* tmp1;
+ Rd_FPR64 = Rd_FPR64 f+ tmp2;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.121 FMLA (by element) page C7-2288 line 133806 MATCH x0f001000/mask=xbfc0f400
+# CONSTRUCT x0f001000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $f* &=$f+$@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@2
+# AUNIT --inst x0f001000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround"
+# Vector, half-precision variant SIMD 4H when Q = 0
+
+:fmla Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
+is b_31=0 & b_30=0 & b_2229=0b00111100 & b_1215=0b0001 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.4H & Rn_VPR64.4H & Re_VPR128Lo.H.vIndexHLM & Zd
+{
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
+ # simd infix TMPD1 = Rn_VPR64.4H f* tmp1 on lane size 2
+ TMPD1[0,16] = Rn_VPR64.4H[0,16] f* tmp1;
+ TMPD1[16,16] = Rn_VPR64.4H[16,16] f* tmp1;
+ TMPD1[32,16] = Rn_VPR64.4H[32,16] f* tmp1;
+ TMPD1[48,16] = Rn_VPR64.4H[48,16] f* tmp1;
+ # simd infix Rd_VPR64.4H = Rd_VPR64.4H f+ TMPD1 on lane size 2
+ Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] f+ TMPD1[0,16];
+ Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] f+ TMPD1[16,16];
+ Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] f+ TMPD1[32,16];
+ Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] f+ TMPD1[48,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.121 FMLA (by element) page C7-2288 line 133806 MATCH x0f001000/mask=xbfc0f400
+# CONSTRUCT x4f001000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $f* &=$f+$@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@2
+# AUNIT --inst x4f001000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround"
+# Vector, half-precision variant SIMD 8H when Q = 1
+
+:fmla Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
+is b_31=0 & b_30=1 & b_2229=0b00111100 & b_1215=0b0001 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.8H & Rn_VPR128.8H & Re_VPR128Lo.H.vIndexHLM & Zd
+{
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
+ # simd infix TMPQ1 = Rn_VPR128.8H f* tmp1 on lane size 2
+ TMPQ1[0,16] = Rn_VPR128.8H[0,16] f* tmp1;
+ TMPQ1[16,16] = Rn_VPR128.8H[16,16] f* tmp1;
+ TMPQ1[32,16] = Rn_VPR128.8H[32,16] f* tmp1;
+ TMPQ1[48,16] = Rn_VPR128.8H[48,16] f* tmp1;
+ TMPQ1[64,16] = Rn_VPR128.8H[64,16] f* tmp1;
+ TMPQ1[80,16] = Rn_VPR128.8H[80,16] f* tmp1;
+ TMPQ1[96,16] = Rn_VPR128.8H[96,16] f* tmp1;
+ TMPQ1[112,16] = Rn_VPR128.8H[112,16] f* tmp1;
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H f+ TMPQ1 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] f+ TMPQ1[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] f+ TMPQ1[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] f+ TMPQ1[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] f+ TMPQ1[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] f+ TMPQ1[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] f+ TMPQ1[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] f+ TMPQ1[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] f+ TMPQ1[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.122 FMLA (vector) page C7-2292 line 134046 MATCH x0e20cc00/mask=xbfa0fc00
+# CONSTRUCT x4e60cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $f*@8 &=$f+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@8
+# AUNIT --inst x4e60cc00/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
+
+:fmla Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.2D & b_1115=0x19 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.2D f* Rm_VPR128.2D on lane size 8
+ TMPQ1[0,64] = Rn_VPR128.2D[0,64] f* Rm_VPR128.2D[0,64];
+ TMPQ1[64,64] = Rn_VPR128.2D[64,64] f* Rm_VPR128.2D[64,64];
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D f+ TMPQ1 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] f+ TMPQ1[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] f+ TMPQ1[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.122 FMLA (vector) page C7-2292 line 134046 MATCH x0e20cc00/mask=xbfa0fc00
+# CONSTRUCT x0e20cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@4
+# AUNIT --inst x0e20cc00/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround"
+
+:fmla Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.2S & b_1115=0x19 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Re_VPR128 & Zd
+{
+ # simd infix TMPD1 = Rn_VPR64.2S f* Rm_VPR64.2S on lane size 4
+ TMPD1[0,32] = Rn_VPR64.2S[0,32] f* Rm_VPR64.2S[0,32];
+ TMPD1[32,32] = Rn_VPR64.2S[32,32] f* Rm_VPR64.2S[32,32];
+ # simd infix Rd_VPR64.2S = Rd_VPR64.2S f+ TMPD1 on lane size 4
+ Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] f+ TMPD1[0,32];
+ Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] f+ TMPD1[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.122 FMLA (vector) page C7-2292 line 134046 MATCH x0e20cc00/mask=xbfa0fc00
+# CONSTRUCT x4e20cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@4
+# AUNIT --inst x4e20cc00/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround"
+
+:fmla Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.4S & b_1115=0x19 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.4S f* Rm_VPR128.4S on lane size 4
+ TMPQ1[0,32] = Rn_VPR128.4S[0,32] f* Rm_VPR128.4S[0,32];
+ TMPQ1[32,32] = Rn_VPR128.4S[32,32] f* Rm_VPR128.4S[32,32];
+ TMPQ1[64,32] = Rn_VPR128.4S[64,32] f* Rm_VPR128.4S[64,32];
+ TMPQ1[96,32] = Rn_VPR128.4S[96,32] f* Rm_VPR128.4S[96,32];
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S f+ TMPQ1 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] f+ TMPQ1[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] f+ TMPQ1[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] f+ TMPQ1[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] f+ TMPQ1[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.122 FMLA (vector) page C7-2292 line 134046 MATCH x0e400c00/mask=xbfe0fc00
+# CONSTRUCT x0e400c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@2
+# AUNIT --inst x0e400c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 4H when Q = 0
+
+:fmla Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b000011 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ # simd infix TMPD1 = Rn_VPR64.4H f* Rm_VPR64.4H on lane size 4
+ TMPD1[0,32] = Rn_VPR64.4H[0,32] f* Rm_VPR64.4H[0,32];
+ TMPD1[32,32] = Rn_VPR64.4H[32,32] f* Rm_VPR64.4H[32,32];
+ # simd infix Rd_VPR64.4H = Rd_VPR64.4H f+ TMPD1 on lane size 4
+ Rd_VPR64.4H[0,32] = Rd_VPR64.4H[0,32] f+ TMPD1[0,32];
+ Rd_VPR64.4H[32,32] = Rd_VPR64.4H[32,32] f+ TMPD1[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.122 FMLA (vector) page C7-2292 line 134046 MATCH x0e400c00/mask=xbfe0fc00
+# CONSTRUCT x4e400c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmla/3@2
+# AUNIT --inst x4e400c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 8H when Q = 1
+
+:fmla Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b000011 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.8H f* Rm_VPR128.8H on lane size 4
+ TMPQ1[0,32] = Rn_VPR128.8H[0,32] f* Rm_VPR128.8H[0,32];
+ TMPQ1[32,32] = Rn_VPR128.8H[32,32] f* Rm_VPR128.8H[32,32];
+ TMPQ1[64,32] = Rn_VPR128.8H[64,32] f* Rm_VPR128.8H[64,32];
+ TMPQ1[96,32] = Rn_VPR128.8H[96,32] f* Rm_VPR128.8H[96,32];
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H f+ TMPQ1 on lane size 4
+ Rd_VPR128.8H[0,32] = Rd_VPR128.8H[0,32] f+ TMPQ1[0,32];
+ Rd_VPR128.8H[32,32] = Rd_VPR128.8H[32,32] f+ TMPQ1[32,32];
+ Rd_VPR128.8H[64,32] = Rd_VPR128.8H[64,32] f+ TMPQ1[64,32];
+ Rd_VPR128.8H[96,32] = Rd_VPR128.8H[96,32] f+ TMPQ1[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.123 FMLAL, FMLAL2 (by element) page C7-2294 line 134165 MATCH x0f800000/mask=xbfc0f400
+# CONSTRUCT x0f800000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[0]:4 ARG3 $f* $float2float@2:8 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal/3@4
+# AUNIT --inst x0f800000/mask=xffc0f400 --rand sfp --status noqemu --comment "ext nofpround"
+# SIMD 2S when Q = 0
+
+:fmlal Rd_VPR64.2S, vRn_VPR64^".2H", Re_VPR128Lo.H.vIndexHLM
+is b_31=0 & b_30=0 & b_2329=0b0011111 & b_22=0 & b_1215=0b0000 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & Re_VPR128Lo.H.vIndexHLM & Zd
+{
+ TMPS1 = Rn_VPR64[0,32];
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
+ # simd infix TMPS2 = TMPS1 f* tmp2 on lane size 2
+ TMPS2[0,16] = TMPS1[0,16] f* tmp2;
+ TMPS2[16,16] = TMPS1[16,16] f* tmp2;
+ # simd resize TMPD3 = float2float(TMPS2) (lane size 2 to 4)
+ TMPD3[0,32] = float2float(TMPS2[0,16]);
+ TMPD3[32,32] = float2float(TMPS2[16,16]);
+ # simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD3 on lane size 4
+ Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD3[0,32];
+ Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD3[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.123 FMLAL, FMLAL2 (by element) page C7-2294 line 134165 MATCH x0f800000/mask=xbfc0f400
+# CONSTRUCT x4f800000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[0]:8 ARG3 $f* $float2float@2:16 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal/3@2
+# AUNIT --inst x4f800000/mask=xffc0f400 --rand sfp --status noqemu --comment "ext nofpround"
+# SIMD 4S when Q = 1
+
+:fmlal Rd_VPR128.4S, vRn_VPR128^".4H", Re_VPR128Lo.H.vIndexHLM
+is b_31=0 & b_30=1 & b_2329=0b0011111 & b_22=0 & b_1215=0b0000 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Re_VPR128Lo.H.vIndexHLM & Zd
+{
+ TMPD1 = Rn_VPR128[0,64];
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
+ # simd infix TMPD2 = TMPD1 f* tmp2 on lane size 2
+ TMPD2[0,16] = TMPD1[0,16] f* tmp2;
+ TMPD2[16,16] = TMPD1[16,16] f* tmp2;
+ TMPD2[32,16] = TMPD1[32,16] f* tmp2;
+ TMPD2[48,16] = TMPD1[48,16] f* tmp2;
+ # simd resize TMPQ3 = float2float(TMPD2) (lane size 2 to 4)
+ TMPQ3[0,32] = float2float(TMPD2[0,16]);
+ TMPQ3[32,32] = float2float(TMPD2[16,16]);
+ TMPQ3[64,32] = float2float(TMPD2[32,16]);
+ TMPQ3[96,32] = float2float(TMPD2[48,16]);
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.123 FMLAL, FMLAL2 (by element) page C7-2294 line 134165 MATCH x2f808000/mask=xbfc0f400
+# CONSTRUCT x2f808000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:4 ARG3 $f* $float2float@2:8 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal2/3@2
+# AUNIT --inst x2f808000/mask=xffc0f400 --rand sfp --status noqemu --comment "ext nofpround"
+# SIMD 2S when Q = 0
+
+:fmlal2 Rd_VPR64.2S, vRn_VPR64^".2H", Re_VPR128Lo.H.vIndexHLM
+is b_31=0 & b_30=0 & b_2329=0b1011111 & b_22=0 & b_1215=0b1000 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & Re_VPR128Lo.H.vIndexHLM & Zd
+{
+ TMPS1 = Rn_VPR64[32,32];
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
+ # simd infix TMPS2 = TMPS1 f* tmp2 on lane size 2
+ TMPS2[0,16] = TMPS1[0,16] f* tmp2;
+ TMPS2[16,16] = TMPS1[16,16] f* tmp2;
+ # simd resize TMPD3 = float2float(TMPS2) (lane size 2 to 4)
+ TMPD3[0,32] = float2float(TMPS2[0,16]);
+ TMPD3[32,32] = float2float(TMPS2[16,16]);
+ # simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD3 on lane size 4
+ Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD3[0,32];
+ Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD3[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.123 FMLAL, FMLAL2 (by element) page C7-2294 line 134165 MATCH x2f808000/mask=xbfc0f400
+# CONSTRUCT x6f808000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 ARG3 $f* $float2float@2:16 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal2/3@2
+# AUNIT --inst x6f808000/mask=xffc0f400 --rand sfp --status noqemu --comment "ext nofpround"
+# SIMD 4S when Q = 1
+
+:fmlal2 Rd_VPR128.4S, vRn_VPR128^".4H", Re_VPR128Lo.H.vIndexHLM
+is b_31=0 & b_30=1 & b_2329=0b1011111 & b_22=0 & b_1215=0b1000 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Re_VPR128Lo.H.vIndexHLM & Zd
+{
+ TMPD1 = Rn_VPR128[64,64];
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
+ # simd infix TMPD2 = TMPD1 f* tmp2 on lane size 2
+ TMPD2[0,16] = TMPD1[0,16] f* tmp2;
+ TMPD2[16,16] = TMPD1[16,16] f* tmp2;
+ TMPD2[32,16] = TMPD1[32,16] f* tmp2;
+ TMPD2[48,16] = TMPD1[48,16] f* tmp2;
+ # simd resize TMPQ3 = float2float(TMPD2) (lane size 2 to 4)
+ TMPQ3[0,32] = float2float(TMPD2[0,16]);
+ TMPQ3[32,32] = float2float(TMPD2[16,16]);
+ TMPQ3[64,32] = float2float(TMPD2[32,16]);
+ TMPQ3[96,32] = float2float(TMPD2[48,16]);
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.124 FMLAL, FMLAL2 (vector) page C7-2296 line 134298 MATCH x0e20ec00/mask=xbfe0fc00
+# CONSTRUCT x0e20ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[0]:4 ARG3[0]:4 $f*@2 $float2float@2:8 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal/3@2
+# AUNIT --inst x0e20ec00/mask=xffe0fc00 --rand sfp --status noqemu --comment "ext nofpround"
+# SIMD 2S when Q = 0
+
+:fmlal Rd_VPR64.2S, vRn_VPR64^".2H", vRm_VPR64^".2H"
+is b_31=0 & b_30=0 & b_2329=0b0011100 & b_22=0 & b_21=1 & b_1015=0b111011 & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & vRm_VPR64 & Rm_VPR64 & Zd
+{
+ TMPS1 = Rn_VPR64[0,32];
+ TMPS2 = Rm_VPR64[0,32];
+ # simd infix TMPS3 = TMPS1 f* TMPS2 on lane size 2
+ TMPS3[0,16] = TMPS1[0,16] f* TMPS2[0,16];
+ TMPS3[16,16] = TMPS1[16,16] f* TMPS2[16,16];
+ # simd resize TMPD4 = float2float(TMPS3) (lane size 2 to 4)
+ TMPD4[0,32] = float2float(TMPS3[0,16]);
+ TMPD4[32,32] = float2float(TMPS3[16,16]);
+ # simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD4 on lane size 4
+ Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD4[0,32];
+ Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD4[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.124 FMLAL, FMLAL2 (vector) page C7-2296 line 134298 MATCH x0e20ec00/mask=xbfe0fc00
+# CONSTRUCT x4e20ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[0]:8 ARG3[0]:8 $f*@2 $float2float@2:16 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal/3@2
+# AUNIT --inst x4e20ec00/mask=xffe0fc00 --rand sfp --status noqemu --comment "ext nofpround"
+# SIMD 4S when Q = 1
+
+:fmlal Rd_VPR128.4S, vRn_VPR128^".4H", Rm_VPR64.4H
+is b_31=0 & b_30=1 & b_2329=0b0011100 & b_22=0 & b_21=1 & b_1015=0b111011 & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Rm_VPR64.4H & Zd
+{
+ TMPD1 = Rn_VPR128[0,64];
+ TMPD2 = Rm_VPR64.4H[0,64];
+ # simd infix TMPD3 = TMPD1 f* TMPD2 on lane size 2
+ TMPD3[0,16] = TMPD1[0,16] f* TMPD2[0,16];
+ TMPD3[16,16] = TMPD1[16,16] f* TMPD2[16,16];
+ TMPD3[32,16] = TMPD1[32,16] f* TMPD2[32,16];
+ TMPD3[48,16] = TMPD1[48,16] f* TMPD2[48,16];
+ # simd resize TMPQ4 = float2float(TMPD3) (lane size 2 to 4)
+ TMPQ4[0,32] = float2float(TMPD3[0,16]);
+ TMPQ4[32,32] = float2float(TMPD3[16,16]);
+ TMPQ4[64,32] = float2float(TMPD3[32,16]);
+ TMPQ4[96,32] = float2float(TMPD3[48,16]);
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ4 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ4[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ4[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ4[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ4[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.124 FMLAL, FMLAL2 (vector) page C7-2296 line 134298 MATCH x2e20cc00/mask=xbfe0fc00
+# CONSTRUCT x2e20cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:4 ARG3[1]:4 $f*@2 $float2float@2:8 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal2/3@2
+# AUNIT --inst x2e20cc00/mask=xffe0fc00 --rand sfp --status noqemu --comment "ext nofpround"
+# SIMD 2S when Q = 0
+
+:fmlal2 Rd_VPR64.2S, vRn_VPR64^".2H", vRm_VPR128^".2H"
+is b_31=0 & b_30=0 & b_2329=0b1011100 & b_22=0 & b_21=1 & b_1015=0b110011 & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & vRm_VPR128 & Rm_VPR128 & Zd
+{
+ TMPS1 = Rn_VPR64[32,32];
+ TMPS2 = Rm_VPR128[32,32];
+ # simd infix TMPS3 = TMPS1 f* TMPS2 on lane size 2
+ TMPS3[0,16] = TMPS1[0,16] f* TMPS2[0,16];
+ TMPS3[16,16] = TMPS1[16,16] f* TMPS2[16,16];
+ # simd resize TMPD4 = float2float(TMPS3) (lane size 2 to 4)
+ TMPD4[0,32] = float2float(TMPS3[0,16]);
+ TMPD4[32,32] = float2float(TMPS3[16,16]);
+ # simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD4 on lane size 4
+ Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD4[0,32];
+ Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD4[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.124 FMLAL, FMLAL2 (vector) page C7-2296 line 134298 MATCH x2e20cc00/mask=xbfe0fc00
+# CONSTRUCT x6e20cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 ARG3 $f*@2 $float2float@2:16 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlal2/3@2
+# AUNIT --inst x6e20cc00/mask=xffe0fc00 --rand sfp --status noqemu --comment "ext nofpround"
+# SIMD 4S when Q = 1
+
+:fmlal2 Rd_VPR128.4S, vRn_VPR128^".4H", Rm_VPR64.4H
+is b_31=0 & b_30=1 & b_2329=0b1011100 & b_22=0 & b_21=1 & b_1015=0b110011 & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Rm_VPR64.4H & Zd
+{
+ TMPD1 = Rn_VPR128[64,64];
+ # simd infix TMPD2 = TMPD1 f* Rm_VPR64.4H on lane size 2
+ TMPD2[0,16] = TMPD1[0,16] f* Rm_VPR64.4H[0,16];
+ TMPD2[16,16] = TMPD1[16,16] f* Rm_VPR64.4H[16,16];
+ TMPD2[32,16] = TMPD1[32,16] f* Rm_VPR64.4H[32,16];
+ TMPD2[48,16] = TMPD1[48,16] f* Rm_VPR64.4H[48,16];
+ # simd resize TMPQ3 = float2float(TMPD2) (lane size 2 to 4)
+ TMPQ3[0,32] = float2float(TMPD2[0,16]);
+ TMPQ3[32,32] = float2float(TMPD2[16,16]);
+ TMPQ3[64,32] = float2float(TMPD2[32,16]);
+ TMPQ3[96,32] = float2float(TMPD2[48,16]);
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.125 FMLS (by element) page C7-2298 line 134425 MATCH x0f805000/mask=xbf80f400
+# CONSTRUCT x4fc05000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $f* &=$f-@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@8
+# AUNIT --inst x4fc05000/mask=xffe0f400 --rand dfp --status pass --comment "nofpround"
+
+:fmls Rd_VPR128.2D, Rn_VPR128.2D, Re_VPR128.D.vIndex
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=3 & b_2121=0 & Re_VPR128.D.vIndex & vIndex & Re_VPR128.D & b_1215=0x5 & b_1010=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ # simd element Re_VPR128.D[vIndex] lane size 8
+ local tmp1:8 = Re_VPR128.D.vIndex;
+ # simd infix TMPQ1 = Rn_VPR128.2D f* tmp1 on lane size 8
+ TMPQ1[0,64] = Rn_VPR128.2D[0,64] f* tmp1;
+ TMPQ1[64,64] = Rn_VPR128.2D[64,64] f* tmp1;
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D f- TMPQ1 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] f- TMPQ1[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] f- TMPQ1[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.125 FMLS (by element) page C7-2298 line 134425 MATCH x0f805000/mask=xbf80f400
+# CONSTRUCT x0f805000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $f* &=$f-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@4
+# AUNIT --inst x0f805000/mask=xffc0f400 --rand sfp --status pass --comment "nofpround"
+
+:fmls Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x5 & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp1:4 = Re_VPR128.S.vIndex;
+ # simd infix TMPD1 = Rn_VPR64.2S f* tmp1 on lane size 4
+ TMPD1[0,32] = Rn_VPR64.2S[0,32] f* tmp1;
+ TMPD1[32,32] = Rn_VPR64.2S[32,32] f* tmp1;
+ # simd infix Rd_VPR64.2S = Rd_VPR64.2S f- TMPD1 on lane size 4
+ Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] f- TMPD1[0,32];
+ Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] f- TMPD1[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.125 FMLS (by element) page C7-2298 line 134425 MATCH x0f805000/mask=xbf80f400
+# CONSTRUCT x4f805000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $f* &=$f-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@4
+# AUNIT --inst x4f805000/mask=xffc0f400 --rand sfp --status fail --comment "nofpround"
+
+:fmls Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x5 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp1:4 = Re_VPR128.S.vIndex;
+ # simd infix TMPQ1 = Rn_VPR128.4S f* tmp1 on lane size 4
+ TMPQ1[0,32] = Rn_VPR128.4S[0,32] f* tmp1;
+ TMPQ1[32,32] = Rn_VPR128.4S[32,32] f* tmp1;
+ TMPQ1[64,32] = Rn_VPR128.4S[64,32] f* tmp1;
+ TMPQ1[96,32] = Rn_VPR128.4S[96,32] f* tmp1;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S f- TMPQ1 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] f- TMPQ1[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] f- TMPQ1[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] f- TMPQ1[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] f- TMPQ1[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.125 FMLS (by element) page C7-2298 line 134425 MATCH x5f005000/mask=xffc0f400
+# CONSTRUCT x5f005000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 f* &=f-
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@2
+# AUNIT --inst x5f005000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround"
+# Scalar half-precision variant
+
+:fmls Rd_FPR16, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM
+is b_2231=0b0101111100 & b_1215=0b0101 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_FPR16 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Zd
+{
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp2:2 = Rn_FPR16 f* tmp1;
+ Rd_FPR16 = Rd_FPR16 f- tmp2;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.125 FMLS (by element) page C7-2298 line 134425 MATCH x5f805000/mask=xff80f400
+# CONSTRUCT x5f805000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 f* &=f-
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@4
+# AUNIT --inst x5f805000/mask=xffc0f400 --rand sfp --status pass --comment "nofpround"
+# Scalar, single-precision and double-precision variant, sz=0
+
+:fmls Rd_FPR32, Rn_FPR32, Re_VPR128.S.vIndex
+is b_2331=0b010111111 & b_22=0 & b_1215=0b0101 & b_10=0 & Re_VPR128.S & vIndex & Rd_FPR32 & Rn_FPR32 & Re_VPR128.S.vIndex & Zd
+{
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp1:4 = Re_VPR128.S.vIndex;
+ local tmp2:4 = Rn_FPR32 f* tmp1;
+ Rd_FPR32 = Rd_FPR32 f- tmp2;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.125 FMLS (by element) page C7-2298 line 134425 MATCH x5f805000/mask=xff80f400
+# CONSTRUCT x5fc05000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 f* &=f-
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@8
+# AUNIT --inst x5fc05000/mask=xffe0f400 --rand dfp --status pass --comment "nofpround"
+# Scalar, single-precision and double-precision variant, sz=1
+
+:fmls Rd_FPR64, Rn_FPR64, Re_VPR128.D.vIndex
+is b_2331=0b010111111 & b_22=1 & b_21=0 & b_1215=0b0101 & b_10=0 & Re_VPR128.D & vIndex & Rd_FPR64 & Rn_FPR64 & Re_VPR128.D.vIndex & Zd
+{
+ # simd element Re_VPR128.D[vIndex] lane size 8
+ local tmp1:8 = Re_VPR128.D.vIndex;
+ local tmp2:8 = Rn_FPR64 f* tmp1;
+ Rd_FPR64 = Rd_FPR64 f- tmp2;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.125 FMLS (by element) page C7-2298 line 134425 MATCH x0f005000/mask=xbfc0f400
+# CONSTRUCT x0f005000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $f*@2 &=$f-$@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@2
+# AUNIT --inst x0f005000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround"
+# Vector, half-precision variant SIMD 4H when Q = 0
+
+:fmls Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
+is b_31=0 & b_30=0 & b_2229=0b00111100 & b_1215=0b0101 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.4H & Rn_VPR64.4H & Re_VPR128Lo.H.vIndexHLM & Zd
+{
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
+ # simd infix TMPD1 = Rn_VPR64.4H f* tmp1 on lane size 2
+ TMPD1[0,16] = Rn_VPR64.4H[0,16] f* tmp1;
+ TMPD1[16,16] = Rn_VPR64.4H[16,16] f* tmp1;
+ TMPD1[32,16] = Rn_VPR64.4H[32,16] f* tmp1;
+ TMPD1[48,16] = Rn_VPR64.4H[48,16] f* tmp1;
+ # simd infix Rd_VPR64.4H = Rd_VPR64.4H f- TMPD1 on lane size 2
+ Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] f- TMPD1[0,16];
+ Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] f- TMPD1[16,16];
+ Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] f- TMPD1[32,16];
+ Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] f- TMPD1[48,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.125 FMLS (by element) page C7-2298 line 134425 MATCH x0f005000/mask=xbfc0f400
+# CONSTRUCT x4f005000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $f*@2 &=$f-$@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@2
+# AUNIT --inst x4f005000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround"
+# Vector, half-precision variant SIMD 8H when Q = 1
+
+:fmls Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
+is b_31=0 & b_30=1 & b_2229=0b00111100 & b_1215=0b0101 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.8H & Rn_VPR128.8H & Re_VPR128Lo.H.vIndexHLM & Zd
+{
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
+ # simd infix TMPQ1 = Rn_VPR128.8H f* tmp1 on lane size 2
+ TMPQ1[0,16] = Rn_VPR128.8H[0,16] f* tmp1;
+ TMPQ1[16,16] = Rn_VPR128.8H[16,16] f* tmp1;
+ TMPQ1[32,16] = Rn_VPR128.8H[32,16] f* tmp1;
+ TMPQ1[48,16] = Rn_VPR128.8H[48,16] f* tmp1;
+ TMPQ1[64,16] = Rn_VPR128.8H[64,16] f* tmp1;
+ TMPQ1[80,16] = Rn_VPR128.8H[80,16] f* tmp1;
+ TMPQ1[96,16] = Rn_VPR128.8H[96,16] f* tmp1;
+ TMPQ1[112,16] = Rn_VPR128.8H[112,16] f* tmp1;
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H f- TMPQ1 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] f- TMPQ1[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] f- TMPQ1[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] f- TMPQ1[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] f- TMPQ1[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] f- TMPQ1[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] f- TMPQ1[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] f- TMPQ1[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] f- TMPQ1[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.126 FMLS (vector) page C7-2302 line 134665 MATCH x0ea0cc00/mask=xbfa0fc00
+# CONSTRUCT x4ee0cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG1 $f*@8 &=$f-@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@8
+# AUNIT --inst x4ee0cc00/mask=xffe0fc00 --rand dfp --status fail --comment "nofpround"
+
+:fmls Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x19 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.2D f* Rd_VPR128.2D on lane size 8
+ TMPQ1[0,64] = Rn_VPR128.2D[0,64] f* Rd_VPR128.2D[0,64];
+ TMPQ1[64,64] = Rn_VPR128.2D[64,64] f* Rd_VPR128.2D[64,64];
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D f- TMPQ1 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] f- TMPQ1[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] f- TMPQ1[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.126 FMLS (vector) page C7-2302 line 134665 MATCH x0ea0cc00/mask=xbfa0fc00
+# CONSTRUCT x0ea0cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $f*@4 &=f-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@4
+# AUNIT --inst x0ea0cc00/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround"
+
+:fmls Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x19 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ # simd infix TMPD1 = Rn_VPR64.2S f* Rm_VPR64.2S on lane size 4
+ TMPD1[0,32] = Rn_VPR64.2S[0,32] f* Rm_VPR64.2S[0,32];
+ TMPD1[32,32] = Rn_VPR64.2S[32,32] f* Rm_VPR64.2S[32,32];
+ Rd_VPR64.2S = Rd_VPR64.2S f- TMPD1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.126 FMLS (vector) page C7-2302 line 134665 MATCH x0ea0cc00/mask=xbfa0fc00
+# CONSTRUCT x4ea0cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@4
+# AUNIT --inst x4ea0cc00/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround"
+
+:fmls Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x19 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.4S f* Rm_VPR128.4S on lane size 4
+ TMPQ1[0,32] = Rn_VPR128.4S[0,32] f* Rm_VPR128.4S[0,32];
+ TMPQ1[32,32] = Rn_VPR128.4S[32,32] f* Rm_VPR128.4S[32,32];
+ TMPQ1[64,32] = Rn_VPR128.4S[64,32] f* Rm_VPR128.4S[64,32];
+ TMPQ1[96,32] = Rn_VPR128.4S[96,32] f* Rm_VPR128.4S[96,32];
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S f- TMPQ1 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] f- TMPQ1[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] f- TMPQ1[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] f- TMPQ1[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] f- TMPQ1[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.126 FMLS (vector) page C7-2302 line 134665 MATCH x0ec00c00/mask=xbfe0fc00
+# CONSTRUCT x0ec00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@2
+# AUNIT --inst x0ec00c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 4H when Q = 0
+
+:fmls Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2129=0b001110110 & b_1015=0b000011 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ # simd infix TMPD1 = Rn_VPR64.4H f* Rm_VPR64.4H on lane size 4
+ TMPD1[0,32] = Rn_VPR64.4H[0,32] f* Rm_VPR64.4H[0,32];
+ TMPD1[32,32] = Rn_VPR64.4H[32,32] f* Rm_VPR64.4H[32,32];
+ # simd infix Rd_VPR64.4H = Rd_VPR64.4H f- TMPD1 on lane size 4
+ Rd_VPR64.4H[0,32] = Rd_VPR64.4H[0,32] f- TMPD1[0,32];
+ Rd_VPR64.4H[32,32] = Rd_VPR64.4H[32,32] f- TMPD1[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.126 FMLS (vector) page C7-2302 line 134665 MATCH x0ec00c00/mask=xbfe0fc00
+# CONSTRUCT x4ec00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $f*@4 &=$f-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmls/3@2
+# AUNIT --inst x4ec00c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 8H when Q = 1
+
+:fmls Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2129=0b001110110 & b_1015=0b000011 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.8H f* Rm_VPR128.8H on lane size 4
+ TMPQ1[0,32] = Rn_VPR128.8H[0,32] f* Rm_VPR128.8H[0,32];
+ TMPQ1[32,32] = Rn_VPR128.8H[32,32] f* Rm_VPR128.8H[32,32];
+ TMPQ1[64,32] = Rn_VPR128.8H[64,32] f* Rm_VPR128.8H[64,32];
+ TMPQ1[96,32] = Rn_VPR128.8H[96,32] f* Rm_VPR128.8H[96,32];
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H f- TMPQ1 on lane size 4
+ Rd_VPR128.8H[0,32] = Rd_VPR128.8H[0,32] f- TMPQ1[0,32];
+ Rd_VPR128.8H[32,32] = Rd_VPR128.8H[32,32] f- TMPQ1[32,32];
+ Rd_VPR128.8H[64,32] = Rd_VPR128.8H[64,32] f- TMPQ1[64,32];
+ Rd_VPR128.8H[96,32] = Rd_VPR128.8H[96,32] f- TMPQ1[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.127 FMLSL, FMLSL2 (by element) page C7-2304 line 134788 MATCH x0f804000/mask=xbfc0f400
+# CONSTRUCT x0f804000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[0]:4 ARG3 $f* $float2float@2:8 &=$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl/3@2
+# AUNIT --inst x0f804000/mask=xffc0f400 --rand sfp --status noqemu --comment "ext nofpround"
+# SIMD 2S when Q = 0
+
+:fmlsl Rd_VPR64.2S, vRn_VPR64^".2H", Re_VPR128Lo.H.vIndexHLM
+is b_31=0 & b_30=0 & b_2329=0b0011111 & b_22=0 & b_1215=0b0100 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & Re_VPR128Lo.H.vIndexHLM & Zd
+{
+ TMPS1 = Rn_VPR64[0,32];
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
+ # simd infix TMPS2 = TMPS1 f* tmp2 on lane size 2
+ TMPS2[0,16] = TMPS1[0,16] f* tmp2;
+ TMPS2[16,16] = TMPS1[16,16] f* tmp2;
+ # simd resize TMPD3 = float2float(TMPS2) (lane size 2 to 4)
+ TMPD3[0,32] = float2float(TMPS2[0,16]);
+ TMPD3[32,32] = float2float(TMPS2[16,16]);
+ # simd infix Rd_VPR64.2S = Rd_VPR64.2S - TMPD3 on lane size 4
+ Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] - TMPD3[0,32];
+ Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] - TMPD3[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.127 FMLSL, FMLSL2 (by element) page C7-2304 line 134788 MATCH x0f804000/mask=xbfc0f400
+# CONSTRUCT x4f804000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[0]:8 ARG3 $f* $float2float@2:16 &=$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl/3@2
+# AUNIT --inst x4f804000/mask=xffc0f400 --rand sfp --status noqemu --comment "ext nofpround"
+# SIMD 4S when Q = 1
+
+:fmlsl Rd_VPR128.4S, vRn_VPR128^".4H", Re_VPR128Lo.H.vIndexHLM
+is b_31=0 & b_30=1 & b_2329=0b0011111 & b_22=0 & b_1215=0b0100 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Re_VPR128Lo.H.vIndexHLM & Zd
+{
+ TMPD1 = Rn_VPR128[0,64];
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
+ # simd infix TMPD2 = TMPD1 f* tmp2 on lane size 2
+ TMPD2[0,16] = TMPD1[0,16] f* tmp2;
+ TMPD2[16,16] = TMPD1[16,16] f* tmp2;
+ TMPD2[32,16] = TMPD1[32,16] f* tmp2;
+ TMPD2[48,16] = TMPD1[48,16] f* tmp2;
+ # simd resize TMPQ3 = float2float(TMPD2) (lane size 2 to 4)
+ TMPQ3[0,32] = float2float(TMPD2[0,16]);
+ TMPQ3[32,32] = float2float(TMPD2[16,16]);
+ TMPQ3[64,32] = float2float(TMPD2[32,16]);
+ TMPQ3[96,32] = float2float(TMPD2[48,16]);
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.127 FMLSL, FMLSL2 (by element) page C7-2304 line 134788 MATCH x2f80c000/mask=xbfc0f400
+# CONSTRUCT x2f80c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:4 ARG3 $f* $float2float@2:8 &=$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl2/3@2
+# AUNIT --inst x2f80c000/mask=xffc0f400 --rand sfp --status noqemu --comment "ext nofpround"
+# SIMD 2S when Q = 0
+
+:fmlsl2 Rd_VPR64.2S, vRn_VPR64^".2H", Re_VPR128Lo.H.vIndexHLM
+is b_31=0 & b_30=0 & b_2329=0b1011111 & b_22=0 & b_1215=0b1100 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & Re_VPR128Lo.H.vIndexHLM & Zd
+{
+ TMPS1 = Rn_VPR64[32,32];
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
+ # simd infix TMPS2 = TMPS1 f* tmp2 on lane size 2
+ TMPS2[0,16] = TMPS1[0,16] f* tmp2;
+ TMPS2[16,16] = TMPS1[16,16] f* tmp2;
+ # simd resize TMPD3 = float2float(TMPS2) (lane size 2 to 4)
+ TMPD3[0,32] = float2float(TMPS2[0,16]);
+ TMPD3[32,32] = float2float(TMPS2[16,16]);
+ # simd infix Rd_VPR64.2S = Rd_VPR64.2S - TMPD3 on lane size 4
+ Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] - TMPD3[0,32];
+ Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] - TMPD3[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.127 FMLSL, FMLSL2 (by element) page C7-2304 line 134788 MATCH x2f80c000/mask=xbfc0f400
+# CONSTRUCT x6f80c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 ARG3 $f* $float2float@2:16 &=$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl2/3@2
+# AUNIT --inst x6f80c000/mask=xffc0f400 --rand sfp --status noqemu --comment "ext nofpround"
+# SIMD 4S when Q = 1
+
+:fmlsl2 Rd_VPR128.4S, vRn_VPR128^".4H", Re_VPR128Lo.H.vIndexHLM
+is b_31=0 & b_30=1 & b_2329=0b1011111 & b_22=0 & b_1215=0b1100 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Re_VPR128Lo.H.vIndexHLM & Zd
+{
+ TMPD1 = Rn_VPR128[64,64];
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
+ # simd infix TMPD2 = TMPD1 f* tmp2 on lane size 2
+ TMPD2[0,16] = TMPD1[0,16] f* tmp2;
+ TMPD2[16,16] = TMPD1[16,16] f* tmp2;
+ TMPD2[32,16] = TMPD1[32,16] f* tmp2;
+ TMPD2[48,16] = TMPD1[48,16] f* tmp2;
+ # simd resize TMPQ3 = float2float(TMPD2) (lane size 2 to 4)
+ TMPQ3[0,32] = float2float(TMPD2[0,16]);
+ TMPQ3[32,32] = float2float(TMPD2[16,16]);
+ TMPQ3[64,32] = float2float(TMPD2[32,16]);
+ TMPQ3[96,32] = float2float(TMPD2[48,16]);
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.128 FMLSL, FMLSL2 (vector) page C7-2306 line 134921 MATCH x0ea0ec00/mask=xbfe0fc00
+# CONSTRUCT x0ea0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[0]:4 ARG3[0]:4 $f*@2 $float2float@2:8 &=$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl/3@2
+# AUNIT --inst x0ea0ec00/mask=xffe0fc00 --rand sfp --status noqemu --comment "ext nofpround"
+# SIMD 2S when Q = 0
+
+:fmlsl Rd_VPR64.2S, vRn_VPR64^".2H", vRm_VPR64^".2H"
+is b_31=0 & b_30=0 & b_2329=0b0011101 & b_22=0 & b_21=1 & b_1015=0b111011 & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & vRm_VPR64 & Rm_VPR64 & Zd
+{
+ TMPS1 = Rn_VPR64[0,32];
+ TMPS2 = Rm_VPR64[0,32];
+ # simd infix TMPS3 = TMPS1 f* TMPS2 on lane size 2
+ TMPS3[0,16] = TMPS1[0,16] f* TMPS2[0,16];
+ TMPS3[16,16] = TMPS1[16,16] f* TMPS2[16,16];
+ # simd resize TMPD4 = float2float(TMPS3) (lane size 2 to 4)
+ TMPD4[0,32] = float2float(TMPS3[0,16]);
+ TMPD4[32,32] = float2float(TMPS3[16,16]);
+ # simd infix Rd_VPR64.2S = Rd_VPR64.2S - TMPD4 on lane size 4
+ Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] - TMPD4[0,32];
+ Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] - TMPD4[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.128 FMLSL, FMLSL2 (vector) page C7-2306 line 134921 MATCH x0ea0ec00/mask=xbfe0fc00
+# CONSTRUCT x4ea0ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[0]:8 ARG3[0]:8 $f*@2 $float2float@2:16 &=$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl/3@2
+# AUNIT --inst x4ea0ec00/mask=xffe0fc00 --rand sfp --status noqemu --comment "ext nofpround"
+# SIMD 4S when Q = 1
+
+:fmlsl Rd_VPR128.4S, vRn_VPR128^".4H", Rm_VPR64.4H
+is b_31=0 & b_30=1 & b_2329=0b0011101 & b_22=0 & b_21=1 & b_1015=0b111011 & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Rm_VPR64.4H & Zd
+{
+ TMPD1 = Rn_VPR128[0,64];
+ TMPD2 = Rm_VPR64.4H[0,64];
+ # simd infix TMPD3 = TMPD1 f* TMPD2 on lane size 2
+ TMPD3[0,16] = TMPD1[0,16] f* TMPD2[0,16];
+ TMPD3[16,16] = TMPD1[16,16] f* TMPD2[16,16];
+ TMPD3[32,16] = TMPD1[32,16] f* TMPD2[32,16];
+ TMPD3[48,16] = TMPD1[48,16] f* TMPD2[48,16];
+ # simd resize TMPQ4 = float2float(TMPD3) (lane size 2 to 4)
+ TMPQ4[0,32] = float2float(TMPD3[0,16]);
+ TMPQ4[32,32] = float2float(TMPD3[16,16]);
+ TMPQ4[64,32] = float2float(TMPD3[32,16]);
+ TMPQ4[96,32] = float2float(TMPD3[48,16]);
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ4 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ4[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ4[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ4[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ4[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.128 FMLSL, FMLSL2 (vector) page C7-2306 line 134921 MATCH x2ea0cc00/mask=xbfe0fc00
+# CONSTRUCT x2ea0cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:4 ARG3[1]:4 $f*@2 $float2float@2:8 &=$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl2/3@2
+# AUNIT --inst x2ea0cc00/mask=xffe0fc00 --rand sfp --status noqemu --comment "ext nofpround"
+# SIMD 2S when Q = 0
+
+:fmlsl2 Rd_VPR64.2S, vRn_VPR64^".2H", vRm_VPR128^".2H"
+is b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=0 & b_21=1 & b_1015=0b110011 & Rd_VPR64.2S & vRn_VPR64 & Rn_VPR64 & vRm_VPR128 & Rm_VPR128 & Zd
+{
+ TMPS1 = Rn_VPR64[32,32];
+ TMPS2 = Rm_VPR128[32,32];
+ # simd infix TMPS3 = TMPS1 f* TMPS2 on lane size 2
+ TMPS3[0,16] = TMPS1[0,16] f* TMPS2[0,16];
+ TMPS3[16,16] = TMPS1[16,16] f* TMPS2[16,16];
+ # simd resize TMPD4 = float2float(TMPS3) (lane size 2 to 4)
+ TMPD4[0,32] = float2float(TMPS3[0,16]);
+ TMPD4[32,32] = float2float(TMPS3[16,16]);
+ # simd infix Rd_VPR64.2S = Rd_VPR64.2S - TMPD4 on lane size 4
+ Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] - TMPD4[0,32];
+ Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] - TMPD4[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.128 FMLSL, FMLSL2 (vector) page C7-2306 line 134921 MATCH x2ea0cc00/mask=xbfe0fc00
+# CONSTRUCT x6ea0cc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 ARG3 $f*@2 $float2float@2:16 &=$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_fmlsl2/3@2
+# AUNIT --inst x6ea0cc00/mask=xffe0fc00 --rand sfp --status noqemu --comment "ext nofpround"
+# SIMD 4S when Q = 1
+
+:fmlsl2 Rd_VPR128.4S, vRn_VPR128^".4H", Rm_VPR64.4H
+is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=0 & b_21=1 & b_1015=0b110011 & Rd_VPR128.4S & vRn_VPR128 & Rn_VPR128 & Rm_VPR64.4H & Zd
+{
+ TMPD1 = Rn_VPR128[64,64];
+ # simd infix TMPD2 = TMPD1 f* Rm_VPR64.4H on lane size 2
+ TMPD2[0,16] = TMPD1[0,16] f* Rm_VPR64.4H[0,16];
+ TMPD2[16,16] = TMPD1[16,16] f* Rm_VPR64.4H[16,16];
+ TMPD2[32,16] = TMPD1[32,16] f* Rm_VPR64.4H[32,16];
+ TMPD2[48,16] = TMPD1[48,16] f* Rm_VPR64.4H[48,16];
+ # simd resize TMPQ3 = float2float(TMPD2) (lane size 2 to 4)
+ TMPQ3[0,32] = float2float(TMPD2[0,16]);
+ TMPQ3[32,32] = float2float(TMPD2[16,16]);
+ TMPQ3[64,32] = float2float(TMPD2[32,16]);
+ TMPQ3[96,32] = float2float(TMPD2[48,16]);
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.129 FMOV (vector, immediate) page C7-2308 line 135048 MATCH x0f00f400/mask=x9ff8fc00
+# C7.2.20 BIC (vector, immediate) page C7-2048 line 119572 MATCH x2f001400/mask=xbff81c00
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00
+# CONSTRUCT x6f00f400/mask=xfff8fc00 MATCHED 4 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1@8
+# AUNIT --inst x6f00f400/mask=xfff8fc00 --rand dfp --status nopcodeop
+
+:fmov Rd_VPR128.2D, Imm_neon_uimm8Shift
+is b_3131=0 & q=1 & b_29=1 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & cmode=0xf & b_1011=1 & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_fmov(Imm_neon_uimm8Shift, 8:1);
+}
+
+# C7.2.129 FMOV (vector, immediate) page C7-2308 line 135048 MATCH x0f00f400/mask=x9ff8fc00
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.212 ORR (vector, immediate) page C7-2507 line 146708 MATCH x0f001400/mask=xbff81c00
+# CONSTRUCT x0f00f400/mask=xfff8fc00 MATCHED 3 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2:4 =NEON_fmov/1@4
+# AUNIT --inst x0f00f400/mask=xfff8fc00 --rand dfp --status nopcodeop
+
+:fmov Rd_VPR64.2S, Imm_neon_uimm8Shift
+is b_3131=0 & q=0 & b_29=0 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & cmode=0xf & b_1011=1 & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_fmov(Imm_neon_uimm8Shift:4, 4:1);
+}
+
+# C7.2.129 FMOV (vector, immediate) page C7-2308 line 135048 MATCH x0f00f400/mask=x9ff8fc00
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.212 ORR (vector, immediate) page C7-2507 line 146708 MATCH x0f001400/mask=xbff81c00
+# CONSTRUCT x4f00f400/mask=xfff8fc00 MATCHED 3 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2:4 =NEON_fmov/1@4
+# AUNIT --inst x4f00f400/mask=xfff8fc00 --rand sfp --status nopcodeop
+
+:fmov Rd_VPR128.4S, Imm_neon_uimm8Shift
+is b_3131=0 & q=1 & b_29=0 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & cmode=0xf & b_1011=1 & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_fmov(Imm_neon_uimm8Shift:4, 4:1);
+}
+
+# C7.2.129 FMOV (vector, immediate) page C7-2308 line 135048 MATCH x0f00fc00/mask=xbff8fc00
+# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x0f00fc00/mask=xbf80fc00
+# CONSTRUCT x0f00fc00/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 int2float:2 &=$dup
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1@2
+# AUNIT --inst x0f00fc00/mask=xfff8fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 4H when Q = 0
+
+:fmov Rd_VPR64.4H, Imm_neon_uimm8Shift
+is b_31=0 & b_30=0 & b_1929=0b00111100000 & b_1015=0b111111 & Rd_VPR64.4H & Imm_neon_uimm8Shift & Zd
+{
+ local tmp1:2 = int2float(Imm_neon_uimm8Shift);
+ # simd duplicate Rd_VPR64.4H = all elements tmp1 (lane size 2)
+ Rd_VPR64.4H[0,16] = tmp1;
+ Rd_VPR64.4H[16,16] = tmp1;
+ Rd_VPR64.4H[32,16] = tmp1;
+ Rd_VPR64.4H[48,16] = tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.129 FMOV (vector, immediate) page C7-2308 line 135048 MATCH x0f00fc00/mask=xbff8fc00
+# C7.2.89 FCVTZS (vector, fixed-point) page C7-2221 line 129809 MATCH x0f00fc00/mask=xbf80fc00
+# CONSTRUCT x4f00fc00/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 int2float:2 &=$dup
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1@2
+# AUNIT --inst x4f00fc00/mask=xfff8fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant SIMD 8H when Q = 1
+
+:fmov Rd_VPR128.8H, Imm_neon_uimm8Shift
+is b_31=0 & b_30=1 & b_1929=0b00111100000 & b_1015=0b111111 & Rd_VPR128.8H & Imm_neon_uimm8Shift & Zd
+{
+ local tmp1:2 = int2float(Imm_neon_uimm8Shift);
+ # simd duplicate Rd_VPR128.8H = all elements tmp1 (lane size 2)
+ Rd_VPR128.8H[0,16] = tmp1;
+ Rd_VPR128.8H[16,16] = tmp1;
+ Rd_VPR128.8H[32,16] = tmp1;
+ Rd_VPR128.8H[48,16] = tmp1;
+ Rd_VPR128.8H[64,16] = tmp1;
+ Rd_VPR128.8H[80,16] = tmp1;
+ Rd_VPR128.8H[96,16] = tmp1;
+ Rd_VPR128.8H[112,16] = tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.130 FMOV (register) page C7-2310 line 135162 MATCH x1e204000/mask=xff3ffc00
+# CONSTRUCT x1ee04000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
+# AUNIT --inst x1ee04000/mask=xfffffc00 --rand hfp --status noqemu
+# Half-precision variant when type == 11 arg1=Rd_FPR16 arg2=Rn_FPR16
+
+:fmov Rd_FPR16, Rn_FPR16
+is b_2431=0b00011110 & b_2223=0b11 & b_1021=0b100000010000 & Rd_FPR16 & Rn_FPR16 & Rd_FPR64 & Zd
+{
+ Rd_FPR16 = Rn_FPR16;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.130 FMOV (register) page C7-2310 line 135162 MATCH x1e204000/mask=xff3ffc00
+# CONSTRUCT x1e204000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
+# AUNIT --inst x1e204000/mask=xfffffc00 --rand sfp --status pass
+# Single-precision variant when type == 00 arg1=Rd_FPR32 arg2=Rn_FPR32
+
+:fmov Rd_FPR32, Rn_FPR32
+is b_2431=0b00011110 & b_2223=0b00 & b_1021=0b100000010000 & Rd_FPR32 & Rn_FPR32 & Zd
+{
+ Rd_FPR32 = Rn_FPR32;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.130 FMOV (register) page C7-2310 line 135162 MATCH x1e204000/mask=xff3ffc00
+# CONSTRUCT x1e604000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
+# AUNIT --inst x1e604000/mask=xfffffc00 --rand dfp --status pass
+# Double-precision variant when type == 01 arg1=Rd_FPR64 arg2=Rn_FPR64
+
+:fmov Rd_FPR64, Rn_FPR64
+is b_2431=0b00011110 & b_2223=0b01 & b_1021=0b100000010000 & Rd_FPR64 & Rn_FPR64 & Zd
+{
+ Rd_FPR64 = Rn_FPR64;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00
+# CONSTRUCT x1e660000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =float2float
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
+# AUNIT --inst x1e660000/mask=xfffffc00 --rand dfp --status noqemu --comment "nofpround"
+# UNDOCUMENTED Double-precision to 32-bit variant when sf == 0 && type == 01 && rmode == 00 && opcode = 110 arg1=Rd_GPR32 arg2=Rn_FPR64
+
+:fmov Rd_GPR32, Rn_FPR64
+is b_31=0 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1920=0b00 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR32 & Rn_FPR64 & Rd_GPR64
+{
+ Rd_GPR32 = float2float(Rn_FPR64);
+ zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
+}
+
+# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00
+# CONSTRUCT x9e260000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =float2float
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
+# AUNIT --inst x9e260000/mask=xfffffc00 --rand sfp --status noqemu --comment "nofpround"
+# UNDOCUMENTED Single-precision to 64-bit variant when sf == 1 && type == 00 && rmode == 00 && opcode = 110 arg1=Rd_GPR64 arg2=Rn_FPR32
+
+:fmov Rd_GPR64, Rn_FPR32
+is b_31=1 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1920=0b00 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR64 & Rn_FPR32
+{
+ Rd_GPR64 = float2float(Rn_FPR32);
+}
+
+# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00
+# CONSTRUCT x1e670000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =float2float
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
+# AUNIT --inst x1e670000/mask=xfffffc00 --rand dfp --status noqemu --comment "nofpround"
+# UNDOCUMENTED 32-bit to Double-precision variant when sf == 0 && type == 01 && rmode == 00 && opcode = 111 arg1=Rd_FPR64 arg2=Rn_GPR32
+
+:fmov Rd_FPR64, Rn_GPR32
+is b_31=0 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1920=0b00 & b_1618=0b111 & b_1015=0b000000 & Rd_FPR64 & Rn_GPR32 & Zd
+{
+ Rd_FPR64 = float2float(Rn_GPR32);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00
+# CONSTRUCT x9e270000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =float2float
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
+# AUNIT --inst x9e270000/mask=xfffffc00 --rand sfp --status noqemu --comment "nofpround"
+# UNDOCUMENTED 64-bit to single-precision variant when sf == 1 && type == 00 && rmode == 00 && opcode = 111 arg1=Rd_FPR32 arg2=Rn_GPR64
+
+:fmov Rd_FPR32, Rn_GPR64
+is b_31=1 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1920=0b00 & b_1618=0b111 & b_1015=0b000000 & Rd_FPR32 & Rn_GPR64 & Zd
+{
+ Rd_FPR32 = float2float(Rn_GPR64);
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00
+# CONSTRUCT x1ee60000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =float2float
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
+# AUNIT --inst x1ee60000/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision to 32-bit variant when sf == 0 && type == 11 && rmode == 00 && opcode == 110 arg1=Rd_GPR32 arg2=Rn_FPR16
+
+:fmov Rd_GPR32, Rn_FPR16
+is b_31=0 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1920=0b00 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR32 & Rn_FPR16 & Rd_GPR64
+{
+ Rd_GPR32 = float2float(Rn_FPR16);
+ zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
+}
+
+# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00
+# CONSTRUCT x9ee60000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =float2float
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
+# AUNIT --inst x9ee60000/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision to 64-bit variant when sf == 1 && type == 11 && rmode == 00 && opcode == 110 arg1=Rd_GPR64 arg2=Rn_FPR16
+
+:fmov Rd_GPR64, Rn_FPR16
+is b_31=1 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1920=0b00 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR64 & Rn_FPR16
+{
+ Rd_GPR64 = float2float(Rn_FPR16);
+}
+
+# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00
+# CONSTRUCT x1ee70000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =float2float
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
+# AUNIT --inst x1ee70000/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# 32-bit to half-precision variant when sf == 0 && type == 11 && rmode == 00 && opcode == 111 arg1=Rd_FPR16 arg2=Rn_GPR32
+
+:fmov Rd_FPR16, Rn_GPR32
+is b_31=0 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1920=0b00 & b_1618=0b111 & b_1015=0b000000 & Rd_FPR16 & Rn_GPR32 & Zd
+{
+ Rd_FPR16 = float2float(Rn_GPR32);
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00
+# CONSTRUCT x1e270000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
+# AUNIT --inst x1e270000/mask=xfffffc00 --rand sfp --status pass --comment "nofpround"
+# 32-bit to single-precision variant when sf == 0 && type == 00 && rmode == 00 && opcode == 111 arg1=Rd_FPR32 arg2=Rn_GPR32
+
+:fmov Rd_FPR32, Rn_GPR32
+is b_31=0 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1920=0b00 & b_1618=0b111 & b_1015=0b000000 & Rd_FPR32 & Rn_GPR32 & Zd
+{
+ Rd_FPR32 = Rn_GPR32;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00
+# CONSTRUCT x1e260000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
+# AUNIT --inst x1e260000/mask=xfffffc00 --rand sfp --status pass --comment "nofpround"
+# Single-precision to 32-bit variant when sf == 0 && type == 00 && rmode == 00 && opcode == 110 arg1=Rd_GPR32 arg2=Rn_FPR32
+
+:fmov Rd_GPR32, Rn_FPR32
+is b_31=0 & b_2430=0b0011110 & b_2223=0b00 & b_21=1 & b_1920=0b00 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR32 & Rn_FPR32 & Rd_GPR64
+{
+ Rd_GPR32 = Rn_FPR32;
+ zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
+}
+
+# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00
+# CONSTRUCT x9ee70000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =float2float
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
+# AUNIT --inst x9ee70000/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# 64-bit to half-precision variant when sf == 1 && type == 11 && rmode == 00 && opcode == 111 arg1=Rd_FPR16 arg2=Rn_GPR64
+
+:fmov Rd_FPR16, Rn_GPR64
+is b_31=1 & b_2430=0b0011110 & b_2223=0b11 & b_21=1 & b_1920=0b00 & b_1618=0b111 & b_1015=0b000000 & Rd_FPR16 & Rn_GPR64 & Zd
+{
+ Rd_FPR16 = float2float(Rn_GPR64);
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00
+# CONSTRUCT x9e670000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
+# AUNIT --inst x9e670000/mask=xfffffc00 --rand dfp --status pass --comment "nofpround"
+# 64-bit to double-precision variant when sf == 1 && type == 01 && rmode == 00 && opcode == 111 arg1=Rd_FPR64 arg2=Rn_GPR64
+
+:fmov Rd_FPR64, Rn_GPR64
+is b_31=1 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1920=0b00 & b_1618=0b111 & b_1015=0b000000 & Rd_FPR64 & Rn_GPR64 & Zd
+{
+ Rd_FPR64 = Rn_GPR64;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00
+# CONSTRUCT x9eaf0000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 1:1 &=$copy@8
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_fmov/2
+# AUNIT --inst x9eaf0000/mask=xfffffc00 --rand dfp --status pass --comment "nofpround"
+# 64-bit to top half of 128-bit variant when sf == 1 && type == 10 && rmode == 01 && opcode == 111 arg1=vRd_VPR128^".D[1]" arg2=Rn_GPR64
+
+:fmov vRd_VPR128^".D[1]", Rn_GPR64
+is b_31=1 & b_2430=0b0011110 & b_2223=0b10 & b_21=1 & b_1920=0b01 & b_1618=0b111 & b_1015=0b000000 & vRd_VPR128 & Rd_VPR128 & Rn_GPR64 & Zd
+{
+ # simd copy Rd_VPR128 element 1:1 = Rn_GPR64 (lane size 8)
+ Rd_VPR128[64,64] = Rn_GPR64;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00
+# CONSTRUCT x9e660000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
+# AUNIT --inst x9e660000/mask=xfffffc00 --rand dfp --status pass --comment "nofpround"
+# Double-precision to 64-bit variant when sf == 1 && type == 01 && rmode == 00 && opcode == 110 arg1=Rd_GPR64 arg2=Rn_FPR64
+
+:fmov Rd_GPR64, Rn_FPR64
+is b_31=1 & b_2430=0b0011110 & b_2223=0b01 & b_21=1 & b_1920=0b00 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR64 & Rn_FPR64
+{
+ Rd_GPR64 = Rn_FPR64;
+}
+
+# C7.2.131 FMOV (general) page C7-2312 line 135254 MATCH x1e260000/mask=x7f36fc00
+# CONSTRUCT x9eae0000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 =ARG2[1]:8
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1@8
+# AUNIT --inst x9eae0000/mask=xfffffc00 --rand dfp --status pass --comment "nofpround"
+# Top half of 128-bit to 64-bit variant when sf == 1 && type == 10 && rmode == 01 && opcode == 110 arg1=Rd_GPR64 arg2=vRd_VPR128^".D[1]"
+
+:fmov Rd_GPR64, vRn_VPR128^".D[1]"
+is b_31=1 & b_2430=0b0011110 & b_2223=0b10 & b_21=1 & b_1920=0b01 & b_1618=0b110 & b_1015=0b000000 & Rd_GPR64 & vRn_VPR128 & Rn_VPR128
+{
+ Rd_GPR64 = Rn_VPR128[64,64];
+}
+
+# C7.2.132 FMOV (scalar, immediate) page C7-2316 line 135493 MATCH x1e201000/mask=xff201fe0
+# CONSTRUCT x1e601001/mask=xffe01fe1 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
+# AUNIT --inst x1e601001/mask=xffe01fe1 --rand dfp --status pass
+
+:fmov Rd_FPR64, Imm8_fmov64_operand
+is ImmS_ImmR_TestSet=1 & m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Imm8_fmov64_operand & b_1012=4 & imm5=0x0 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = Imm8_fmov64_operand:8;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.132 FMOV (scalar, immediate) page C7-2316 line 135493 MATCH x1e201000/mask=xff201fe0
+# CONSTRUCT x1e201000/mask=xffe01fe0 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
+# AUNIT --inst x1e201000/mask=xffe01fe0 --rand sfp --status pass
+
+:fmov Rd_FPR32, Imm8_fmov32_operand
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Imm8_fmov32_operand & b_1012=4 & imm5=0x0 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = Imm8_fmov32_operand:4;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.132 FMOV (scalar, immediate) page C7-2316 line 135493 MATCH x1e201000/mask=xff201fe0
+# CONSTRUCT x1ee01000/mask=xffe01fe0 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fmov/1
+# AUNIT --inst x1ee01000/mask=xffe01fe0 --rand hfp --status noqemu
+
+:fmov Rd_FPR16, Imm8_fmov16_operand
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Imm8_fmov16_operand & b_1012=4 & imm5=0x0 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = Imm8_fmov16_operand:2;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.133 FMSUB page C7-2318 line 135582 MATCH x1f008000/mask=xff208000
+# CONSTRUCT x1f408000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fmsub/3
+# AUNIT --inst x1f408000/mask=xffe08000 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fmsub Rd_FPR64, Rn_FPR64, Rm_FPR64, Ra_FPR64
+is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=1 & b_21=0 & Rm_FPR64 & b_15=1 & Ra_FPR64 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_fmsub(Rn_FPR64, Rm_FPR64, Ra_FPR64);
+}
+
+# C7.2.133 FMSUB page C7-2318 line 135582 MATCH x1f008000/mask=xff208000
+# CONSTRUCT x1f008000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fmsub/3
+# AUNIT --inst x1f008000/mask=xffe08000 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fmsub Rd_FPR32, Rn_FPR32, Rm_FPR32, Ra_FPR32
+is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=0 & b_21=0 & Rm_FPR32 & b_15=1 & Ra_FPR32 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_fmsub(Rn_FPR32, Rm_FPR32, Ra_FPR32);
+}
+
+# C7.2.133 FMSUB page C7-2318 line 135582 MATCH x1f008000/mask=xff208000
+# CONSTRUCT x1fc08000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fmsub/3
+# AUNIT --inst x1fc08000/mask=xffe08000 --rand hfp --status noqemu --comment "nofpround"
+
+:fmsub Rd_FPR16, Rn_FPR16, Rm_FPR16, Ra_FPR16
+is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=3 & b_21=0 & Rm_FPR16 & b_15=1 & Ra_FPR16 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_fmsub(Rn_FPR16, Rm_FPR16, Ra_FPR16);
+}
+
+# C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x5f009000/mask=xffc0f400
+# CONSTRUCT x5f009000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =f*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@2
+# AUNIT --inst x5f009000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround"
+# FMUL (by element) Scalar, half-precision
+
+:fmul Rd_FPR16, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM
+is b_2231=0b0101111100 & b_1215=0b1001 & b_10=0 & Rd_FPR16 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd
+{
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
+ Rd_FPR16 = Rn_FPR16 f* tmp1;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x5f809000/mask=xff80f400
+# CONSTRUCT x5f809000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =f*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@4
+# AUNIT --inst x5f809000/mask=xffc0f400 --rand sfp --status pass --comment "nofpround"
+# FMUL (by element) Scalar, single-precision and double-precision sz=0
+
+:fmul Rd_FPR32, Rn_FPR32, Re_VPR128.S.vIndex
+is b_2331=0b010111111 & b_22=0 & b_1215=0b1001 & b_10=0 & Re_VPR128.S & vIndex & Rd_FPR32 & Rn_FPR32 & Re_VPR128.S.vIndex & Zd
+{
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp1:4 = Re_VPR128.S.vIndex;
+ Rd_FPR32 = Rn_FPR32 f* tmp1;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x5f809000/mask=xff80f400
+# CONSTRUCT x5fc09000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =f*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@8
+# AUNIT --inst x5fc09000/mask=xffe0f400 --rand dfp --status pass --comment "nofpround"
+# FMUL (by element) Scalar, single-precision and double-precision sz=1
+
+:fmul Rd_FPR64, Rn_FPR64, Re_VPR128.D.vIndex
+is b_2331=0b010111111 & b_22=1 & b_21=0 & b_1215=0b1001 & b_10=0 & Re_VPR128.D & vIndex & Rd_FPR64 & Rn_FPR64 & Re_VPR128.D.vIndex & Zd
+{
+ # simd element Re_VPR128.D[vIndex] lane size 8
+ local tmp1:8 = Re_VPR128.D.vIndex;
+ Rd_FPR64 = Rn_FPR64 f* tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x0f009000/mask=xbfc0f400
+# CONSTRUCT x0f009000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@2
+# AUNIT --inst x0f009000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround"
+# FMUL (by element) Vector, half-precision, Q=0
+
+:fmul Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
+is b_31=0 &b_30=0 & b_2229=0b00111100 & b_1215=0b1001 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR64.4H & Rn_VPR64.4H & Re_VPR128Lo.H.vIndexHLM & Zd
+{
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
+ # simd infix Rd_VPR64.4H = Rn_VPR64.4H f* tmp1 on lane size 2
+ Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f* tmp1;
+ Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f* tmp1;
+ Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f* tmp1;
+ Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f* tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x0f009000/mask=xbfc0f400
+# CONSTRUCT x4f009000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@2
+# AUNIT --inst x4f009000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround"
+# FMUL (by element) Vector, half-precision, Q=1
+
+:fmul Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
+is b_31=0 &b_30=1 & b_2229=0b00111100 & b_1215=0b1001 & b_10=0 & Re_VPR128Lo.H & vIndexHLM & Rd_VPR128.8H & Rn_VPR128.8H & Re_VPR128Lo.H.vIndexHLM & Zd
+{
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
+ # simd infix Rd_VPR128.8H = Rn_VPR128.8H f* tmp1 on lane size 2
+ Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f* tmp1;
+ Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f* tmp1;
+ Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f* tmp1;
+ Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f* tmp1;
+ Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f* tmp1;
+ Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f* tmp1;
+ Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f* tmp1;
+ Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f* tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x0f809000/mask=xbf80f400
+# CONSTRUCT x4fc09000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@8
+# AUNIT --inst x4fc09000/mask=xffe0f400 --rand dfp --status pass --comment "nofpround"
+# Vector, single-precision and double-precision Q=1 and sz:L=10
+
+:fmul Rd_VPR128.2D, Rn_VPR128.2D, Re_VPR128.D.vIndex
+is b_31=0 & b_30=1 & b_2329=0b0011111 & b_22=1 & b_21=0 & b_1215=0b1001 & b_10=0 & Re_VPR128.D.vIndex & vIndex & Re_VPR128.D & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ # simd element Re_VPR128.D[vIndex] lane size 8
+ local tmp1:8 = Re_VPR128.D.vIndex;
+ # simd infix Rd_VPR128.2D = Rn_VPR128.2D f* tmp1 on lane size 8
+ Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] f* tmp1;
+ Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] f* tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x0f809000/mask=xbf80f400
+# CONSTRUCT x0f809000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@4
+# AUNIT --inst x0f809000/mask=xffc0f400 --rand sfp --status fail --comment "nofpround"
+# Vector, single-precision and double-precision Q=0 and sz:L=0x
+
+:fmul Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex
+is b_31=0 & b_30=0 & b_2329=0b0011111 & b_22=0 & b_1215=0b1001 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp1:4 = Re_VPR128.S.vIndex;
+ # simd infix Rd_VPR64.2S = Rn_VPR64.2S f* tmp1 on lane size 4
+ Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] f* tmp1;
+ Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] f* tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.134 FMUL (by element) page C7-2320 line 135711 MATCH x0f809000/mask=xbf80f400
+# CONSTRUCT x4f809000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@4
+# AUNIT --inst x4f809000/mask=xffc0f400 --rand sfp --status fail --comment "nofpround"
+# Vector, single-precision and double-precision Q=1 and sz:L=0x
+
+:fmul Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex
+is b_31=0 & b_30=1 & b_2329=0b0011111 & b_22=0 & b_1215=0b1001 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp1:4 = Re_VPR128.S.vIndex;
+ # simd infix Rd_VPR128.4S = Rn_VPR128.4S f* tmp1 on lane size 4
+ Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] f* tmp1;
+ Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] f* tmp1;
+ Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] f* tmp1;
+ Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] f* tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.135 FMUL (vector) page C7-2324 line 135951 MATCH x2e20dc00/mask=xbfa0fc00
+# CONSTRUCT x6e60dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f*@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@8
+# AUNIT --inst x6e60dc00/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
+
+:fmul Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1b & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ # simd infix Rd_VPR128.2D = Rn_VPR128.2D f* Rm_VPR128.2D on lane size 8
+ Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] f* Rm_VPR128.2D[0,64];
+ Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] f* Rm_VPR128.2D[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.135 FMUL (vector) page C7-2324 line 135951 MATCH x2e20dc00/mask=xbfa0fc00
+# CONSTRUCT x2e20dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f*@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@4
+# AUNIT --inst x2e20dc00/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround"
+
+:fmul Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1b & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ # simd infix Rd_VPR64.2S = Rn_VPR64.2S f* Rm_VPR64.2S on lane size 4
+ Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] f* Rm_VPR64.2S[0,32];
+ Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] f* Rm_VPR64.2S[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.135 FMUL (vector) page C7-2324 line 135951 MATCH x2e20dc00/mask=xbfa0fc00
+# CONSTRUCT x6e20dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f*@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@4
+# AUNIT --inst x6e20dc00/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround"
+
+:fmul Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1b & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd infix Rd_VPR128.4S = Rn_VPR128.4S f* Rm_VPR128.4S on lane size 4
+ Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] f* Rm_VPR128.4S[0,32];
+ Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] f* Rm_VPR128.4S[32,32];
+ Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] f* Rm_VPR128.4S[64,32];
+ Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] f* Rm_VPR128.4S[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.135 FMUL (vector) page C7-2324 line 135951 MATCH x2e401c00/mask=xbfe0fc00
+# CONSTRUCT x2e401c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f*@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@2
+# AUNIT --inst x2e401c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant when Q=0 suf=VPR64.4H
+
+:fmul Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2129=0b101110010 & b_1015=0b000111 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ # simd infix Rd_VPR64.4H = Rn_VPR64.4H f* Rm_VPR64.4H on lane size 2
+ Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f* Rm_VPR64.4H[0,16];
+ Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f* Rm_VPR64.4H[16,16];
+ Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f* Rm_VPR64.4H[32,16];
+ Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f* Rm_VPR64.4H[48,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.135 FMUL (vector) page C7-2324 line 135951 MATCH x2e401c00/mask=xbfe0fc00
+# CONSTRUCT x6e401c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f*@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2@2
+# AUNIT --inst x6e401c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant when Q=1 suf=VPR128.8H
+
+:fmul Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2129=0b101110010 & b_1015=0b000111 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ # simd infix Rd_VPR128.8H = Rn_VPR128.8H f* Rm_VPR128.8H on lane size 2
+ Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f* Rm_VPR128.8H[0,16];
+ Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f* Rm_VPR128.8H[16,16];
+ Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f* Rm_VPR128.8H[32,16];
+ Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f* Rm_VPR128.8H[48,16];
+ Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f* Rm_VPR128.8H[64,16];
+ Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f* Rm_VPR128.8H[80,16];
+ Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f* Rm_VPR128.8H[96,16];
+ Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f* Rm_VPR128.8H[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.136 FMUL (scalar) page C7-2326 line 136066 MATCH x1e200800/mask=xff20fc00
+# CONSTRUCT x1e600800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =f*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2
+# AUNIT --inst x1e600800/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
+
+:fmul Rd_FPR64, Rn_FPR64, Rm_FPR64
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x0 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = Rn_FPR64 f* Rm_FPR64;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.136 FMUL (scalar) page C7-2326 line 136066 MATCH x1e200800/mask=xff20fc00
+# CONSTRUCT x1e200800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =f*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2
+# AUNIT --inst x1e200800/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround"
+
+:fmul Rd_FPR32, Rn_FPR32, Rm_FPR32
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x0 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = Rn_FPR32 f* Rm_FPR32;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.136 FMUL (scalar) page C7-2326 line 136066 MATCH x1e200800/mask=xff20fc00
+# CONSTRUCT x1ee00800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =f*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmul/2
+# AUNIT --inst x1ee00800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+
+:fmul Rd_FPR16, Rn_FPR16, Rm_FPR16
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x0 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = Rn_FPR16 f* Rm_FPR16;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.137 FMULX (by element) page C7-2328 line 136175 MATCH x2f809000/mask=xbf80f400
+# CONSTRUCT x6fc09000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@8
+# AUNIT --inst x6fc09000/mask=xffe0f400 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fmulx Rd_VPR128.2D, Rn_VPR128.2D, Re_VPR128.D.vIndex
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=3 & b_2121=0 & Re_VPR128.D.vIndex & vIndex & Re_VPR128.D & b_1215=0x9 & b_1010=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ local tmp1:8 = SIMD_PIECE(Re_VPR128.D, vIndex:1);
+ Rd_VPR128.2D = NEON_fmulx(Rn_VPR128.2D, tmp1, 8:1);
+}
+
+# C7.2.137 FMULX (by element) page C7-2328 line 136175 MATCH x2f809000/mask=xbf80f400
+# CONSTRUCT x2f809000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@4
+# AUNIT --inst x2f809000/mask=xffc0f400 --rand sfp --status fail --comment "nofpround"
+
+:fmulx Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x9 & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp1:4 = Re_VPR128.S.vIndex;
+ # simd infix Rd_VPR64.2S = Rn_VPR64.2S f* tmp1 on lane size 4
+ Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] f* tmp1;
+ Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] f* tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.137 FMULX (by element) page C7-2328 line 136175 MATCH x2f809000/mask=xbf80f400
+# CONSTRUCT x6f809000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@4
+# AUNIT --inst x6f809000/mask=xffc0f400 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fmulx Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x9 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ local tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1);
+ Rd_VPR128.4S = NEON_fmulx(Rn_VPR128.4S, tmp1, 4:1);
+}
+
+# C7.2.137 FMULX (by element) page C7-2328 line 136175 MATCH x7f009000/mask=xffc0f400
+# CONSTRUCT x7f009000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =f*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@2
+# AUNIT --inst x7f009000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround"
+# Scalar, half-precision variant
+
+:fmulx Rd_FPR16, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM
+is b_2231=0b0111111100 & b_1215=0b1001 & b_10=0 & Rd_FPR16 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd
+{
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
+ Rd_FPR16 = Rn_FPR16 f* tmp1;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.137 FMULX (by element) page C7-2328 line 136175 MATCH x7f809000/mask=xff80f400
+# CONSTRUCT x7f809000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =f*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@4
+# AUNIT --inst x7f809000/mask=xffc0f400 --rand sfp --status pass --comment "nofpround"
+# Scalar, single-precision and double-precision variant when sz=0 Ts=S V=32
+
+:fmulx Rd_FPR32, Rn_FPR32, Re_VPR128.S.vIndex
+is b_2331=0b011111111 & b_22=0 & b_1215=0b1001 & b_10=0 & Rd_FPR32 & Rn_FPR32 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Zd
+{
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp1:4 = Re_VPR128.S.vIndex;
+ Rd_FPR32 = Rn_FPR32 f* tmp1;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.137 FMULX (by element) page C7-2328 line 136175 MATCH x7f809000/mask=xff80f400
+# CONSTRUCT x7fc09000/mask=xffe0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =f*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@8
+# AUNIT --inst x7fc09000/mask=xffe0f400 --rand dfp --status pass --comment "nofpround"
+# Scalar, single-precision and double-precision variant when sz=1 Ts=D V=64
+
+:fmulx Rd_FPR64, Rn_FPR64, Re_VPR128.D.vIndex
+is b_2331=0b011111111 & b_22=1 & b_21=0 & b_1215=0b1001 & b_10=0 & Rd_FPR64 & Rn_FPR64 & Re_VPR128.D.vIndex & Re_VPR128.D & vIndex & Zd
+{
+ # simd element Re_VPR128.D[vIndex] lane size 8
+ local tmp1:8 = Re_VPR128.D.vIndex;
+ Rd_FPR64 = Rn_FPR64 f* tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.137 FMULX (by element) page C7-2328 line 136175 MATCH x2f009000/mask=xbfc0f400
+# CONSTRUCT x2f009000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f*@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@2
+# AUNIT --inst x2f009000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround"
+# Vector, half-precision variant when Q = 0 suf=64.4H
+
+:fmulx Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
+is b_31=0 & b_30=0 & b_2229=0b10111100 & b_1215=0b1001 & b_10=0 & Rd_VPR64.4H & Rn_VPR64.4H & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd
+{
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
+ # simd infix Rd_VPR64.4H = Rn_VPR64.4H f* tmp1 on lane size 2
+ Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f* tmp1;
+ Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f* tmp1;
+ Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f* tmp1;
+ Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f* tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.137 FMULX (by element) page C7-2328 line 136175 MATCH x2f009000/mask=xbfc0f400
+# CONSTRUCT x6f009000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f*@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@2
+# AUNIT --inst x6f009000/mask=xffc0f400 --rand hfp --status noqemu --comment "nofpround"
+# Vector, half-precision variant when Q = 1 suf=128.8H
+
+:fmulx Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
+is b_31=0 & b_30=1 & b_2229=0b10111100 & b_1215=0b1001 & b_10=0 & Rd_VPR128.8H & Rn_VPR128.8H & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd
+{
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
+ # simd infix Rd_VPR128.8H = Rn_VPR128.8H f* tmp1 on lane size 2
+ Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f* tmp1;
+ Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f* tmp1;
+ Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f* tmp1;
+ Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f* tmp1;
+ Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f* tmp1;
+ Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f* tmp1;
+ Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f* tmp1;
+ Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f* tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.138 FMULX page C7-2332 line 136418 MATCH x5e20dc00/mask=xffa0fc00
+# CONSTRUCT x5e60dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2
+# AUNIT --inst x5e60dc00/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fmulx Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_3031=1 & u=0 & b_2428=0x1e & size_high=0 & b_2122=3 & Rm_FPR64 & b_1115=0x1b & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_fmulx(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.138 FMULX page C7-2332 line 136418 MATCH x5e20dc00/mask=xffa0fc00
+# CONSTRUCT x5e20dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2
+# AUNIT --inst x5e20dc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fmulx Rd_FPR32, Rn_FPR32, Rm_FPR32
+is b_3031=1 & u=0 & b_2428=0x1e & size_high=0 & b_2122=1 & Rm_FPR32 & b_1115=0x1b & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_fmulx(Rn_FPR32, Rm_FPR32);
+}
+
+# C7.2.138 FMULX page C7-2332 line 136418 MATCH x0e20dc00/mask=xbfa0fc00
+# CONSTRUCT x4e60dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@8
+# AUNIT --inst x4e60dc00/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fmulx Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1b & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_fmulx(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.138 FMULX page C7-2332 line 136418 MATCH x0e20dc00/mask=xbfa0fc00
+# CONSTRUCT x0e20dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@4
+# AUNIT --inst x0e20dc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fmulx Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1b & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_fmulx(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.138 FMULX page C7-2332 line 136418 MATCH x0e20dc00/mask=xbfa0fc00
+# CONSTRUCT x4e20dc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@4
+# AUNIT --inst x4e20dc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fmulx Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1b & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_fmulx(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.138 FMULX page C7-2332 line 136418 MATCH x5e401c00/mask=xffe0fc00
+# CONSTRUCT x5e401c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =f*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2
+# AUNIT --inst x5e401c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Scalar half precision variant
+
+:fmulx Rd_FPR16, Rn_FPR16, Rm_FPR16
+is b_2131=0b01011110010 & b_1015=0b000111 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd
+{
+ Rd_FPR16 = Rn_FPR16 f* Rm_FPR16;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.138 FMULX page C7-2332 line 136418 MATCH x0e401c00/mask=xbfe0fc00
+# CONSTRUCT x0e401c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f*@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@2
+# AUNIT --inst x0e401c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Vector half precision variant when Q=0 suf=64.4H
+
+:fmulx Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b000111 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ # simd infix Rd_VPR64.4H = Rn_VPR64.4H f* Rm_VPR64.4H on lane size 2
+ Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f* Rm_VPR64.4H[0,16];
+ Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f* Rm_VPR64.4H[16,16];
+ Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f* Rm_VPR64.4H[32,16];
+ Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f* Rm_VPR64.4H[48,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.138 FMULX page C7-2332 line 136418 MATCH x0e401c00/mask=xbfe0fc00
+# CONSTRUCT x4e401c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f*@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fmulx/2@2
+# AUNIT --inst x4e401c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Vector half precision variant when Q=1 suf=128.8H
+
+:fmulx Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b000111 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ # simd infix Rd_VPR128.8H = Rn_VPR128.8H f* Rm_VPR128.8H on lane size 2
+ Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f* Rm_VPR128.8H[0,16];
+ Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f* Rm_VPR128.8H[16,16];
+ Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f* Rm_VPR128.8H[32,16];
+ Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f* Rm_VPR128.8H[48,16];
+ Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f* Rm_VPR128.8H[64,16];
+ Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f* Rm_VPR128.8H[80,16];
+ Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f* Rm_VPR128.8H[96,16];
+ Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f* Rm_VPR128.8H[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.139 FNEG (vector) page C7-2335 line 136615 MATCH x2ea0f800/mask=xbfbffc00
+# CONSTRUCT x6ee0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$fneg@8
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1@8
+# AUNIT --inst x6ee0f800/mask=xfffffc00 --rand dfp --status pass
+
+:fneg Rd_VPR128.2D, Rn_VPR128.2D
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0xf & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ # simd unary Rd_VPR128.2D = f-(Rn_VPR128.2D) on lane size 8
+ Rd_VPR128.2D[0,64] = f-(Rn_VPR128.2D[0,64]);
+ Rd_VPR128.2D[64,64] = f-(Rn_VPR128.2D[64,64]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.139 FNEG (vector) page C7-2335 line 136615 MATCH x2ea0f800/mask=xbfbffc00
+# CONSTRUCT x2ea0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$fneg@4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1@4
+# AUNIT --inst x2ea0f800/mask=xfffffc00 --rand sfp --status pass
+
+:fneg Rd_VPR64.2S, Rn_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xf & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ # simd unary Rd_VPR64.2S = f-(Rn_VPR64.2S) on lane size 4
+ Rd_VPR64.2S[0,32] = f-(Rn_VPR64.2S[0,32]);
+ Rd_VPR64.2S[32,32] = f-(Rn_VPR64.2S[32,32]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.139 FNEG (vector) page C7-2335 line 136615 MATCH x2ea0f800/mask=xbfbffc00
+# CONSTRUCT x6ea0f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$fneg@4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1@4
+# AUNIT --inst x6ea0f800/mask=xfffffc00 --rand sfp --status pass
+
+:fneg Rd_VPR128.4S, Rn_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xf & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd unary Rd_VPR128.4S = f-(Rn_VPR128.4S) on lane size 4
+ Rd_VPR128.4S[0,32] = f-(Rn_VPR128.4S[0,32]);
+ Rd_VPR128.4S[32,32] = f-(Rn_VPR128.4S[32,32]);
+ Rd_VPR128.4S[64,32] = f-(Rn_VPR128.4S[64,32]);
+ Rd_VPR128.4S[96,32] = f-(Rn_VPR128.4S[96,32]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.139 FNEG (vector) page C7-2335 line 136615 MATCH x2ef8f800/mask=xbffffc00
+# CONSTRUCT x2ef8f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$fneg@2
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1@2
+# AUNIT --inst x2ef8f800/mask=xfffffc00 --rand hfp --status noqemu
+# Half-precision variant when Q=0 suf=64.4H
+
+:fneg Rd_VPR64.4H, Rn_VPR64.4H
+is b_31=0 & b_30=0 & b_1029=0b10111011111000111110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
+{
+ # simd unary Rd_VPR64.4H = f-(Rn_VPR64.4H) on lane size 2
+ Rd_VPR64.4H[0,16] = f-(Rn_VPR64.4H[0,16]);
+ Rd_VPR64.4H[16,16] = f-(Rn_VPR64.4H[16,16]);
+ Rd_VPR64.4H[32,16] = f-(Rn_VPR64.4H[32,16]);
+ Rd_VPR64.4H[48,16] = f-(Rn_VPR64.4H[48,16]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.139 FNEG (vector) page C7-2335 line 136615 MATCH x2ef8f800/mask=xbffffc00
+# CONSTRUCT x6ef8f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$fneg@2
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1@2
+# AUNIT --inst x6ef8f800/mask=xfffffc00 --rand hfp --status noqemu
+# Half-precision variant when Q=1 suf=128.8H
+
+:fneg Rd_VPR128.8H, Rn_VPR128.8H
+is b_31=0 & b_30=1 & b_1029=0b10111011111000111110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
+{
+ # simd unary Rd_VPR128.8H = f-(Rn_VPR128.8H) on lane size 2
+ Rd_VPR128.8H[0,16] = f-(Rn_VPR128.8H[0,16]);
+ Rd_VPR128.8H[16,16] = f-(Rn_VPR128.8H[16,16]);
+ Rd_VPR128.8H[32,16] = f-(Rn_VPR128.8H[32,16]);
+ Rd_VPR128.8H[48,16] = f-(Rn_VPR128.8H[48,16]);
+ Rd_VPR128.8H[64,16] = f-(Rn_VPR128.8H[64,16]);
+ Rd_VPR128.8H[80,16] = f-(Rn_VPR128.8H[80,16]);
+ Rd_VPR128.8H[96,16] = f-(Rn_VPR128.8H[96,16]);
+ Rd_VPR128.8H[112,16] = f-(Rn_VPR128.8H[112,16]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.140 FNEG (scalar) page C7-2337 line 136726 MATCH x1e214000/mask=xff3ffc00
+# CONSTRUCT x1e614000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =fneg
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1
+# AUNIT --inst x1e614000/mask=xfffffc00 --rand dfp --status pass
+
+:fneg Rd_FPR64, Rn_FPR64
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & fpDpOpcode=0x2 & b_1014=0x10 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = f- Rn_FPR64;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.140 FNEG (scalar) page C7-2337 line 136726 MATCH x1e214000/mask=xff3ffc00
+# CONSTRUCT x1e214000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =fneg
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1
+# AUNIT --inst x1e214000/mask=xfffffc00 --rand sfp --status pass
+
+:fneg Rd_FPR32, Rn_FPR32
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & fpDpOpcode=0x2 & b_1014=0x10 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = f- Rn_FPR32;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.140 FNEG (scalar) page C7-2337 line 136726 MATCH x1e214000/mask=xff3ffc00
+# CONSTRUCT x1ee14000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =fneg
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fneg/1
+# AUNIT --inst x1ee14000/mask=xfffffc00 --rand hfp --status noqemu
+
+:fneg Rd_FPR16, Rn_FPR16
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & fpDpOpcode=0x2 & b_1014=0x10 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = f- Rn_FPR16;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.141 FNMADD page C7-2339 line 136822 MATCH x1f200000/mask=xff208000
+# CONSTRUCT x1f600000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 fneg =NEON_fnmadd/3
+# AUNIT --inst x1f600000/mask=xffe08000 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fnmadd Rd_FPR64, Rn_FPR64, Rm_FPR64, Ra_FPR64
+is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=1 & b_21=1 & Rm_FPR64 & b_15=0 & Ra_FPR64 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ local tmp1:8 = f- Ra_FPR64;
+ Rd_FPR64 = NEON_fnmadd(Rn_FPR64, Rm_FPR64, tmp1);
+}
+
+# C7.2.141 FNMADD page C7-2339 line 136822 MATCH x1f200000/mask=xff208000
+# CONSTRUCT x1f200000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 fneg =NEON_fnmadd/3
+# AUNIT --inst x1f200000/mask=xffe08000 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fnmadd Rd_FPR32, Rn_FPR32, Rm_FPR32, Ra_FPR32
+is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=0 & b_21=1 & Rm_FPR32 & b_15=0 & Ra_FPR32 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ local tmp1:4 = f- Ra_FPR32;
+ Rd_FPR32 = NEON_fnmadd(Rn_FPR32, Rm_FPR32, tmp1);
+}
+
+# C7.2.141 FNMADD page C7-2339 line 136822 MATCH x1f200000/mask=xff208000
+# CONSTRUCT x1fe00000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 fneg =NEON_fnmadd/3
+# AUNIT --inst x1fe00000/mask=xffe08000 --rand hfp --status noqemu --comment "nofpround"
+
+:fnmadd Rd_FPR16, Rn_FPR16, Rm_FPR16, Ra_FPR16
+is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=3 & b_21=1 & Rm_FPR16 & b_15=0 & Ra_FPR16 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ local tmp1:2 = f- Ra_FPR16;
+ Rd_FPR16 = NEON_fnmadd(Rn_FPR16, Rm_FPR16, tmp1);
+}
+
+# C7.2.142 FNMSUB page C7-2341 line 136952 MATCH x1f208000/mask=xff208000
+# CONSTRUCT x1f608000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fnmsub/3
+# AUNIT --inst x1f608000/mask=xffe08000 --rand dfp --status nopcodeop --comment "nofpround"
+
+:fnmsub Rd_FPR64, Rn_FPR64, Rm_FPR64, Ra_FPR64
+is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=1 & b_21=1 & Rm_FPR64 & b_15=1 & Ra_FPR64 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_fnmsub(Rn_FPR64, Rm_FPR64, Ra_FPR64);
+}
+
+# C7.2.142 FNMSUB page C7-2341 line 136952 MATCH x1f208000/mask=xff208000
+# CONSTRUCT x1f208000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fnmsub/3
+# AUNIT --inst x1f208000/mask=xffe08000 --rand sfp --status nopcodeop --comment "nofpround"
+
+:fnmsub Rd_FPR32, Rn_FPR32, Rm_FPR32, Ra_FPR32
+is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=0 & b_21=1 & Rm_FPR32 & b_15=1 & Ra_FPR32 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_fnmsub(Rn_FPR32, Rm_FPR32, Ra_FPR32);
+}
+
+# C7.2.142 FNMSUB page C7-2341 line 136952 MATCH x1f208000/mask=xff208000
+# CONSTRUCT x1fe08000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_fnmsub/3
+# AUNIT --inst x1fe08000/mask=xffe08000 --rand hfp --status noqemu --comment "nofpround"
+
+:fnmsub Rd_FPR16, Rn_FPR16, Rm_FPR16, Ra_FPR16
+is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=3 & b_21=1 & Rm_FPR16 & b_15=1 & Ra_FPR16 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_fnmsub(Rn_FPR16, Rm_FPR16, Ra_FPR16);
+}
+
+# C7.2.143 FNMUL (scalar) page C7-2343 line 137081 MATCH x1e208800/mask=xff20fc00
+# CONSTRUCT x1e608800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 f* =fneg
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fnmul/2
+# AUNIT --inst x1e608800/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
+
+:fnmul Rd_FPR64, Rn_FPR64, Rm_FPR64
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x8 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ local tmp1:8 = Rn_FPR64 f* Rm_FPR64;
+ Rd_FPR64 = f- tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.143 FNMUL (scalar) page C7-2343 line 137081 MATCH x1e208800/mask=xff20fc00
+# CONSTRUCT x1e208800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 f* =fneg
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fnmul/2
+# AUNIT --inst x1e208800/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround"
+
+:fnmul Rd_FPR32, Rn_FPR32, Rm_FPR32
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x8 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ local tmp1:4 = Rn_FPR32 f* Rm_FPR32;
+ Rd_FPR32 = f- tmp1;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.143 FNMUL (scalar) page C7-2343 line 137081 MATCH x1e208800/mask=xff20fc00
+# CONSTRUCT x1ee08800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 f* =fneg
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fnmul/2
+# AUNIT --inst x1ee08800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+
+:fnmul Rd_FPR16, Rn_FPR16, Rm_FPR16
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x8 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ local tmp1:2 = Rn_FPR16 f* Rm_FPR16;
+ Rd_FPR16 = f- tmp1;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.144 FRECPE page C7-2345 line 137191 MATCH x0ea1d800/mask=xbfbffc00
+# CONSTRUCT x4ee1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1@8
+# AUNIT --inst x4ee1d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround"
+
+:frecpe Rd_VPR128.2D, Rn_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & size_high=1 & b_1722=0x30 & b_1216=0x1d & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_frecpe(Rn_VPR128.2D, 8:1);
+}
+
+# C7.2.144 FRECPE page C7-2345 line 137191 MATCH x0ea1d800/mask=xbfbffc00
+# CONSTRUCT x0ea1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1@4
+# AUNIT --inst x0ea1d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:frecpe Rd_VPR64.2S, Rn_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & size_high=1 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_frecpe(Rn_VPR64.2S, 4:1);
+}
+
+# C7.2.144 FRECPE page C7-2345 line 137191 MATCH x0ea1d800/mask=xbfbffc00
+# CONSTRUCT x4ea1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1@4
+# AUNIT --inst x4ea1d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:frecpe Rd_VPR128.4S, Rn_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & size_high=1 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_frecpe(Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.144 FRECPE page C7-2345 line 137191 MATCH x5ea1d800/mask=xffbffc00
+# CONSTRUCT x5ee1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1
+# AUNIT --inst x5ee1d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround"
+
+:frecpe Rd_FPR64, Rn_FPR64
+is b_3031=1 & u=0 & b_2428=0x1e & size_high=1 & b_1722=0x30 & b_1216=0x1d & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_frecpe(Rn_FPR64);
+}
+
+# C7.2.144 FRECPE page C7-2345 line 137191 MATCH x5ea1d800/mask=xffbffc00
+# CONSTRUCT x5ea1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1
+# AUNIT --inst x5ea1d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:frecpe Rd_FPR32, Rn_FPR32
+is b_3031=1 & u=0 & b_2428=0x1e & size_high=1 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_frecpe(Rn_FPR32);
+}
+
+# C7.2.144 FRECPE page C7-2345 line 137191 MATCH x5ef9d800/mask=xfffffc00
+# CONSTRUCT x5ef9d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1
+# AUNIT --inst x5ef9d800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Scalar half precision variant
+
+:frecpe Rd_FPR16, Rn_FPR16
+is b_1031=0b0101111011111001110110 & Rd_FPR16 & Rn_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_frecpe(Rn_FPR16);
+}
+
+# C7.2.144 FRECPE page C7-2345 line 137191 MATCH x0ef9d800/mask=xbffffc00
+# CONSTRUCT x0ef9d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1@2
+# AUNIT --inst x0ef9d800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Vector half precision variant when Q=0 suf=64.4H
+
+:frecpe Rd_VPR64.4H, Rn_VPR64.4H
+is b_31=0 & b_30=0 & b_1029=0b00111011111001110110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_frecpe(Rn_VPR64.4H, 2:1);
+}
+
+# C7.2.144 FRECPE page C7-2345 line 137191 MATCH x0ef9d800/mask=xbffffc00
+# CONSTRUCT x4ef9d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpe/1@2
+# AUNIT --inst x4ef9d800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Vector half precision variant when Q=1 suf=128.8H
+
+:frecpe Rd_VPR128.8H, Rn_VPR128.8H
+is b_31=0 & b_30=1 & b_1029=0b00111011111001110110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_frecpe(Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.145 FRECPS page C7-2348 line 137379 MATCH x5e20fc00/mask=xffa0fc00
+# CONSTRUCT x5e60fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2
+# AUNIT --inst x5e60fc00/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
+
+:frecps Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_3031=1 & u=0 & b_2428=0x1e & size_high=0 & b_2122=3 & Rm_FPR64 & b_1115=0x1f & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_frecps(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.145 FRECPS page C7-2348 line 137379 MATCH x5e20fc00/mask=xffa0fc00
+# CONSTRUCT x5e20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2
+# AUNIT --inst x5e20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:frecps Rd_FPR32, Rn_FPR32, Rm_FPR32
+is b_3031=1 & u=0 & b_2428=0x1e & size_high=0 & b_2122=1 & Rm_FPR32 & b_1115=0x1f & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_frecps(Rn_FPR32, Rm_FPR32);
+}
+
+# C7.2.145 FRECPS page C7-2348 line 137379 MATCH x0e20fc00/mask=xbfa0fc00
+# CONSTRUCT x4e60fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2@8
+# AUNIT --inst x4e60fc00/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
+
+:frecps Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_21=1 & Rm_VPR128.2D & b_1115=0x1f & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_frecps(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.145 FRECPS page C7-2348 line 137379 MATCH x0e20fc00/mask=xbfa0fc00
+# CONSTRUCT x0e20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2@4
+# AUNIT --inst x0e20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:frecps Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR64.2S & b_1115=0x1f & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_frecps(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.145 FRECPS page C7-2348 line 137379 MATCH x0e20fc00/mask=xbfa0fc00
+# CONSTRUCT x4e20fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2@4
+# AUNIT --inst x4e20fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+
+:frecps Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_21=1 & Rm_VPR128.4S & b_1115=0x1f & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_frecps(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.145 FRECPS page C7-2348 line 137379 MATCH x5e403c00/mask=xffe0fc00
+# CONSTRUCT x5e403c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2
+# AUNIT --inst x5e403c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Scalar half precision variant
+
+:frecps Rd_FPR16, Rn_FPR16, Rm_FPR16
+is b_2131=0b01011110010 & b_1015=0b001111 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_frecps(Rn_FPR16, Rm_FPR16);
+}
+
+# C7.2.145 FRECPS page C7-2348 line 137379 MATCH x0e403c00/mask=xbfe0fc00
+# CONSTRUCT x0e403c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2@2
+# AUNIT --inst x0e403c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Vector half precision variant when Q=0 suf=64.4H
+
+:frecps Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2129=0b001110010 & b_1015=0b001111 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_frecps(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.145 FRECPS page C7-2348 line 137379 MATCH x0e403c00/mask=xbfe0fc00
+# CONSTRUCT x4e403c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frecps/2@2
+# AUNIT --inst x4e403c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Vector half precision variant when Q=1 suf=128.8H
+
+:frecps Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2129=0b001110010 & b_1015=0b001111 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_frecps(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.146 FRECPX page C7-2351 line 137576 MATCH x5ef9f800/mask=xfffffc00
+# CONSTRUCT x5ef9f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpx/1
+# AUNIT --inst x5ef9f800/mask=xfffffc00 --rand hfp --status noqemu
+# Half-precision variant
+
+:frecpx Rd_FPR16, Rn_FPR16
+is b_1031=0b0101111011111001111110 & Rd_FPR16 & Rn_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_frecpx(Rn_FPR16);
+}
+
+# C7.2.146 FRECPX page C7-2351 line 137576 MATCH x5ea1f800/mask=xffbffc00
+# CONSTRUCT x5ea1f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpx/1
+# AUNIT --inst x5ea1f800/mask=xfffffc00 --rand sfp --status nopcodeop
+# Single-precision and double-precision variant when sz=0 suf=32
+
+:frecpx Rd_FPR32, Rn_FPR32
+is b_2331=0b010111101 & b_22=0 & b_1021=0b100001111110 & Rd_FPR32 & Rn_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_frecpx(Rn_FPR32);
+}
+
+# C7.2.146 FRECPX page C7-2351 line 137576 MATCH x5ea1f800/mask=xffbffc00
+# CONSTRUCT x5ee1f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frecpx/1
+# AUNIT --inst x5ee1f800/mask=xfffffc00 --rand dfp --status nopcodeop
+# Single-precision and double-precision variant when sz=1 suf=64
+
+:frecpx Rd_FPR64, Rn_FPR64
+is b_2331=0b010111101 & b_22=1 & b_1021=0b100001111110 & Rd_FPR64 & Rn_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_frecpx(Rn_FPR64);
+}
+
+# C7.2.140 FRINTA (vector) page C7-1313 line 76386 KEEPWITH
+
+frint_vmode: "a" is b_29=1 & b_23=0 & b_12=0 { }
+frint_vmode: "i" is b_29=1 & b_23=1 & b_12=1 { }
+frint_vmode: "m" is b_29=0 & b_23=0 & b_12=1 { }
+frint_vmode: "n" is b_29=0 & b_23=0 & b_12=0 { }
+frint_vmode: "p" is b_29=0 & b_23=1 & b_12=0 { }
+frint_vmode: "x" is b_29=1 & b_23=0 & b_12=1 { }
+frint_vmode: "z" is b_29=0 & b_23=1 & b_12=1 { }
+
+# C7.2.155 FRINTA (vector) page C7-2369 line 138408 MATCH x2e798800/mask=xbffffc00
+# C7.2.157 FRINTI (vector) page C7-2373 line 138642 MATCH x2ef99800/mask=xbffffc00
+# C7.2.159 FRINTM (vector) page C7-2377 line 138880 MATCH x0e799800/mask=xbffffc00
+# C7.2.161 FRINTN (vector) page C7-2381 line 139118 MATCH x0e798800/mask=xbffffc00
+# C7.2.163 FRINTP (vector) page C7-2385 line 139356 MATCH x0ef98800/mask=xbffffc00
+# C7.2.165 FRINTX (vector) page C7-2389 line 139594 MATCH x2e799800/mask=xbffffc00
+# C7.2.167 FRINTZ (vector) page C7-2393 line 139833 MATCH x0ef99800/mask=xbffffc00
+# CONSTRUCT x0e798800/mask=xdf7fec00 MATCHED 7 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$trunc@2
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1@2
+# AUNIT --inst x0e798800/mask=xdf7fec00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant when Q=0 suf=64.4H
+
+:frint^frint_vmode Rd_VPR64.4H, Rn_VPR64.4H
+is b_31=0 & b_30=0 & b_29 & b_2428=0b01110 & b_23 & b_1322=0b1111001100 & b_12 & b_1011=0b10 & frint_vmode & Rd_VPR64.4H & Rn_VPR64.4H & Zd
+{
+ # simd unary Rd_VPR64.4H = trunc(Rn_VPR64.4H) on lane size 2
+ Rd_VPR64.4H[0,16] = trunc(Rn_VPR64.4H[0,16]);
+ Rd_VPR64.4H[16,16] = trunc(Rn_VPR64.4H[16,16]);
+ Rd_VPR64.4H[32,16] = trunc(Rn_VPR64.4H[32,16]);
+ Rd_VPR64.4H[48,16] = trunc(Rn_VPR64.4H[48,16]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.155 FRINTA (vector) page C7-2369 line 138408 MATCH x2e798800/mask=xbffffc00
+# C7.2.157 FRINTI (vector) page C7-2373 line 138642 MATCH x2ef99800/mask=xbffffc00
+# C7.2.159 FRINTM (vector) page C7-2377 line 138880 MATCH x0e799800/mask=xbffffc00
+# C7.2.161 FRINTN (vector) page C7-2381 line 139118 MATCH x0e798800/mask=xbffffc00
+# C7.2.163 FRINTP (vector) page C7-2385 line 139356 MATCH x0ef98800/mask=xbffffc00
+# C7.2.165 FRINTX (vector) page C7-2389 line 139594 MATCH x2e799800/mask=xbffffc00
+# C7.2.167 FRINTZ (vector) page C7-2393 line 139833 MATCH x0ef99800/mask=xbffffc00
+# CONSTRUCT x4e798800/mask=xdf7fec00 MATCHED 7 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$trunc@2
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1@2
+# AUNIT --inst x4e798800/mask=xdf7fec00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant when Q=1 suf=128.8H
+
+:frint^frint_vmode Rd_VPR128.8H, Rn_VPR128.8H
+is b_31=0 & b_30=1 & b_29 & b_2428=0b01110 & b_23 & b_1322=0b1111001100 & b_12 & b_1011=0b10 & frint_vmode & Rd_VPR128.8H & Rn_VPR128.8H & Zd
+{
+ # simd unary Rd_VPR128.8H = trunc(Rn_VPR128.8H) on lane size 2
+ Rd_VPR128.8H[0,16] = trunc(Rn_VPR128.8H[0,16]);
+ Rd_VPR128.8H[16,16] = trunc(Rn_VPR128.8H[16,16]);
+ Rd_VPR128.8H[32,16] = trunc(Rn_VPR128.8H[32,16]);
+ Rd_VPR128.8H[48,16] = trunc(Rn_VPR128.8H[48,16]);
+ Rd_VPR128.8H[64,16] = trunc(Rn_VPR128.8H[64,16]);
+ Rd_VPR128.8H[80,16] = trunc(Rn_VPR128.8H[80,16]);
+ Rd_VPR128.8H[96,16] = trunc(Rn_VPR128.8H[96,16]);
+ Rd_VPR128.8H[112,16] = trunc(Rn_VPR128.8H[112,16]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.155 FRINTA (vector) page C7-2369 line 138408 MATCH x2e218800/mask=xbfbffc00
+# C7.2.157 FRINTI (vector) page C7-2373 line 138642 MATCH x2ea19800/mask=xbfbffc00
+# C7.2.159 FRINTM (vector) page C7-2377 line 138880 MATCH x0e219800/mask=xbfbffc00
+# C7.2.161 FRINTN (vector) page C7-2381 line 139118 MATCH x0e218800/mask=xbfbffc00
+# C7.2.163 FRINTP (vector) page C7-2385 line 139356 MATCH x0ea18800/mask=xbfbffc00
+# C7.2.165 FRINTX (vector) page C7-2389 line 139594 MATCH x2e219800/mask=xbfbffc00
+# C7.2.167 FRINTZ (vector) page C7-2393 line 139833 MATCH x0ea19800/mask=xbfbffc00
+# CONSTRUCT x0e218800/mask=xdf7fec00 MATCHED 7 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$trunc@4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1@4
+# AUNIT --inst x0e218800/mask=xdf7fec00 --rand sfp --status fail --comment "nofpround"
+# Single-precision and double-precision variant when sz=0 Q=0 suf=64.2S
+
+:frint^frint_vmode Rd_VPR64.2S, Rn_VPR64.2S
+is b_31=0 & b_30=0 & b_29 & b_2428=0b01110 & b_23 & b_22=0b0 & b_1321=0b100001100 & b_12 & b_1011=0b10 & frint_vmode & Rd_VPR64.2S & Rn_VPR64.2S & Zd
+{
+ # simd unary Rd_VPR64.2S = trunc(Rn_VPR64.2S) on lane size 4
+ Rd_VPR64.2S[0,32] = trunc(Rn_VPR64.2S[0,32]);
+ Rd_VPR64.2S[32,32] = trunc(Rn_VPR64.2S[32,32]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.155 FRINTA (vector) page C7-2369 line 138408 MATCH x2e218800/mask=xbfbffc00
+# C7.2.157 FRINTI (vector) page C7-2373 line 138642 MATCH x2ea19800/mask=xbfbffc00
+# C7.2.159 FRINTM (vector) page C7-2377 line 138880 MATCH x0e219800/mask=xbfbffc00
+# C7.2.161 FRINTN (vector) page C7-2381 line 139118 MATCH x0e218800/mask=xbfbffc00
+# C7.2.163 FRINTP (vector) page C7-2385 line 139356 MATCH x0ea18800/mask=xbfbffc00
+# C7.2.165 FRINTX (vector) page C7-2389 line 139594 MATCH x2e219800/mask=xbfbffc00
+# C7.2.167 FRINTZ (vector) page C7-2393 line 139833 MATCH x0ea19800/mask=xbfbffc00
+# CONSTRUCT x4e218800/mask=xdf7fec00 MATCHED 7 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$trunc@4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1@4
+# AUNIT --inst x4e218800/mask=xdf7fec00 --rand sfp --status fail --comment "nofpround"
+# Single-precision and double-precision variant when sz=0 Q=1 suf=128.4S
+
+:frint^frint_vmode Rd_VPR128.4S, Rn_VPR128.4S
+is b_31=0 & b_30=1 & b_29 & b_2428=0b01110 & b_23 & b_22=0b0 & b_1321=0b100001100 & b_12 & b_1011=0b10 & frint_vmode & Rd_VPR128.4S & Rn_VPR128.4S & Zd
+{
+ # simd unary Rd_VPR128.4S = trunc(Rn_VPR128.4S) on lane size 4
+ Rd_VPR128.4S[0,32] = trunc(Rn_VPR128.4S[0,32]);
+ Rd_VPR128.4S[32,32] = trunc(Rn_VPR128.4S[32,32]);
+ Rd_VPR128.4S[64,32] = trunc(Rn_VPR128.4S[64,32]);
+ Rd_VPR128.4S[96,32] = trunc(Rn_VPR128.4S[96,32]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.155 FRINTA (vector) page C7-2369 line 138408 MATCH x2e218800/mask=xbfbffc00
+# C7.2.157 FRINTI (vector) page C7-2373 line 138642 MATCH x2ea19800/mask=xbfbffc00
+# C7.2.159 FRINTM (vector) page C7-2377 line 138880 MATCH x0e219800/mask=xbfbffc00
+# C7.2.161 FRINTN (vector) page C7-2381 line 139118 MATCH x0e218800/mask=xbfbffc00
+# C7.2.163 FRINTP (vector) page C7-2385 line 139356 MATCH x0ea18800/mask=xbfbffc00
+# C7.2.165 FRINTX (vector) page C7-2389 line 139594 MATCH x2e219800/mask=xbfbffc00
+# C7.2.167 FRINTZ (vector) page C7-2393 line 139833 MATCH x0ea19800/mask=xbfbffc00
+# CONSTRUCT x4e618800/mask=xdf7fec00 MATCHED 7 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$trunc@8
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1@8
+# AUNIT --inst x4e618800/mask=xdf7fec00 --rand dfp --status fail --comment "nofpround"
+# Single-precision and double-precision variant when sz=1 Q=1 suf=128.2D
+
+:frint^frint_vmode Rd_VPR128.2D, Rn_VPR128.2D
+is b_31=0 & b_30=1 & b_29 & b_2428=0b01110 & b_23 & b_22=0b1 & b_1321=0b100001100 & b_12 & b_1011=0b10 & frint_vmode & Rd_VPR128.2D & Rn_VPR128.2D & Zd
+{
+ # simd unary Rd_VPR128.2D = trunc(Rn_VPR128.2D) on lane size 8
+ Rd_VPR128.2D[0,64] = trunc(Rn_VPR128.2D[0,64]);
+ Rd_VPR128.2D[64,64] = trunc(Rn_VPR128.2D[64,64]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.141 FRINTA (scalar) page C7-1315 line 76515 KEEPWITH
+# FP rounding instruction (not implemented)
+
+frint_smode: "a" is b_1517=0b100 { }
+frint_smode: "i" is b_1517=0b111 { }
+frint_smode: "m" is b_1517=0b010 { }
+frint_smode: "n" is b_1517=0b000 { }
+frint_smode: "p" is b_1517=0b001 { }
+frint_smode: "x" is b_1517=0b110 { }
+frint_smode: "z" is b_1517=0b011 { }
+
+# C7.2.156 FRINTA (scalar) page C7-2371 line 138539 MATCH x1e264000/mask=xff3ffc00
+# C7.2.158 FRINTI (scalar) page C7-2375 line 138773 MATCH x1e27c000/mask=xff3ffc00
+# C7.2.160 FRINTM (scalar) page C7-2379 line 139011 MATCH x1e254000/mask=xff3ffc00
+# C7.2.162 FRINTN (scalar) page C7-2383 line 139249 MATCH x1e244000/mask=xff3ffc00
+# C7.2.164 FRINTP (scalar) page C7-2387 line 139487 MATCH x1e24c000/mask=xff3ffc00
+# C7.2.166 FRINTX (scalar) page C7-2391 line 139726 MATCH x1e274000/mask=xff3ffc00
+# C7.2.168 FRINTZ (scalar) page C7-2395 line 139964 MATCH x1e25c000/mask=xff3ffc00
+# CONSTRUCT x1ee44000/mask=xfffc7c00 MATCHED 7 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =trunc
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1
+# AUNIT --inst x1ee44000/mask=xfffc7c00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant when type = 11 suf=16
+
+:frint^frint_smode Rd_FPR16, Rn_FPR16
+is b_2431=0b00011110 & b_2223=0b11 & b_1821=0b1001 & b_1517 & b_1014=0b10000 & frint_smode & Rd_FPR16 & Rn_FPR16 & Zd
+{
+ Rd_FPR16 = trunc(Rn_FPR16);
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.156 FRINTA (scalar) page C7-2371 line 138539 MATCH x1e264000/mask=xff3ffc00
+# C7.2.158 FRINTI (scalar) page C7-2375 line 138773 MATCH x1e27c000/mask=xff3ffc00
+# C7.2.160 FRINTM (scalar) page C7-2379 line 139011 MATCH x1e254000/mask=xff3ffc00
+# C7.2.162 FRINTN (scalar) page C7-2383 line 139249 MATCH x1e244000/mask=xff3ffc00
+# C7.2.164 FRINTP (scalar) page C7-2387 line 139487 MATCH x1e24c000/mask=xff3ffc00
+# C7.2.166 FRINTX (scalar) page C7-2391 line 139726 MATCH x1e274000/mask=xff3ffc00
+# C7.2.168 FRINTZ (scalar) page C7-2395 line 139964 MATCH x1e25c000/mask=xff3ffc00
+# CONSTRUCT x1e244000/mask=xfffc7c00 MATCHED 7 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =trunc
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1
+# AUNIT --inst x1e244000/mask=xfffc7c00 --rand sfp --status fail --comment "nofpround"
+# Single-precision variant when type = 00 suf=32
+
+:frint^frint_smode Rd_FPR32, Rn_FPR32
+is b_2431=0b00011110 & b_2223=0b00 & b_1821=0b1001 & b_1517 & b_1014=0b10000 & frint_smode & Rd_FPR32 & Rn_FPR32 & Zd
+{
+ Rd_FPR32 = trunc(Rn_FPR32);
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.156 FRINTA (scalar) page C7-2371 line 138539 MATCH x1e264000/mask=xff3ffc00
+# C7.2.158 FRINTI (scalar) page C7-2375 line 138773 MATCH x1e27c000/mask=xff3ffc00
+# C7.2.160 FRINTM (scalar) page C7-2379 line 139011 MATCH x1e254000/mask=xff3ffc00
+# C7.2.162 FRINTN (scalar) page C7-2383 line 139249 MATCH x1e244000/mask=xff3ffc00
+# C7.2.164 FRINTP (scalar) page C7-2387 line 139487 MATCH x1e24c000/mask=xff3ffc00
+# C7.2.166 FRINTX (scalar) page C7-2391 line 139726 MATCH x1e274000/mask=xff3ffc00
+# C7.2.168 FRINTZ (scalar) page C7-2395 line 139964 MATCH x1e25c000/mask=xff3ffc00
+# CONSTRUCT x1e644000/mask=xfffc7c00 MATCHED 7 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =trunc
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frint_aimnpxz/1
+# AUNIT --inst x1e644000/mask=xfffc7c00 --rand dfp --status fail --comment "nofpround"
+# Double-precision variant when type = 01 suf=64
+
+:frint^frint_smode Rd_FPR64, Rn_FPR64
+is b_2431=0b00011110 & b_2223=0b01 & b_1821=0b1001 & b_1517 & b_1014=0b10000 & frint_smode & Rd_FPR64 & Rn_FPR64 & Zd
+{
+ Rd_FPR64 = trunc(Rn_FPR64);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.169 FRSQRTE page C7-2397 line 140071 MATCH x7ef9d800/mask=xfffffc00
+# CONSTRUCT x7ef9d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1
+# AUNIT --inst x7ef9d800/mask=xfffffc00 --status noqemu --comment "nofpround"
+# Scalar half precision variant when Q=1 sz=1 ba=11 bb=111 V=FPR16 esize=
+
+:frsqrte Rd_FPR16, Rn_FPR16
+is b_31=0 & b_30=1 & b_2329=0b1111101 & b_22=1 & b_1021=0b111001110110 & Rd_FPR16 & Rn_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_frsqrte(Rn_FPR16);
+}
+
+# C7.2.169 FRSQRTE page C7-2397 line 140071 MATCH x7ea1d800/mask=xffbffc00
+# CONSTRUCT x7ea1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1
+# AUNIT --inst x7ea1d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
+# Scalar single-precision and double-precision variant when Q=1 sz=0 ba=11 bb=100 V=FPR32 esize=
+
+:frsqrte Rd_FPR32, Rn_FPR32
+is b_31=0 & b_30=1 & b_2329=0b1111101 & b_22=0 & b_1021=0b100001110110 & Rd_FPR32 & Rn_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_frsqrte(Rn_FPR32);
+}
+
+# C7.2.169 FRSQRTE page C7-2397 line 140071 MATCH x7ea1d800/mask=xffbffc00
+# CONSTRUCT x7ee1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1
+# AUNIT --inst x7ee1d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround"
+# Scalar single-precision and double-precision variant when Q=1 sz=1 ba=11 bb=100 V=FPR64 esize=
+
+:frsqrte Rd_FPR64, Rn_FPR64
+is b_31=0 & b_30=1 & b_2329=0b1111101 & b_22=1 & b_1021=0b100001110110 & Rd_FPR64 & Rn_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_frsqrte(Rn_FPR64);
+}
+
+# C7.2.169 FRSQRTE page C7-2397 line 140071 MATCH x2ef9d800/mask=xbffffc00
+# CONSTRUCT x2ef9d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1@2
+# AUNIT --inst x2ef9d800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Vector half precision variant when Q=0 sz=1 ba=10 bb=111 V=VPR64.4H esize=@2
+
+:frsqrte Rd_VPR64.4H, Rn_VPR64.4H
+is b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=1 & b_1021=0b111001110110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_frsqrte(Rn_VPR64.4H, 2:1);
+}
+
+# C7.2.169 FRSQRTE page C7-2397 line 140071 MATCH x2ef9d800/mask=xbffffc00
+# CONSTRUCT x6ef9d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1@2
+# AUNIT --inst x6ef9d800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Vector half precision variant when Q=1 sz=1 ba=10 bb=111 V=VPR128.8H esize=@2
+
+:frsqrte Rd_VPR128.8H, Rn_VPR128.8H
+is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=1 & b_1021=0b111001110110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_frsqrte(Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.169 FRSQRTE page C7-2397 line 140071 MATCH x2ea1d800/mask=xbfbffc00
+# CONSTRUCT x2ea1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1@4
+# AUNIT --inst x2ea1d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
+# Vector single-precision and double-precision variant when Q=0 sz=0 ba=10 bb=100 V=VPR64.2S esize=@4
+
+:frsqrte Rd_VPR64.2S, Rn_VPR64.2S
+is b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=0 & b_1021=0b100001110110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_frsqrte(Rn_VPR64.2S, 4:1);
+}
+
+# C7.2.169 FRSQRTE page C7-2397 line 140071 MATCH x2ea1d800/mask=xbfbffc00
+# CONSTRUCT x6ea1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1@4
+# AUNIT --inst x6ea1d800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
+# Vector single-precision and double-precision variant when Q=1 sz=0 ba=10 bb=100 V=VPR128.4S esize=@4
+
+:frsqrte Rd_VPR128.4S, Rn_VPR128.4S
+is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=0 & b_1021=0b100001110110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_frsqrte(Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.169 FRSQRTE page C7-2397 line 140071 MATCH x2ea1d800/mask=xbfbffc00
+# CONSTRUCT x6ee1d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrte/1@8
+# AUNIT --inst x6ee1d800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround"
+# Vector single-precision and double-precision variant when Q=1 sz=1 ba=10 bb=100 V=VPR128.2D esize=@8
+
+:frsqrte Rd_VPR128.2D, Rn_VPR128.2D
+is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=1 & b_1021=0b100001110110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_frsqrte(Rn_VPR128.2D, 8:1);
+}
+
+# C7.2.170 FRSQRTS page C7-2400 line 140259 MATCH x5ec03c00/mask=xffe0fc00
+# CONSTRUCT x5ec03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_frsqrts/1
+# AUNIT --inst x5ec03c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Scalar half precision variant when Q=1 sz=1 ba=01 bb=0 bc=00 V=FPR16 esize=
+
+:frsqrts Rd_FPR16, Rn_FPR16, Rm_FPR16
+is b_31=0 & b_30=1 & b_2329=0b0111101 & b_22=1 & b_21=0 & b_1015=0b001111 & Rd_FPR16 & Rn_FPR16 & Rm_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_frsqrts(Rn_FPR16);
+}
+
+# C7.2.170 FRSQRTS page C7-2400 line 140259 MATCH x5ea0fc00/mask=xffa0fc00
+# CONSTRUCT x5ea0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2
+# AUNIT --inst x5ea0fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+# Scalar single-precision and double-precision variant when Q=1 sz=0 ba=01 bb=1 bc=11 V=FPR32 esize=
+
+:frsqrts Rd_FPR32, Rn_FPR32, Rm_FPR32
+is b_31=0 & b_30=1 & b_2329=0b0111101 & b_22=0 & b_21=1 & b_1015=0b111111 & Rd_FPR32 & Rn_FPR32 & Rm_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_frsqrts(Rn_FPR32, Rm_FPR32);
+}
+
+# C7.2.170 FRSQRTS page C7-2400 line 140259 MATCH x5ea0fc00/mask=xffa0fc00
+# CONSTRUCT x5ee0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2
+# AUNIT --inst x5ee0fc00/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
+# Scalar single-precision and double-precision variant when Q=1 sz=1 ba=01 bb=1 bc=11 V=FPR64 esize=
+
+:frsqrts Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_31=0 & b_30=1 & b_2329=0b0111101 & b_22=1 & b_21=1 & b_1015=0b111111 & Rd_FPR64 & Rn_FPR64 & Rm_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_frsqrts(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.170 FRSQRTS page C7-2400 line 140259 MATCH x0ec03c00/mask=xbfe0fc00
+# CONSTRUCT x0ec03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2@2
+# AUNIT --inst x0ec03c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Vector half precision variant when Q=0 sz=1 ba=00 bb=0 bc=00 V=VPR64.4H esize=@2
+
+:frsqrts Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2329=0b0011101 & b_22=1 & b_21=0 & b_1015=0b001111 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_frsqrts(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.170 FRSQRTS page C7-2400 line 140259 MATCH x0ec03c00/mask=xbfe0fc00
+# CONSTRUCT x4ec03c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2@2
+# AUNIT --inst x4ec03c00/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Vector half precision variant when Q=1 sz=1 ba=00 bb=0 bc=00 V=VPR128.8H esize=@2
+
+:frsqrts Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2329=0b0011101 & b_22=1 & b_21=0 & b_1015=0b001111 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_frsqrts(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.170 FRSQRTS page C7-2400 line 140259 MATCH x0ea0fc00/mask=xbfa0fc00
+# CONSTRUCT x0ea0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2@4
+# AUNIT --inst x0ea0fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+# Vector single-precision and double-precision variant when Q=0 sz=0 ba=00 bb=1 bc=11 V=VPR64.2S esize=@4
+
+:frsqrts Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_31=0 & b_30=0 & b_2329=0b0011101 & b_22=0 & b_21=1 & b_1015=0b111111 & Rd_VPR64.2S & Rn_VPR64.2S & Rm_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_frsqrts(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.170 FRSQRTS page C7-2400 line 140259 MATCH x0ea0fc00/mask=xbfa0fc00
+# CONSTRUCT x4ea0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2@4
+# AUNIT --inst x4ea0fc00/mask=xffe0fc00 --rand sfp --status nopcodeop --comment "nofpround"
+# Vector single-precision and double-precision variant when Q=1 sz=0 ba=00 bb=1 bc=11 V=VPR128.4S esize=@4
+
+:frsqrts Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_31=0 & b_30=1 & b_2329=0b0011101 & b_22=0 & b_21=1 & b_1015=0b111111 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_frsqrts(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.170 FRSQRTS page C7-2400 line 140259 MATCH x0ea0fc00/mask=xbfa0fc00
+# CONSTRUCT x4ee0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_frsqrts/2@8
+# AUNIT --inst x4ee0fc00/mask=xffe0fc00 --rand dfp --status nopcodeop --comment "nofpround"
+# Vector single-precision and double-precision variant when Q=1 sz=1 ba=00 bb=1 bc=11 V=VPR128.2D esize=@8
+
+:frsqrts Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_31=0 & b_30=1 & b_2329=0b0011101 & b_22=1 & b_21=1 & b_1015=0b111111 & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_frsqrts(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.171 FSQRT (vector) page C7-2403 line 140456 MATCH x2ef9f800/mask=xbffffc00
+# CONSTRUCT x2ef9f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1@2
+# AUNIT --inst x2ef9f800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant when Q=0 sz=1 ba=111 esize=2 suf=VPR64.4H
+
+:fsqrt Rd_VPR64.4H, Rn_VPR64.4H
+is b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=1 & b_1021=0b111001111110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_fsqrt(Rn_VPR64.4H, 2:1);
+}
+
+# C7.2.171 FSQRT (vector) page C7-2403 line 140456 MATCH x2ef9f800/mask=xbffffc00
+# CONSTRUCT x6ef9f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1@2
+# AUNIT --inst x6ef9f800/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant when Q=1 sz=1 ba=111 esize=2 suf=VPR128.8H
+
+:fsqrt Rd_VPR128.8H, Rn_VPR128.8H
+is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=1 & b_1021=0b111001111110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_fsqrt(Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.171 FSQRT (vector) page C7-2403 line 140456 MATCH x2ea1f800/mask=xbfbffc00
+# CONSTRUCT x2ea1f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1@4
+# AUNIT --inst x2ea1f800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
+# Single-precision and double-precision variant when Q=0 sz=0 ba=100 esize=4 suf=VPR64.2S
+
+:fsqrt Rd_VPR64.2S, Rn_VPR64.2S
+is b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=0 & b_1021=0b100001111110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_fsqrt(Rn_VPR64.2S, 4:1);
+}
+
+# C7.2.171 FSQRT (vector) page C7-2403 line 140456 MATCH x2ea1f800/mask=xbfbffc00
+# CONSTRUCT x6ea1f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1@4
+# AUNIT --inst x6ea1f800/mask=xfffffc00 --rand sfp --status nopcodeop --comment "nofpround"
+# Single-precision and double-precision variant when Q=1 sz=0 ba=100 esize=4 suf=VPR128.4S
+
+:fsqrt Rd_VPR128.4S, Rn_VPR128.4S
+is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=0 & b_1021=0b100001111110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_fsqrt(Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.171 FSQRT (vector) page C7-2403 line 140456 MATCH x2ea1f800/mask=xbfbffc00
+# CONSTRUCT x6ee1f800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1@8
+# AUNIT --inst x6ee1f800/mask=xfffffc00 --rand dfp --status nopcodeop --comment "nofpround"
+# Single-precision and double-precision variant when Q=1 sz=1 ba=100 esize=8 suf=VPR128.2D
+
+:fsqrt Rd_VPR128.2D, Rn_VPR128.2D
+is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=1 & b_1021=0b100001111110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_fsqrt(Rn_VPR128.2D, 8:1);
+}
+
+# C7.2.172 FSQRT (scalar) page C7-2405 line 140566 MATCH x1e21c000/mask=xff3ffc00
+# CONSTRUCT x1ee1c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =sqrt/1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1
+# AUNIT --inst x1ee1c000/mask=xfffffc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant
+
+:fsqrt Rd_FPR16, Rn_FPR16
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & fpDpOpcode=0x3 & b_1014=0x10 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = sqrt(Rn_FPR16);
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.172 FSQRT (scalar) page C7-2405 line 140566 MATCH x1e21c000/mask=xff3ffc00
+# CONSTRUCT x1e21c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =sqrt/1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1
+# AUNIT --inst x1e21c000/mask=xfffffc00 --rand sfp --status fail --comment "nofpround"
+# Single-precision variant
+
+:fsqrt Rd_FPR32, Rn_FPR32
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & fpDpOpcode=0x3 & b_1014=0x10 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = sqrt(Rn_FPR32);
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.172 FSQRT (scalar) page C7-2405 line 140566 MATCH x1e21c000/mask=xff3ffc00
+# CONSTRUCT x1e61c000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =sqrt/1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_fsqrt/1
+# AUNIT --inst x1e61c000/mask=xfffffc00 --rand dfp --status fail --comment "nofpround"
+# Double-precision variant
+
+:fsqrt Rd_FPR64, Rn_FPR64
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & fpDpOpcode=0x3 & b_1014=0x10 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = sqrt(Rn_FPR64);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.173 FSUB (vector) page C7-2407 line 140666 MATCH x0ea0d400/mask=xbfa0fc00
+# CONSTRUCT x4ee0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f-@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2@8
+# AUNIT --inst x4ee0d400/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
+
+:fsub Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_21=1 & Rm_VPR128.2D & b_1115=0x1a & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ # simd infix Rd_VPR128.2D = Rn_VPR128.2D f- Rm_VPR128.2D on lane size 8
+ Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] f- Rm_VPR128.2D[0,64];
+ Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] f- Rm_VPR128.2D[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.173 FSUB (vector) page C7-2407 line 140666 MATCH x0ea0d400/mask=xbfa0fc00
+# CONSTRUCT x0ea0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2@4
+# AUNIT --inst x0ea0d400/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround"
+
+:fsub Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR64.2S & b_1115=0x1a & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ # simd infix Rd_VPR64.2S = Rn_VPR64.2S f- Rm_VPR64.2S on lane size 4
+ Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] f- Rm_VPR64.2S[0,32];
+ Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] f- Rm_VPR64.2S[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.173 FSUB (vector) page C7-2407 line 140666 MATCH x0ea0d400/mask=xbfa0fc00
+# CONSTRUCT x4ea0d400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2@4
+# AUNIT --inst x4ea0d400/mask=xffe0fc00 --rand sfp --status fail --comment "nofpround"
+
+:fsub Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_21=1 & Rm_VPR128.4S & b_1115=0x1a & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd infix Rd_VPR128.4S = Rn_VPR128.4S f- Rm_VPR128.4S on lane size 4
+ Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] f- Rm_VPR128.4S[0,32];
+ Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] f- Rm_VPR128.4S[32,32];
+ Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] f- Rm_VPR128.4S[64,32];
+ Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] f- Rm_VPR128.4S[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.173 FSUB (vector) page C7-2407 line 140666 MATCH x0ec01400/mask=xbfe0fc00
+# CONSTRUCT x0ec01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f-@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2@2
+# AUNIT --inst x0ec01400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant when Q=0 suf=VPR64.4H
+
+:fsub Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2129=0b001110110 & b_1015=0b000101 & Rd_VPR64.4H & Rn_VPR64.4H & Rm_VPR64.4H & Zd
+{
+ # simd infix Rd_VPR64.4H = Rn_VPR64.4H f- Rm_VPR64.4H on lane size 2
+ Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] f- Rm_VPR64.4H[0,16];
+ Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] f- Rm_VPR64.4H[16,16];
+ Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] f- Rm_VPR64.4H[32,16];
+ Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] f- Rm_VPR64.4H[48,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.173 FSUB (vector) page C7-2407 line 140666 MATCH x0ec01400/mask=xbfe0fc00
+# CONSTRUCT x4ec01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$f-@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2@2
+# AUNIT --inst x4ec01400/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+# Half-precision variant when Q=1 suf=VPR128.8H
+
+:fsub Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2129=0b001110110 & b_1015=0b000101 & Rd_VPR128.8H & Rn_VPR128.8H & Rm_VPR128.8H & Zd
+{
+ # simd infix Rd_VPR128.8H = Rn_VPR128.8H f- Rm_VPR128.8H on lane size 2
+ Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] f- Rm_VPR128.8H[0,16];
+ Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] f- Rm_VPR128.8H[16,16];
+ Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] f- Rm_VPR128.8H[32,16];
+ Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] f- Rm_VPR128.8H[48,16];
+ Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] f- Rm_VPR128.8H[64,16];
+ Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] f- Rm_VPR128.8H[80,16];
+ Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] f- Rm_VPR128.8H[96,16];
+ Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] f- Rm_VPR128.8H[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.174 FSUB (scalar) page C7-2409 line 140785 MATCH x1e203800/mask=xff20fc00
+# CONSTRUCT x1e603800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =f-
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2
+# AUNIT --inst x1e603800/mask=xffe0fc00 --rand dfp --status pass --comment "nofpround"
+
+:fsub Rd_FPR64, Rn_FPR64, Rm_FPR64
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & Rm_FPR64 & b_1215=0x3 & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = Rn_FPR64 f- Rm_FPR64;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.174 FSUB (scalar) page C7-2409 line 140785 MATCH x1e203800/mask=xff20fc00
+# CONSTRUCT x1e203800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =f-
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2
+# AUNIT --inst x1e203800/mask=xffe0fc00 --rand sfp --status pass --comment "nofpround"
+
+:fsub Rd_FPR32, Rn_FPR32, Rm_FPR32
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & Rm_FPR32 & b_1215=0x3 & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = Rn_FPR32 f- Rm_FPR32;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.174 FSUB (scalar) page C7-2409 line 140785 MATCH x1e203800/mask=xff20fc00
+# CONSTRUCT x1ee03800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =f-
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_fsub/2
+# AUNIT --inst x1ee03800/mask=xffe0fc00 --rand hfp --status noqemu --comment "nofpround"
+
+:fsub Rd_FPR16, Rn_FPR16, Rm_FPR16
+is m=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & Rm_FPR16 & b_1215=0x3 & b_1011=2 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = Rn_FPR16 f- Rm_FPR16;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.189 LDNP (SIMD&FP) page C7-2456 line 143778 MATCH x2c400000/mask=x3fc00000
+# CONSTRUCT x2c400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG3 =load ext ARG2 ARG3 4 +:8 =load ext
+# SMACRO(pseudo) ARG1 ARG3 =NEON_ldnp1/1 ARG2 ARG3 =NEON_ldnp2/1
+# AUNIT --inst x2c400000/mask=xffc00000 --status nomem
+
+:ldnp Rt_FPR32, Rt2_FPR32, addrPairIndexed
+is b_3031=0b00 & b_2229=0b10110001 & Rt2_FPR32 & addrPairIndexed & Rt_FPR32 & Zt & Zt2
+{
+ Rt_FPR32 = * addrPairIndexed;
+ zext_zs(Zt); # zero upper 28 bytes of Zt
+ local tmp1:8 = addrPairIndexed + 4;
+ Rt2_FPR32 = * tmp1;
+ zext_zs(Zt2); # zero upper 28 bytes of Zt2
+}
+
+# C7.2.189 LDNP (SIMD&FP) page C7-2456 line 143778 MATCH x2c400000/mask=x3fc00000
+# CONSTRUCT x6c400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG3 =load ext ARG2 ARG3 8 +:8 =load ext
+# SMACRO(pseudo) ARG1 ARG3 =NEON_ldnp1/1 ARG2 ARG3 =NEON_ldnp2/1
+# AUNIT --inst x6c400000/mask=xffc00000 --status nomem
+
+:ldnp Rt_FPR64, Rt2_FPR64, addrPairIndexed
+is b_3031=0b01 & b_2229=0b10110001 & Rt2_FPR64 & addrPairIndexed & Rt_FPR64 & Zt & Zt2
+{
+ Rt_FPR64 = * addrPairIndexed;
+ zext_zd(Zt); # zero upper 24 bytes of Zt
+ local tmp1:8 = addrPairIndexed + 8;
+ Rt2_FPR64 = * tmp1;
+ zext_zd(Zt2); # zero upper 24 bytes of Zt2
+}
+
+# C7.2.189 LDNP (SIMD&FP) page C7-2456 line 143778 MATCH x2c400000/mask=x3fc00000
+# CONSTRUCT xac400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG3 =load ext ARG2 ARG3 16 +:8 =load ext
+# SMACRO(pseudo) ARG1 ARG3 =NEON_ldnp1/1 ARG2 ARG3 =NEON_ldnp2/1
+# AUNIT --inst xac400000/mask=xffc00000 --status nomem
+
+:ldnp Rt_FPR128, Rt2_FPR128, addrPairIndexed
+is b_3031=0b10 & b_2229=0b10110001 & Rt2_FPR128 & addrPairIndexed & Rt_FPR128 & Zt & Zt2
+{
+ Rt_FPR128 = * addrPairIndexed;
+ zext_zq(Zt); # zero upper 16 bytes of Zt
+ local tmp1:8 = addrPairIndexed + 16;
+ Rt2_FPR128 = * tmp1;
+ zext_zq(Zt2); # zero upper 16 bytes of Zt2
+}
+
+# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2cc00000/mask=x3fc00000
+# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2dc00000/mask=x3fc00000
+# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2d400000/mask=x3fc00000
+# C7.2.189 LDNP (SIMD&FP) page C7-2456 line 143778 MATCH x2c400000/mask=x3fc00000
+# CONSTRUCT xac400000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG3 =load ext ARG2 ARG3 16 +:8 =load ext
+# SMACRO(pseudo) ARG1 ARG3 =NEON_ldp1/1 ARG2 ARG3 =NEON_ldp2/1
+# AUNIT --inst xac400000/mask=xfe400000 --status nomem
+
+:ldp Rt_FPR128, Rt2_FPR128, addrPairIndexed
+is b_3031=0b10 & b_2529=0b10110 & b_22=0b1 & Rt2_FPR128 & addrPairIndexed & Rt_FPR128 & Zt & Zt2
+{
+ Rt_FPR128 = * addrPairIndexed;
+ zext_zq(Zt); # zero upper 16 bytes of Zt
+ local tmp1:8 = addrPairIndexed + 16;
+ Rt2_FPR128 = * tmp1;
+ zext_zq(Zt2); # zero upper 16 bytes of Zt2
+}
+
+# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2cc00000/mask=x3fc00000
+# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2dc00000/mask=x3fc00000
+# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2d400000/mask=x3fc00000
+# C7.2.189 LDNP (SIMD&FP) page C7-2456 line 143778 MATCH x2c400000/mask=x3fc00000
+# CONSTRUCT x2c400000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG3 =load ext ARG2 ARG3 4 +:8 =load ext
+# SMACRO(pseudo) ARG1 ARG3 =NEON_ldp1/1 ARG2 ARG3 =NEON_ldp2/1
+# AUNIT --inst x2c400000/mask=xfe400000 --status nomem
+
+:ldp Rt_FPR32, Rt2_FPR32, addrPairIndexed
+is b_3031=0b00 & b_2529=0b10110 & b_22=0b1 & Rt2_FPR32 & addrPairIndexed & Rt_FPR32 & Zt & Zt2
+{
+ Rt_FPR32 = * addrPairIndexed;
+ zext_zs(Zt); # zero upper 28 bytes of Zt
+ local tmp1:8 = addrPairIndexed + 4;
+ Rt2_FPR32 = * tmp1;
+ zext_zs(Zt2); # zero upper 28 bytes of Zt2
+}
+
+# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2cc00000/mask=x3fc00000
+# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2dc00000/mask=x3fc00000
+# C7.2.190 LDP (SIMD&FP) page C7-2458 line 143922 MATCH x2d400000/mask=x3fc00000
+# C7.2.189 LDNP (SIMD&FP) page C7-2456 line 143778 MATCH x2c400000/mask=x3fc00000
+# CONSTRUCT x6c400000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG3 =load ext ARG2 ARG3 8 +:8 =load ext
+# SMACRO(pseudo) ARG1 ARG3 =NEON_ldp1/1 ARG2 ARG3 =NEON_ldp2/1
+# AUNIT --inst x6c400000/mask=xfe400000 --status nomem
+
+:ldp Rt_FPR64, Rt2_FPR64, addrPairIndexed
+is b_3031=0b01 & b_2529=0b10110 & b_22=0b1 & Rt2_FPR64 & addrPairIndexed & Rt_FPR64 & Zt & Zt2
+{
+ Rt_FPR64 = * addrPairIndexed;
+ zext_zd(Zt); # zero upper 24 bytes of Zt
+ local tmp1:8 = addrPairIndexed + 8;
+ Rt2_FPR64 = * tmp1;
+ zext_zd(Zt2); # zero upper 24 bytes of Zt2
+}
+
+# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400400/mask=x3f600c00
+# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400c00/mask=x3f600c00
+# CONSTRUCT x3c400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =load
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
+# AUNIT --inst x3c400400/mask=xffe00400 --status nomem
+# Post- and Pre-index 8-bit variant when size==00 && opc==01 F=FPR8
+
+:ldr Rt_FPR8, addrIndexed
+is b_3031=0b00 & b_2429=0b111100 & b_2223=0b01 & b_21=0 & b_10=1 & Rt_FPR8 & addrIndexed & Zt
+{
+ Rt_FPR8 = * addrIndexed;
+ zext_zb(Zt); # zero upper 31 bytes of Zt
+}
+
+# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400400/mask=x3f600c00
+# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400c00/mask=x3f600c00
+# CONSTRUCT x7c400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =load
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
+# AUNIT --inst x7c400400/mask=xffe00400 --status nomem
+# Post- and Pre-index 16-bit variant when size==01 && opc==01 F=FPR16
+
+:ldr Rt_FPR16, addrIndexed
+is b_3031=0b01 & b_2429=0b111100 & b_2223=0b01 & b_21=0 & b_10=1 & Rt_FPR16 & addrIndexed & Zt
+{
+ Rt_FPR16 = * addrIndexed;
+ zext_zh(Zt); # zero upper 30 bytes of Zt
+}
+
+# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400400/mask=x3f600c00
+# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400c00/mask=x3f600c00
+# CONSTRUCT xbc400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =load
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
+# AUNIT --inst xbc400400/mask=xffe00400 --status nomem
+# Post- and Pre-index 32-bit variant when size==10 && opc==01 F=FPR32
+
+:ldr Rt_FPR32, addrIndexed
+is b_3031=0b10 & b_2429=0b111100 & b_2223=0b01 & b_21=0 & b_10=1 & Rt_FPR32 & addrIndexed & Zt
+{
+ Rt_FPR32 = * addrIndexed;
+ zext_zs(Zt); # zero upper 28 bytes of Zt
+}
+
+# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400400/mask=x3f600c00
+# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400c00/mask=x3f600c00
+# CONSTRUCT xfc400400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =load
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
+# AUNIT --inst xfc400400/mask=xffe00400 --status nomem
+# Post- and Pre-index 64-bit variant when size==11 && opc==01 F=FPR64
+
+:ldr Rt_FPR64, addrIndexed
+is b_3031=0b11 & b_2429=0b111100 & b_2223=0b01 & b_21=0 & b_10=1 & Rt_FPR64 & addrIndexed & Zt
+{
+ Rt_FPR64 = * addrIndexed;
+ zext_zd(Zt); # zero upper 24 bytes of Zt
+}
+
+# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400400/mask=x3f600c00
+# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3c400c00/mask=x3f600c00
+# CONSTRUCT x3cc00400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =load
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
+# AUNIT --inst x3cc00400/mask=xffe00400 --status nomem
+# Post- and Pre-index 128-bit variant when size==00 && opc==11 F=FPR128
+
+:ldr Rt_FPR128, addrIndexed
+is b_3031=0b00 & b_2429=0b111100 & b_2223=0b11 & b_21=0 & b_10=1 & Rt_FPR128 & addrIndexed & Zt
+{
+ Rt_FPR128 = * addrIndexed;
+ zext_zq(Zt); # zero upper 16 bytes of Zt
+}
+
+# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3d400000/mask=x3f400000
+# CONSTRUCT x3d400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =load
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
+# AUNIT --inst x3d400000/mask=xffc00000 --status nomem
+# Unsigned offset 8-bit variant when size == 00 && opc == 01 F=FPR8
+
+:ldr Rt_FPR8, addrUIMM
+is b_3031=0b00 & b_2429=0b111101 & b_2223=0b01 & Rt_FPR8 & addrUIMM & Zt
+{
+ Rt_FPR8 = * addrUIMM;
+ zext_zb(Zt); # zero upper 31 bytes of Zt
+}
+
+# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3d400000/mask=x3f400000
+# CONSTRUCT x7d400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =load
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
+# AUNIT --inst x7d400000/mask=xffc00000 --status nomem
+# Unsigned offset 16-bit variant when size == 01 && opc == 01 F=FPR16
+
+:ldr Rt_FPR16, addrUIMM
+is b_3031=0b01 & b_2429=0b111101 & b_2223=0b01 & Rt_FPR16 & addrUIMM & Zt
+{
+ Rt_FPR16 = * addrUIMM;
+ zext_zh(Zt); # zero upper 30 bytes of Zt
+}
+
+# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3d400000/mask=x3f400000
+# CONSTRUCT xbd400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =load
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
+# AUNIT --inst xbd400000/mask=xffc00000 --status nomem
+# Unsigned offset 32-bit variant when size == 10 && opc == 01 F=FPR32
+
+:ldr Rt_FPR32, addrUIMM
+is b_3031=0b10 & b_2429=0b111101 & b_2223=0b01 & Rt_FPR32 & addrUIMM & Zt
+{
+ Rt_FPR32 = * addrUIMM;
+ zext_zs(Zt); # zero upper 28 bytes of Zt
+}
+
+# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3d400000/mask=x3f400000
+# CONSTRUCT xfd400000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =load
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
+# AUNIT --inst xfd400000/mask=xffc00000 --status nomem
+# Unsigned offset 64-bit variant when size == 11 && opc == 01 F=FPR64
+
+:ldr Rt_FPR64, addrUIMM
+is b_3031=0b11 & b_2429=0b111101 & b_2223=0b01 & Rt_FPR64 & addrUIMM & Zt
+{
+ Rt_FPR64 = * addrUIMM;
+ zext_zd(Zt); # zero upper 24 bytes of Zt
+}
+
+# C7.2.191 LDR (immediate, SIMD&FP) page C7-2462 line 144163 MATCH x3d400000/mask=x3f400000
+# CONSTRUCT x3dc00000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =load
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
+# AUNIT --inst x3dc00000/mask=xffc00000 --status nomem
+# Unsigned offset 128-bit variant when size == 00 && opc == 11 F=FPR128
+
+:ldr Rt_FPR128, addrUIMM
+is b_3031=0b00 & b_2429=0b111101 & b_2223=0b11 & Rt_FPR128 & addrUIMM & Zt
+{
+ Rt_FPR128 = * addrUIMM;
+ zext_zq(Zt); # zero upper 16 bytes of Zt
+}
+
+# C7.2.192 LDR (literal, SIMD&FP) page C7-2466 line 144427 MATCH x1c000000/mask=x3f000000
+# CONSTRUCT x5c000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =load:8
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
+# AUNIT --inst x5c000000/mask=xff000000 --status nomem
+
+:ldr Rt_FPR64, AddrLoc19
+is size.ldstr=1 & b_2729=3 & v=1 & b_2425=0 & AddrLoc19 & Rt_FPR64 & Zt
+{
+ Rt_FPR64 = *:8 AddrLoc19;
+ zext_zd(Zt); # zero upper 24 bytes of Zt
+}
+
+# C7.2.192 LDR (literal, SIMD&FP) page C7-2466 line 144427 MATCH x1c000000/mask=x3f000000
+# CONSTRUCT x9c000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =load:16
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
+# AUNIT --inst x9c000000/mask=xff000000 --status nomem
+
+:ldr Rt_FPR128, AddrLoc19
+is size.ldstr=2 & b_2729=3 & v=1 & b_2425=0 & AddrLoc19 & Rt_FPR128 & Zt
+{
+ Rt_FPR128 = *:16 AddrLoc19;
+ zext_zq(Zt); # zero upper 16 bytes of Zt
+}
+
+# C7.2.192 LDR (literal, SIMD&FP) page C7-2466 line 144427 MATCH x1c000000/mask=x3f000000
+# CONSTRUCT x1c000000/mask=xff000000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =load:4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ldr/1
+# AUNIT --inst x1c000000/mask=xff000000 --status nomem
+
+:ldr Rt_FPR32, AddrLoc19
+is size.ldstr=0 & b_2729=3 & v=1 & b_2425=0 & AddrLoc19 & Rt_FPR32 & Zt
+{
+ Rt_FPR32 = *:4 AddrLoc19;
+ zext_zs(Zt); # zero upper 28 bytes of Zt
+}
+
+# C7.2.178 LDR (register, SIMD&FP) page C7-1411 line 82199 KEEPWITH
+
+extend_amount: "" is b_3031=0b00 & b_23=0 & b_12=0 { export 0:1; }
+extend_amount: " #0" is b_3031=0b00 & b_23=0 & b_12=1 { export 0:1; }
+extend_amount: "" is b_3031=0b01 & b_23=0 & b_12=0 { export 0:1; }
+extend_amount: " #1" is b_3031=0b01 & b_23=0 & b_12=1 { export 1:1; }
+extend_amount: "" is b_3031=0b10 & b_23=0 & b_12=0 { export 0:1; }
+extend_amount: " #2" is b_3031=0b10 & b_23=0 & b_12=1 { export 2:1; }
+extend_amount: "" is b_3031=0b11 & b_23=0 & b_12=0 { export 0:1; }
+extend_amount: " #3" is b_3031=0b11 & b_23=0 & b_12=1 { export 3:1; }
+extend_amount: "" is b_3031=0b00 & b_23=1 & b_12=0 { export 0:1; }
+extend_amount: " #4" is b_3031=0b00 & b_23=1 & b_12=1 { export 4:1; }
+
+extend_spec: ", uxtw" is b_1315=0b010 & Rm_GPR32 { local tmp:8 = zext(Rm_GPR32); export tmp; }
+extend_spec: ", sxtw" is b_1315=0b110 & Rm_GPR32 { local tmp:8 = sext(Rm_GPR32); export tmp; }
+extend_spec: ", sxtx" is b_1315=0b111 & Rm_GPR64 { export Rm_GPR64; }
+extend_spec: ", lsl" is b_1315=0b011 & b_12=1 & Rm_GPR64 { export Rm_GPR64; } # same as uxtx
+extend_spec: "" is b_1315=0b011 & b_12=0 & Rm_GPR64 { export Rm_GPR64; } # same as uxtx
+
+# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00
+# CONSTRUCT x3c600800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load
+# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3
+# AUNIT --inst x3c600800/mask=xffe02c00 --status nomem
+# 8-fsreg,LDR-8-fsreg variant when size == 00 && opc == 01 && option is not 011 bb=b_13 option=0 F=FPR8 G=GPR32
+
+:ldr Rt_FPR8, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]
+is b_3031=0b00 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR8 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zt
+{
+ local tmp1:8 = extend_spec << extend_amount;
+ local tmp2:8 = Rn_GPR64xsp + tmp1;
+ Rt_FPR8 = * tmp2;
+ zext_zb(Zt); # zero upper 31 bytes of Zt
+}
+
+# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00
+# CONSTRUCT x3c602800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load
+# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3
+# AUNIT --inst x3c602800/mask=xffe02c00 --status nomem
+# 8-fsreg,LDR-8-fsreg variant when size == 00 && opc == 01 && option is not 011 bb=b_13 option=1 F=FPR8 G=GPR64
+
+:ldr Rt_FPR8, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]
+is b_3031=0b00 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR8 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zt
+{
+ local tmp1:8 = extend_spec << extend_amount;
+ local tmp2:8 = Rn_GPR64xsp + tmp1;
+ Rt_FPR8 = * tmp2;
+ zext_zb(Zt); # zero upper 31 bytes of Zt
+}
+
+# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00
+# CONSTRUCT x3c606800/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load
+# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3
+# AUNIT --inst x3c606800/mask=xffe0ec00 --status nomem
+# 8-fsreg,LDR-8-fsreg variant when size == 00 && opc == 01 && option is 011 bb=b_1315 option=0b011 F=FPR8 G=GPR64
+
+:ldr Rt_FPR8, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]
+is b_3031=0b00 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_1315=0b011 & b_1011=0b10 & Rt_FPR8 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zt
+{
+ local tmp1:8 = extend_spec << extend_amount;
+ local tmp2:8 = Rn_GPR64xsp + tmp1;
+ Rt_FPR8 = * tmp2;
+ zext_zb(Zt); # zero upper 31 bytes of Zt
+}
+
+# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00
+# CONSTRUCT x7c600800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load
+# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3
+# AUNIT --inst x7c600800/mask=xffe02c00 --status nomem
+# 16-fsreg,LDR-16-fsreg variant when size == 01 && opc == 01 bb=b_13 option=0 F=FPR16 G=GPR32
+
+:ldr Rt_FPR16, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]
+is b_3031=0b01 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR16 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zt
+{
+ local tmp1:8 = extend_spec << extend_amount;
+ local tmp2:8 = Rn_GPR64xsp + tmp1;
+ Rt_FPR16 = * tmp2;
+ zext_zh(Zt); # zero upper 30 bytes of Zt
+}
+
+# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00
+# CONSTRUCT x7c602800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load
+# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3
+# AUNIT --inst x7c602800/mask=xffe02c00 --status nomem
+# 16-fsreg,LDR-16-fsreg variant when size == 01 && opc == 01 bb=b_13 option=1 F=FPR16 G=GPR64
+
+:ldr Rt_FPR16, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]
+is b_3031=0b01 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR16 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zt
+{
+ local tmp1:8 = extend_spec << extend_amount;
+ local tmp2:8 = Rn_GPR64xsp + tmp1;
+ Rt_FPR16 = * tmp2;
+ zext_zh(Zt); # zero upper 30 bytes of Zt
+}
+
+# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00
+# CONSTRUCT xbc600800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load
+# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3
+# AUNIT --inst xbc600800/mask=xffe02c00 --status nomem
+# 32-fsreg,LDR-32-fsreg variant when size == 10 && opc == 01 bb=b_13 option=0 F=FPR32 G=GPR32
+
+:ldr Rt_FPR32, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]
+is b_3031=0b10 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR32 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zt
+{
+ local tmp1:8 = extend_spec << extend_amount;
+ local tmp2:8 = Rn_GPR64xsp + tmp1;
+ Rt_FPR32 = * tmp2;
+ zext_zs(Zt); # zero upper 28 bytes of Zt
+}
+
+# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00
+# CONSTRUCT xbc602800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load
+# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3
+# AUNIT --inst xbc602800/mask=xffe02c00 --status nomem
+# 32-fsreg,LDR-32-fsreg variant when size == 10 && opc == 01 bb=b_13 option=1 F=FPR32 G=GPR64
+
+:ldr Rt_FPR32, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]
+is b_3031=0b10 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR32 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zt
+{
+ local tmp1:8 = extend_spec << extend_amount;
+ local tmp2:8 = Rn_GPR64xsp + tmp1;
+ Rt_FPR32 = * tmp2;
+ zext_zs(Zt); # zero upper 28 bytes of Zt
+}
+
+# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00
+# CONSTRUCT xfc600800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load
+# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3
+# AUNIT --inst xfc600800/mask=xffe02c00 --status nomem
+# 64-fsreg,LDR-64-fsreg variant when size == 11 && opc == 01 bb=b_13 option=0 F=FPR64 G=GPR32
+
+:ldr Rt_FPR64, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]
+is b_3031=0b11 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR64 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zt
+{
+ local tmp1:8 = extend_spec << extend_amount;
+ local tmp2:8 = Rn_GPR64xsp + tmp1;
+ Rt_FPR64 = * tmp2;
+ zext_zd(Zt); # zero upper 24 bytes of Zt
+}
+
+# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00
+# CONSTRUCT xfc602800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load
+# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3
+# AUNIT --inst xfc602800/mask=xffe02c00 --status nomem
+# 64-fsreg,LDR-64-fsreg variant when size == 11 && opc == 01 bb=b_13 option=1 F=FPR64 G=GPR64
+
+:ldr Rt_FPR64, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]
+is b_3031=0b11 & b_2429=0b111100 & b_2223=0b01 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR64 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zt
+{
+ local tmp1:8 = extend_spec << extend_amount;
+ local tmp2:8 = Rn_GPR64xsp + tmp1;
+ Rt_FPR64 = * tmp2;
+ zext_zd(Zt); # zero upper 24 bytes of Zt
+}
+
+# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00
+# CONSTRUCT x3ce00800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load
+# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3
+# AUNIT --inst x3ce00800/mask=xffe02c00 --status nomem
+# 128-fsreg,LDR-128-fsreg variant when size == 00 && opc == 11 bb=b_13 option=0 F=FPR128 G=GPR32
+
+:ldr Rt_FPR128, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]
+is b_3031=0b00 & b_2429=0b111100 & b_2223=0b11 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR128 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zt
+{
+ local tmp1:8 = extend_spec << extend_amount;
+ local tmp2:8 = Rn_GPR64xsp + tmp1;
+ Rt_FPR128 = * tmp2;
+ zext_zq(Zt); # zero upper 16 bytes of Zt
+}
+
+# C7.2.193 LDR (register, SIMD&FP) page C7-2468 line 144528 MATCH x3c600800/mask=x3f600c00
+# CONSTRUCT x3ce02800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =load
+# SMACRO(pseudo) ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_ldr/3
+# AUNIT --inst x3ce02800/mask=xffe02c00 --status nomem
+# 128-fsreg,LDR-128-fsreg variant when size == 00 && opc == 11 bb=b_13 option=1 F=FPR128 G=GPR64
+
+:ldr Rt_FPR128, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]
+is b_3031=0b00 & b_2429=0b111100 & b_2223=0b11 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR128 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zt
+{
+ local tmp1:8 = extend_spec << extend_amount;
+ local tmp2:8 = Rn_GPR64xsp + tmp1;
+ Rt_FPR128 = * tmp2;
+ zext_zq(Zt); # zero upper 16 bytes of Zt
+}
+
+# C7.2.194 LDUR (SIMD&FP) page C7-2471 line 144715 MATCH x3c400000/mask=x3f600c00
+# CONSTRUCT x3cc00000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =load
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ldur/1
+# AUNIT --inst x3cc00000/mask=xffe00c00 --status nomem
+
+:ldur Rt_FPR128, addrIndexed
+is size.ldstr=0 & b_2729=7 & v=1 & b_2425=0 & b_23=1 & b_2222=1 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR128 & Zt
+{
+ Rt_FPR128 = * addrIndexed;
+ zext_zq(Zt); # zero upper 16 bytes of Zt
+}
+
+# C7.2.194 LDUR (SIMD&FP) page C7-2471 line 144715 MATCH x3c400000/mask=x3f600c00
+# CONSTRUCT x7c400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =load
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ldur/1
+# AUNIT --inst x7c400000/mask=xffe00c00 --status nomem
+
+:ldur Rt_FPR16, addrIndexed
+is size.ldstr=1 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR16 & Zt
+{
+ Rt_FPR16 = * addrIndexed;
+ zext_zh(Zt); # zero upper 30 bytes of Zt
+}
+
+# C7.2.194 LDUR (SIMD&FP) page C7-2471 line 144715 MATCH x3c400000/mask=x3f600c00
+# CONSTRUCT xbc400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =load
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ldur/1
+# AUNIT --inst xbc400000/mask=xffe00c00 --status nomem
+
+:ldur Rt_FPR32, addrIndexed
+is size.ldstr=2 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR32 & Zt
+{
+ Rt_FPR32 = * addrIndexed;
+ zext_zs(Zt); # zero upper 28 bytes of Zt
+}
+
+# C7.2.194 LDUR (SIMD&FP) page C7-2471 line 144715 MATCH x3c400000/mask=x3f600c00
+# CONSTRUCT xfc400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =load
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ldur/1
+# AUNIT --inst xfc400000/mask=xffe00c00 --status nomem
+
+:ldur Rt_FPR64, addrIndexed
+is size.ldstr=3 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR64 & Zt
+{
+ Rt_FPR64 = * addrIndexed;
+ zext_zd(Zt); # zero upper 24 bytes of Zt
+}
+
+# C7.2.194 LDUR (SIMD&FP) page C7-2471 line 144715 MATCH x3c400000/mask=x3f600c00
+# CONSTRUCT x3c400000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =load
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ldur/1
+# AUNIT --inst x3c400000/mask=xffe00c00 --status nomem
+
+:ldur Rt_FPR8, addrIndexed
+is size.ldstr=0 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=1 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR8 & Zt
+{
+ Rt_FPR8 = * addrIndexed;
+ zext_zb(Zt); # zero upper 31 bytes of Zt
+}
+
+# C7.2.195 MLA (by element) page C7-2473 line 144842 MATCH x2f000000/mask=xbf00f400
+# CONSTRUCT x2f800000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $* &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@4
+# AUNIT --inst x2f800000/mask=xffc0f400 --status pass
+
+:mla Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & vIndex & Re_VPR128.S & b_1215=0x0 & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp1:4 = Re_VPR128.S.vIndex;
+ # simd infix TMPD1 = Rn_VPR64.2S * tmp1 on lane size 4
+ TMPD1[0,32] = Rn_VPR64.2S[0,32] * tmp1;
+ TMPD1[32,32] = Rn_VPR64.2S[32,32] * tmp1;
+ # simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4
+ Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32];
+ Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.195 MLA (by element) page C7-2473 line 144842 MATCH x2f000000/mask=xbf00f400
+# CONSTRUCT x2f400000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $* &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@2
+# AUNIT --inst x2f400000/mask=xffc0f400 --status pass
+
+:mla Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x0 & b_1010=0 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
+ # simd infix TMPD1 = Rn_VPR64.4H * tmp1 on lane size 2
+ TMPD1[0,16] = Rn_VPR64.4H[0,16] * tmp1;
+ TMPD1[16,16] = Rn_VPR64.4H[16,16] * tmp1;
+ TMPD1[32,16] = Rn_VPR64.4H[32,16] * tmp1;
+ TMPD1[48,16] = Rn_VPR64.4H[48,16] * tmp1;
+ # simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2
+ Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16];
+ Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16];
+ Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16];
+ Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.195 MLA (by element) page C7-2473 line 144842 MATCH x2f000000/mask=xbf00f400
+# CONSTRUCT x6f800000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $* &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@4
+# AUNIT --inst x6f800000/mask=xffc0f400 --status pass
+
+:mla Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x0 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp1:4 = Re_VPR128.S.vIndex;
+ # simd infix TMPQ1 = Rn_VPR128.4S * tmp1 on lane size 4
+ TMPQ1[0,32] = Rn_VPR128.4S[0,32] * tmp1;
+ TMPQ1[32,32] = Rn_VPR128.4S[32,32] * tmp1;
+ TMPQ1[64,32] = Rn_VPR128.4S[64,32] * tmp1;
+ TMPQ1[96,32] = Rn_VPR128.4S[96,32] * tmp1;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.195 MLA (by element) page C7-2473 line 144842 MATCH x2f000000/mask=xbf00f400
+# CONSTRUCT x6f400000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $* &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@2
+# AUNIT --inst x6f400000/mask=xffc0f400 --status pass
+
+:mla Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x0 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
+ # simd infix TMPQ1 = Rn_VPR128.8H * tmp1 on lane size 2
+ TMPQ1[0,16] = Rn_VPR128.8H[0,16] * tmp1;
+ TMPQ1[16,16] = Rn_VPR128.8H[16,16] * tmp1;
+ TMPQ1[32,16] = Rn_VPR128.8H[32,16] * tmp1;
+ TMPQ1[48,16] = Rn_VPR128.8H[48,16] * tmp1;
+ TMPQ1[64,16] = Rn_VPR128.8H[64,16] * tmp1;
+ TMPQ1[80,16] = Rn_VPR128.8H[80,16] * tmp1;
+ TMPQ1[96,16] = Rn_VPR128.8H[96,16] * tmp1;
+ TMPQ1[112,16] = Rn_VPR128.8H[112,16] * tmp1;
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.196 MLA (vector) page C7-2475 line 144975 MATCH x0e209400/mask=xbf20fc00
+# CONSTRUCT x4e209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $*@1 &=$+@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@1
+# AUNIT --inst x4e209400/mask=xffe0fc00 --status pass
+
+:mla Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x12 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.16B * Rm_VPR128.16B on lane size 1
+ TMPQ1[0,8] = Rn_VPR128.16B[0,8] * Rm_VPR128.16B[0,8];
+ TMPQ1[8,8] = Rn_VPR128.16B[8,8] * Rm_VPR128.16B[8,8];
+ TMPQ1[16,8] = Rn_VPR128.16B[16,8] * Rm_VPR128.16B[16,8];
+ TMPQ1[24,8] = Rn_VPR128.16B[24,8] * Rm_VPR128.16B[24,8];
+ TMPQ1[32,8] = Rn_VPR128.16B[32,8] * Rm_VPR128.16B[32,8];
+ TMPQ1[40,8] = Rn_VPR128.16B[40,8] * Rm_VPR128.16B[40,8];
+ TMPQ1[48,8] = Rn_VPR128.16B[48,8] * Rm_VPR128.16B[48,8];
+ TMPQ1[56,8] = Rn_VPR128.16B[56,8] * Rm_VPR128.16B[56,8];
+ TMPQ1[64,8] = Rn_VPR128.16B[64,8] * Rm_VPR128.16B[64,8];
+ TMPQ1[72,8] = Rn_VPR128.16B[72,8] * Rm_VPR128.16B[72,8];
+ TMPQ1[80,8] = Rn_VPR128.16B[80,8] * Rm_VPR128.16B[80,8];
+ TMPQ1[88,8] = Rn_VPR128.16B[88,8] * Rm_VPR128.16B[88,8];
+ TMPQ1[96,8] = Rn_VPR128.16B[96,8] * Rm_VPR128.16B[96,8];
+ TMPQ1[104,8] = Rn_VPR128.16B[104,8] * Rm_VPR128.16B[104,8];
+ TMPQ1[112,8] = Rn_VPR128.16B[112,8] * Rm_VPR128.16B[112,8];
+ TMPQ1[120,8] = Rn_VPR128.16B[120,8] * Rm_VPR128.16B[120,8];
+ # simd infix Rd_VPR128.16B = Rd_VPR128.16B + TMPQ1 on lane size 1
+ Rd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] + TMPQ1[0,8];
+ Rd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] + TMPQ1[8,8];
+ Rd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] + TMPQ1[16,8];
+ Rd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] + TMPQ1[24,8];
+ Rd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] + TMPQ1[32,8];
+ Rd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] + TMPQ1[40,8];
+ Rd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] + TMPQ1[48,8];
+ Rd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] + TMPQ1[56,8];
+ Rd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] + TMPQ1[64,8];
+ Rd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] + TMPQ1[72,8];
+ Rd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] + TMPQ1[80,8];
+ Rd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] + TMPQ1[88,8];
+ Rd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] + TMPQ1[96,8];
+ Rd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] + TMPQ1[104,8];
+ Rd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] + TMPQ1[112,8];
+ Rd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] + TMPQ1[120,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.196 MLA (vector) page C7-2475 line 144975 MATCH x0e209400/mask=xbf20fc00
+# CONSTRUCT x0ea09400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $*@4 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@4
+# AUNIT --inst x0ea09400/mask=xffe0fc00 --status pass
+
+:mla Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x12 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ # simd infix TMPD1 = Rn_VPR64.2S * Rm_VPR64.2S on lane size 4
+ TMPD1[0,32] = Rn_VPR64.2S[0,32] * Rm_VPR64.2S[0,32];
+ TMPD1[32,32] = Rn_VPR64.2S[32,32] * Rm_VPR64.2S[32,32];
+ # simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4
+ Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32];
+ Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.196 MLA (vector) page C7-2475 line 144975 MATCH x0e209400/mask=xbf20fc00
+# CONSTRUCT x0e609400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $*@2 &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@2
+# AUNIT --inst x0e609400/mask=xffe0fc00 --status pass
+
+:mla Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x12 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ # simd infix TMPD1 = Rn_VPR64.4H * Rm_VPR64.4H on lane size 2
+ TMPD1[0,16] = Rn_VPR64.4H[0,16] * Rm_VPR64.4H[0,16];
+ TMPD1[16,16] = Rn_VPR64.4H[16,16] * Rm_VPR64.4H[16,16];
+ TMPD1[32,16] = Rn_VPR64.4H[32,16] * Rm_VPR64.4H[32,16];
+ TMPD1[48,16] = Rn_VPR64.4H[48,16] * Rm_VPR64.4H[48,16];
+ # simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2
+ Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16];
+ Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16];
+ Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16];
+ Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.196 MLA (vector) page C7-2475 line 144975 MATCH x0e209400/mask=xbf20fc00
+# CONSTRUCT x4ea09400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $*@4 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@4
+# AUNIT --inst x4ea09400/mask=xffe0fc00 --status pass
+
+:mla Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x12 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.4S * Rm_VPR128.4S on lane size 4
+ TMPQ1[0,32] = Rn_VPR128.4S[0,32] * Rm_VPR128.4S[0,32];
+ TMPQ1[32,32] = Rn_VPR128.4S[32,32] * Rm_VPR128.4S[32,32];
+ TMPQ1[64,32] = Rn_VPR128.4S[64,32] * Rm_VPR128.4S[64,32];
+ TMPQ1[96,32] = Rn_VPR128.4S[96,32] * Rm_VPR128.4S[96,32];
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.196 MLA (vector) page C7-2475 line 144975 MATCH x0e209400/mask=xbf20fc00
+# CONSTRUCT x0e209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $*@1 &=$+@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@1
+# AUNIT --inst x0e209400/mask=xffe0fc00 --status pass
+
+:mla Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x12 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ # simd infix TMPD1 = Rn_VPR64.8B * Rm_VPR64.8B on lane size 1
+ TMPD1[0,8] = Rn_VPR64.8B[0,8] * Rm_VPR64.8B[0,8];
+ TMPD1[8,8] = Rn_VPR64.8B[8,8] * Rm_VPR64.8B[8,8];
+ TMPD1[16,8] = Rn_VPR64.8B[16,8] * Rm_VPR64.8B[16,8];
+ TMPD1[24,8] = Rn_VPR64.8B[24,8] * Rm_VPR64.8B[24,8];
+ TMPD1[32,8] = Rn_VPR64.8B[32,8] * Rm_VPR64.8B[32,8];
+ TMPD1[40,8] = Rn_VPR64.8B[40,8] * Rm_VPR64.8B[40,8];
+ TMPD1[48,8] = Rn_VPR64.8B[48,8] * Rm_VPR64.8B[48,8];
+ TMPD1[56,8] = Rn_VPR64.8B[56,8] * Rm_VPR64.8B[56,8];
+ # simd infix Rd_VPR64.8B = Rd_VPR64.8B + TMPD1 on lane size 1
+ Rd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] + TMPD1[0,8];
+ Rd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] + TMPD1[8,8];
+ Rd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] + TMPD1[16,8];
+ Rd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] + TMPD1[24,8];
+ Rd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] + TMPD1[32,8];
+ Rd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] + TMPD1[40,8];
+ Rd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] + TMPD1[48,8];
+ Rd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] + TMPD1[56,8];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.196 MLA (vector) page C7-2475 line 144975 MATCH x0e209400/mask=xbf20fc00
+# CONSTRUCT x4e609400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $*@2 &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mla/3@2
+# AUNIT --inst x4e609400/mask=xffe0fc00 --status pass
+
+:mla Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x12 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.8H * Rm_VPR128.8H on lane size 2
+ TMPQ1[0,16] = Rn_VPR128.8H[0,16] * Rm_VPR128.8H[0,16];
+ TMPQ1[16,16] = Rn_VPR128.8H[16,16] * Rm_VPR128.8H[16,16];
+ TMPQ1[32,16] = Rn_VPR128.8H[32,16] * Rm_VPR128.8H[32,16];
+ TMPQ1[48,16] = Rn_VPR128.8H[48,16] * Rm_VPR128.8H[48,16];
+ TMPQ1[64,16] = Rn_VPR128.8H[64,16] * Rm_VPR128.8H[64,16];
+ TMPQ1[80,16] = Rn_VPR128.8H[80,16] * Rm_VPR128.8H[80,16];
+ TMPQ1[96,16] = Rn_VPR128.8H[96,16] * Rm_VPR128.8H[96,16];
+ TMPQ1[112,16] = Rn_VPR128.8H[112,16] * Rm_VPR128.8H[112,16];
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.197 MLS (by element) page C7-2477 line 145080 MATCH x2f004000/mask=xbf00f400
+# CONSTRUCT x2f804000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $* &=$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@4
+# AUNIT --inst x2f804000/mask=xffc0f400 --status pass
+
+:mls Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x4 & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp1:4 = Re_VPR128.S.vIndex;
+ # simd infix TMPD1 = Rn_VPR64.2S * tmp1 on lane size 4
+ TMPD1[0,32] = Rn_VPR64.2S[0,32] * tmp1;
+ TMPD1[32,32] = Rn_VPR64.2S[32,32] * tmp1;
+ # simd infix Rd_VPR64.2S = Rd_VPR64.2S - TMPD1 on lane size 4
+ Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] - TMPD1[0,32];
+ Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] - TMPD1[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.197 MLS (by element) page C7-2477 line 145080 MATCH x2f004000/mask=xbf00f400
+# CONSTRUCT x2f404000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $* &=$-@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@2
+# AUNIT --inst x2f404000/mask=xffc0f400 --status pass
+
+:mls Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x4 & b_1010=0 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
+ # simd infix TMPD1 = Rn_VPR64.4H * tmp1 on lane size 2
+ TMPD1[0,16] = Rn_VPR64.4H[0,16] * tmp1;
+ TMPD1[16,16] = Rn_VPR64.4H[16,16] * tmp1;
+ TMPD1[32,16] = Rn_VPR64.4H[32,16] * tmp1;
+ TMPD1[48,16] = Rn_VPR64.4H[48,16] * tmp1;
+ # simd infix Rd_VPR64.4H = Rd_VPR64.4H - TMPD1 on lane size 2
+ Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] - TMPD1[0,16];
+ Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] - TMPD1[16,16];
+ Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] - TMPD1[32,16];
+ Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] - TMPD1[48,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.197 MLS (by element) page C7-2477 line 145080 MATCH x2f004000/mask=xbf00f400
+# CONSTRUCT x6f804000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $* &=$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@4
+# AUNIT --inst x6f804000/mask=xffc0f400 --status pass
+
+:mls Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x4 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp1:4 = Re_VPR128.S.vIndex;
+ # simd infix TMPQ1 = Rn_VPR128.4S * tmp1 on lane size 4
+ TMPQ1[0,32] = Rn_VPR128.4S[0,32] * tmp1;
+ TMPQ1[32,32] = Rn_VPR128.4S[32,32] * tmp1;
+ TMPQ1[64,32] = Rn_VPR128.4S[64,32] * tmp1;
+ TMPQ1[96,32] = Rn_VPR128.4S[96,32] * tmp1;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ1 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ1[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ1[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ1[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ1[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.197 MLS (by element) page C7-2477 line 145080 MATCH x2f004000/mask=xbf00f400
+# CONSTRUCT x6f404000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $* &=$-@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@2
+# AUNIT --inst x6f404000/mask=xffc0f400 --status pass
+
+:mls Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x4 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
+ # simd infix TMPQ1 = Rn_VPR128.8H * tmp1 on lane size 2
+ TMPQ1[0,16] = Rn_VPR128.8H[0,16] * tmp1;
+ TMPQ1[16,16] = Rn_VPR128.8H[16,16] * tmp1;
+ TMPQ1[32,16] = Rn_VPR128.8H[32,16] * tmp1;
+ TMPQ1[48,16] = Rn_VPR128.8H[48,16] * tmp1;
+ TMPQ1[64,16] = Rn_VPR128.8H[64,16] * tmp1;
+ TMPQ1[80,16] = Rn_VPR128.8H[80,16] * tmp1;
+ TMPQ1[96,16] = Rn_VPR128.8H[96,16] * tmp1;
+ TMPQ1[112,16] = Rn_VPR128.8H[112,16] * tmp1;
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H - TMPQ1 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] - TMPQ1[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] - TMPQ1[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] - TMPQ1[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] - TMPQ1[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] - TMPQ1[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] - TMPQ1[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] - TMPQ1[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] - TMPQ1[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.198 MLS (vector) page C7-2479 line 145213 MATCH x2e209400/mask=xbf20fc00
+# CONSTRUCT x6e209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $*@1 &=$-@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@1
+# AUNIT --inst x6e209400/mask=xffe0fc00 --status pass
+
+:mls Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x12 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.16B * Rm_VPR128.16B on lane size 1
+ TMPQ1[0,8] = Rn_VPR128.16B[0,8] * Rm_VPR128.16B[0,8];
+ TMPQ1[8,8] = Rn_VPR128.16B[8,8] * Rm_VPR128.16B[8,8];
+ TMPQ1[16,8] = Rn_VPR128.16B[16,8] * Rm_VPR128.16B[16,8];
+ TMPQ1[24,8] = Rn_VPR128.16B[24,8] * Rm_VPR128.16B[24,8];
+ TMPQ1[32,8] = Rn_VPR128.16B[32,8] * Rm_VPR128.16B[32,8];
+ TMPQ1[40,8] = Rn_VPR128.16B[40,8] * Rm_VPR128.16B[40,8];
+ TMPQ1[48,8] = Rn_VPR128.16B[48,8] * Rm_VPR128.16B[48,8];
+ TMPQ1[56,8] = Rn_VPR128.16B[56,8] * Rm_VPR128.16B[56,8];
+ TMPQ1[64,8] = Rn_VPR128.16B[64,8] * Rm_VPR128.16B[64,8];
+ TMPQ1[72,8] = Rn_VPR128.16B[72,8] * Rm_VPR128.16B[72,8];
+ TMPQ1[80,8] = Rn_VPR128.16B[80,8] * Rm_VPR128.16B[80,8];
+ TMPQ1[88,8] = Rn_VPR128.16B[88,8] * Rm_VPR128.16B[88,8];
+ TMPQ1[96,8] = Rn_VPR128.16B[96,8] * Rm_VPR128.16B[96,8];
+ TMPQ1[104,8] = Rn_VPR128.16B[104,8] * Rm_VPR128.16B[104,8];
+ TMPQ1[112,8] = Rn_VPR128.16B[112,8] * Rm_VPR128.16B[112,8];
+ TMPQ1[120,8] = Rn_VPR128.16B[120,8] * Rm_VPR128.16B[120,8];
+ # simd infix Rd_VPR128.16B = Rd_VPR128.16B - TMPQ1 on lane size 1
+ Rd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] - TMPQ1[0,8];
+ Rd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] - TMPQ1[8,8];
+ Rd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] - TMPQ1[16,8];
+ Rd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] - TMPQ1[24,8];
+ Rd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] - TMPQ1[32,8];
+ Rd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] - TMPQ1[40,8];
+ Rd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] - TMPQ1[48,8];
+ Rd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] - TMPQ1[56,8];
+ Rd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] - TMPQ1[64,8];
+ Rd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] - TMPQ1[72,8];
+ Rd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] - TMPQ1[80,8];
+ Rd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] - TMPQ1[88,8];
+ Rd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] - TMPQ1[96,8];
+ Rd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] - TMPQ1[104,8];
+ Rd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] - TMPQ1[112,8];
+ Rd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] - TMPQ1[120,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.198 MLS (vector) page C7-2479 line 145213 MATCH x2e209400/mask=xbf20fc00
+# CONSTRUCT x2ea09400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $*@4 &=$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@4
+# AUNIT --inst x2ea09400/mask=xffe0fc00 --status pass
+
+:mls Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x12 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ # simd infix TMPD1 = Rn_VPR64.2S * Rm_VPR64.2S on lane size 4
+ TMPD1[0,32] = Rn_VPR64.2S[0,32] * Rm_VPR64.2S[0,32];
+ TMPD1[32,32] = Rn_VPR64.2S[32,32] * Rm_VPR64.2S[32,32];
+ # simd infix Rd_VPR64.2S = Rd_VPR64.2S - TMPD1 on lane size 4
+ Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] - TMPD1[0,32];
+ Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] - TMPD1[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.198 MLS (vector) page C7-2479 line 145213 MATCH x2e209400/mask=xbf20fc00
+# CONSTRUCT x2e609400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $*@2 &=$-@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@2
+# AUNIT --inst x2e609400/mask=xffe0fc00 --status pass
+
+:mls Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x12 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ # simd infix TMPD1 = Rn_VPR64.4H * Rm_VPR64.4H on lane size 2
+ TMPD1[0,16] = Rn_VPR64.4H[0,16] * Rm_VPR64.4H[0,16];
+ TMPD1[16,16] = Rn_VPR64.4H[16,16] * Rm_VPR64.4H[16,16];
+ TMPD1[32,16] = Rn_VPR64.4H[32,16] * Rm_VPR64.4H[32,16];
+ TMPD1[48,16] = Rn_VPR64.4H[48,16] * Rm_VPR64.4H[48,16];
+ # simd infix Rd_VPR64.4H = Rd_VPR64.4H - TMPD1 on lane size 2
+ Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] - TMPD1[0,16];
+ Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] - TMPD1[16,16];
+ Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] - TMPD1[32,16];
+ Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] - TMPD1[48,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.198 MLS (vector) page C7-2479 line 145213 MATCH x2e209400/mask=xbf20fc00
+# CONSTRUCT x6ea09400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $*@4 &=$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@4
+# AUNIT --inst x6ea09400/mask=xffe0fc00 --status pass
+
+:mls Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x12 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.4S * Rm_VPR128.4S on lane size 4
+ TMPQ1[0,32] = Rn_VPR128.4S[0,32] * Rm_VPR128.4S[0,32];
+ TMPQ1[32,32] = Rn_VPR128.4S[32,32] * Rm_VPR128.4S[32,32];
+ TMPQ1[64,32] = Rn_VPR128.4S[64,32] * Rm_VPR128.4S[64,32];
+ TMPQ1[96,32] = Rn_VPR128.4S[96,32] * Rm_VPR128.4S[96,32];
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ1 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ1[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ1[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ1[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ1[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.198 MLS (vector) page C7-2479 line 145213 MATCH x2e209400/mask=xbf20fc00
+# CONSTRUCT x2e209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $*@1 &=$-@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@1
+# AUNIT --inst x2e209400/mask=xffe0fc00 --status pass
+
+:mls Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x12 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ # simd infix TMPD1 = Rn_VPR64.8B * Rm_VPR64.8B on lane size 1
+ TMPD1[0,8] = Rn_VPR64.8B[0,8] * Rm_VPR64.8B[0,8];
+ TMPD1[8,8] = Rn_VPR64.8B[8,8] * Rm_VPR64.8B[8,8];
+ TMPD1[16,8] = Rn_VPR64.8B[16,8] * Rm_VPR64.8B[16,8];
+ TMPD1[24,8] = Rn_VPR64.8B[24,8] * Rm_VPR64.8B[24,8];
+ TMPD1[32,8] = Rn_VPR64.8B[32,8] * Rm_VPR64.8B[32,8];
+ TMPD1[40,8] = Rn_VPR64.8B[40,8] * Rm_VPR64.8B[40,8];
+ TMPD1[48,8] = Rn_VPR64.8B[48,8] * Rm_VPR64.8B[48,8];
+ TMPD1[56,8] = Rn_VPR64.8B[56,8] * Rm_VPR64.8B[56,8];
+ # simd infix Rd_VPR64.8B = Rd_VPR64.8B - TMPD1 on lane size 1
+ Rd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] - TMPD1[0,8];
+ Rd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] - TMPD1[8,8];
+ Rd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] - TMPD1[16,8];
+ Rd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] - TMPD1[24,8];
+ Rd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] - TMPD1[32,8];
+ Rd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] - TMPD1[40,8];
+ Rd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] - TMPD1[48,8];
+ Rd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] - TMPD1[56,8];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.198 MLS (vector) page C7-2479 line 145213 MATCH x2e209400/mask=xbf20fc00
+# CONSTRUCT x6e609400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $*@2 &=$-@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_mls/3@2
+# AUNIT --inst x6e609400/mask=xffe0fc00 --status pass
+
+:mls Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x12 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.8H * Rm_VPR128.8H on lane size 2
+ TMPQ1[0,16] = Rn_VPR128.8H[0,16] * Rm_VPR128.8H[0,16];
+ TMPQ1[16,16] = Rn_VPR128.8H[16,16] * Rm_VPR128.8H[16,16];
+ TMPQ1[32,16] = Rn_VPR128.8H[32,16] * Rm_VPR128.8H[32,16];
+ TMPQ1[48,16] = Rn_VPR128.8H[48,16] * Rm_VPR128.8H[48,16];
+ TMPQ1[64,16] = Rn_VPR128.8H[64,16] * Rm_VPR128.8H[64,16];
+ TMPQ1[80,16] = Rn_VPR128.8H[80,16] * Rm_VPR128.8H[80,16];
+ TMPQ1[96,16] = Rn_VPR128.8H[96,16] * Rm_VPR128.8H[96,16];
+ TMPQ1[112,16] = Rn_VPR128.8H[112,16] * Rm_VPR128.8H[112,16];
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H - TMPQ1 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] - TMPQ1[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] - TMPQ1[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] - TMPQ1[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] - TMPQ1[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] - TMPQ1[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] - TMPQ1[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] - TMPQ1[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] - TMPQ1[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.200 MOV (element) page C7-2483 line 145410 MATCH x6e000400/mask=xffe08400
+# C7.2.175 INS (element) page C7-2411 line 140892 MATCH x6e000400/mask=xffe08400
+# CONSTRUCT x6e010400/mask=xffe18400 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO Rd_VPR128 ARG2 imm_neon_uimm4:1 &=$copy
+# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm4:1 &=NEON_mov/3@1
+# AUNIT --inst x6e010400/mask=xffe18400 --status pass
+
+:mov Rd_VPR128.B.imm_neon_uimm4, Rn_VPR128.B.immN_neon_uimm4
+is b_3131=0 & q=1 & b_29=1 & b_2428=0xe & b_2123=0 & Rd_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & Rn_VPR128.B.immN_neon_uimm4 & immN_neon_uimm4 & b_1010=1 & Rn_VPR128 & Rd_VPR128 & Zd
+{
+ # simd element Rn_VPR128[immN_neon_uimm4] lane size 1
+ local tmp1:1 = Rn_VPR128.B.immN_neon_uimm4;
+ # simd copy Rd_VPR128 element imm_neon_uimm4:1 = tmp1 (lane size 1)
+ Rd_VPR128.B.imm_neon_uimm4 = tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.200 MOV (element) page C7-2483 line 145410 MATCH x6e000400/mask=xffe08400
+# C7.2.175 INS (element) page C7-2411 line 140892 MATCH x6e000400/mask=xffe08400
+# CONSTRUCT x6e080400/mask=xffef8400 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO Rd_VPR128 ARG2 imm_neon_uimm1:1 &=$copy
+# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm1:1 &=NEON_mov/3@8
+# AUNIT --inst x6e080400/mask=xffef8400 --status pass
+
+:mov Rd_VPR128.D.imm_neon_uimm1, Rn_VPR128.D.immN_neon_uimm1
+is b_3131=0 & q=1 & b_29=1 & b_2428=0xe & b_2123=0 & Rd_VPR128.D.imm_neon_uimm1 & b_1619=0x8 & b_1515=0 & Rn_VPR128.D.immN_neon_uimm1 & immN_neon_uimm1 & Imm4 & b_1010=1 & Rn_VPR128 & Rd_VPR128 & Zd
+{
+ # simd element Rn_VPR128[immN_neon_uimm1] lane size 8
+ local tmp1:8 = Rn_VPR128.D.immN_neon_uimm1;
+ # simd copy Rd_VPR128 element imm_neon_uimm1:1 = tmp1 (lane size 8)
+ Rd_VPR128.D.imm_neon_uimm1 = tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.200 MOV (element) page C7-2483 line 145410 MATCH x6e000400/mask=xffe08400
+# C7.2.175 INS (element) page C7-2411 line 140892 MATCH x6e000400/mask=xffe08400
+# CONSTRUCT x6e020400/mask=xffe38400 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO Rd_VPR128 ARG2 imm_neon_uimm3:1 &=$copy
+# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm3:1 &=NEON_mov/3@2
+# AUNIT --inst x6e020400/mask=xffe38400 --status pass
+
+:mov Rd_VPR128.H.imm_neon_uimm3, Rn_VPR128.H.immN_neon_uimm3
+is b_3131=0 & q=1 & b_29=1 & b_2428=0xe & b_2123=0 & Rd_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & Rn_VPR128.H.immN_neon_uimm3 & immN_neon_uimm3 & Imm4 & b_1010=1 & Rn_VPR128 & Rd_VPR128 & Zd
+{
+ # simd element Rn_VPR128[immN_neon_uimm3] lane size 2
+ local tmp1:2 = Rn_VPR128.H.immN_neon_uimm3;
+ # simd copy Rd_VPR128 element imm_neon_uimm3:1 = tmp1 (lane size 2)
+ Rd_VPR128.H.imm_neon_uimm3 = tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.200 MOV (element) page C7-2483 line 145410 MATCH x6e000400/mask=xffe08400
+# C7.2.175 INS (element) page C7-2411 line 140892 MATCH x6e000400/mask=xffe08400
+# CONSTRUCT x6e040400/mask=xffe78400 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO Rd_VPR128 ARG2 imm_neon_uimm2:1 &=$copy
+# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm2:1 &=NEON_mov/3@4
+# AUNIT --inst x6e040400/mask=xffe78400 --status pass
+
+:mov Rd_VPR128.S.imm_neon_uimm2, Rn_VPR128.S.immN_neon_uimm2
+is b_3131=0 & q=1 & b_29=1 & b_2428=0xe & b_2123=0 & Rd_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & Rn_VPR128.S.immN_neon_uimm2 & immN_neon_uimm2 & Imm4 & b_1010=1 & Rn_VPR128 & Rd_VPR128 & Zd
+{
+ # simd element Rn_VPR128[immN_neon_uimm2] lane size 4
+ local tmp1:4 = Rn_VPR128.S.immN_neon_uimm2;
+ # simd copy Rd_VPR128 element imm_neon_uimm2:1 = tmp1 (lane size 4)
+ Rd_VPR128.S.imm_neon_uimm2 = tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.201 MOV (from general) page C7-2485 line 145507 MATCH x4e001c00/mask=xffe0fc00
+# C7.2.176 INS (general) page C7-2413 line 141002 MATCH x4e001c00/mask=xffe0fc00
+# CONSTRUCT x4e011c00/mask=xffe1fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO Rd_VPR128 ARG2[0]:1 imm_neon_uimm4:1 &=$copy
+# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm4:1 &=NEON_mov/3@1
+# AUNIT --inst x4e011c00/mask=xffe1fc00 --status pass
+
+:mov Rd_VPR128.B.imm_neon_uimm4, Rn_GPR32
+is b_3131=0 & q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rd_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x3 & b_1010=1 & Rn_GPR32 & Rd_VPR128 & Zd
+{
+ local tmp1:1 = Rn_GPR32[0,8];
+ # simd copy Rd_VPR128 element imm_neon_uimm4:1 = tmp1 (lane size 1)
+ Rd_VPR128.B.imm_neon_uimm4 = tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.201 MOV (from general) page C7-2485 line 145507 MATCH x4e001c00/mask=xffe0fc00
+# C7.2.176 INS (general) page C7-2413 line 141002 MATCH x4e001c00/mask=xffe0fc00
+# CONSTRUCT x4e081c00/mask=xffeffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO Rd_VPR128 ARG2 imm_neon_uimm1:1 &=$copy
+# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm1:1 &=NEON_mov/3@8
+# AUNIT --inst x4e081c00/mask=xffeffc00 --status pass
+
+:mov Rd_VPR128.D.imm_neon_uimm1, Rn_GPR64
+is b_3131=0 & q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rd_VPR128.D.imm_neon_uimm1 & b_1619=0x8 & b_1515=0 & imm4=0x3 & b_1010=1 & Rn_GPR64 & Rd_VPR128 & Zd
+{
+ # simd copy Rd_VPR128 element imm_neon_uimm1:1 = Rn_GPR64 (lane size 8)
+ Rd_VPR128.D.imm_neon_uimm1 = Rn_GPR64;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.201 MOV (from general) page C7-2485 line 145507 MATCH x4e001c00/mask=xffe0fc00
+# C7.2.176 INS (general) page C7-2413 line 141002 MATCH x4e001c00/mask=xffe0fc00
+# CONSTRUCT x4e021c00/mask=xffe3fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO Rd_VPR128 ARG2[0]:2 imm_neon_uimm3:1 &=$copy
+# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm3:1 &=NEON_mov/3@2
+# AUNIT --inst x4e021c00/mask=xffe3fc00 --status pass
+
+:mov Rd_VPR128.H.imm_neon_uimm3, Rn_GPR32
+is b_3131=0 & q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rd_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x3 & b_1010=1 & Rn_GPR32 & Rd_VPR128 & Zd
+{
+ local tmp1:2 = Rn_GPR32[0,16];
+ # simd copy Rd_VPR128 element imm_neon_uimm3:1 = tmp1 (lane size 2)
+ Rd_VPR128.H.imm_neon_uimm3 = tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.201 MOV (from general) page C7-2485 line 145507 MATCH x4e001c00/mask=xffe0fc00
+# C7.2.176 INS (general) page C7-2413 line 141002 MATCH x4e001c00/mask=xffe0fc00
+# CONSTRUCT x4e041c00/mask=xffe7fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO(force-primitive) Rd_VPR128 ARG2 imm_neon_uimm2:1 &=$copy
+# SMACRO(pseudo) Rd_VPR128 ARG2 imm_neon_uimm2:1 &=NEON_mov/3@2
+# AUNIT --inst x4e041c00/mask=xffe7fc00 --status pass
+
+:mov Rd_VPR128.S.imm_neon_uimm2, Rn_GPR32
+is b_3131=0 & q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rd_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & imm4=0x3 & b_1010=1 & Rn_GPR32 & Rd_VPR128 & Zd
+{
+ # simd copy Rd_VPR128 element imm_neon_uimm2:1 = Rn_GPR32 (lane size 4)
+ Rd_VPR128.S.imm_neon_uimm2 = Rn_GPR32;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.202 MOV (vector) page C7-2487 line 145604 MATCH x0ea01c00/mask=xbfe0fc00
+# C7.2.213 ORR (vector, register) page C7-2509 line 146837 MATCH x0ea01c00/mask=xbfe0fc00
+# CONSTRUCT x4ea01c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =
+# SMACRO(pseudo) ARG1 ARG2 =NEON_mov/1@1
+# AUNIT --inst x4ea01c00/mask=xffe0fc00 --status pass
+
+:mov Rd_VPR128.16B, Rn_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Rn=Rm & Zd
+{
+ Rd_VPR128.16B = Rn_VPR128.16B;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.202 MOV (vector) page C7-2487 line 145604 MATCH x0ea01c00/mask=xbfe0fc00
+# C7.2.213 ORR (vector, register) page C7-2509 line 146837 MATCH x0ea01c00/mask=xbfe0fc00
+# CONSTRUCT x0ea01c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =
+# SMACRO(pseudo) ARG1 ARG2 =NEON_mov/1@1
+# AUNIT --inst x0ea01c00/mask=xffe0fc00 --status pass
+
+:mov Rd_VPR64.8B, Rn_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Rn=Rm & Zd
+{
+ Rd_VPR64.8B = Rn_VPR64.8B;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.203 MOV (to general) page C7-2488 line 145671 MATCH x0e003c00/mask=xbfe3fc00
+# C7.2.371 UMOV page C7-2868 line 167415 MATCH x0e003c00/mask=xbfe0fc00
+# CONSTRUCT x0e043c00/mask=xffe7fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO(force-primitive) ARG1 ARG2 =
+# SMACRO(pseudo) ARG1 ARG2 =NEON_mov/1@4
+# AUNIT --inst x0e043c00/mask=xffe7fc00 --status pass
+
+:mov Rd_GPR32, Rn_VPR128.S.imm_neon_uimm2
+is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & imm4=0x7 & b_1010=1 & Rn_VPR128 & Rd_GPR32 & Rd_GPR64 & Rd_VPR128
+{
+ # simd element Rn_VPR128[imm_neon_uimm2] lane size 4
+ local tmp1:4 = Rn_VPR128.S.imm_neon_uimm2;
+ Rd_GPR32 = tmp1;
+ zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
+}
+
+# C7.2.203 MOV (to general) page C7-2488 line 145671 MATCH x0e003c00/mask=xbfe3fc00
+# C7.2.371 UMOV page C7-2868 line 167415 MATCH x0e003c00/mask=xbfe0fc00
+# CONSTRUCT x4e083c00/mask=xffeffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =
+# SMACRO(pseudo) ARG1 ARG2 =NEON_mov/1@8
+# AUNIT --inst x4e083c00/mask=xffeffc00 --status pass
+
+:mov Rd_GPR64, Rn_VPR128.D.imm_neon_uimm1
+is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.D.imm_neon_uimm1 & b_1619=0x8 & b_1515=0 & imm4=0x7 & b_1010=1 & Rn_VPR128 & Rd_GPR64
+{
+ # simd element Rn_VPR128[imm_neon_uimm1] lane size 8
+ local tmp1:8 = Rn_VPR128.D.imm_neon_uimm1;
+ Rd_GPR64 = tmp1;
+}
+
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00
+# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x2f00e400/mask=xbf80fc00
+# CONSTRUCT x2f00e400/mask=xfff8fc00 MATCHED 3 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =
+# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1
+# AUNIT --inst x2f00e400/mask=xfff8fc00 --status pass
+# MOVI 64-bit scalar variant when datasize=64 q == 0 && op == 1 && cmode == 1110
+
+:movi Rd_FPR64, Imm_neon_uimm8Shift
+is b_31=0 & b_30=0 & b_29=1 & b_1928=0b0111100000 & b_1215=0b1110 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = Imm_neon_uimm8Shift:8;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x0f00e400/mask=xbf80fc00
+# CONSTRUCT x4f00e400/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2:1 &=$dup
+# SMACRO(pseudo) ARG1 ARG2:1 =NEON_movi/1@1
+# AUNIT --inst x4f00e400/mask=xfff8fc00 --status pass
+# MOVI 8-bit variant when datasize=128 q == 1 && op == 0 && cmode == 0b1110
+
+:movi Rd_VPR128.16B, Imm_neon_uimm8Shift
+is b_31=0 & b_30=1 & b_29=0 & b_1928=0b0111100000 & b_1215=0b1110 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR128.16B & Zd
+{
+ # simd duplicate Rd_VPR128.16B = all elements Imm_neon_uimm8Shift:1 (lane size 1)
+ Rd_VPR128.16B[0,8] = Imm_neon_uimm8Shift:1;
+ Rd_VPR128.16B[8,8] = Imm_neon_uimm8Shift:1;
+ Rd_VPR128.16B[16,8] = Imm_neon_uimm8Shift:1;
+ Rd_VPR128.16B[24,8] = Imm_neon_uimm8Shift:1;
+ Rd_VPR128.16B[32,8] = Imm_neon_uimm8Shift:1;
+ Rd_VPR128.16B[40,8] = Imm_neon_uimm8Shift:1;
+ Rd_VPR128.16B[48,8] = Imm_neon_uimm8Shift:1;
+ Rd_VPR128.16B[56,8] = Imm_neon_uimm8Shift:1;
+ Rd_VPR128.16B[64,8] = Imm_neon_uimm8Shift:1;
+ Rd_VPR128.16B[72,8] = Imm_neon_uimm8Shift:1;
+ Rd_VPR128.16B[80,8] = Imm_neon_uimm8Shift:1;
+ Rd_VPR128.16B[88,8] = Imm_neon_uimm8Shift:1;
+ Rd_VPR128.16B[96,8] = Imm_neon_uimm8Shift:1;
+ Rd_VPR128.16B[104,8] = Imm_neon_uimm8Shift:1;
+ Rd_VPR128.16B[112,8] = Imm_neon_uimm8Shift:1;
+ Rd_VPR128.16B[120,8] = Imm_neon_uimm8Shift:1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00
+# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x2f00e400/mask=xbf80fc00
+# CONSTRUCT x6f00e400/mask=xfff8fc00 MATCHED 3 DOCUMENTED OPCODES
+# SMACRO(force-primitive) ARG1 ARG2 =var:8 &=$dup
+# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@8
+# AUNIT --inst x6f00e400/mask=xfff8fc00 --status pass
+# MOVI 64-bit vector variant when datasize=128 q == 1 && op == 1 && cmode == 1110
+
+:movi Rd_VPR128.2D, Imm_neon_uimm8Shift
+is b_31=0 & b_30=1 & b_29=1 & b_1928=0b0111100000 & b_1215=0b1110 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR128.2D & Zd
+{
+ local tmp1:8 = Imm_neon_uimm8Shift;
+ # simd duplicate Rd_VPR128.2D = all elements tmp1 (lane size 8)
+ Rd_VPR128.2D[0,64] = tmp1;
+ Rd_VPR128.2D[64,64] = tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x0f00e400/mask=xbf80fc00
+# CONSTRUCT x0f00e400/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =
+# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@1
+# AUNIT --inst x0f00e400/mask=xfff8fc00 --status pass
+# MOVI 8-bit variant when datasize=64 q == 0 && op == 0 && cmode == 1110
+
+:movi Rd_VPR64.8B, Imm_neon_uimm8Shift
+is b_31=0 & b_30=0 & b_29=0 & b_1928=0b0111100000 & b_1215=0b1110 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = Imm_neon_uimm8Shift:8;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00
+# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00
+# CONSTRUCT x0f000400/mask=xfff89c00 MATCHED 3 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =
+# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@4
+# AUNIT --inst x0f000400/mask=xfff89c00 --status pass
+# MOVI 32-bit shifted immediate variant when datasize=64 q == 0 && op == 0 && cmode == 0xx0
+
+:movi Rd_VPR64.2S, Imm_neon_uimm8Shift
+is b_31=0 & b_30=0 & b_29=0 & b_1928=0b0111100000 & b_15=0 & b_12=0 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = Imm_neon_uimm8Shift:8;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.256 SHRN, SHRN2 page C7-2587 line 151244 MATCH x0f008400/mask=xbf80fc00
+# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00
+# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00
+# CONSTRUCT x0f008400/mask=xfff8dc00 MATCHED 4 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =
+# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@2
+# AUNIT --inst x0f008400/mask=xfff8dc00 --status pass
+# MOVI 16-bit shifted immediate variant when datasize=64 q == 0 && op == 0 && cmode == 10x0
+
+:movi Rd_VPR64.4H, Imm_neon_uimm8Shift
+is b_31=0 & b_30=0 & b_29=0 & b_1928=0b0111100000 & b_1415=0b10 & b_12=0 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = Imm_neon_uimm8Shift:8;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00
+# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00
+# CONSTRUCT x4f000400/mask=xfff89c00 MATCHED 3 DOCUMENTED OPCODES
+# SMACRO(force-primitive) ARG1 ARG2:4 &=$dup
+# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@4
+# AUNIT --inst x4f000400/mask=xfff89c00 --status pass
+# MOVI 32-bit shifted immediate variant when datasize=128 q == 1 && op == 0 && cmode == 0xx0
+
+:movi Rd_VPR128.4S, Imm_neon_uimm8Shift
+is b_31=0 & b_30=1 & b_29=0 & b_1928=0b0111100000 & b_15=0 & b_12=0 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR128.4S & Zd
+{
+ # simd duplicate Rd_VPR128.4S = all elements Imm_neon_uimm8Shift:4 (lane size 4)
+ Rd_VPR128.4S[0,32] = Imm_neon_uimm8Shift:4;
+ Rd_VPR128.4S[32,32] = Imm_neon_uimm8Shift:4;
+ Rd_VPR128.4S[64,32] = Imm_neon_uimm8Shift:4;
+ Rd_VPR128.4S[96,32] = Imm_neon_uimm8Shift:4;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.256 SHRN, SHRN2 page C7-2587 line 151244 MATCH x0f008400/mask=xbf80fc00
+# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00
+# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00
+# CONSTRUCT x4f008400/mask=xfff8dc00 MATCHED 4 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2:2 &=$dup
+# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@2
+# AUNIT --inst x4f008400/mask=xfff8dc00 --status pass
+# MOVI 16-bit shifted immediate variant when datasize=128 q == 1 && op == 0 && cmode == 10x0
+
+:movi Rd_VPR128.8H, Imm_neon_uimm8Shift
+is b_31=0 & b_30=1 & b_29=0 & b_1928=0b0111100000 & b_1415=0b10 & b_12=0 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR128.8H & Zd
+{
+ # simd duplicate Rd_VPR128.8H = all elements Imm_neon_uimm8Shift:2 (lane size 2)
+ Rd_VPR128.8H[0,16] = Imm_neon_uimm8Shift:2;
+ Rd_VPR128.8H[16,16] = Imm_neon_uimm8Shift:2;
+ Rd_VPR128.8H[32,16] = Imm_neon_uimm8Shift:2;
+ Rd_VPR128.8H[48,16] = Imm_neon_uimm8Shift:2;
+ Rd_VPR128.8H[64,16] = Imm_neon_uimm8Shift:2;
+ Rd_VPR128.8H[80,16] = Imm_neon_uimm8Shift:2;
+ Rd_VPR128.8H[96,16] = Imm_neon_uimm8Shift:2;
+ Rd_VPR128.8H[112,16] = Imm_neon_uimm8Shift:2;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.212 ORR (vector, immediate) page C7-2507 line 146708 MATCH x0f001400/mask=xbff81c00
+# CONSTRUCT x0f00c400/mask=xfff8ec00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =
+# SMACRO(pseudo) ARG1 ARG2 =NEON_movi/1@4
+# AUNIT --inst x0f00c400/mask=xfff8ec00 --status pass
+# MOVI 32-bit shifting ones variant when datasize=64 q == 0 && op == 0 && cmode == 110x
+
+:movi Rd_VPR64.2S, Imm_neon_uimm8Shift
+is b_31=0 & b_30=0 & b_29=0 & b_1928=0b0111100000 & b_1315=0b110 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = Imm_neon_uimm8Shift:8;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.212 ORR (vector, immediate) page C7-2507 line 146708 MATCH x0f001400/mask=xbff81c00
+# CONSTRUCT x4f00c400/mask=xfff8ec00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2:4 &=$dup
+# SMACRO(pseudo) ARG1 ARG2:4 =NEON_movi/1@4
+# AUNIT --inst x4f00c400/mask=xfff8ec00 --status pass
+# MOVI 32-bit shifting ones variant when datasize=128 q == 1 && op == 0 && cmode == 110x
+
+:movi Rd_VPR128.4S, Imm_neon_uimm8Shift
+is b_31=0 & b_30=1 & b_29=0 & b_1928=0b0111100000 & b_1315=0b110 & b_1011=0b01 & Imm_neon_uimm8Shift & Rd_VPR128.4S & Zd
+{
+ # simd duplicate Rd_VPR128.4S = all elements Imm_neon_uimm8Shift:4 (lane size 4)
+ Rd_VPR128.4S[0,32] = Imm_neon_uimm8Shift:4;
+ Rd_VPR128.4S[32,32] = Imm_neon_uimm8Shift:4;
+ Rd_VPR128.4S[64,32] = Imm_neon_uimm8Shift:4;
+ Rd_VPR128.4S[96,32] = Imm_neon_uimm8Shift:4;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.205 MUL (by element) page C7-2493 line 145949 MATCH x0f008000/mask=xbf00f400
+# CONSTRUCT x0f808000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@4
+# AUNIT --inst x0f808000/mask=xffc0f400 --status pass
+
+:mul Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x8 & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp1:4 = Re_VPR128.S.vIndex;
+ # simd infix Rd_VPR64.2S = Rn_VPR64.2S * tmp1 on lane size 4
+ Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] * tmp1;
+ Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] * tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.205 MUL (by element) page C7-2493 line 145949 MATCH x0f008000/mask=xbf00f400
+# CONSTRUCT x0f408000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@2
+# AUNIT --inst x0f408000/mask=xffc0f400 --status pass
+
+:mul Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x8 & b_1010=0 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
+ # simd infix Rd_VPR64.4H = Rn_VPR64.4H * tmp1 on lane size 2
+ Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] * tmp1;
+ Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] * tmp1;
+ Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] * tmp1;
+ Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] * tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.205 MUL (by element) page C7-2493 line 145949 MATCH x0f008000/mask=xbf00f400
+# CONSTRUCT x4f808000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(force-primitive) ARG1 ARG2 ARG3 =$*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@4
+# AUNIT --inst x4f808000/mask=xffc0f400 --status pass
+
+:mul Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x8 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp1:4 = Re_VPR128.S.vIndex;
+ # simd infix Rd_VPR128.4S = Rn_VPR128.4S * tmp1 on lane size 4
+ Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] * tmp1;
+ Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] * tmp1;
+ Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] * tmp1;
+ Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] * tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.205 MUL (by element) page C7-2493 line 145949 MATCH x0f008000/mask=xbf00f400
+# CONSTRUCT x4f408000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@2
+# AUNIT --inst x4f408000/mask=xffc0f400 --status pass
+
+:mul Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x8 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
+ # simd infix Rd_VPR128.8H = Rn_VPR128.8H * tmp1 on lane size 2
+ Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] * tmp1;
+ Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] * tmp1;
+ Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] * tmp1;
+ Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] * tmp1;
+ Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] * tmp1;
+ Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] * tmp1;
+ Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] * tmp1;
+ Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] * tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.206 MUL (vector) page C7-2495 line 146079 MATCH x0e209c00/mask=xbf20fc00
+# CONSTRUCT x4e209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$*@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@1
+# AUNIT --inst x4e209c00/mask=xffe0fc00 --status pass
+
+:mul Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x13 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ # simd infix Rd_VPR128.16B = Rn_VPR128.16B * Rm_VPR128.16B on lane size 1
+ Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] * Rm_VPR128.16B[0,8];
+ Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] * Rm_VPR128.16B[8,8];
+ Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] * Rm_VPR128.16B[16,8];
+ Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] * Rm_VPR128.16B[24,8];
+ Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] * Rm_VPR128.16B[32,8];
+ Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] * Rm_VPR128.16B[40,8];
+ Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] * Rm_VPR128.16B[48,8];
+ Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] * Rm_VPR128.16B[56,8];
+ Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] * Rm_VPR128.16B[64,8];
+ Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] * Rm_VPR128.16B[72,8];
+ Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] * Rm_VPR128.16B[80,8];
+ Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] * Rm_VPR128.16B[88,8];
+ Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] * Rm_VPR128.16B[96,8];
+ Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] * Rm_VPR128.16B[104,8];
+ Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] * Rm_VPR128.16B[112,8];
+ Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] * Rm_VPR128.16B[120,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.206 MUL (vector) page C7-2495 line 146079 MATCH x0e209c00/mask=xbf20fc00
+# CONSTRUCT x0ea09c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$*@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@4
+# AUNIT --inst x0ea09c00/mask=xffe0fc00 --status pass
+
+:mul Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x13 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ # simd infix Rd_VPR64.2S = Rn_VPR64.2S * Rm_VPR64.2S on lane size 4
+ Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] * Rm_VPR64.2S[0,32];
+ Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] * Rm_VPR64.2S[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.206 MUL (vector) page C7-2495 line 146079 MATCH x0e209c00/mask=xbf20fc00
+# CONSTRUCT x0e609c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$*@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@2
+# AUNIT --inst x0e609c00/mask=xffe0fc00 --status pass
+
+:mul Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x13 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ # simd infix Rd_VPR64.4H = Rn_VPR64.4H * Rm_VPR64.4H on lane size 2
+ Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] * Rm_VPR64.4H[0,16];
+ Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] * Rm_VPR64.4H[16,16];
+ Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] * Rm_VPR64.4H[32,16];
+ Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] * Rm_VPR64.4H[48,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.206 MUL (vector) page C7-2495 line 146079 MATCH x0e209c00/mask=xbf20fc00
+# CONSTRUCT x4ea09c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$*@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@4
+# AUNIT --inst x4ea09c00/mask=xffe0fc00 --status pass
+
+:mul Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x13 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd infix Rd_VPR128.4S = Rn_VPR128.4S * Rm_VPR128.4S on lane size 4
+ Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] * Rm_VPR128.4S[0,32];
+ Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] * Rm_VPR128.4S[32,32];
+ Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] * Rm_VPR128.4S[64,32];
+ Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] * Rm_VPR128.4S[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.206 MUL (vector) page C7-2495 line 146079 MATCH x0e209c00/mask=xbf20fc00
+# CONSTRUCT x0e209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$*@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@1
+# AUNIT --inst x0e209c00/mask=xffe0fc00 --status pass
+
+:mul Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x13 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ # simd infix Rd_VPR64.8B = Rn_VPR64.8B * Rm_VPR64.8B on lane size 1
+ Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] * Rm_VPR64.8B[0,8];
+ Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] * Rm_VPR64.8B[8,8];
+ Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] * Rm_VPR64.8B[16,8];
+ Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] * Rm_VPR64.8B[24,8];
+ Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] * Rm_VPR64.8B[32,8];
+ Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] * Rm_VPR64.8B[40,8];
+ Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] * Rm_VPR64.8B[48,8];
+ Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] * Rm_VPR64.8B[56,8];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.206 MUL (vector) page C7-2495 line 146079 MATCH x0e209c00/mask=xbf20fc00
+# CONSTRUCT x4e609c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$*@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_mul/2@2
+# AUNIT --inst x4e609c00/mask=xffe0fc00 --status pass
+
+:mul Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x13 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ # simd infix Rd_VPR128.8H = Rn_VPR128.8H * Rm_VPR128.8H on lane size 2
+ Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] * Rm_VPR128.8H[0,16];
+ Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] * Rm_VPR128.8H[16,16];
+ Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] * Rm_VPR128.8H[32,16];
+ Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] * Rm_VPR128.8H[48,16];
+ Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] * Rm_VPR128.8H[64,16];
+ Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] * Rm_VPR128.8H[80,16];
+ Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] * Rm_VPR128.8H[96,16];
+ Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] * Rm_VPR128.8H[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.207 MVN page C7-2497 line 146183 MATCH x2e205800/mask=xbffffc00
+# C7.2.210 NOT page C7-2503 line 146536 MATCH x2e205800/mask=xbffffc00
+# CONSTRUCT x6e205800/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$~@1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_mvn/1@1
+# AUNIT --inst x6e205800/mask=xfffffc00 --status pass
+
+:mvn Rd_VPR128.16B, Rn_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=16 & b_1216=5 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ # simd unary Rd_VPR128.16B = ~(Rn_VPR128.16B) on lane size 1
+ Rd_VPR128.16B[0,8] = ~(Rn_VPR128.16B[0,8]);
+ Rd_VPR128.16B[8,8] = ~(Rn_VPR128.16B[8,8]);
+ Rd_VPR128.16B[16,8] = ~(Rn_VPR128.16B[16,8]);
+ Rd_VPR128.16B[24,8] = ~(Rn_VPR128.16B[24,8]);
+ Rd_VPR128.16B[32,8] = ~(Rn_VPR128.16B[32,8]);
+ Rd_VPR128.16B[40,8] = ~(Rn_VPR128.16B[40,8]);
+ Rd_VPR128.16B[48,8] = ~(Rn_VPR128.16B[48,8]);
+ Rd_VPR128.16B[56,8] = ~(Rn_VPR128.16B[56,8]);
+ Rd_VPR128.16B[64,8] = ~(Rn_VPR128.16B[64,8]);
+ Rd_VPR128.16B[72,8] = ~(Rn_VPR128.16B[72,8]);
+ Rd_VPR128.16B[80,8] = ~(Rn_VPR128.16B[80,8]);
+ Rd_VPR128.16B[88,8] = ~(Rn_VPR128.16B[88,8]);
+ Rd_VPR128.16B[96,8] = ~(Rn_VPR128.16B[96,8]);
+ Rd_VPR128.16B[104,8] = ~(Rn_VPR128.16B[104,8]);
+ Rd_VPR128.16B[112,8] = ~(Rn_VPR128.16B[112,8]);
+ Rd_VPR128.16B[120,8] = ~(Rn_VPR128.16B[120,8]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.207 MVN page C7-2497 line 146183 MATCH x2e205800/mask=xbffffc00
+# C7.2.210 NOT page C7-2503 line 146536 MATCH x2e205800/mask=xbffffc00
+# CONSTRUCT x2e205800/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$~@1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_mvn/1@1
+# AUNIT --inst x2e205800/mask=xfffffc00 --status pass
+
+:mvn Rd_VPR64.8B, Rn_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=16 & b_1216=5 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ # simd unary Rd_VPR64.8B = ~(Rn_VPR64.8B) on lane size 1
+ Rd_VPR64.8B[0,8] = ~(Rn_VPR64.8B[0,8]);
+ Rd_VPR64.8B[8,8] = ~(Rn_VPR64.8B[8,8]);
+ Rd_VPR64.8B[16,8] = ~(Rn_VPR64.8B[16,8]);
+ Rd_VPR64.8B[24,8] = ~(Rn_VPR64.8B[24,8]);
+ Rd_VPR64.8B[32,8] = ~(Rn_VPR64.8B[32,8]);
+ Rd_VPR64.8B[40,8] = ~(Rn_VPR64.8B[40,8]);
+ Rd_VPR64.8B[48,8] = ~(Rn_VPR64.8B[48,8]);
+ Rd_VPR64.8B[56,8] = ~(Rn_VPR64.8B[56,8]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00
+# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00
+# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00
+# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00
+# CONSTRUCT x2f000400/mask=xfff89c00 MATCHED 6 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2:4 ~ &=$dup
+# SMACRO(pseudo) ARG1 ARG2:4 =NEON_mvni/1@4
+# AUNIT --inst x2f000400/mask=xfff89c00 --status pass
+
+:mvni Rd_VPR64.2S, Imm_neon_uimm8Shift
+is b_3131=0 & q=0 & b_29=1 & b_2428=0xf & b_1923=0x0 & b_1515=0 & Imm_neon_uimm8Shift & b_1012=1 & Rd_VPR64.2S & Zd
+{
+ local tmp1:4 = ~ Imm_neon_uimm8Shift:4;
+ # simd duplicate Rd_VPR64.2S = all elements tmp1 (lane size 4)
+ Rd_VPR64.2S[0,32] = tmp1;
+ Rd_VPR64.2S[32,32] = tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x2f008400/mask=xbf80fc00
+# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00
+# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00
+# CONSTRUCT x2f008400/mask=xfff8dc00 MATCHED 5 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2:2 ~ &=$dup
+# SMACRO(pseudo) ARG1 ARG2:2 =NEON_mvni/1@2
+# AUNIT --inst x2f008400/mask=xfff8dc00 --status pass
+
+:mvni Rd_VPR64.4H, Imm_neon_uimm8Shift
+is b_3131=0 & q=0 & b_29=1 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1415=2 & b_1012=1 & Rd_VPR64.4H & Zd
+{
+ local tmp1:2 = ~ Imm_neon_uimm8Shift:2;
+ # simd duplicate Rd_VPR64.4H = all elements tmp1 (lane size 2)
+ Rd_VPR64.4H[0,16] = tmp1;
+ Rd_VPR64.4H[16,16] = tmp1;
+ Rd_VPR64.4H[32,16] = tmp1;
+ Rd_VPR64.4H[48,16] = tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00
+# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00
+# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00
+# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00
+# CONSTRUCT x6f000400/mask=xfff89c00 MATCHED 6 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2:4 ~ &=$dup
+# SMACRO(pseudo) ARG1 ARG2:4 =NEON_mvni/1@4
+# AUNIT --inst x6f000400/mask=xfff89c00 --status pass
+
+:mvni Rd_VPR128.4S, Imm_neon_uimm8Shift
+is b_3131=0 & q=1 & b_29=1 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1515=0 & b_1012=1 & Rd_VPR128.4S & Zd
+{
+ local tmp1:4 = ~ Imm_neon_uimm8Shift:4;
+ # simd duplicate Rd_VPR128.4S = all elements tmp1 (lane size 4)
+ Rd_VPR128.4S[0,32] = tmp1;
+ Rd_VPR128.4S[32,32] = tmp1;
+ Rd_VPR128.4S[64,32] = tmp1;
+ Rd_VPR128.4S[96,32] = tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x2f008400/mask=xbf80fc00
+# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00
+# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00
+# CONSTRUCT x6f008400/mask=xfff8dc00 MATCHED 5 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2:2 ~ &=$dup
+# SMACRO(pseudo) ARG1 ARG2:2 =NEON_mvni/1@2
+# AUNIT --inst x6f008400/mask=xfff8dc00 --status pass
+
+:mvni Rd_VPR128.8H, Imm_neon_uimm8Shift
+is b_3131=0 & q=1 & b_29=1 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1415=2 & b_1012=1 & Rd_VPR128.8H & Zd
+{
+ local tmp1:2 = ~ Imm_neon_uimm8Shift:2;
+ # simd duplicate Rd_VPR128.8H = all elements tmp1 (lane size 2)
+ Rd_VPR128.8H[0,16] = tmp1;
+ Rd_VPR128.8H[16,16] = tmp1;
+ Rd_VPR128.8H[32,16] = tmp1;
+ Rd_VPR128.8H[48,16] = tmp1;
+ Rd_VPR128.8H[64,16] = tmp1;
+ Rd_VPR128.8H[80,16] = tmp1;
+ Rd_VPR128.8H[96,16] = tmp1;
+ Rd_VPR128.8H[112,16] = tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00
+# C7.2.20 BIC (vector, immediate) page C7-2048 line 119572 MATCH x2f001400/mask=xbff81c00
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# CONSTRUCT x2f00c400/mask=xfff8ec00 MATCHED 3 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2:4 ~ &=$dup
+# SMACRO(pseudo) ARG1 ARG2:4 =NEON_mvni/1@4
+# AUNIT --inst x2f00c400/mask=xfff8ec00 --status pass
+
+:mvni Rd_VPR64.2S, Imm_neon_uimm8Shift
+is b_3131=0 & q=0 & b_29=1 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1315=6 & b_1011=1 & Rd_VPR64.2S & Zd
+{
+ local tmp1:4 = ~ Imm_neon_uimm8Shift:4;
+ # simd duplicate Rd_VPR64.2S = all elements tmp1 (lane size 4)
+ Rd_VPR64.2S[0,32] = tmp1;
+ Rd_VPR64.2S[32,32] = tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.208 MVNI page C7-2498 line 146251 MATCH x2f000400/mask=xbff80c00
+# C7.2.20 BIC (vector, immediate) page C7-2048 line 119572 MATCH x2f001400/mask=xbff81c00
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# CONSTRUCT x6f00c400/mask=xfff8ec00 MATCHED 3 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2:4 ~ &=$dup
+# SMACRO(pseudo) ARG1 ARG2:4 =NEON_mvni/1@4
+# AUNIT --inst x6f00c400/mask=xfff8ec00 --status pass
+
+:mvni Rd_VPR128.4S, Imm_neon_uimm8Shift
+is b_3131=0 & q=1 & b_29=1 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1315=6 & b_1011=1 & Rd_VPR128.4S & Zd
+{
+ local tmp1:4 = ~ Imm_neon_uimm8Shift:4;
+ # simd duplicate Rd_VPR128.4S = all elements tmp1 (lane size 4)
+ Rd_VPR128.4S[0,32] = tmp1;
+ Rd_VPR128.4S[32,32] = tmp1;
+ Rd_VPR128.4S[64,32] = tmp1;
+ Rd_VPR128.4S[96,32] = tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.209 NEG (vector) page C7-2501 line 146404 MATCH x7e20b800/mask=xff3ffc00
+# CONSTRUCT x7ee0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =2comp
+# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1
+# AUNIT --inst x7ee0b800/mask=xfffffc00 --status pass
+
+:neg Rd_VPR64, Rn_VPR64
+is b_3131=0 & q=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR64 & Rd_VPR64 & Zd
+{
+ Rd_VPR64 = - Rn_VPR64;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.209 NEG (vector) page C7-2501 line 146404 MATCH x2e20b800/mask=xbf3ffc00
+# CONSTRUCT x2e20b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@1
+# AUNIT --inst x2e20b800/mask=xfffffc00 --status nopcodeop
+
+:neg Rd_VPR64.8B, Rn_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_neg(Rn_VPR64.8B, 1:1);
+}
+
+# C7.2.209 NEG (vector) page C7-2501 line 146404 MATCH x2e20b800/mask=xbf3ffc00
+# CONSTRUCT x6e20b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@1
+# AUNIT --inst x6e20b800/mask=xfffffc00 --status nopcodeop
+
+:neg Rd_VPR128.16B, Rn_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_neg(Rn_VPR128.16B, 1:1);
+}
+
+# C7.2.209 NEG (vector) page C7-2501 line 146404 MATCH x2e20b800/mask=xbf3ffc00
+# CONSTRUCT x2e60b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@2
+# AUNIT --inst x2e60b800/mask=xfffffc00 --status nopcodeop
+
+:neg Rd_VPR64.4H, Rn_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_neg(Rn_VPR64.4H, 2:1);
+}
+
+# C7.2.209 NEG (vector) page C7-2501 line 146404 MATCH x2e20b800/mask=xbf3ffc00
+# CONSTRUCT x6e60b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@2
+# AUNIT --inst x6e60b800/mask=xfffffc00 --status nopcodeop
+
+:neg Rd_VPR128.8H, Rn_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_neg(Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.209 NEG (vector) page C7-2501 line 146404 MATCH x2e20b800/mask=xbf3ffc00
+# CONSTRUCT x2ea0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@4
+# AUNIT --inst x2ea0b800/mask=xfffffc00 --status nopcodeop
+
+:neg Rd_VPR64.2S, Rn_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_neg(Rn_VPR64.2S, 4:1);
+}
+
+# C7.2.209 NEG (vector) page C7-2501 line 146404 MATCH x2e20b800/mask=xbf3ffc00
+# CONSTRUCT x6ea0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@4
+# AUNIT --inst x6ea0b800/mask=xfffffc00 --status nopcodeop
+
+:neg Rd_VPR128.4S, Rn_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_neg(Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.209 NEG (vector) page C7-2501 line 146404 MATCH x2e20b800/mask=xbf3ffc00
+# CONSTRUCT x6ee0b800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_neg/1@8
+# AUNIT --inst x6ee0b800/mask=xfffffc00 --status nopcodeop
+
+:neg Rd_VPR128.2D, Rn_VPR128.2D
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_1721=0x10 & b_1216=0xb & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_neg(Rn_VPR128.2D, 8:1);
+}
+
+# C7.2.211 ORN (vector) page C7-2505 line 146624 MATCH x0ee01c00/mask=xbfe0fc00
+# CONSTRUCT x4ee01c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $~@1 =$|@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_orn/2@1
+# AUNIT --inst x4ee01c00/mask=xffe0fc00 --status pass
+
+:orn Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ # simd unary TMPQ1 = ~(Rm_VPR128.16B) on lane size 1
+ TMPQ1[0,8] = ~(Rm_VPR128.16B[0,8]);
+ TMPQ1[8,8] = ~(Rm_VPR128.16B[8,8]);
+ TMPQ1[16,8] = ~(Rm_VPR128.16B[16,8]);
+ TMPQ1[24,8] = ~(Rm_VPR128.16B[24,8]);
+ TMPQ1[32,8] = ~(Rm_VPR128.16B[32,8]);
+ TMPQ1[40,8] = ~(Rm_VPR128.16B[40,8]);
+ TMPQ1[48,8] = ~(Rm_VPR128.16B[48,8]);
+ TMPQ1[56,8] = ~(Rm_VPR128.16B[56,8]);
+ TMPQ1[64,8] = ~(Rm_VPR128.16B[64,8]);
+ TMPQ1[72,8] = ~(Rm_VPR128.16B[72,8]);
+ TMPQ1[80,8] = ~(Rm_VPR128.16B[80,8]);
+ TMPQ1[88,8] = ~(Rm_VPR128.16B[88,8]);
+ TMPQ1[96,8] = ~(Rm_VPR128.16B[96,8]);
+ TMPQ1[104,8] = ~(Rm_VPR128.16B[104,8]);
+ TMPQ1[112,8] = ~(Rm_VPR128.16B[112,8]);
+ TMPQ1[120,8] = ~(Rm_VPR128.16B[120,8]);
+ # simd infix Rd_VPR128.16B = Rn_VPR128.16B | TMPQ1 on lane size 1
+ Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] | TMPQ1[0,8];
+ Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] | TMPQ1[8,8];
+ Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] | TMPQ1[16,8];
+ Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] | TMPQ1[24,8];
+ Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] | TMPQ1[32,8];
+ Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] | TMPQ1[40,8];
+ Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] | TMPQ1[48,8];
+ Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] | TMPQ1[56,8];
+ Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] | TMPQ1[64,8];
+ Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] | TMPQ1[72,8];
+ Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] | TMPQ1[80,8];
+ Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] | TMPQ1[88,8];
+ Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] | TMPQ1[96,8];
+ Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] | TMPQ1[104,8];
+ Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] | TMPQ1[112,8];
+ Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] | TMPQ1[120,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.211 ORN (vector) page C7-2505 line 146624 MATCH x0ee01c00/mask=xbfe0fc00
+# CONSTRUCT x0ee01c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $~@1 =$|@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_orn/2@1
+# AUNIT --inst x0ee01c00/mask=xffe0fc00 --status pass
+
+:orn Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ # simd unary TMPD1 = ~(Rm_VPR64.8B) on lane size 1
+ TMPD1[0,8] = ~(Rm_VPR64.8B[0,8]);
+ TMPD1[8,8] = ~(Rm_VPR64.8B[8,8]);
+ TMPD1[16,8] = ~(Rm_VPR64.8B[16,8]);
+ TMPD1[24,8] = ~(Rm_VPR64.8B[24,8]);
+ TMPD1[32,8] = ~(Rm_VPR64.8B[32,8]);
+ TMPD1[40,8] = ~(Rm_VPR64.8B[40,8]);
+ TMPD1[48,8] = ~(Rm_VPR64.8B[48,8]);
+ TMPD1[56,8] = ~(Rm_VPR64.8B[56,8]);
+ # simd infix Rd_VPR64.8B = Rn_VPR64.8B | TMPD1 on lane size 1
+ Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] | TMPD1[0,8];
+ Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] | TMPD1[8,8];
+ Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] | TMPD1[16,8];
+ Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] | TMPD1[24,8];
+ Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] | TMPD1[32,8];
+ Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] | TMPD1[40,8];
+ Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] | TMPD1[48,8];
+ Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] | TMPD1[56,8];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.212 ORR (vector, immediate) page C7-2507 line 146708 MATCH x0f001400/mask=xbff81c00
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00
+# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00
+# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00
+# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00
+# CONSTRUCT x0f001400/mask=xfff89c00 MATCHED 6 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2:4 &=$|@4
+# SMACRO(pseudo) ARG1 ARG2:4 &=NEON_orn/2@4
+# AUNIT --inst x0f001400/mask=xfff89c00 --status pass
+
+:orr Rd_VPR64.2S, Imm_neon_uimm8Shift
+is b_3131=0 & q=0 & b_29=0 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1515=0 & b_1012=5 & Rd_VPR64.2S & Zd
+{
+ # simd infix Rd_VPR64.2S = Rd_VPR64.2S | Imm_neon_uimm8Shift:4 on lane size 4
+ Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] | Imm_neon_uimm8Shift:4;
+ Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] | Imm_neon_uimm8Shift:4;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.212 ORR (vector, immediate) page C7-2507 line 146708 MATCH x0f001400/mask=xbff81c00
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x0f009400/mask=xbf80fc00
+# CONSTRUCT x0f009400/mask=xfff8dc00 MATCHED 3 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2:2 &=$|@2
+# SMACRO(pseudo) ARG1 ARG2:2 &=NEON_orn/2@2
+# AUNIT --inst x0f009400/mask=xfff8dc00 --status pass
+
+:orr Rd_VPR64.4H, Imm_neon_uimm8Shift
+is b_3131=0 & q=0 & b_29=0 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1415=2 & b_1012=5 & Rd_VPR64.4H & Zd
+{
+ # simd infix Rd_VPR64.4H = Rd_VPR64.4H | Imm_neon_uimm8Shift:2 on lane size 2
+ Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] | Imm_neon_uimm8Shift:2;
+ Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] | Imm_neon_uimm8Shift:2;
+ Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] | Imm_neon_uimm8Shift:2;
+ Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] | Imm_neon_uimm8Shift:2;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.212 ORR (vector, immediate) page C7-2507 line 146708 MATCH x0f001400/mask=xbff81c00
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00
+# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00
+# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00
+# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00
+# CONSTRUCT x4f001400/mask=xfff89c00 MATCHED 6 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2:4 &=$|
+# SMACRO(pseudo) ARG1 ARG2:4 &=NEON_orn/2@4
+# AUNIT --inst x4f001400/mask=xfff89c00 --status pass
+
+:orr Rd_VPR128.4S, Imm_neon_uimm8Shift
+is b_3131=0 & q=1 & b_29=0 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1515=0 & b_1012=5 & Rd_VPR128.4S & Zd
+{
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S | Imm_neon_uimm8Shift:4 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] | Imm_neon_uimm8Shift:4;
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] | Imm_neon_uimm8Shift:4;
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] | Imm_neon_uimm8Shift:4;
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] | Imm_neon_uimm8Shift:4;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.212 ORR (vector, immediate) page C7-2507 line 146708 MATCH x0f001400/mask=xbff81c00
+# C7.2.204 MOVI page C7-2490 line 145763 MATCH x0f000400/mask=x9ff80c00
+# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x0f009400/mask=xbf80fc00
+# CONSTRUCT x4f009400/mask=xfff8dc00 MATCHED 3 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2:2 &=$|
+# SMACRO(pseudo) ARG1 ARG2:2 &=NEON_orr/2@2
+# AUNIT --inst x4f009400/mask=xfff8dc00 --status pass
+
+:orr Rd_VPR128.8H, Imm_neon_uimm8Shift
+is b_3131=0 & q=1 & b_29=0 & b_2428=0xf & b_1923=0x0 & Imm_neon_uimm8Shift & b_1415=2 & b_1012=5 & Rd_VPR128.8H & Zd
+{
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H | Imm_neon_uimm8Shift:2 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] | Imm_neon_uimm8Shift:2;
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] | Imm_neon_uimm8Shift:2;
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] | Imm_neon_uimm8Shift:2;
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] | Imm_neon_uimm8Shift:2;
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] | Imm_neon_uimm8Shift:2;
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] | Imm_neon_uimm8Shift:2;
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] | Imm_neon_uimm8Shift:2;
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] | Imm_neon_uimm8Shift:2;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.213 ORR (vector, register) page C7-2509 line 146837 MATCH x0ea01c00/mask=xbfe0fc00
+# C7.2.202 MOV (vector) page C7-2487 line 145604 MATCH x0ea01c00/mask=xbfe0fc00
+# CONSTRUCT x4ea01c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$|@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_orr/2@1
+# AUNIT --inst x4ea01c00/mask=xffe0fc00 --status pass
+
+:orr Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.16B & b_1115=0x3 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ # simd infix Rd_VPR128.16B = Rn_VPR128.16B | Rm_VPR128.16B on lane size 1
+ Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] | Rm_VPR128.16B[0,8];
+ Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] | Rm_VPR128.16B[8,8];
+ Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] | Rm_VPR128.16B[16,8];
+ Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] | Rm_VPR128.16B[24,8];
+ Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] | Rm_VPR128.16B[32,8];
+ Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] | Rm_VPR128.16B[40,8];
+ Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] | Rm_VPR128.16B[48,8];
+ Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] | Rm_VPR128.16B[56,8];
+ Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] | Rm_VPR128.16B[64,8];
+ Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] | Rm_VPR128.16B[72,8];
+ Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] | Rm_VPR128.16B[80,8];
+ Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] | Rm_VPR128.16B[88,8];
+ Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] | Rm_VPR128.16B[96,8];
+ Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] | Rm_VPR128.16B[104,8];
+ Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] | Rm_VPR128.16B[112,8];
+ Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] | Rm_VPR128.16B[120,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.213 ORR (vector, register) page C7-2509 line 146837 MATCH x0ea01c00/mask=xbfe0fc00
+# C7.2.202 MOV (vector) page C7-2487 line 145604 MATCH x0ea01c00/mask=xbfe0fc00
+# CONSTRUCT x0ea01c00/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$|@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_orr/2@1
+# AUNIT --inst x0ea01c00/mask=xffe0fc00 --status pass
+
+:orr Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.8B & b_1115=0x3 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ # simd infix Rd_VPR64.8B = Rn_VPR64.8B | Rm_VPR64.8B on lane size 1
+ Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] | Rm_VPR64.8B[0,8];
+ Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] | Rm_VPR64.8B[8,8];
+ Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] | Rm_VPR64.8B[16,8];
+ Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] | Rm_VPR64.8B[24,8];
+ Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] | Rm_VPR64.8B[32,8];
+ Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] | Rm_VPR64.8B[40,8];
+ Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] | Rm_VPR64.8B[48,8];
+ Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] | Rm_VPR64.8B[56,8];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.214 PMUL page C7-2511 line 146928 MATCH x2e209c00/mask=xbf20fc00
+# CONSTRUCT x6e209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_pmul/2@1
+# AUNIT --inst x6e209c00/mask=xffe0fc00 --status nopcodeop
+
+:pmul Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x13 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_pmul(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.214 PMUL page C7-2511 line 146928 MATCH x2e209c00/mask=xbf20fc00
+# CONSTRUCT x2e209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_pmul/2@1
+# AUNIT --inst x2e209c00/mask=xffe0fc00 --status nopcodeop
+
+:pmul Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x13 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_pmul(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.215 PMULL, PMULL2 page C7-2513 line 147032 MATCH x0e20e000/mask=xbf20fc00
+# CONSTRUCT x0ee0e000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_pmull/2@8
+# AUNIT --inst x0ee0e000/mask=xffe0fc00 --status nopcodeop --comment "ext"
+
+:pmull Rd_VPR128.1Q, Rn_VPR64.1D, Rm_VPR64.1D
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR64.1D & b_1215=0xe & b_1011=0 & Rn_VPR64.1D & Rd_VPR128.1Q & Zd
+{
+ Rd_VPR128.1Q = NEON_pmull(Rn_VPR64.1D, Rm_VPR64.1D, 8:1);
+}
+
+# C7.2.215 PMULL, PMULL2 page C7-2513 line 147032 MATCH x0e20e000/mask=xbf20fc00
+# CONSTRUCT x0e20e000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_pmull/2@1
+# AUNIT --inst x0e20e000/mask=xffe0fc00 --status nopcodeop --comment "ext"
+
+:pmull Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0xe & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_pmull(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.215 PMULL, PMULL2 page C7-2513 line 147032 MATCH x0e20e000/mask=xbf20fc00
+# CONSTRUCT x4ee0e000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_pmull2/2@8
+# AUNIT --inst x4ee0e000/mask=xffe0fc00 --status nopcodeop --comment "ext"
+
+:pmull2 Rd_VPR128.1Q, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1215=0xe & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.1Q & Zd
+{
+ Rd_VPR128.1Q = NEON_pmull2(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.215 PMULL, PMULL2 page C7-2513 line 147032 MATCH x0e20e000/mask=xbf20fc00
+# CONSTRUCT x4e20e000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_pmull2/2@1
+# AUNIT --inst x4e20e000/mask=xffe0fc00 --status nopcodeop --comment "ext"
+
+:pmull2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0xe & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_pmull2(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.216 RADDHN, RADDHN2 page C7-2515 line 147152 MATCH x2e204000/mask=xbf20fc00
+# CONSTRUCT x6e204000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $+@2 0x80:2 &=$+@2 &=$shuffle@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15:1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_raddhn2/3@2
+# AUNIT --inst x6e204000/mask=xffe0fc00 --status pass --comment "intround"
+
+:raddhn2 Rd_VPR128.16B, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x4 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.8H + Rm_VPR128.8H on lane size 2
+ TMPQ1[0,16] = Rn_VPR128.8H[0,16] + Rm_VPR128.8H[0,16];
+ TMPQ1[16,16] = Rn_VPR128.8H[16,16] + Rm_VPR128.8H[16,16];
+ TMPQ1[32,16] = Rn_VPR128.8H[32,16] + Rm_VPR128.8H[32,16];
+ TMPQ1[48,16] = Rn_VPR128.8H[48,16] + Rm_VPR128.8H[48,16];
+ TMPQ1[64,16] = Rn_VPR128.8H[64,16] + Rm_VPR128.8H[64,16];
+ TMPQ1[80,16] = Rn_VPR128.8H[80,16] + Rm_VPR128.8H[80,16];
+ TMPQ1[96,16] = Rn_VPR128.8H[96,16] + Rm_VPR128.8H[96,16];
+ TMPQ1[112,16] = Rn_VPR128.8H[112,16] + Rm_VPR128.8H[112,16];
+ # simd infix TMPQ1 = TMPQ1 + 0x80:2 on lane size 2
+ TMPQ1[0,16] = TMPQ1[0,16] + 0x80:2;
+ TMPQ1[16,16] = TMPQ1[16,16] + 0x80:2;
+ TMPQ1[32,16] = TMPQ1[32,16] + 0x80:2;
+ TMPQ1[48,16] = TMPQ1[48,16] + 0x80:2;
+ TMPQ1[64,16] = TMPQ1[64,16] + 0x80:2;
+ TMPQ1[80,16] = TMPQ1[80,16] + 0x80:2;
+ TMPQ1[96,16] = TMPQ1[96,16] + 0x80:2;
+ TMPQ1[112,16] = TMPQ1[112,16] + 0x80:2;
+ # simd shuffle Rd_VPR128.16B = TMPQ1 (@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15) lane size 1
+ Rd_VPR128.16B[64,8] = TMPQ1[8,8];
+ Rd_VPR128.16B[72,8] = TMPQ1[24,8];
+ Rd_VPR128.16B[80,8] = TMPQ1[40,8];
+ Rd_VPR128.16B[88,8] = TMPQ1[56,8];
+ Rd_VPR128.16B[96,8] = TMPQ1[72,8];
+ Rd_VPR128.16B[104,8] = TMPQ1[88,8];
+ Rd_VPR128.16B[112,8] = TMPQ1[104,8];
+ Rd_VPR128.16B[120,8] = TMPQ1[120,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.216 RADDHN, RADDHN2 page C7-2515 line 147152 MATCH x2e204000/mask=xbf20fc00
+# CONSTRUCT x6ea04000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $+@8 0x80000000:8 &=$+@8 &=$shuffle@1-2@3-3:4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_raddhn2/3@8
+# AUNIT --inst x6ea04000/mask=xffe0fc00 --status pass --comment "intround"
+
+:raddhn2 Rd_VPR128.4S, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x4 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.2D + Rm_VPR128.2D on lane size 8
+ TMPQ1[0,64] = Rn_VPR128.2D[0,64] + Rm_VPR128.2D[0,64];
+ TMPQ1[64,64] = Rn_VPR128.2D[64,64] + Rm_VPR128.2D[64,64];
+ # simd infix TMPQ1 = TMPQ1 + 0x80000000:8 on lane size 8
+ TMPQ1[0,64] = TMPQ1[0,64] + 0x80000000:8;
+ TMPQ1[64,64] = TMPQ1[64,64] + 0x80000000:8;
+ # simd shuffle Rd_VPR128.4S = TMPQ1 (@1-2@3-3) lane size 4
+ Rd_VPR128.4S[64,32] = TMPQ1[32,32];
+ Rd_VPR128.4S[96,32] = TMPQ1[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.216 RADDHN, RADDHN2 page C7-2515 line 147152 MATCH x2e204000/mask=xbf20fc00
+# CONSTRUCT x6e604000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $+@4 0x8000:4 &=$+@4 &=$shuffle@1-4@3-5@5-6@7-7:2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_raddhn2/3@4
+# AUNIT --inst x6e604000/mask=xffe0fc00 --status pass --comment "intround"
+
+:raddhn2 Rd_VPR128.8H, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x4 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.4S + Rm_VPR128.4S on lane size 4
+ TMPQ1[0,32] = Rn_VPR128.4S[0,32] + Rm_VPR128.4S[0,32];
+ TMPQ1[32,32] = Rn_VPR128.4S[32,32] + Rm_VPR128.4S[32,32];
+ TMPQ1[64,32] = Rn_VPR128.4S[64,32] + Rm_VPR128.4S[64,32];
+ TMPQ1[96,32] = Rn_VPR128.4S[96,32] + Rm_VPR128.4S[96,32];
+ # simd infix TMPQ1 = TMPQ1 + 0x8000:4 on lane size 4
+ TMPQ1[0,32] = TMPQ1[0,32] + 0x8000:4;
+ TMPQ1[32,32] = TMPQ1[32,32] + 0x8000:4;
+ TMPQ1[64,32] = TMPQ1[64,32] + 0x8000:4;
+ TMPQ1[96,32] = TMPQ1[96,32] + 0x8000:4;
+ # simd shuffle Rd_VPR128.8H = TMPQ1 (@1-4@3-5@5-6@7-7) lane size 2
+ Rd_VPR128.8H[64,16] = TMPQ1[16,16];
+ Rd_VPR128.8H[80,16] = TMPQ1[48,16];
+ Rd_VPR128.8H[96,16] = TMPQ1[80,16];
+ Rd_VPR128.8H[112,16] = TMPQ1[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.216 RADDHN, RADDHN2 page C7-2515 line 147152 MATCH x2e204000/mask=xbf20fc00
+# CONSTRUCT x2ea04000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_raddhn/3@8
+# AUNIT --inst x2ea04000/mask=xffe0fc00 --status nopcodeop
+
+:raddhn Rd_VPR64.2S, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x4 & b_1011=0 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_raddhn(Rd_VPR64.2S, Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.216 RADDHN, RADDHN2 page C7-2515 line 147152 MATCH x2e204000/mask=xbf20fc00
+# CONSTRUCT x2e604000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_raddhn/3@4
+# AUNIT --inst x2e604000/mask=xffe0fc00 --status nopcodeop
+
+:raddhn Rd_VPR64.4H, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x4 & b_1011=0 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_raddhn(Rd_VPR64.4H, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.216 RADDHN, RADDHN2 page C7-2515 line 147152 MATCH x2e204000/mask=xbf20fc00
+# CONSTRUCT x2e204000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_raddhn/3@2
+# AUNIT --inst x2e204000/mask=xffe0fc00 --status nopcodeop
+
+:raddhn Rd_VPR64.8B, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x4 & b_1011=0 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_raddhn(Rd_VPR64.8B, Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.217 RAX1 page C7-2517 line 147279 MATCH xce608c00/mask=xffe0fc00
+# CONSTRUCT xce608c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 1:8 $<<@8 =$|@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_rax1/2@8
+# AUNIT --inst xce608c00/mask=xffe0fc00 --status noqemu
+
+:rax1 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_2131=0b11001110011 & b_1015=0b100011 & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd
+{
+ # simd infix TMPQ1 = Rm_VPR128.2D << 1:8 on lane size 8
+ TMPQ1[0,64] = Rm_VPR128.2D[0,64] << 1:8;
+ TMPQ1[64,64] = Rm_VPR128.2D[64,64] << 1:8;
+ # simd infix Rd_VPR128.2D = Rn_VPR128.2D | TMPQ1 on lane size 8
+ Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] | TMPQ1[0,64];
+ Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] | TMPQ1[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.218 RBIT (vector) page C7-2518 line 147347 MATCH x2e605800/mask=xbffffc00
+# CONSTRUCT x2e605800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_rbit/1@1
+# AUNIT --inst x2e605800/mask=xfffffc00 --status nopcodeop
+
+:rbit Rd_VPR64.8B, Rn_VPR64.8B
+is b_31=0 & b_30=0 & b_1029=0b10111001100000010110 & Rd_VPR64.8B & Rn_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_rbit(Rn_VPR64.8B, 1:1);
+}
+
+# C7.2.218 RBIT (vector) page C7-2518 line 147347 MATCH x2e605800/mask=xbffffc00
+# CONSTRUCT x6e605800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_rbit/1@1
+# AUNIT --inst x6e605800/mask=xfffffc00 --status nopcodeop
+
+:rbit Rd_VPR128.16B, Rn_VPR128.16B
+is b_31=0 & b_30=1 & b_1029=0b10111001100000010110 & Rd_VPR128.16B & Rn_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_rbit(Rn_VPR128.16B, 1:1);
+}
+
+# C7.2.219 REV16 (vector) page C7-2520 line 147435 MATCH x0e201800/mask=xbf3ffc00
+# CONSTRUCT x4e201800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_rev16/1@1
+# AUNIT --inst x4e201800/mask=xfffffc00 --status nopcodeop
+
+:rev16 Rd_VPR128.16B, Rn_VPR128.16B
+is b_3131=0 & Q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x1 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_rev16(Rn_VPR128.16B, 1:1);
+}
+
+# C7.2.219 REV16 (vector) page C7-2520 line 147435 MATCH x0e201800/mask=xbf3ffc00
+# CONSTRUCT x0e201800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_rev16/1@1
+# AUNIT --inst x0e201800/mask=xfffffc00 --status nopcodeop
+
+:rev16 Rd_VPR64.8B, Rn_VPR64.8B
+is b_3131=0 & Q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x1 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_rev16(Rn_VPR64.8B, 1:1);
+}
+
+# C7.2.220 REV32 (vector) page C7-2522 line 147553 MATCH x2e200800/mask=xbf3ffc00
+# CONSTRUCT x6e200800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_rev32/1@1
+# AUNIT --inst x6e200800/mask=xfffffc00 --status nopcodeop
+
+:rev32 Rd_VPR128.16B, Rn_VPR128.16B
+is b_3131=0 & Q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_rev32(Rn_VPR128.16B, 1:1);
+}
+
+# C7.2.220 REV32 (vector) page C7-2522 line 147553 MATCH x2e200800/mask=xbf3ffc00
+# CONSTRUCT x2e600800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_rev32/1@2
+# AUNIT --inst x2e600800/mask=xfffffc00 --status nopcodeop
+
+:rev32 Rd_VPR64.4H, Rn_VPR64.4H
+is b_3131=0 & Q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_rev32(Rn_VPR64.4H, 2:1);
+}
+
+# C7.2.220 REV32 (vector) page C7-2522 line 147553 MATCH x2e200800/mask=xbf3ffc00
+# CONSTRUCT x2e200800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_rev32/1@1
+# AUNIT --inst x2e200800/mask=xfffffc00 --status nopcodeop
+
+:rev32 Rd_VPR64.8B, Rn_VPR64.8B
+is b_3131=0 & Q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_rev32(Rn_VPR64.8B, 1:1);
+}
+
+# C7.2.220 REV32 (vector) page C7-2522 line 147553 MATCH x2e200800/mask=xbf3ffc00
+# CONSTRUCT x6e600800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_rev32/1@2
+# AUNIT --inst x6e600800/mask=xfffffc00 --status nopcodeop
+
+:rev32 Rd_VPR128.8H, Rn_VPR128.8H
+is b_3131=0 & Q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_rev32(Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.221 REV64 page C7-2524 line 147671 MATCH x0e200800/mask=xbf3ffc00
+# CONSTRUCT x4e200800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_rev64/1@1
+# AUNIT --inst x4e200800/mask=xfffffc00 --status nopcodeop
+
+:rev64 Rd_VPR128.16B, Rn_VPR128.16B
+is b_3131=0 & Q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_rev64(Rn_VPR128.16B, 1:1);
+}
+
+# C7.2.221 REV64 page C7-2524 line 147671 MATCH x0e200800/mask=xbf3ffc00
+# CONSTRUCT x0ea00800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_rev64/1@4
+# AUNIT --inst x0ea00800/mask=xfffffc00 --status nopcodeop
+
+:rev64 Rd_VPR64.2S, Rn_VPR64.2S
+is b_3131=0 & Q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_rev64(Rn_VPR64.2S, 4:1);
+}
+
+# C7.2.221 REV64 page C7-2524 line 147671 MATCH x0e200800/mask=xbf3ffc00
+# CONSTRUCT x0e600800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_rev64/1@2
+# AUNIT --inst x0e600800/mask=xfffffc00 --status nopcodeop
+
+:rev64 Rd_VPR64.4H, Rn_VPR64.4H
+is b_3131=0 & Q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_rev64(Rn_VPR64.4H, 2:1);
+}
+
+# C7.2.221 REV64 page C7-2524 line 147671 MATCH x0e200800/mask=xbf3ffc00
+# CONSTRUCT x4ea00800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_rev64/1@4
+# AUNIT --inst x4ea00800/mask=xfffffc00 --status nopcodeop
+
+:rev64 Rd_VPR128.4S, Rn_VPR128.4S
+is b_3131=0 & Q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_rev64(Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.221 REV64 page C7-2524 line 147671 MATCH x0e200800/mask=xbf3ffc00
+# CONSTRUCT x0e200800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_rev64/1@1
+# AUNIT --inst x0e200800/mask=xfffffc00 --status nopcodeop
+
+:rev64 Rd_VPR64.8B, Rn_VPR64.8B
+is b_3131=0 & Q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_rev64(Rn_VPR64.8B, 1:1);
+}
+
+# C7.2.221 REV64 page C7-2524 line 147671 MATCH x0e200800/mask=xbf3ffc00
+# CONSTRUCT x4e600800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_rev64/1@2
+# AUNIT --inst x4e600800/mask=xfffffc00 --status nopcodeop
+
+:rev64 Rd_VPR128.8H, Rn_VPR128.8H
+is b_3131=0 & Q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x0 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_rev64(Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.222 RSHRN, RSHRN2 page C7-2526 line 147791 MATCH x0f008c00/mask=xbf80fc00
+# CONSTRUCT x4f088c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_rshrn2/3@2
+# AUNIT --inst x4f088c00/mask=xfff8fc00 --status nopcodeop --comment "nointround"
+
+:rshrn2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x11 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_rshrn2(Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
+}
+
+# C7.2.222 RSHRN, RSHRN2 page C7-2526 line 147791 MATCH x0f008c00/mask=xbf80fc00
+# CONSTRUCT x0f208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_rshrn/3@8
+# AUNIT --inst x0f208c00/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:rshrn Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x11 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_rshrn(Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
+}
+
+# C7.2.222 RSHRN, RSHRN2 page C7-2526 line 147791 MATCH x0f008c00/mask=xbf80fc00
+# CONSTRUCT x0f108c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_rshrn/3@4
+# AUNIT --inst x0f108c00/mask=xfff0fc00 --status nopcodeop --comment "nointround"
+
+:rshrn Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x11 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_rshrn(Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
+}
+
+# C7.2.222 RSHRN, RSHRN2 page C7-2526 line 147791 MATCH x0f008c00/mask=xbf80fc00
+# CONSTRUCT x4f208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_rshrn2/3@8
+# AUNIT --inst x4f208c00/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:rshrn2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x11 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_rshrn2(Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
+}
+
+# C7.2.222 RSHRN, RSHRN2 page C7-2526 line 147791 MATCH x0f008c00/mask=xbf80fc00
+# CONSTRUCT x0f088c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_rshrn/3@2
+# AUNIT --inst x0f088c00/mask=xfff8fc00 --status nopcodeop --comment "nointround"
+
+:rshrn Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x11 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_rshrn(Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
+}
+
+# C7.2.222 RSHRN, RSHRN2 page C7-2526 line 147791 MATCH x0f008c00/mask=xbf80fc00
+# CONSTRUCT x4f108c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_rshrn2/3@4
+# AUNIT --inst x4f108c00/mask=xfff0fc00 --status nopcodeop --comment "nointround"
+
+:rshrn2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x11 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_rshrn2(Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
+}
+
+# C7.2.223 RSUBHN, RSUBHN2 page C7-2528 line 147915 MATCH x2e206000/mask=xbf20fc00
+# CONSTRUCT x6e206000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_rsubhn2/3@2
+# AUNIT --inst x6e206000/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:rsubhn2 Rd_VPR128.16B, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x6 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_rsubhn2(Rd_VPR128.16B, Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.223 RSUBHN, RSUBHN2 page C7-2528 line 147915 MATCH x2e206000/mask=xbf20fc00
+# CONSTRUCT x6ea06000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_rsubhn2/3@8
+# AUNIT --inst x6ea06000/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:rsubhn2 Rd_VPR128.4S, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x6 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_rsubhn2(Rd_VPR128.4S, Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.223 RSUBHN, RSUBHN2 page C7-2528 line 147915 MATCH x2e206000/mask=xbf20fc00
+# CONSTRUCT x6e606000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_rsubhn2/3@4
+# AUNIT --inst x6e606000/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:rsubhn2 Rd_VPR128.8H, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x6 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_rsubhn2(Rd_VPR128.8H, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.223 RSUBHN, RSUBHN2 page C7-2528 line 147915 MATCH x2e206000/mask=xbf20fc00
+# CONSTRUCT x2ea06000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_rsubhn/3@8
+# AUNIT --inst x2ea06000/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:rsubhn Rd_VPR64.2S, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x6 & b_1011=0 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_rsubhn(Rd_VPR64.2S, Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.223 RSUBHN, RSUBHN2 page C7-2528 line 147915 MATCH x2e206000/mask=xbf20fc00
+# CONSTRUCT x2e606000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_rsubhn/3@4
+# AUNIT --inst x2e606000/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:rsubhn Rd_VPR64.4H, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x6 & b_1011=0 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_rsubhn(Rd_VPR64.4H, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.223 RSUBHN, RSUBHN2 page C7-2528 line 147915 MATCH x2e206000/mask=xbf20fc00
+# CONSTRUCT x2e206000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_rsubhn/3@2
+# AUNIT --inst x2e206000/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:rsubhn Rd_VPR64.8B, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x6 & b_1011=0 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_rsubhn(Rd_VPR64.8B, Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.224 SABA page C7-2530 line 148042 MATCH x0e207c00/mask=xbf20fc00
+# CONSTRUCT x4e207c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saba/3@1
+# AUNIT --inst x4e207c00/mask=xffe0fc00 --status nopcodeop --comment "abd"
+
+:saba Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xf & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_saba(Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.224 SABA page C7-2530 line 148042 MATCH x0e207c00/mask=xbf20fc00
+# CONSTRUCT x0ea07c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saba/3@4
+# AUNIT --inst x0ea07c00/mask=xffe0fc00 --status nopcodeop --comment "abd"
+
+:saba Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xf & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_saba(Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.224 SABA page C7-2530 line 148042 MATCH x0e207c00/mask=xbf20fc00
+# CONSTRUCT x0e607c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saba/3@2
+# AUNIT --inst x0e607c00/mask=xffe0fc00 --status nopcodeop --comment "abd"
+
+:saba Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xf & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_saba(Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.224 SABA page C7-2530 line 148042 MATCH x0e207c00/mask=xbf20fc00
+# CONSTRUCT x4ea07c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saba/3@4
+# AUNIT --inst x4ea07c00/mask=xffe0fc00 --status nopcodeop --comment "abd"
+
+:saba Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xf & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_saba(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.224 SABA page C7-2530 line 148042 MATCH x0e207c00/mask=xbf20fc00
+# CONSTRUCT x0e207c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saba/3@1
+# AUNIT --inst x0e207c00/mask=xffe0fc00 --status nopcodeop --comment "abd"
+
+:saba Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xf & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_saba(Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.224 SABA page C7-2530 line 148042 MATCH x0e207c00/mask=xbf20fc00
+# CONSTRUCT x4e607c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saba/3@2
+# AUNIT --inst x4e607c00/mask=xffe0fc00 --status nopcodeop --comment "abd"
+
+:saba Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xf & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_saba(Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.225 SABAL, SABAL2 page C7-2532 line 148144 MATCH x0e205000/mask=xbf20fc00
+# CONSTRUCT x0ea05000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 $-@8 $abs@8 &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabal/3@4
+# AUNIT --inst x0ea05000/mask=xffe0fc00 --status pass --comment "ext abd"
+
+:sabal Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x5 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);
+ TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);
+ # simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 8
+ TMPQ3[0,64] = TMPQ1[0,64] - TMPQ2[0,64];
+ TMPQ3[64,64] = TMPQ1[64,64] - TMPQ2[64,64];
+ # simd unary TMPQ4 = MP_INT_ABS(TMPQ3) on lane size 8
+ TMPQ4[0,64] = MP_INT_ABS(TMPQ3[0,64]);
+ TMPQ4[64,64] = MP_INT_ABS(TMPQ3[64,64]);
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ4 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ4[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ4[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.225 SABAL, SABAL2 page C7-2532 line 148144 MATCH x0e205000/mask=xbf20fc00
+# CONSTRUCT x0e605000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 $-@4 $abs@4 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabal/3@2
+# AUNIT --inst x0e605000/mask=xffe0fc00 --status pass --comment "ext abd"
+
+:sabal Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x5 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);
+ TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);
+ TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);
+ TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);
+ # simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 4
+ TMPQ3[0,32] = TMPQ1[0,32] - TMPQ2[0,32];
+ TMPQ3[32,32] = TMPQ1[32,32] - TMPQ2[32,32];
+ TMPQ3[64,32] = TMPQ1[64,32] - TMPQ2[64,32];
+ TMPQ3[96,32] = TMPQ1[96,32] - TMPQ2[96,32];
+ # simd unary TMPQ4 = MP_INT_ABS(TMPQ3) on lane size 4
+ TMPQ4[0,32] = MP_INT_ABS(TMPQ3[0,32]);
+ TMPQ4[32,32] = MP_INT_ABS(TMPQ3[32,32]);
+ TMPQ4[64,32] = MP_INT_ABS(TMPQ3[64,32]);
+ TMPQ4[96,32] = MP_INT_ABS(TMPQ3[96,32]);
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ4 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ4[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ4[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ4[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ4[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.225 SABAL, SABAL2 page C7-2532 line 148144 MATCH x0e205000/mask=xbf20fc00
+# CONSTRUCT x0e205000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 $-@2 $abs@2 &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabal/3@1
+# AUNIT --inst x0e205000/mask=xffe0fc00 --status pass --comment "ext abd"
+
+:sabal Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x5 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)
+ TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);
+ TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);
+ TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);
+ TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);
+ TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);
+ TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);
+ TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);
+ TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2)
+ TMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]);
+ TMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]);
+ TMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]);
+ TMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]);
+ TMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]);
+ TMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]);
+ TMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]);
+ TMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]);
+ # simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 2
+ TMPQ3[0,16] = TMPQ1[0,16] - TMPQ2[0,16];
+ TMPQ3[16,16] = TMPQ1[16,16] - TMPQ2[16,16];
+ TMPQ3[32,16] = TMPQ1[32,16] - TMPQ2[32,16];
+ TMPQ3[48,16] = TMPQ1[48,16] - TMPQ2[48,16];
+ TMPQ3[64,16] = TMPQ1[64,16] - TMPQ2[64,16];
+ TMPQ3[80,16] = TMPQ1[80,16] - TMPQ2[80,16];
+ TMPQ3[96,16] = TMPQ1[96,16] - TMPQ2[96,16];
+ TMPQ3[112,16] = TMPQ1[112,16] - TMPQ2[112,16];
+ # simd unary TMPQ4 = MP_INT_ABS(TMPQ3) on lane size 2
+ TMPQ4[0,16] = MP_INT_ABS(TMPQ3[0,16]);
+ TMPQ4[16,16] = MP_INT_ABS(TMPQ3[16,16]);
+ TMPQ4[32,16] = MP_INT_ABS(TMPQ3[32,16]);
+ TMPQ4[48,16] = MP_INT_ABS(TMPQ3[48,16]);
+ TMPQ4[64,16] = MP_INT_ABS(TMPQ3[64,16]);
+ TMPQ4[80,16] = MP_INT_ABS(TMPQ3[80,16]);
+ TMPQ4[96,16] = MP_INT_ABS(TMPQ3[96,16]);
+ TMPQ4[112,16] = MP_INT_ABS(TMPQ3[112,16]);
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ4 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ4[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ4[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ4[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ4[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ4[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ4[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ4[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ4[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.225 SABAL, SABAL2 page C7-2532 line 148144 MATCH x0e205000/mask=xbf20fc00
+# CONSTRUCT x4ea05000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $-@8 $abs@8 &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabal2/3@4
+# AUNIT --inst x4ea05000/mask=xffe0fc00 --status pass --comment "ext abd"
+
+:sabal2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x5 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(TMPD1[0,32]);
+ TMPQ2[64,64] = sext(TMPD1[32,32]);
+ TMPD3 = Rm_VPR128.4S[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)
+ TMPQ4[0,64] = sext(TMPD3[0,32]);
+ TMPQ4[64,64] = sext(TMPD3[32,32]);
+ # simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 8
+ TMPQ5[0,64] = TMPQ2[0,64] - TMPQ4[0,64];
+ TMPQ5[64,64] = TMPQ2[64,64] - TMPQ4[64,64];
+ # simd unary TMPQ6 = MP_INT_ABS(TMPQ5) on lane size 8
+ TMPQ6[0,64] = MP_INT_ABS(TMPQ5[0,64]);
+ TMPQ6[64,64] = MP_INT_ABS(TMPQ5[64,64]);
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ6 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ6[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ6[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.225 SABAL, SABAL2 page C7-2532 line 148144 MATCH x0e205000/mask=xbf20fc00
+# CONSTRUCT x4e605000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $-@4 $abs@4 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabal2/3@2
+# AUNIT --inst x4e605000/mask=xffe0fc00 --status pass --comment "ext abd"
+
+:sabal2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x5 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(TMPD1[0,16]);
+ TMPQ2[32,32] = sext(TMPD1[16,16]);
+ TMPQ2[64,32] = sext(TMPD1[32,16]);
+ TMPQ2[96,32] = sext(TMPD1[48,16]);
+ TMPD3 = Rm_VPR128.8H[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)
+ TMPQ4[0,32] = sext(TMPD3[0,16]);
+ TMPQ4[32,32] = sext(TMPD3[16,16]);
+ TMPQ4[64,32] = sext(TMPD3[32,16]);
+ TMPQ4[96,32] = sext(TMPD3[48,16]);
+ # simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 4
+ TMPQ5[0,32] = TMPQ2[0,32] - TMPQ4[0,32];
+ TMPQ5[32,32] = TMPQ2[32,32] - TMPQ4[32,32];
+ TMPQ5[64,32] = TMPQ2[64,32] - TMPQ4[64,32];
+ TMPQ5[96,32] = TMPQ2[96,32] - TMPQ4[96,32];
+ # simd unary TMPQ6 = MP_INT_ABS(TMPQ5) on lane size 4
+ TMPQ6[0,32] = MP_INT_ABS(TMPQ5[0,32]);
+ TMPQ6[32,32] = MP_INT_ABS(TMPQ5[32,32]);
+ TMPQ6[64,32] = MP_INT_ABS(TMPQ5[64,32]);
+ TMPQ6[96,32] = MP_INT_ABS(TMPQ5[96,32]);
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ6 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ6[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ6[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ6[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ6[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.225 SABAL, SABAL2 page C7-2532 line 148144 MATCH x0e205000/mask=xbf20fc00
+# CONSTRUCT x4e205000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 $-@2 $abs@2 &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabal2/3@1
+# AUNIT --inst x4e205000/mask=xffe0fc00 --status pass --comment "ext abd"
+
+:sabal2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x5 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
+{
+ TMPD1 = Rn_VPR128.16B[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)
+ TMPQ2[0,16] = sext(TMPD1[0,8]);
+ TMPQ2[16,16] = sext(TMPD1[8,8]);
+ TMPQ2[32,16] = sext(TMPD1[16,8]);
+ TMPQ2[48,16] = sext(TMPD1[24,8]);
+ TMPQ2[64,16] = sext(TMPD1[32,8]);
+ TMPQ2[80,16] = sext(TMPD1[40,8]);
+ TMPQ2[96,16] = sext(TMPD1[48,8]);
+ TMPQ2[112,16] = sext(TMPD1[56,8]);
+ TMPD3 = Rm_VPR128.16B[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2)
+ TMPQ4[0,16] = sext(TMPD3[0,8]);
+ TMPQ4[16,16] = sext(TMPD3[8,8]);
+ TMPQ4[32,16] = sext(TMPD3[16,8]);
+ TMPQ4[48,16] = sext(TMPD3[24,8]);
+ TMPQ4[64,16] = sext(TMPD3[32,8]);
+ TMPQ4[80,16] = sext(TMPD3[40,8]);
+ TMPQ4[96,16] = sext(TMPD3[48,8]);
+ TMPQ4[112,16] = sext(TMPD3[56,8]);
+ # simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 2
+ TMPQ5[0,16] = TMPQ2[0,16] - TMPQ4[0,16];
+ TMPQ5[16,16] = TMPQ2[16,16] - TMPQ4[16,16];
+ TMPQ5[32,16] = TMPQ2[32,16] - TMPQ4[32,16];
+ TMPQ5[48,16] = TMPQ2[48,16] - TMPQ4[48,16];
+ TMPQ5[64,16] = TMPQ2[64,16] - TMPQ4[64,16];
+ TMPQ5[80,16] = TMPQ2[80,16] - TMPQ4[80,16];
+ TMPQ5[96,16] = TMPQ2[96,16] - TMPQ4[96,16];
+ TMPQ5[112,16] = TMPQ2[112,16] - TMPQ4[112,16];
+ # simd unary TMPQ6 = MP_INT_ABS(TMPQ5) on lane size 2
+ TMPQ6[0,16] = MP_INT_ABS(TMPQ5[0,16]);
+ TMPQ6[16,16] = MP_INT_ABS(TMPQ5[16,16]);
+ TMPQ6[32,16] = MP_INT_ABS(TMPQ5[32,16]);
+ TMPQ6[48,16] = MP_INT_ABS(TMPQ5[48,16]);
+ TMPQ6[64,16] = MP_INT_ABS(TMPQ5[64,16]);
+ TMPQ6[80,16] = MP_INT_ABS(TMPQ5[80,16]);
+ TMPQ6[96,16] = MP_INT_ABS(TMPQ5[96,16]);
+ TMPQ6[112,16] = MP_INT_ABS(TMPQ5[112,16]);
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ6 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ6[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ6[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ6[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ6[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ6[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ6[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ6[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ6[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.226 SABD page C7-2534 line 148264 MATCH x0e207400/mask=xbf20fc00
+# CONSTRUCT x4e207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@1
+# AUNIT --inst x4e207400/mask=xffe0fc00 --status nopcodeop --comment "abd"
+
+:sabd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xe & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_sabd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.226 SABD page C7-2534 line 148264 MATCH x0e207400/mask=xbf20fc00
+# CONSTRUCT x0ea07400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $-@4 ARG3 ARG2 $-@4 2:4 &=$* ARG2 ARG3 $sless@4 &=$*@4 =$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@4
+# AUNIT --inst x0ea07400/mask=xffe0fc00 --status pass --comment "abd"
+# This abd instruction is implemented correctly to document a correct
+# way to implement the signed absolute difference semantic.
+
+:sabd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xe & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ # simd infix TMPD1 = Rn_VPR64.2S - Rm_VPR64.2S on lane size 4
+ TMPD1[0,32] = Rn_VPR64.2S[0,32] - Rm_VPR64.2S[0,32];
+ TMPD1[32,32] = Rn_VPR64.2S[32,32] - Rm_VPR64.2S[32,32];
+ # simd infix TMPD2 = Rm_VPR64.2S - Rn_VPR64.2S on lane size 4
+ TMPD2[0,32] = Rm_VPR64.2S[0,32] - Rn_VPR64.2S[0,32];
+ TMPD2[32,32] = Rm_VPR64.2S[32,32] - Rn_VPR64.2S[32,32];
+ # simd infix TMPD2 = TMPD2 * 2:4 on lane size 4
+ TMPD2[0,32] = TMPD2[0,32] * 2:4;
+ TMPD2[32,32] = TMPD2[32,32] * 2:4;
+ # simd infix TMPD3 = Rn_VPR64.2S s< Rm_VPR64.2S on lane size 4
+ TMPD3[0,32] = zext(Rn_VPR64.2S[0,32] s< Rm_VPR64.2S[0,32]);
+ TMPD3[32,32] = zext(Rn_VPR64.2S[32,32] s< Rm_VPR64.2S[32,32]);
+ # simd infix TMPD2 = TMPD2 * TMPD3 on lane size 4
+ TMPD2[0,32] = TMPD2[0,32] * TMPD3[0,32];
+ TMPD2[32,32] = TMPD2[32,32] * TMPD3[32,32];
+ # simd infix Rd_VPR64.2S = TMPD1 + TMPD2 on lane size 4
+ Rd_VPR64.2S[0,32] = TMPD1[0,32] + TMPD2[0,32];
+ Rd_VPR64.2S[32,32] = TMPD1[32,32] + TMPD2[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.226 SABD page C7-2534 line 148264 MATCH x0e207400/mask=xbf20fc00
+# CONSTRUCT x0e607400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@2
+# AUNIT --inst x0e607400/mask=xffe0fc00 --status nopcodeop --comment "abd"
+
+:sabd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xe & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_sabd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.226 SABD page C7-2534 line 148264 MATCH x0e207400/mask=xbf20fc00
+# CONSTRUCT x4ea07400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@4
+# AUNIT --inst x4ea07400/mask=xffe0fc00 --status nopcodeop --comment "abd"
+
+:sabd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xe & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sabd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.226 SABD page C7-2534 line 148264 MATCH x0e207400/mask=xbf20fc00
+# CONSTRUCT x0e207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@1
+# AUNIT --inst x0e207400/mask=xffe0fc00 --status nopcodeop --comment "abd"
+
+:sabd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xe & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_sabd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.226 SABD page C7-2534 line 148264 MATCH x0e207400/mask=xbf20fc00
+# CONSTRUCT x4e607400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sabd/2@2
+# AUNIT --inst x4e607400/mask=xffe0fc00 --status nopcodeop --comment "abd"
+
+:sabd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xe & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_sabd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.227 SABDL, SABDL2 page C7-2536 line 148366 MATCH x0e207000/mask=xbf20fc00
+# CONSTRUCT x0ea07000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 $-@8 =$abs@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabdl/3@4
+# AUNIT --inst x0ea07000/mask=xffe0fc00 --status pass --comment "ext abd"
+
+:sabdl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x7 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);
+ TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);
+ # simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 8
+ TMPQ3[0,64] = TMPQ1[0,64] - TMPQ2[0,64];
+ TMPQ3[64,64] = TMPQ1[64,64] - TMPQ2[64,64];
+ # simd unary Rd_VPR128.2D = MP_INT_ABS(TMPQ3) on lane size 8
+ Rd_VPR128.2D[0,64] = MP_INT_ABS(TMPQ3[0,64]);
+ Rd_VPR128.2D[64,64] = MP_INT_ABS(TMPQ3[64,64]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.227 SABDL, SABDL2 page C7-2536 line 148366 MATCH x0e207000/mask=xbf20fc00
+# CONSTRUCT x0e607000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 $-@4 =$abs@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabdl/3@2
+# AUNIT --inst x0e607000/mask=xffe0fc00 --status pass --comment "ext abd"
+
+:sabdl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x7 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);
+ TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);
+ TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);
+ TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);
+ # simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 4
+ TMPQ3[0,32] = TMPQ1[0,32] - TMPQ2[0,32];
+ TMPQ3[32,32] = TMPQ1[32,32] - TMPQ2[32,32];
+ TMPQ3[64,32] = TMPQ1[64,32] - TMPQ2[64,32];
+ TMPQ3[96,32] = TMPQ1[96,32] - TMPQ2[96,32];
+ # simd unary Rd_VPR128.4S = MP_INT_ABS(TMPQ3) on lane size 4
+ Rd_VPR128.4S[0,32] = MP_INT_ABS(TMPQ3[0,32]);
+ Rd_VPR128.4S[32,32] = MP_INT_ABS(TMPQ3[32,32]);
+ Rd_VPR128.4S[64,32] = MP_INT_ABS(TMPQ3[64,32]);
+ Rd_VPR128.4S[96,32] = MP_INT_ABS(TMPQ3[96,32]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.227 SABDL, SABDL2 page C7-2536 line 148366 MATCH x0e207000/mask=xbf20fc00
+# CONSTRUCT x0e207000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 $-@2 =$abs@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabdl/3@1
+# AUNIT --inst x0e207000/mask=xffe0fc00 --status pass --comment "ext abd"
+
+:sabdl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x7 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)
+ TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);
+ TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);
+ TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);
+ TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);
+ TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);
+ TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);
+ TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);
+ TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2)
+ TMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]);
+ TMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]);
+ TMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]);
+ TMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]);
+ TMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]);
+ TMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]);
+ TMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]);
+ TMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]);
+ # simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 2
+ TMPQ3[0,16] = TMPQ1[0,16] - TMPQ2[0,16];
+ TMPQ3[16,16] = TMPQ1[16,16] - TMPQ2[16,16];
+ TMPQ3[32,16] = TMPQ1[32,16] - TMPQ2[32,16];
+ TMPQ3[48,16] = TMPQ1[48,16] - TMPQ2[48,16];
+ TMPQ3[64,16] = TMPQ1[64,16] - TMPQ2[64,16];
+ TMPQ3[80,16] = TMPQ1[80,16] - TMPQ2[80,16];
+ TMPQ3[96,16] = TMPQ1[96,16] - TMPQ2[96,16];
+ TMPQ3[112,16] = TMPQ1[112,16] - TMPQ2[112,16];
+ # simd unary Rd_VPR128.8H = MP_INT_ABS(TMPQ3) on lane size 2
+ Rd_VPR128.8H[0,16] = MP_INT_ABS(TMPQ3[0,16]);
+ Rd_VPR128.8H[16,16] = MP_INT_ABS(TMPQ3[16,16]);
+ Rd_VPR128.8H[32,16] = MP_INT_ABS(TMPQ3[32,16]);
+ Rd_VPR128.8H[48,16] = MP_INT_ABS(TMPQ3[48,16]);
+ Rd_VPR128.8H[64,16] = MP_INT_ABS(TMPQ3[64,16]);
+ Rd_VPR128.8H[80,16] = MP_INT_ABS(TMPQ3[80,16]);
+ Rd_VPR128.8H[96,16] = MP_INT_ABS(TMPQ3[96,16]);
+ Rd_VPR128.8H[112,16] = MP_INT_ABS(TMPQ3[112,16]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.227 SABDL, SABDL2 page C7-2536 line 148366 MATCH x0e207000/mask=xbf20fc00
+# CONSTRUCT x4ea07000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $-@8 =$abs@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabdl2/3@4
+# AUNIT --inst x4ea07000/mask=xffe0fc00 --status pass --comment "ext abd"
+
+:sabdl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x7 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(TMPD1[0,32]);
+ TMPQ2[64,64] = sext(TMPD1[32,32]);
+ TMPD3 = Rm_VPR128.4S[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)
+ TMPQ4[0,64] = sext(TMPD3[0,32]);
+ TMPQ4[64,64] = sext(TMPD3[32,32]);
+ # simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 8
+ TMPQ5[0,64] = TMPQ2[0,64] - TMPQ4[0,64];
+ TMPQ5[64,64] = TMPQ2[64,64] - TMPQ4[64,64];
+ # simd unary Rd_VPR128.2D = MP_INT_ABS(TMPQ5) on lane size 8
+ Rd_VPR128.2D[0,64] = MP_INT_ABS(TMPQ5[0,64]);
+ Rd_VPR128.2D[64,64] = MP_INT_ABS(TMPQ5[64,64]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.227 SABDL, SABDL2 page C7-2536 line 148366 MATCH x0e207000/mask=xbf20fc00
+# CONSTRUCT x4e607000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $-@4 =$abs@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabdl2/3@2
+# AUNIT --inst x4e607000/mask=xffe0fc00 --status pass --comment "ext abd"
+
+:sabdl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x7 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(TMPD1[0,16]);
+ TMPQ2[32,32] = sext(TMPD1[16,16]);
+ TMPQ2[64,32] = sext(TMPD1[32,16]);
+ TMPQ2[96,32] = sext(TMPD1[48,16]);
+ TMPD3 = Rm_VPR128.8H[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)
+ TMPQ4[0,32] = sext(TMPD3[0,16]);
+ TMPQ4[32,32] = sext(TMPD3[16,16]);
+ TMPQ4[64,32] = sext(TMPD3[32,16]);
+ TMPQ4[96,32] = sext(TMPD3[48,16]);
+ # simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 4
+ TMPQ5[0,32] = TMPQ2[0,32] - TMPQ4[0,32];
+ TMPQ5[32,32] = TMPQ2[32,32] - TMPQ4[32,32];
+ TMPQ5[64,32] = TMPQ2[64,32] - TMPQ4[64,32];
+ TMPQ5[96,32] = TMPQ2[96,32] - TMPQ4[96,32];
+ # simd unary Rd_VPR128.4S = MP_INT_ABS(TMPQ5) on lane size 4
+ Rd_VPR128.4S[0,32] = MP_INT_ABS(TMPQ5[0,32]);
+ Rd_VPR128.4S[32,32] = MP_INT_ABS(TMPQ5[32,32]);
+ Rd_VPR128.4S[64,32] = MP_INT_ABS(TMPQ5[64,32]);
+ Rd_VPR128.4S[96,32] = MP_INT_ABS(TMPQ5[96,32]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.227 SABDL, SABDL2 page C7-2536 line 148366 MATCH x0e207000/mask=xbf20fc00
+# CONSTRUCT x4e207000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 $-@2 =$abs@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sabdl2/3@1
+# AUNIT --inst x4e207000/mask=xffe0fc00 --status pass --comment "ext abd"
+
+:sabdl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x7 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
+{
+ TMPD1 = Rn_VPR128.16B[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)
+ TMPQ2[0,16] = sext(TMPD1[0,8]);
+ TMPQ2[16,16] = sext(TMPD1[8,8]);
+ TMPQ2[32,16] = sext(TMPD1[16,8]);
+ TMPQ2[48,16] = sext(TMPD1[24,8]);
+ TMPQ2[64,16] = sext(TMPD1[32,8]);
+ TMPQ2[80,16] = sext(TMPD1[40,8]);
+ TMPQ2[96,16] = sext(TMPD1[48,8]);
+ TMPQ2[112,16] = sext(TMPD1[56,8]);
+ TMPD3 = Rm_VPR128.16B[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2)
+ TMPQ4[0,16] = sext(TMPD3[0,8]);
+ TMPQ4[16,16] = sext(TMPD3[8,8]);
+ TMPQ4[32,16] = sext(TMPD3[16,8]);
+ TMPQ4[48,16] = sext(TMPD3[24,8]);
+ TMPQ4[64,16] = sext(TMPD3[32,8]);
+ TMPQ4[80,16] = sext(TMPD3[40,8]);
+ TMPQ4[96,16] = sext(TMPD3[48,8]);
+ TMPQ4[112,16] = sext(TMPD3[56,8]);
+ # simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 2
+ TMPQ5[0,16] = TMPQ2[0,16] - TMPQ4[0,16];
+ TMPQ5[16,16] = TMPQ2[16,16] - TMPQ4[16,16];
+ TMPQ5[32,16] = TMPQ2[32,16] - TMPQ4[32,16];
+ TMPQ5[48,16] = TMPQ2[48,16] - TMPQ4[48,16];
+ TMPQ5[64,16] = TMPQ2[64,16] - TMPQ4[64,16];
+ TMPQ5[80,16] = TMPQ2[80,16] - TMPQ4[80,16];
+ TMPQ5[96,16] = TMPQ2[96,16] - TMPQ4[96,16];
+ TMPQ5[112,16] = TMPQ2[112,16] - TMPQ4[112,16];
+ # simd unary Rd_VPR128.8H = MP_INT_ABS(TMPQ5) on lane size 2
+ Rd_VPR128.8H[0,16] = MP_INT_ABS(TMPQ5[0,16]);
+ Rd_VPR128.8H[16,16] = MP_INT_ABS(TMPQ5[16,16]);
+ Rd_VPR128.8H[32,16] = MP_INT_ABS(TMPQ5[32,16]);
+ Rd_VPR128.8H[48,16] = MP_INT_ABS(TMPQ5[48,16]);
+ Rd_VPR128.8H[64,16] = MP_INT_ABS(TMPQ5[64,16]);
+ Rd_VPR128.8H[80,16] = MP_INT_ABS(TMPQ5[80,16]);
+ Rd_VPR128.8H[96,16] = MP_INT_ABS(TMPQ5[96,16]);
+ Rd_VPR128.8H[112,16] = MP_INT_ABS(TMPQ5[112,16]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.228 SADALP page C7-2538 line 148486 MATCH x0e206800/mask=xbf3ffc00
+# CONSTRUCT x0e206800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 var:8 ARG2 =#+ &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sadalp/2@1
+# AUNIT --inst x0e206800/mask=xfffffc00 --status pass --comment "ext"
+# Vector variant when 4H when size = 00 , Q = 0 Ta=VPR64.4H Tb=VPR64.8B e1=1 e2=2 s2=16
+
+:sadalp Rd_VPR64.4H, Rn_VPR64.8B
+is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000011010 & Rd_VPR64.4H & Rn_VPR64.8B & Zd
+{
+ TMPD1 = 0;
+ # sipd infix TMPD1 = +(Rn_VPR64.8B) on pairs lane size (1 to 2)
+ local tmp2 = Rn_VPR64.8B[0,8];
+ local tmp4 = sext(tmp2);
+ local tmp3 = Rn_VPR64.8B[8,8];
+ local tmp5 = sext(tmp3);
+ TMPD1[0,16] = tmp4 + tmp5;
+ tmp2 = Rn_VPR64.8B[16,8];
+ tmp4 = sext(tmp2);
+ tmp3 = Rn_VPR64.8B[24,8];
+ tmp5 = sext(tmp3);
+ TMPD1[16,16] = tmp4 + tmp5;
+ tmp2 = Rn_VPR64.8B[32,8];
+ tmp4 = sext(tmp2);
+ tmp3 = Rn_VPR64.8B[40,8];
+ tmp5 = sext(tmp3);
+ TMPD1[32,16] = tmp4 + tmp5;
+ tmp2 = Rn_VPR64.8B[48,8];
+ tmp4 = sext(tmp2);
+ tmp3 = Rn_VPR64.8B[56,8];
+ tmp5 = sext(tmp3);
+ TMPD1[48,16] = tmp4 + tmp5;
+ # simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2
+ Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16];
+ Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16];
+ Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16];
+ Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.228 SADALP page C7-2538 line 148486 MATCH x0e206800/mask=xbf3ffc00
+# CONSTRUCT x4e206800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 var:16 ARG2 =#+ &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sadalp/2@1
+# AUNIT --inst x4e206800/mask=xfffffc00 --status pass --comment "ext"
+# Vector variant when 8H when size = 00 , Q = 1 Ta=VPR128.8H Tb=VPR128.16B e1=1 e2=2 s2=32
+
+:sadalp Rd_VPR128.8H, Rn_VPR128.16B
+is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000011010 & Rd_VPR128.8H & Rn_VPR128.16B & Zd
+{
+ TMPQ1 = 0;
+ # sipd infix TMPQ1 = +(Rn_VPR128.16B) on pairs lane size (1 to 2)
+ local tmp2 = Rn_VPR128.16B[0,8];
+ local tmp4 = sext(tmp2);
+ local tmp3 = Rn_VPR128.16B[8,8];
+ local tmp5 = sext(tmp3);
+ TMPQ1[0,16] = tmp4 + tmp5;
+ tmp2 = Rn_VPR128.16B[16,8];
+ tmp4 = sext(tmp2);
+ tmp3 = Rn_VPR128.16B[24,8];
+ tmp5 = sext(tmp3);
+ TMPQ1[16,16] = tmp4 + tmp5;
+ tmp2 = Rn_VPR128.16B[32,8];
+ tmp4 = sext(tmp2);
+ tmp3 = Rn_VPR128.16B[40,8];
+ tmp5 = sext(tmp3);
+ TMPQ1[32,16] = tmp4 + tmp5;
+ tmp2 = Rn_VPR128.16B[48,8];
+ tmp4 = sext(tmp2);
+ tmp3 = Rn_VPR128.16B[56,8];
+ tmp5 = sext(tmp3);
+ TMPQ1[48,16] = tmp4 + tmp5;
+ tmp2 = Rn_VPR128.16B[64,8];
+ tmp4 = sext(tmp2);
+ tmp3 = Rn_VPR128.16B[72,8];
+ tmp5 = sext(tmp3);
+ TMPQ1[64,16] = tmp4 + tmp5;
+ tmp2 = Rn_VPR128.16B[80,8];
+ tmp4 = sext(tmp2);
+ tmp3 = Rn_VPR128.16B[88,8];
+ tmp5 = sext(tmp3);
+ TMPQ1[80,16] = tmp4 + tmp5;
+ tmp2 = Rn_VPR128.16B[96,8];
+ tmp4 = sext(tmp2);
+ tmp3 = Rn_VPR128.16B[104,8];
+ tmp5 = sext(tmp3);
+ TMPQ1[96,16] = tmp4 + tmp5;
+ tmp2 = Rn_VPR128.16B[112,8];
+ tmp4 = sext(tmp2);
+ tmp3 = Rn_VPR128.16B[120,8];
+ tmp5 = sext(tmp3);
+ TMPQ1[112,16] = tmp4 + tmp5;
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.228 SADALP page C7-2538 line 148486 MATCH x0e206800/mask=xbf3ffc00
+# CONSTRUCT x0e606800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 var:8 ARG2 =#+ &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sadalp/2@2
+# AUNIT --inst x0e606800/mask=xfffffc00 --status pass --comment "ext"
+# Vector variant when 2S when size = 01 , Q = 0 Ta=VPR64.2S Tb=VPR64.4H e1=2 e2=4 s2=16
+
+:sadalp Rd_VPR64.2S, Rn_VPR64.4H
+is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000011010 & Rd_VPR64.2S & Rn_VPR64.4H & Zd
+{
+ TMPD1 = 0;
+ # sipd infix TMPD1 = +(Rn_VPR64.4H) on pairs lane size (2 to 4)
+ local tmp2 = Rn_VPR64.4H[0,16];
+ local tmp4 = sext(tmp2);
+ local tmp3 = Rn_VPR64.4H[16,16];
+ local tmp5 = sext(tmp3);
+ TMPD1[0,32] = tmp4 + tmp5;
+ tmp2 = Rn_VPR64.4H[32,16];
+ tmp4 = sext(tmp2);
+ tmp3 = Rn_VPR64.4H[48,16];
+ tmp5 = sext(tmp3);
+ TMPD1[32,32] = tmp4 + tmp5;
+ # simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4
+ Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32];
+ Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.228 SADALP page C7-2538 line 148486 MATCH x0e206800/mask=xbf3ffc00
+# CONSTRUCT x4e606800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 var:16 ARG2 =#+ &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sadalp/2@2
+# AUNIT --inst x4e606800/mask=xfffffc00 --status pass --comment "ext"
+# Vector variant when 4S when size = 01 , Q = 1 Ta=VPR128.4S Tb=VPR128.8H e1=2 e2=4 s2=32
+
+:sadalp Rd_VPR128.4S, Rn_VPR128.8H
+is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000011010 & Rd_VPR128.4S & Rn_VPR128.8H & Zd
+{
+ TMPQ1 = 0;
+ # sipd infix TMPQ1 = +(Rn_VPR128.8H) on pairs lane size (2 to 4)
+ local tmp2 = Rn_VPR128.8H[0,16];
+ local tmp4 = sext(tmp2);
+ local tmp3 = Rn_VPR128.8H[16,16];
+ local tmp5 = sext(tmp3);
+ TMPQ1[0,32] = tmp4 + tmp5;
+ tmp2 = Rn_VPR128.8H[32,16];
+ tmp4 = sext(tmp2);
+ tmp3 = Rn_VPR128.8H[48,16];
+ tmp5 = sext(tmp3);
+ TMPQ1[32,32] = tmp4 + tmp5;
+ tmp2 = Rn_VPR128.8H[64,16];
+ tmp4 = sext(tmp2);
+ tmp3 = Rn_VPR128.8H[80,16];
+ tmp5 = sext(tmp3);
+ TMPQ1[64,32] = tmp4 + tmp5;
+ tmp2 = Rn_VPR128.8H[96,16];
+ tmp4 = sext(tmp2);
+ tmp3 = Rn_VPR128.8H[112,16];
+ tmp5 = sext(tmp3);
+ TMPQ1[96,32] = tmp4 + tmp5;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.228 SADALP page C7-2538 line 148486 MATCH x0e206800/mask=xbf3ffc00
+# CONSTRUCT x0ea06800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 var:8 ARG2 =#+ &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sadalp/2@4
+# AUNIT --inst x0ea06800/mask=xfffffc00 --status pass --comment "ext"
+# Vector variant when 1D when size = 10 , Q = 0 Ta=VPR64.1D Tb=VPR64.2S e1=4 e2=8 s2=16
+
+:sadalp Rd_VPR64.1D, Rn_VPR64.2S
+is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000011010 & Rd_VPR64.1D & Rn_VPR64.2S & Zd
+{
+ TMPD1 = 0;
+ # sipd infix TMPD1 = +(Rn_VPR64.2S) on pairs lane size (4 to 8)
+ local tmp2 = Rn_VPR64.2S[0,32];
+ local tmp4 = sext(tmp2);
+ local tmp3 = Rn_VPR64.2S[32,32];
+ local tmp5 = sext(tmp3);
+ TMPD1 = tmp4 + tmp5;
+ # simd infix Rd_VPR64.1D = Rd_VPR64.1D + TMPD1 on lane size 8
+ Rd_VPR64.1D = Rd_VPR64.1D + TMPD1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.228 SADALP page C7-2538 line 148486 MATCH x0e206800/mask=xbf3ffc00
+# CONSTRUCT x4ea06800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 var:16 ARG2 =#+ &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sadalp/2@4
+# AUNIT --inst x4ea06800/mask=xfffffc00 --status pass --comment "ext"
+# Vector variant when 2D when size = 10 , Q = 1 Ta=VPR128.2D Tb=VPR128.4S e1=4 e2=8 s2=32
+
+:sadalp Rd_VPR128.2D, Rn_VPR128.4S
+is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000011010 & Rd_VPR128.2D & Rn_VPR128.4S & Zd
+{
+ TMPQ1 = 0;
+ # sipd infix TMPQ1 = +(Rn_VPR128.4S) on pairs lane size (4 to 8)
+ local tmp2 = Rn_VPR128.4S[0,32];
+ local tmp4 = sext(tmp2);
+ local tmp3 = Rn_VPR128.4S[32,32];
+ local tmp5 = sext(tmp3);
+ TMPQ1[0,64] = tmp4 + tmp5;
+ tmp2 = Rn_VPR128.4S[64,32];
+ tmp4 = sext(tmp2);
+ tmp3 = Rn_VPR128.4S[96,32];
+ tmp5 = sext(tmp3);
+ TMPQ1[64,64] = tmp4 + tmp5;
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ1 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ1[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ1[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.229 SADDL, SADDL2 page C7-2540 line 148596 MATCH x0e200000/mask=xbf20fc00
+# CONSTRUCT x0ea00000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 =$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_saddl/2@4
+# AUNIT --inst x0ea00000/mask=xffe0fc00 --status pass --comment "ext"
+
+:saddl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x0 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);
+ TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);
+ # simd infix Rd_VPR128.2D = TMPQ1 + TMPQ2 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ1[0,64] + TMPQ2[0,64];
+ Rd_VPR128.2D[64,64] = TMPQ1[64,64] + TMPQ2[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.229 SADDL, SADDL2 page C7-2540 line 148596 MATCH x0e200000/mask=xbf20fc00
+# CONSTRUCT x0e600000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 =$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddl/2@2
+# AUNIT --inst x0e600000/mask=xffe0fc00 --status pass --comment "ext"
+
+:saddl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x0 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);
+ TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);
+ TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);
+ TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);
+ # simd infix Rd_VPR128.4S = TMPQ1 + TMPQ2 on lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ1[0,32] + TMPQ2[0,32];
+ Rd_VPR128.4S[32,32] = TMPQ1[32,32] + TMPQ2[32,32];
+ Rd_VPR128.4S[64,32] = TMPQ1[64,32] + TMPQ2[64,32];
+ Rd_VPR128.4S[96,32] = TMPQ1[96,32] + TMPQ2[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.229 SADDL, SADDL2 page C7-2540 line 148596 MATCH x0e200000/mask=xbf20fc00
+# CONSTRUCT x0e200000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 =$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddl/2@1
+# AUNIT --inst x0e200000/mask=xffe0fc00 --status pass --comment "ext"
+
+:saddl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x0 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)
+ TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);
+ TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);
+ TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);
+ TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);
+ TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);
+ TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);
+ TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);
+ TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2)
+ TMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]);
+ TMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]);
+ TMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]);
+ TMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]);
+ TMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]);
+ TMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]);
+ TMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]);
+ TMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]);
+ # simd infix Rd_VPR128.8H = TMPQ1 + TMPQ2 on lane size 2
+ Rd_VPR128.8H[0,16] = TMPQ1[0,16] + TMPQ2[0,16];
+ Rd_VPR128.8H[16,16] = TMPQ1[16,16] + TMPQ2[16,16];
+ Rd_VPR128.8H[32,16] = TMPQ1[32,16] + TMPQ2[32,16];
+ Rd_VPR128.8H[48,16] = TMPQ1[48,16] + TMPQ2[48,16];
+ Rd_VPR128.8H[64,16] = TMPQ1[64,16] + TMPQ2[64,16];
+ Rd_VPR128.8H[80,16] = TMPQ1[80,16] + TMPQ2[80,16];
+ Rd_VPR128.8H[96,16] = TMPQ1[96,16] + TMPQ2[96,16];
+ Rd_VPR128.8H[112,16] = TMPQ1[112,16] + TMPQ2[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.229 SADDL, SADDL2 page C7-2540 line 148596 MATCH x0e200000/mask=xbf20fc00
+# CONSTRUCT x4ea00000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 =$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddl2/2@4
+# AUNIT --inst x4ea00000/mask=xffe0fc00 --status pass --comment "ext"
+
+:saddl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x0 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(TMPD1[0,32]);
+ TMPQ2[64,64] = sext(TMPD1[32,32]);
+ TMPD3 = Rm_VPR128.4S[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)
+ TMPQ4[0,64] = sext(TMPD3[0,32]);
+ TMPQ4[64,64] = sext(TMPD3[32,32]);
+ # simd infix Rd_VPR128.2D = TMPQ2 + TMPQ4 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ2[0,64] + TMPQ4[0,64];
+ Rd_VPR128.2D[64,64] = TMPQ2[64,64] + TMPQ4[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.229 SADDL, SADDL2 page C7-2540 line 148596 MATCH x0e200000/mask=xbf20fc00
+# CONSTRUCT x4e600000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 =$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddl2/2@2
+# AUNIT --inst x4e600000/mask=xffe0fc00 --status pass --comment "ext"
+
+:saddl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x0 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(TMPD1[0,16]);
+ TMPQ2[32,32] = sext(TMPD1[16,16]);
+ TMPQ2[64,32] = sext(TMPD1[32,16]);
+ TMPQ2[96,32] = sext(TMPD1[48,16]);
+ TMPD3 = Rm_VPR128.8H[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)
+ TMPQ4[0,32] = sext(TMPD3[0,16]);
+ TMPQ4[32,32] = sext(TMPD3[16,16]);
+ TMPQ4[64,32] = sext(TMPD3[32,16]);
+ TMPQ4[96,32] = sext(TMPD3[48,16]);
+ # simd infix Rd_VPR128.4S = TMPQ2 + TMPQ4 on lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ2[0,32] + TMPQ4[0,32];
+ Rd_VPR128.4S[32,32] = TMPQ2[32,32] + TMPQ4[32,32];
+ Rd_VPR128.4S[64,32] = TMPQ2[64,32] + TMPQ4[64,32];
+ Rd_VPR128.4S[96,32] = TMPQ2[96,32] + TMPQ4[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.229 SADDL, SADDL2 page C7-2540 line 148596 MATCH x0e200000/mask=xbf20fc00
+# CONSTRUCT x4e200000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 =$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddl2/2@1
+# AUNIT --inst x4e200000/mask=xffe0fc00 --status pass --comment "ext"
+
+:saddl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x0 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
+{
+ TMPD1 = Rn_VPR128.16B[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)
+ TMPQ2[0,16] = sext(TMPD1[0,8]);
+ TMPQ2[16,16] = sext(TMPD1[8,8]);
+ TMPQ2[32,16] = sext(TMPD1[16,8]);
+ TMPQ2[48,16] = sext(TMPD1[24,8]);
+ TMPQ2[64,16] = sext(TMPD1[32,8]);
+ TMPQ2[80,16] = sext(TMPD1[40,8]);
+ TMPQ2[96,16] = sext(TMPD1[48,8]);
+ TMPQ2[112,16] = sext(TMPD1[56,8]);
+ TMPD3 = Rm_VPR128.16B[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2)
+ TMPQ4[0,16] = sext(TMPD3[0,8]);
+ TMPQ4[16,16] = sext(TMPD3[8,8]);
+ TMPQ4[32,16] = sext(TMPD3[16,8]);
+ TMPQ4[48,16] = sext(TMPD3[24,8]);
+ TMPQ4[64,16] = sext(TMPD3[32,8]);
+ TMPQ4[80,16] = sext(TMPD3[40,8]);
+ TMPQ4[96,16] = sext(TMPD3[48,8]);
+ TMPQ4[112,16] = sext(TMPD3[56,8]);
+ # simd infix Rd_VPR128.8H = TMPQ2 + TMPQ4 on lane size 2
+ Rd_VPR128.8H[0,16] = TMPQ2[0,16] + TMPQ4[0,16];
+ Rd_VPR128.8H[16,16] = TMPQ2[16,16] + TMPQ4[16,16];
+ Rd_VPR128.8H[32,16] = TMPQ2[32,16] + TMPQ4[32,16];
+ Rd_VPR128.8H[48,16] = TMPQ2[48,16] + TMPQ4[48,16];
+ Rd_VPR128.8H[64,16] = TMPQ2[64,16] + TMPQ4[64,16];
+ Rd_VPR128.8H[80,16] = TMPQ2[80,16] + TMPQ4[80,16];
+ Rd_VPR128.8H[96,16] = TMPQ2[96,16] + TMPQ4[96,16];
+ Rd_VPR128.8H[112,16] = TMPQ2[112,16] + TMPQ4[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.230 SADDLP page C7-2542 line 148719 MATCH x0e202800/mask=xbf3ffc00
+# CONSTRUCT x0ea02800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =var =#+@4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlp/1@4
+# AUNIT --inst x0ea02800/mask=xfffffc00 --status pass --comment "ext"
+
+:saddlp Rd_VPR64.1D, Rn_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=2 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.1D & Zd
+{
+ TMPD1 = Rn_VPR64.2S;
+ # sipd infix Rd_VPR64.1D = +(TMPD1) on pairs lane size (4 to 8)
+ local tmp2 = TMPD1[0,32];
+ local tmp4 = sext(tmp2);
+ local tmp3 = TMPD1[32,32];
+ local tmp5 = sext(tmp3);
+ Rd_VPR64.1D = tmp4 + tmp5;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.230 SADDLP page C7-2542 line 148719 MATCH x0e202800/mask=xbf3ffc00
+# CONSTRUCT x0e602800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =var =#+@2
+# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlp/1@2
+# AUNIT --inst x0e602800/mask=xfffffc00 --status pass --comment "ext"
+
+:saddlp Rd_VPR64.2S, Rn_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=2 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.2S & Zd
+{
+ TMPD1 = Rn_VPR64.4H;
+ # sipd infix Rd_VPR64.2S = +(TMPD1) on pairs lane size (2 to 4)
+ local tmp2 = TMPD1[0,16];
+ local tmp4 = sext(tmp2);
+ local tmp3 = TMPD1[16,16];
+ local tmp5 = sext(tmp3);
+ Rd_VPR64.2S[0,32] = tmp4 + tmp5;
+ tmp2 = TMPD1[32,16];
+ tmp4 = sext(tmp2);
+ tmp3 = TMPD1[48,16];
+ tmp5 = sext(tmp3);
+ Rd_VPR64.2S[32,32] = tmp4 + tmp5;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.230 SADDLP page C7-2542 line 148719 MATCH x0e202800/mask=xbf3ffc00
+# CONSTRUCT x0e202800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =var =#+@1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlp/1@1
+# AUNIT --inst x0e202800/mask=xfffffc00 --status pass --comment "ext"
+
+:saddlp Rd_VPR64.4H, Rn_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=2 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.4H & Zd
+{
+ TMPD1 = Rn_VPR64.8B;
+ # sipd infix Rd_VPR64.4H = +(TMPD1) on pairs lane size (1 to 2)
+ local tmp2 = TMPD1[0,8];
+ local tmp4 = sext(tmp2);
+ local tmp3 = TMPD1[8,8];
+ local tmp5 = sext(tmp3);
+ Rd_VPR64.4H[0,16] = tmp4 + tmp5;
+ tmp2 = TMPD1[16,8];
+ tmp4 = sext(tmp2);
+ tmp3 = TMPD1[24,8];
+ tmp5 = sext(tmp3);
+ Rd_VPR64.4H[16,16] = tmp4 + tmp5;
+ tmp2 = TMPD1[32,8];
+ tmp4 = sext(tmp2);
+ tmp3 = TMPD1[40,8];
+ tmp5 = sext(tmp3);
+ Rd_VPR64.4H[32,16] = tmp4 + tmp5;
+ tmp2 = TMPD1[48,8];
+ tmp4 = sext(tmp2);
+ tmp3 = TMPD1[56,8];
+ tmp5 = sext(tmp3);
+ Rd_VPR64.4H[48,16] = tmp4 + tmp5;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.230 SADDLP page C7-2542 line 148719 MATCH x0e202800/mask=xbf3ffc00
+# CONSTRUCT x4ea02800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =var =#+@4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlp/1@4
+# AUNIT --inst x4ea02800/mask=xfffffc00 --status pass --comment "ext"
+
+:saddlp Rd_VPR128.2D, Rn_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=2 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPQ1 = Rn_VPR128.4S;
+ # sipd infix Rd_VPR128.2D = +(TMPQ1) on pairs lane size (4 to 8)
+ local tmp2 = TMPQ1[0,32];
+ local tmp4 = sext(tmp2);
+ local tmp3 = TMPQ1[32,32];
+ local tmp5 = sext(tmp3);
+ Rd_VPR128.2D[0,64] = tmp4 + tmp5;
+ tmp2 = TMPQ1[64,32];
+ tmp4 = sext(tmp2);
+ tmp3 = TMPQ1[96,32];
+ tmp5 = sext(tmp3);
+ Rd_VPR128.2D[64,64] = tmp4 + tmp5;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.230 SADDLP page C7-2542 line 148719 MATCH x0e202800/mask=xbf3ffc00
+# CONSTRUCT x4e602800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =var =#+@2
+# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlp/1@2
+# AUNIT --inst x4e602800/mask=xfffffc00 --status pass --comment "ext"
+
+:saddlp Rd_VPR128.4S, Rn_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=2 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPQ1 = Rn_VPR128.8H;
+ # sipd infix Rd_VPR128.4S = +(TMPQ1) on pairs lane size (2 to 4)
+ local tmp2 = TMPQ1[0,16];
+ local tmp4 = sext(tmp2);
+ local tmp3 = TMPQ1[16,16];
+ local tmp5 = sext(tmp3);
+ Rd_VPR128.4S[0,32] = tmp4 + tmp5;
+ tmp2 = TMPQ1[32,16];
+ tmp4 = sext(tmp2);
+ tmp3 = TMPQ1[48,16];
+ tmp5 = sext(tmp3);
+ Rd_VPR128.4S[32,32] = tmp4 + tmp5;
+ tmp2 = TMPQ1[64,16];
+ tmp4 = sext(tmp2);
+ tmp3 = TMPQ1[80,16];
+ tmp5 = sext(tmp3);
+ Rd_VPR128.4S[64,32] = tmp4 + tmp5;
+ tmp2 = TMPQ1[96,16];
+ tmp4 = sext(tmp2);
+ tmp3 = TMPQ1[112,16];
+ tmp5 = sext(tmp3);
+ Rd_VPR128.4S[96,32] = tmp4 + tmp5;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.230 SADDLP page C7-2542 line 148719 MATCH x0e202800/mask=xbf3ffc00
+# CONSTRUCT x4e202800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =var =#+@1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlp/1@1
+# AUNIT --inst x4e202800/mask=xfffffc00 --status pass --comment "ext"
+
+:saddlp Rd_VPR128.8H, Rn_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=2 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
+{
+ TMPQ1 = Rn_VPR128.16B;
+ # sipd infix Rd_VPR128.8H = +(TMPQ1) on pairs lane size (1 to 2)
+ local tmp2 = TMPQ1[0,8];
+ local tmp4 = sext(tmp2);
+ local tmp3 = TMPQ1[8,8];
+ local tmp5 = sext(tmp3);
+ Rd_VPR128.8H[0,16] = tmp4 + tmp5;
+ tmp2 = TMPQ1[16,8];
+ tmp4 = sext(tmp2);
+ tmp3 = TMPQ1[24,8];
+ tmp5 = sext(tmp3);
+ Rd_VPR128.8H[16,16] = tmp4 + tmp5;
+ tmp2 = TMPQ1[32,8];
+ tmp4 = sext(tmp2);
+ tmp3 = TMPQ1[40,8];
+ tmp5 = sext(tmp3);
+ Rd_VPR128.8H[32,16] = tmp4 + tmp5;
+ tmp2 = TMPQ1[48,8];
+ tmp4 = sext(tmp2);
+ tmp3 = TMPQ1[56,8];
+ tmp5 = sext(tmp3);
+ Rd_VPR128.8H[48,16] = tmp4 + tmp5;
+ tmp2 = TMPQ1[64,8];
+ tmp4 = sext(tmp2);
+ tmp3 = TMPQ1[72,8];
+ tmp5 = sext(tmp3);
+ Rd_VPR128.8H[64,16] = tmp4 + tmp5;
+ tmp2 = TMPQ1[80,8];
+ tmp4 = sext(tmp2);
+ tmp3 = TMPQ1[88,8];
+ tmp5 = sext(tmp3);
+ Rd_VPR128.8H[80,16] = tmp4 + tmp5;
+ tmp2 = TMPQ1[96,8];
+ tmp4 = sext(tmp2);
+ tmp3 = TMPQ1[104,8];
+ tmp5 = sext(tmp3);
+ Rd_VPR128.8H[96,16] = tmp4 + tmp5;
+ tmp2 = TMPQ1[112,8];
+ tmp4 = sext(tmp2);
+ tmp3 = TMPQ1[120,8];
+ tmp5 = sext(tmp3);
+ Rd_VPR128.8H[112,16] = tmp4 + tmp5;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.231 SADDLV page C7-2544 line 148829 MATCH x0e303800/mask=xbf3ffc00
+# CONSTRUCT x4eb03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlv/1@4
+# AUNIT --inst x4eb03800/mask=xfffffc00 --status nopcodeop --comment "ext"
+
+:saddlv Rd_FPR64, Rn_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR128.4S & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_saddlv(Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.231 SADDLV page C7-2544 line 148829 MATCH x0e303800/mask=xbf3ffc00
+# CONSTRUCT x4e303800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlv/1@1
+# AUNIT --inst x4e303800/mask=xfffffc00 --status nopcodeop --comment "ext"
+
+:saddlv Rd_FPR16, Rn_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR128.16B & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_saddlv(Rn_VPR128.16B, 1:1);
+}
+
+# C7.2.231 SADDLV page C7-2544 line 148829 MATCH x0e303800/mask=xbf3ffc00
+# CONSTRUCT x0e303800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlv/1@1
+# AUNIT --inst x0e303800/mask=xfffffc00 --status nopcodeop --comment "ext"
+
+:saddlv Rd_FPR16, Rn_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR64.8B & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_saddlv(Rn_VPR64.8B, 1:1);
+}
+
+# C7.2.231 SADDLV page C7-2544 line 148829 MATCH x0e303800/mask=xbf3ffc00
+# CONSTRUCT x0e703800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlv/1@2
+# AUNIT --inst x0e703800/mask=xfffffc00 --status nopcodeop --comment "ext"
+
+:saddlv Rd_FPR32, Rn_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR64.4H & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_saddlv(Rn_VPR64.4H, 2:1);
+}
+
+# C7.2.231 SADDLV page C7-2544 line 148829 MATCH x0e303800/mask=xbf3ffc00
+# CONSTRUCT x4e703800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_saddlv/1@2
+# AUNIT --inst x4e703800/mask=xfffffc00 --status nopcodeop --comment "ext"
+
+:saddlv Rd_FPR32, Rn_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR128.8H & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_saddlv(Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.232 SADDW, SADDW2 page C7-2546 line 148929 MATCH x0e201000/mask=xbf20fc00
+# CONSTRUCT x0ea01000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $sext@4:16 =$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddw/2@4
+# AUNIT --inst x0ea01000/mask=xffe0fc00 --status pass --comment "ext"
+
+:saddw Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x1 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = sext(Rm_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = sext(Rm_VPR64.2S[0,32]);
+ TMPQ1[64,64] = sext(Rm_VPR64.2S[32,32]);
+ # simd infix Rd_VPR128.2D = Rn_VPR128.2D + TMPQ1 on lane size 8
+ Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] + TMPQ1[0,64];
+ Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] + TMPQ1[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.232 SADDW, SADDW2 page C7-2546 line 148929 MATCH x0e201000/mask=xbf20fc00
+# CONSTRUCT x0e601000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $sext@2:16 =$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddw/2@2
+# AUNIT --inst x0e601000/mask=xffe0fc00 --status pass --comment "ext"
+
+:saddw Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x1 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = sext(Rm_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = sext(Rm_VPR64.4H[0,16]);
+ TMPQ1[32,32] = sext(Rm_VPR64.4H[16,16]);
+ TMPQ1[64,32] = sext(Rm_VPR64.4H[32,16]);
+ TMPQ1[96,32] = sext(Rm_VPR64.4H[48,16]);
+ # simd infix Rd_VPR128.4S = Rn_VPR128.4S + TMPQ1 on lane size 4
+ Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] + TMPQ1[0,32];
+ Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] + TMPQ1[32,32];
+ Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] + TMPQ1[64,32];
+ Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] + TMPQ1[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.232 SADDW, SADDW2 page C7-2546 line 148929 MATCH x0e201000/mask=xbf20fc00
+# CONSTRUCT x0e201000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $sext@1:16 =$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddw/2@1
+# AUNIT --inst x0e201000/mask=xffe0fc00 --status pass --comment "ext"
+
+:saddw Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x1 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ # simd resize TMPQ1 = sext(Rm_VPR64.8B) (lane size 1 to 2)
+ TMPQ1[0,16] = sext(Rm_VPR64.8B[0,8]);
+ TMPQ1[16,16] = sext(Rm_VPR64.8B[8,8]);
+ TMPQ1[32,16] = sext(Rm_VPR64.8B[16,8]);
+ TMPQ1[48,16] = sext(Rm_VPR64.8B[24,8]);
+ TMPQ1[64,16] = sext(Rm_VPR64.8B[32,8]);
+ TMPQ1[80,16] = sext(Rm_VPR64.8B[40,8]);
+ TMPQ1[96,16] = sext(Rm_VPR64.8B[48,8]);
+ TMPQ1[112,16] = sext(Rm_VPR64.8B[56,8]);
+ # simd infix Rd_VPR128.8H = Rn_VPR128.8H + TMPQ1 on lane size 2
+ Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] + TMPQ1[0,16];
+ Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] + TMPQ1[16,16];
+ Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] + TMPQ1[32,16];
+ Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] + TMPQ1[48,16];
+ Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] + TMPQ1[64,16];
+ Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] + TMPQ1[80,16];
+ Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] + TMPQ1[96,16];
+ Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] + TMPQ1[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.232 SADDW, SADDW2 page C7-2546 line 148929 MATCH x0e201000/mask=xbf20fc00
+# CONSTRUCT x4ea01000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3[1]:8 $sext@4:16 =$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddw2/2@4
+# AUNIT --inst x4ea01000/mask=xffe0fc00 --status pass --comment "ext"
+
+:saddw2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x1 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rm_VPR128.4S[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(TMPD1[0,32]);
+ TMPQ2[64,64] = sext(TMPD1[32,32]);
+ # simd infix Rd_VPR128.2D = Rn_VPR128.2D + TMPQ2 on lane size 8
+ Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] + TMPQ2[0,64];
+ Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] + TMPQ2[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.232 SADDW, SADDW2 page C7-2546 line 148929 MATCH x0e201000/mask=xbf20fc00
+# CONSTRUCT x4e601000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3[1]:8 $sext@2:16 =$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddw2/2@2
+# AUNIT --inst x4e601000/mask=xffe0fc00 --status pass --comment "ext"
+
+:saddw2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x1 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rm_VPR128.8H[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(TMPD1[0,16]);
+ TMPQ2[32,32] = sext(TMPD1[16,16]);
+ TMPQ2[64,32] = sext(TMPD1[32,16]);
+ TMPQ2[96,32] = sext(TMPD1[48,16]);
+ # simd infix Rd_VPR128.4S = Rn_VPR128.4S + TMPQ2 on lane size 4
+ Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] + TMPQ2[0,32];
+ Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] + TMPQ2[32,32];
+ Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] + TMPQ2[64,32];
+ Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] + TMPQ2[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.232 SADDW, SADDW2 page C7-2546 line 148929 MATCH x0e201000/mask=xbf20fc00
+# CONSTRUCT x4e201000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3[1]:8 $sext@1:16 =$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_saddw2/2@1
+# AUNIT --inst x4e201000/mask=xffe0fc00 --status pass --comment "ext"
+
+:saddw2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x1 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ TMPD1 = Rm_VPR128.16B[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)
+ TMPQ2[0,16] = sext(TMPD1[0,8]);
+ TMPQ2[16,16] = sext(TMPD1[8,8]);
+ TMPQ2[32,16] = sext(TMPD1[16,8]);
+ TMPQ2[48,16] = sext(TMPD1[24,8]);
+ TMPQ2[64,16] = sext(TMPD1[32,8]);
+ TMPQ2[80,16] = sext(TMPD1[40,8]);
+ TMPQ2[96,16] = sext(TMPD1[48,8]);
+ TMPQ2[112,16] = sext(TMPD1[56,8]);
+ # simd infix Rd_VPR128.8H = Rn_VPR128.8H + TMPQ2 on lane size 2
+ Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] + TMPQ2[0,16];
+ Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] + TMPQ2[16,16];
+ Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] + TMPQ2[32,16];
+ Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] + TMPQ2[48,16];
+ Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] + TMPQ2[64,16];
+ Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] + TMPQ2[80,16];
+ Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] + TMPQ2[96,16];
+ Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] + TMPQ2[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x5f00e400/mask=xff80fc00
+# CONSTRUCT x5f40e400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2
+# AUNIT --inst x5f40e400/mask=xffc0fc00 --status nopcodeop --comment "nofpround"
+
+:scvtf Rd_FPR64, Rn_FPR64, Imm_shr_imm64
+is b_3031=1 & u=0 & b_2428=0x1f & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x1c & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_scvtf(Rn_FPR64, Imm_shr_imm64:4);
+}
+
+# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x5f00e400/mask=xff80fc00
+# CONSTRUCT x5f20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2
+# AUNIT --inst x5f20e400/mask=xffe0fc00 --status nopcodeop --comment "nofpround"
+
+:scvtf Rd_FPR32, Rn_FPR32, Imm_shr_imm32
+is b_3031=1 & u=0 & b_2428=0x1f & b_2123=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_scvtf(Rn_FPR32, Imm_shr_imm32:4);
+}
+
+# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x5f00e400/mask=xff80fc00
+# CONSTRUCT x5f10e400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2
+# AUNIT --inst x5f10e400/mask=xfff0fc00 --status noqemu --comment "nofpround"
+
+:scvtf Rd_FPR16, Rn_FPR16, Imm_shr_imm16
+is b_3031=1 & u=0 & b_2428=0x1f & b_2023=1 & Imm_shr_imm16 & b_1115=0x1c & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_scvtf(Rn_FPR16, Imm_shr_imm16:4);
+}
+
+# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x0f00e400/mask=xbf80fc00
+# CONSTRUCT x4f40e400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2@8
+# AUNIT --inst x4f40e400/mask=xffc0fc00 --status nopcodeop --comment "nofpround"
+
+:scvtf Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x1c & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_scvtf(Rn_VPR128.2D, Imm_shr_imm64:4, 8:1);
+}
+
+# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x0f00e400/mask=xbf80fc00
+# CONSTRUCT x0f20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2@4
+# AUNIT --inst x0f20e400/mask=xffe0fc00 --status nopcodeop --comment "nofpround"
+
+:scvtf Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_scvtf(Rn_VPR64.2S, Imm_shr_imm32:4, 4:1);
+}
+
+# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x0f00e400/mask=xbf80fc00
+# CONSTRUCT x4f20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2@4
+# AUNIT --inst x4f20e400/mask=xffe0fc00 --status nopcodeop --comment "nofpround"
+
+:scvtf Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_scvtf(Rn_VPR128.4S, Imm_shr_imm32:4, 4:1);
+}
+
+# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x0f00e400/mask=xbf80fc00
+# CONSTRUCT x0f10e400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2@2
+# AUNIT --inst x0f10e400/mask=xfff0fc00 --status noqemu --comment "nofpround"
+
+:scvtf Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm32
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_scvtf(Rn_VPR64.4H, Imm_shr_imm32:4, 2:1);
+}
+
+# C7.2.233 SCVTF (vector, fixed-point) page C7-2548 line 149051 MATCH x0f00e400/mask=xbf80fc00
+# CONSTRUCT x4f10e400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:4 =NEON_scvtf/2@2
+# AUNIT --inst x4f10e400/mask=xfff0fc00 --status noqemu --comment "nofpround"
+
+:scvtf Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm32
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_scvtf(Rn_VPR128.8H, Imm_shr_imm32:4, 2:1);
+}
+
+# C7.2.234 SCVTF (vector, integer) page C7-2551 line 149206 MATCH x5e21d800/mask=xffbffc00
+# CONSTRUCT x5e21d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =int2float
+# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1
+# AUNIT --inst x5e21d800/mask=xfffffc00 --status fail --comment "nofpround"
+
+:scvtf Rd_FPR32, Rn_FPR32
+is b_3031=1 & u=0 & b_2428=0x1e & size_high=0 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = int2float(Rn_FPR32);
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.234 SCVTF (vector, integer) page C7-2551 line 149206 MATCH x5e21d800/mask=xffbffc00
+# CONSTRUCT x5e61d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =int2float
+# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1
+# AUNIT --inst x5e61d800/mask=xfffffc00 --status pass --comment "nofpround"
+
+:scvtf Rd_FPR64, Rn_FPR64
+is b_3031=1 & u=0 & b_2428=0x1e & size_high=0 & b_1722=0x30 & b_1216=0x1d & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = int2float(Rn_FPR64);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.234 SCVTF (vector, integer) page C7-2551 line 149206 MATCH x0e21d800/mask=xbfbffc00
+# CONSTRUCT x4e61d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1@8
+# AUNIT --inst x4e61d800/mask=xfffffc00 --status nopcodeop --comment "nofpround"
+
+:scvtf Rd_VPR128.2D, Rn_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & size_high=0 & b_1722=0x30 & b_1216=0x1d & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_scvtf(Rn_VPR128.2D, 8:1);
+}
+
+# C7.2.234 SCVTF (vector, integer) page C7-2551 line 149206 MATCH x0e21d800/mask=xbfbffc00
+# CONSTRUCT x0e21d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1@4
+# AUNIT --inst x0e21d800/mask=xfffffc00 --status nopcodeop --comment "nofpround"
+
+:scvtf Rd_VPR64.2S, Rn_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & size_high=0 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_scvtf(Rn_VPR64.2S, 4:1);
+}
+
+# C7.2.234 SCVTF (vector, integer) page C7-2551 line 149206 MATCH x0e21d800/mask=xbfbffc00
+# CONSTRUCT x4e21d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1@4
+# AUNIT --inst x4e21d800/mask=xfffffc00 --status nopcodeop --comment "nofpround"
+
+:scvtf Rd_VPR128.4S, Rn_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & size_high=0 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_scvtf(Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.234 SCVTF (vector, integer) page C7-2551 line 149206 MATCH x5e79d800/mask=xfffffc00
+# CONSTRUCT x5e79d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =int2float
+# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1
+# AUNIT --inst x5e79d800/mask=xfffffc00 --status noqemu --comment "nofpround"
+# Scalar half precision variant
+
+:scvtf Rd_FPR16, Rn_FPR16
+is b_1031=0b0101111001111001110110 & Rd_FPR16 & Rn_FPR16 & Zd
+{
+ Rd_FPR16 = int2float(Rn_FPR16);
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.234 SCVTF (vector, integer) page C7-2551 line 149206 MATCH x0e79d800/mask=xbffffc00
+# CONSTRUCT x0e79d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1@2
+# AUNIT --inst x0e79d800/mask=xfffffc00 --status noqemu --comment "nofpround"
+# Vector half precision variant when Q=0 suf=VPR64.4H
+
+:scvtf Rd_VPR64.4H, Rn_VPR64.4H
+is b_31=0 & b_30=0 & b_1029=0b00111001111001110110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_scvtf(Rn_VPR64.4H, 2:1);
+}
+
+# C7.2.234 SCVTF (vector, integer) page C7-2551 line 149206 MATCH x0e79d800/mask=xbffffc00
+# CONSTRUCT x4e79d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1@2
+# AUNIT --inst x4e79d800/mask=xfffffc00 --status noqemu --comment "nofpround"
+# Vector half precision variant when Q=1 suf=VPR128.8H
+
+:scvtf Rd_VPR128.8H, Rn_VPR128.8H
+is b_31=0 & b_30=1 & b_1029=0b00111001111001110110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_scvtf(Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.235 SCVTF (scalar, fixed-point) page C7-2554 line 149390 MATCH x1e020000/mask=x7f3f0000
+# CONSTRUCT x1ec28000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 int2float:2 FBits16 =f/
+# SMACRO(pseudo) ARG1 ARG2 FBits16 =NEON_scvtf/2
+# AUNIT --inst x1ec28000/mask=xffff8000 --status noqemu --comment "nofpround"
+# 32-bit to half-precision variant when sf == 0 && type == 11
+
+:scvtf Rd_FPR16, Rn_GPR32, FBitsOp
+is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=0 & mode=0 & fpOpcode=2 & b_15=1 & FBitsOp & FBits16 & Rn_GPR32 & Rd_FPR16 & Zd
+{
+ local tmp1:2 = int2float(Rn_GPR32);
+ Rd_FPR16 = tmp1 f/ FBits16;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.235 SCVTF (scalar, fixed-point) page C7-2554 line 149390 MATCH x1e020000/mask=x7f3f0000
+# CONSTRUCT x9ec20000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 int2float:2 FBits16 =f/
+# SMACRO(pseudo) ARG1 ARG2 FBits16 =NEON_scvtf/2
+# AUNIT --inst x9ec20000/mask=xffff0000 --status noqemu --comment "nofpround"
+# 64-bit to half-precision variant when sf == 1 && type == 11
+
+:scvtf Rd_FPR16, Rn_GPR64, FBitsOp
+is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=0 & mode=0 & fpOpcode=2 & FBitsOp & FBits16 & Rn_GPR64 & Rd_FPR16 & Zd
+{
+ local tmp1:2 = int2float(Rn_GPR64);
+ Rd_FPR16 = tmp1 f/ FBits16;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.235 SCVTF (scalar, fixed-point) page C7-2554 line 149390 MATCH x1e020000/mask=x7f3f0000
+# CONSTRUCT x1e428000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 int2float:8 FBits64 =f/
+# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_scvtf/2
+# AUNIT --inst x1e428000/mask=xffff8000 --status pass --comment "nofpround"
+
+:scvtf Rd_FPR64, Rn_GPR32, FBitsOp
+is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=0 & mode=0 & fpOpcode=2 & b_15=1 & FBitsOp & FBits64 & Rn_GPR32 & Rd_FPR64 & Zd
+{
+ local tmp1:8 = int2float(Rn_GPR32);
+ Rd_FPR64 = tmp1 f/ FBits64;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.235 SCVTF (scalar, fixed-point) page C7-2554 line 149390 MATCH x1e020000/mask=x7f3f0000
+# CONSTRUCT x1e028000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 int2float FBits32 =f/
+# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_scvtf/2
+# AUNIT --inst x1e028000/mask=xffff8000 --status fail --comment "nofpround"
+
+:scvtf Rd_FPR32, Rn_GPR32, FBitsOp
+is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=0 & mode=0 & fpOpcode=2 & b_15=1 & FBitsOp & FBits32 & Rn_GPR32 & Rd_FPR32 & Zd
+{
+ local tmp1:4 = int2float(Rn_GPR32);
+ Rd_FPR32 = tmp1 f/ FBits32;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.235 SCVTF (scalar, fixed-point) page C7-2554 line 149390 MATCH x1e020000/mask=x7f3f0000
+# CONSTRUCT x9e420000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 int2float FBits64 =f/
+# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_scvtf/2
+# AUNIT --inst x9e420000/mask=xffff0000 --status fail --comment "nofpround"
+
+:scvtf Rd_FPR64, Rn_GPR64, FBitsOp
+is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=0 & mode=0 & fpOpcode=2 & FBitsOp & FBits64 & Rn_GPR64 & Rd_FPR64 & Zd
+{
+ local tmp1:8 = int2float(Rn_GPR64);
+ Rd_FPR64 = tmp1 f/ FBits64;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.235 SCVTF (scalar, fixed-point) page C7-2554 line 149390 MATCH x1e020000/mask=x7f3f0000
+# CONSTRUCT x9e020000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 int2float:4 FBits32 =f/
+# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_scvtf/2
+# AUNIT --inst x9e020000/mask=xffff0000 --status fail --comment "nofpround"
+
+:scvtf Rd_FPR32, Rn_GPR64, FBitsOp
+is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=0 & mode=0 & fpOpcode=2 & FBitsOp & FBits32 & Rn_GPR64 & Rd_FPR32 & Rd_FPR64 & Zd
+{
+ local tmp1:4 = int2float(Rn_GPR64);
+ Rd_FPR32 = tmp1 f/ FBits32;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.236 SCVTF (scalar, integer) page C7-2556 line 149525 MATCH x1e220000/mask=x7f3ffc00
+# CONSTRUCT x1ee20000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =int2float/1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1
+# AUNIT --inst x1ee20000/mask=xfffffc00 --status noqemu --comment "nofpround"
+
+:scvtf Rd_FPR16, Rn_GPR32
+is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & rmode=0 & fpOpcode=2 & b_1015=0x0 & Rn_GPR32 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = int2float(Rn_GPR32);
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.236 SCVTF (scalar, integer) page C7-2556 line 149525 MATCH x1e220000/mask=x7f3ffc00
+# CONSTRUCT x9ee20000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =int2float/1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1
+# AUNIT --inst x9ee20000/mask=xfffffc00 --status noqemu --comment "nofpround"
+
+:scvtf Rd_FPR16, Rn_GPR64
+is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & rmode=0 & fpOpcode=2 & b_1015=0x0 & Rn_GPR64 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = int2float(Rn_GPR64);
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.236 SCVTF (scalar, integer) page C7-2556 line 149525 MATCH x1e220000/mask=x7f3ffc00
+# CONSTRUCT x1e620000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =int2float/1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1
+# AUNIT --inst x1e620000/mask=xfffffc00 --status pass --comment "nofpround"
+
+:scvtf Rd_FPR64, Rn_GPR32
+is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & rmode=0 & fpOpcode=2 & b_1015=0x0 & Rn_GPR32 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = int2float(Rn_GPR32);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.236 SCVTF (scalar, integer) page C7-2556 line 149525 MATCH x1e220000/mask=x7f3ffc00
+# CONSTRUCT x9e620000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =int2float/1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1
+# AUNIT --inst x9e620000/mask=xfffffc00 --status pass --comment "nofpround"
+
+:scvtf Rd_FPR64, Rn_GPR64
+is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & rmode=0 & fpOpcode=2 & b_1015=0x0 & Rn_GPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = int2float(Rn_GPR64);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.236 SCVTF (scalar, integer) page C7-2556 line 149525 MATCH x1e220000/mask=x7f3ffc00
+# CONSTRUCT x1e220000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =int2float/1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1
+# AUNIT --inst x1e220000/mask=xfffffc00 --status fail --comment "nofpround"
+
+:scvtf Rd_FPR32, Rn_GPR32
+is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & rmode=0 & fpOpcode=2 & b_1015=0x0 & Rn_GPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = int2float(Rn_GPR32);
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.236 SCVTF (scalar, integer) page C7-2556 line 149525 MATCH x1e220000/mask=x7f3ffc00
+# CONSTRUCT x9e220000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =int2float/1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_scvtf/1
+# AUNIT --inst x9e220000/mask=xfffffc00 --status fail --comment "nofpround"
+
+:scvtf Rd_FPR32, Rn_GPR64
+is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & rmode=0 & fpOpcode=2 & b_1015=0x0 & Rn_GPR64 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = int2float(Rn_GPR64);
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.237 SDOT (by element) page C7-2558 line 149653 MATCH x0f00e000/mask=xbf00f400
+# CONSTRUCT x0f80e000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 Re_VPR128.S.vIndex =NEON_sdot/2@1
+# AUNIT --inst x0f80e000/mask=xffc0f400 --status noqemu
+# Vector variant when Q=0 Ta=64.2S Tb=64.8B
+
+:sdot Rd_VPR64.2S, Rn_VPR64.8B, Re_VPR128.B.vIndex
+is b_31=0 & b_30=0 & b_2429=0b001111 & b_2223=0b10 & b_1215=0b1110 & b_10=0 & Rd_VPR64.2S & Rn_VPR64.8B & Re_VPR128.B.vIndex & Re_VPR128.S & vIndex & Zd
+{
+ local tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1);
+ Rd_VPR64.2S = NEON_sdot(Rn_VPR64.8B, tmp1, 1:1);
+}
+
+# C7.2.237 SDOT (by element) page C7-2558 line 149653 MATCH x0f00e000/mask=xbf00f400
+# CONSTRUCT x4f80e000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 Re_VPR128.S.vIndex =NEON_sdot/2@1
+# AUNIT --inst x4f80e000/mask=xffc0f400 --status noqemu
+# Vector variant when Q=1 Ta=128.4S Tb=128.16B
+
+:sdot Rd_VPR128.4S, Rn_VPR128.16B, Re_VPR128.B.vIndex
+is b_31=0 & b_30=1 & b_2429=0b001111 & b_2223=0b10 & b_1215=0b1110 & b_10=0 & Rd_VPR128.4S & Rn_VPR128.16B & Re_VPR128.B.vIndex & Re_VPR128.S & vIndex & Zd
+{
+ local tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1);
+ Rd_VPR128.4S = NEON_sdot(Rn_VPR128.16B, tmp1, 1:1);
+}
+
+# C7.2.238 SDOT (vector) page C7-2560 line 149755 MATCH x0e009400/mask=xbf20fc00
+# CONSTRUCT x0e809400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sdot/2@1
+# AUNIT --inst x0e809400/mask=xffe0fc00 --status noqemu
+# Three registers of the same type variant when Q=0 Ta=64.2S Tb=64.8B
+
+:sdot Rd_VPR64.2S, Rn_VPR64.8B, Rm_VPR64.8B
+is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_21=0 & b_1015=0b100101 & Rd_VPR64.2S & Rn_VPR64.8B & Rm_VPR64.8B & Zd
+{
+ Rd_VPR64.2S = NEON_sdot(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.238 SDOT (vector) page C7-2560 line 149755 MATCH x0e009400/mask=xbf20fc00
+# CONSTRUCT x4e809400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sdot/2@1
+# AUNIT --inst x4e809400/mask=xffe0fc00 --status noqemu
+# Three registers of the same type variant when Q=1 Ta=128.4S Tb=128.16B
+
+:sdot Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B
+is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_21=0 & b_1015=0b100101 & Rd_VPR128.4S & Rn_VPR128.16B & Rm_VPR128.16B & Zd
+{
+ Rd_VPR128.4S = NEON_sdot(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.239 SHA1C page C7-2562 line 149854 MATCH x5e000000/mask=xffe0fc00
+# CONSTRUCT x5e000000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha1c/3@4
+# AUNIT --inst x5e000000/mask=xffe0fc00 --status noqemu
+
+:sha1c Rd_VPR128, Rn_FPR32, Rm_VPR128.4S
+is b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b000000 & Rn_FPR32 & Rd_VPR128 & Zd
+{
+ Rd_VPR128 = NEON_sha1c(Rd_VPR128, Rn_FPR32, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.240 SHA1H page C7-2563 line 149925 MATCH x5e280800/mask=xfffffc00
+# CONSTRUCT x5e280800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 30:1 =<<
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sha1h/1
+# AUNIT --inst x5e280800/mask=xfffffc00 --status noqemu
+
+:sha1h Rd_FPR32, Rn_FPR32
+is b_2431=0b01011110 & b_2223=0b00 & b_1721=0b10100 & b_1216=0b00000 & b_1011=0b10 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = Rn_FPR32 << 30:1;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.241 SHA1M page C7-2564 line 149984 MATCH x5e002000/mask=xffe0fc00
+# CONSTRUCT x5e002000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha1m/3@4
+# AUNIT --inst x5e002000/mask=xffe0fc00 --status noqemu
+
+:sha1m Rd_VPR128, Rn_FPR32, Rm_VPR128.4S
+is b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b001000 & Rn_FPR32 & Rd_VPR128 & Zd
+{
+ Rd_VPR128 = NEON_sha1m(Rd_VPR128, Rn_FPR32, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.242 SHA1P page C7-2565 line 150055 MATCH x5e001000/mask=xffe0fc00
+# CONSTRUCT x5e001000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha1p/3@4
+# AUNIT --inst x5e001000/mask=xffe0fc00 --status noqemu
+
+:sha1p Rd_VPR128, Rn_FPR32, Rm_VPR128.4S
+is b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b000100 & Rn_FPR32 & Rd_VPR128 & Zd
+{
+ Rd_VPR128 = NEON_sha1p(Rd_VPR128, Rn_FPR32, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.243 SHA1SU0 page C7-2566 line 150126 MATCH x5e003000/mask=xffe0fc00
+# CONSTRUCT x5e003000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha1su0/3@4
+# AUNIT --inst x5e003000/mask=xffe0fc00 --status noqemu
+
+:sha1su0 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b001100 & Rn_VPR128.4S & Rd_VPR128.4S & Rd_VPR128 & Zd
+{
+ Rd_VPR128.4S = NEON_sha1su0(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.244 SHA1SU1 page C7-2567 line 150194 MATCH x5e281800/mask=xfffffc00
+# CONSTRUCT x5e281800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sha1su1/2@4
+# AUNIT --inst x5e281800/mask=xfffffc00 --status noqemu
+
+:sha1su1 Rd_VPR128.4S, Rn_VPR128.4S
+is b_2431=0b01011110 & b_2223=0b00 & b_2121=1 & b_1620=0b01000 & b_1015=0b000110 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sha1su1(Rd_VPR128.4S, Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.245 SHA256H2 page C7-2568 line 150260 MATCH x5e005000/mask=xffe0fc00
+# CONSTRUCT x5e005000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha256h2/3@4
+# AUNIT --inst x5e005000/mask=xffe0fc00 --status noqemu
+
+:sha256h2 Rd_VPR128, Rn_VPR128, Rm_VPR128.4S
+is b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b010100 & Rn_VPR128 & Rd_VPR128 & Zd
+{
+ Rd_VPR128 = NEON_sha256h2(Rd_VPR128, Rn_VPR128, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.246 SHA256H page C7-2569 line 150322 MATCH x5e004000/mask=xffe0fc00
+# CONSTRUCT x5e004000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha256h/3@4
+# AUNIT --inst x5e004000/mask=xffe0fc00 --status noqemu
+
+:sha256h Rd_VPR128, Rn_VPR128, Rm_VPR128.4S
+is b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b010000 & Rn_VPR128 & Rd_VPR128 & Zd
+{
+ Rd_VPR128 = NEON_sha256h(Rd_VPR128, Rn_VPR128, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.247 SHA256SU0 page C7-2570 line 150384 MATCH x5e282800/mask=xfffffc00
+# CONSTRUCT x5e282800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sha256su0/2@4
+# AUNIT --inst x5e282800/mask=xfffffc00 --status noqemu
+
+:sha256su0 Rd_VPR128.4S, Rn_VPR128.4S
+is b_2431=0b01011110 & b_2223=0b00 & b_2121=1 & b_1620=0b01000 & b_1015=0b001010 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sha256su0(Rd_VPR128.4S, Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.248 SHA256SU1 page C7-2571 line 150452 MATCH x5e006000/mask=xffe0fc00
+# CONSTRUCT x5e006000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha256su1/3@4
+# AUNIT --inst x5e006000/mask=xffe0fc00 --status noqemu
+
+:sha256su1 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_2431=0b01011110 & b_2223=0b00 & b_2121=0 & Rm_VPR128.4S & b_1015=0b011000 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sha256su1(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.249 SHA512H page C7-2573 line 150543 MATCH xce608000/mask=xffe0fc00
+# CONSTRUCT xce608000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha512h/3@8
+# AUNIT --inst xce608000/mask=xffe0fc00 --status noqemu
+
+:sha512h Rd_VPR128, Rn_VPR128, Rm_VPR128.2D
+is b_2131=0b11001110011 & b_1015=0b100000 & Rd_VPR128 & Rn_VPR128 & Rm_VPR128.2D & Zd
+{
+ Rd_VPR128 = NEON_sha512h(Rd_VPR128, Rn_VPR128, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.250 SHA512H2 page C7-2575 line 150631 MATCH xce608400/mask=xffe0fc00
+# CONSTRUCT xce608400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha512h2/3@8
+# AUNIT --inst xce608400/mask=xffe0fc00 --status noqemu
+
+:sha512h2 Rd_VPR128, Rn_VPR128, Rm_VPR128.2D
+is b_2131=0b11001110011 & b_1015=0b100001 & Rd_VPR128 & Rn_VPR128 & Rm_VPR128.2D & Zd
+{
+ Rd_VPR128 = NEON_sha512h2(Rd_VPR128, Rn_VPR128, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.251 SHA512SU0 page C7-2577 line 150719 MATCH xcec08000/mask=xfffffc00
+# CONSTRUCT xcec08000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sha512su0/2@8
+# AUNIT --inst xcec08000/mask=xfffffc00 --status noqemu
+
+:sha512su0 Rd_VPR128.2D, Rn_VPR128.2D
+is b_1031=0b1100111011000000100000 & Rd_VPR128.2D & Rn_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_sha512su0(Rd_VPR128.2D, Rn_VPR128.2D, 8:1);
+}
+
+# C7.2.252 SHA512SU1 page C7-2578 line 150789 MATCH xce608800/mask=xffe0fc00
+# CONSTRUCT xce608800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sha512su1/3@8
+# AUNIT --inst xce608800/mask=xffe0fc00 --status noqemu
+
+:sha512su1 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_2131=0b11001110011 & b_1015=0b100010 & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_sha512su1(Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.253 SHADD page C7-2580 line 150875 MATCH x0e200400/mask=xbf20fc00
+# CONSTRUCT x4e200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shadd/2@1
+# AUNIT --inst x4e200400/mask=xffe0fc00 --status nopcodeop
+
+:shadd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x0 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_shadd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.253 SHADD page C7-2580 line 150875 MATCH x0e200400/mask=xbf20fc00
+# CONSTRUCT x0ea00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shadd/2@4
+# AUNIT --inst x0ea00400/mask=xffe0fc00 --status nopcodeop
+
+:shadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x0 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_shadd(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.253 SHADD page C7-2580 line 150875 MATCH x0e200400/mask=xbf20fc00
+# CONSTRUCT x0e600400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shadd/2@2
+# AUNIT --inst x0e600400/mask=xffe0fc00 --status nopcodeop
+
+:shadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x0 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_shadd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.253 SHADD page C7-2580 line 150875 MATCH x0e200400/mask=xbf20fc00
+# CONSTRUCT x4ea00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shadd/2@4
+# AUNIT --inst x4ea00400/mask=xffe0fc00 --status nopcodeop
+
+:shadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x0 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_shadd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.253 SHADD page C7-2580 line 150875 MATCH x0e200400/mask=xbf20fc00
+# CONSTRUCT x0e200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shadd/2@1
+# AUNIT --inst x0e200400/mask=xffe0fc00 --status nopcodeop
+
+:shadd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x0 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_shadd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.253 SHADD page C7-2580 line 150875 MATCH x0e200400/mask=xbf20fc00
+# CONSTRUCT x4e600400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shadd/2@2
+# AUNIT --inst x4e600400/mask=xffe0fc00 --status nopcodeop
+
+:shadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x0 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_shadd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.254 SHL page C7-2582 line 150977 MATCH x5f005400/mask=xff80fc00
+# CONSTRUCT x5f405400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2
+# AUNIT --inst x5f405400/mask=xffc0fc00 --status nopcodeop
+
+:shl Rd_FPR64, Rn_FPR64, Imm_imm0_63
+is b_3031=1 & u=0 & b_2428=0x1f & b_2223=0b01 & Imm_imm0_63 & b_1115=0xa & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_shl(Rn_FPR64, Imm_imm0_63:1);
+}
+
+# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00
+# CONSTRUCT x4f085400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =var:1 =$<<@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@1
+# AUNIT --inst x4f085400/mask=xfff8fc00 --status pass
+
+:shl Rd_VPR128.16B, Rn_VPR128.16B, Imm_uimm3
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xa & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ local tmp1:1 = Imm_uimm3;
+ # simd infix Rd_VPR128.16B = Rn_VPR128.16B << tmp1 on lane size 1
+ Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] << tmp1;
+ Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] << tmp1;
+ Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] << tmp1;
+ Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] << tmp1;
+ Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] << tmp1;
+ Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] << tmp1;
+ Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] << tmp1;
+ Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] << tmp1;
+ Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] << tmp1;
+ Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] << tmp1;
+ Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] << tmp1;
+ Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] << tmp1;
+ Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] << tmp1;
+ Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] << tmp1;
+ Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] << tmp1;
+ Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] << tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00
+# CONSTRUCT x4f405400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =var:8 =$<<@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@8
+# AUNIT --inst x4f405400/mask=xffc0fc00 --status pass
+
+:shl Rd_VPR128.2D, Rn_VPR128.2D, Imm_imm0_63
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_imm0_63 & b_1115=0xa & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ local tmp1:8 = Imm_imm0_63;
+ # simd infix Rd_VPR128.2D = Rn_VPR128.2D << tmp1 on lane size 8
+ Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] << tmp1;
+ Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] << tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00
+# CONSTRUCT x0f205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =var:4 =$<<@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@4
+# AUNIT --inst x0f205400/mask=xffe0fc00 --status pass
+
+:shl Rd_VPR64.2S, Rn_VPR64.2S, Imm_uimm5
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xa & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ local tmp1:4 = Imm_uimm5;
+ # simd infix Rd_VPR64.2S = Rn_VPR64.2S << tmp1 on lane size 4
+ Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] << tmp1;
+ Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] << tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00
+# CONSTRUCT x0f105400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =var:2 =$<<@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@2
+# AUNIT --inst x0f105400/mask=xfff0fc00 --status pass
+
+:shl Rd_VPR64.4H, Rn_VPR64.4H, Imm_uimm4
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xa & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ local tmp1:2 = Imm_uimm4;
+ # simd infix Rd_VPR64.4H = Rn_VPR64.4H << tmp1 on lane size 2
+ Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] << tmp1;
+ Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] << tmp1;
+ Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] << tmp1;
+ Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] << tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00
+# CONSTRUCT x4f205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =var:4 =$<<@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@4
+# AUNIT --inst x4f205400/mask=xffe0fc00 --status pass
+
+:shl Rd_VPR128.4S, Rn_VPR128.4S, Imm_uimm5
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xa & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ local tmp1:4 = Imm_uimm5;
+ # simd infix Rd_VPR128.4S = Rn_VPR128.4S << tmp1 on lane size 4
+ Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] << tmp1;
+ Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] << tmp1;
+ Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] << tmp1;
+ Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] << tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00
+# CONSTRUCT x0f085400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =var:1 =$<<@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@1
+# AUNIT --inst x0f085400/mask=xfff8fc00 --status pass
+
+:shl Rd_VPR64.8B, Rn_VPR64.8B, Imm_uimm3
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xa & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ local tmp1:1 = Imm_uimm3;
+ # simd infix Rd_VPR64.8B = Rn_VPR64.8B << tmp1 on lane size 1
+ Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] << tmp1;
+ Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] << tmp1;
+ Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] << tmp1;
+ Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] << tmp1;
+ Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] << tmp1;
+ Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] << tmp1;
+ Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] << tmp1;
+ Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] << tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.254 SHL page C7-2582 line 150977 MATCH x0f005400/mask=xbf80fc00
+# CONSTRUCT x4f105400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =var:2 =$<<@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_shl/2@2
+# AUNIT --inst x4f105400/mask=xfff0fc00 --status pass
+
+:shl Rd_VPR128.8H, Rn_VPR128.8H, Imm_uimm4
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xa & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ local tmp1:2 = Imm_uimm4;
+ # simd infix Rd_VPR128.8H = Rn_VPR128.8H << tmp1 on lane size 2
+ Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] << tmp1;
+ Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] << tmp1;
+ Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] << tmp1;
+ Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] << tmp1;
+ Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] << tmp1;
+ Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] << tmp1;
+ Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] << tmp1;
+ Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] << tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.255 SHLL, SHLL2 page C7-2585 line 151125 MATCH x2e213800/mask=xbf3ffc00
+# CONSTRUCT x2ea13800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@4:16 ARG3 zext:8 =$<<@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shll/2@4
+# AUNIT --inst x2ea13800/mask=xfffffc00 --status pass --comment "ext"
+
+:shll Rd_VPR128.2D, Rn_VPR64.2S, Imm_uimm_exact32
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & Imm_uimm_exact32 & b_1721=0x10 & b_1216=0x13 & b_1011=2 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
+ local tmp2:8 = zext(Imm_uimm_exact32);
+ # simd infix Rd_VPR128.2D = TMPQ1 << tmp2 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ1[0,64] << tmp2;
+ Rd_VPR128.2D[64,64] = TMPQ1[64,64] << tmp2;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.255 SHLL, SHLL2 page C7-2585 line 151125 MATCH x2e213800/mask=xbf3ffc00
+# CONSTRUCT x2e613800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@2:16 ARG3:4 =$<<@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shll/2@2
+# AUNIT --inst x2e613800/mask=xfffffc00 --status pass --comment "ext"
+
+:shll Rd_VPR128.4S, Rn_VPR64.4H, Imm_uimm_exact16
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & Imm_uimm_exact16 & b_1721=0x10 & b_1216=0x13 & b_1011=2 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
+ # simd infix Rd_VPR128.4S = TMPQ1 << Imm_uimm_exact16:4 on lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ1[0,32] << Imm_uimm_exact16:4;
+ Rd_VPR128.4S[32,32] = TMPQ1[32,32] << Imm_uimm_exact16:4;
+ Rd_VPR128.4S[64,32] = TMPQ1[64,32] << Imm_uimm_exact16:4;
+ Rd_VPR128.4S[96,32] = TMPQ1[96,32] << Imm_uimm_exact16:4;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.255 SHLL, SHLL2 page C7-2585 line 151125 MATCH x2e213800/mask=xbf3ffc00
+# CONSTRUCT x2e213800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@1:16 ARG3:2 =$<<@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shll/2@1
+# AUNIT --inst x2e213800/mask=xfffffc00 --status pass --comment "ext"
+
+:shll Rd_VPR128.8H, Rn_VPR64.8B, Imm_uimm_exact8
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & Imm_uimm_exact8 & b_1721=0x10 & b_1216=0x13 & b_1011=2 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)
+ TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);
+ TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);
+ TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);
+ TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);
+ TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);
+ TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);
+ TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);
+ TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);
+ # simd infix Rd_VPR128.8H = TMPQ1 << Imm_uimm_exact8:2 on lane size 2
+ Rd_VPR128.8H[0,16] = TMPQ1[0,16] << Imm_uimm_exact8:2;
+ Rd_VPR128.8H[16,16] = TMPQ1[16,16] << Imm_uimm_exact8:2;
+ Rd_VPR128.8H[32,16] = TMPQ1[32,16] << Imm_uimm_exact8:2;
+ Rd_VPR128.8H[48,16] = TMPQ1[48,16] << Imm_uimm_exact8:2;
+ Rd_VPR128.8H[64,16] = TMPQ1[64,16] << Imm_uimm_exact8:2;
+ Rd_VPR128.8H[80,16] = TMPQ1[80,16] << Imm_uimm_exact8:2;
+ Rd_VPR128.8H[96,16] = TMPQ1[96,16] << Imm_uimm_exact8:2;
+ Rd_VPR128.8H[112,16] = TMPQ1[112,16] << Imm_uimm_exact8:2;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.255 SHLL, SHLL2 page C7-2585 line 151125 MATCH x2e213800/mask=xbf3ffc00
+# CONSTRUCT x6ea13800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 zext:8 =$<<@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shll2/2@4
+# AUNIT --inst x6ea13800/mask=xfffffc00 --status pass --comment "ext"
+
+:shll2 Rd_VPR128.2D, Rn_VPR128.4S, Imm_uimm_exact32
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & Imm_uimm_exact32 & b_1721=0x10 & b_1216=0x13 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(TMPD1[0,32]);
+ TMPQ2[64,64] = sext(TMPD1[32,32]);
+ local tmp3:8 = zext(Imm_uimm_exact32);
+ # simd infix Rd_VPR128.2D = TMPQ2 << tmp3 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ2[0,64] << tmp3;
+ Rd_VPR128.2D[64,64] = TMPQ2[64,64] << tmp3;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.255 SHLL, SHLL2 page C7-2585 line 151125 MATCH x2e213800/mask=xbf3ffc00
+# CONSTRUCT x6e613800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3:4 =$<<@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shll2/2@2
+# AUNIT --inst x6e613800/mask=xfffffc00 --status pass --comment "ext"
+
+:shll2 Rd_VPR128.4S, Rn_VPR128.8H, Imm_uimm_exact16
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & Imm_uimm_exact16 & b_1721=0x10 & b_1216=0x13 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(TMPD1[0,16]);
+ TMPQ2[32,32] = sext(TMPD1[16,16]);
+ TMPQ2[64,32] = sext(TMPD1[32,16]);
+ TMPQ2[96,32] = sext(TMPD1[48,16]);
+ # simd infix Rd_VPR128.4S = TMPQ2 << Imm_uimm_exact16:4 on lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ2[0,32] << Imm_uimm_exact16:4;
+ Rd_VPR128.4S[32,32] = TMPQ2[32,32] << Imm_uimm_exact16:4;
+ Rd_VPR128.4S[64,32] = TMPQ2[64,32] << Imm_uimm_exact16:4;
+ Rd_VPR128.4S[96,32] = TMPQ2[96,32] << Imm_uimm_exact16:4;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.255 SHLL, SHLL2 page C7-2585 line 151125 MATCH x2e213800/mask=xbf3ffc00
+# CONSTRUCT x6e213800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3:2 =$<<@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shll2/2@1
+# AUNIT --inst x6e213800/mask=xfffffc00 --status pass --comment "ext"
+
+:shll2 Rd_VPR128.8H, Rn_VPR128.16B, Imm_uimm_exact8
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & Imm_uimm_exact8 & b_1721=0x10 & b_1216=0x13 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
+{
+ TMPD1 = Rn_VPR128.16B[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)
+ TMPQ2[0,16] = sext(TMPD1[0,8]);
+ TMPQ2[16,16] = sext(TMPD1[8,8]);
+ TMPQ2[32,16] = sext(TMPD1[16,8]);
+ TMPQ2[48,16] = sext(TMPD1[24,8]);
+ TMPQ2[64,16] = sext(TMPD1[32,8]);
+ TMPQ2[80,16] = sext(TMPD1[40,8]);
+ TMPQ2[96,16] = sext(TMPD1[48,8]);
+ TMPQ2[112,16] = sext(TMPD1[56,8]);
+ # simd infix Rd_VPR128.8H = TMPQ2 << Imm_uimm_exact8:2 on lane size 2
+ Rd_VPR128.8H[0,16] = TMPQ2[0,16] << Imm_uimm_exact8:2;
+ Rd_VPR128.8H[16,16] = TMPQ2[16,16] << Imm_uimm_exact8:2;
+ Rd_VPR128.8H[32,16] = TMPQ2[32,16] << Imm_uimm_exact8:2;
+ Rd_VPR128.8H[48,16] = TMPQ2[48,16] << Imm_uimm_exact8:2;
+ Rd_VPR128.8H[64,16] = TMPQ2[64,16] << Imm_uimm_exact8:2;
+ Rd_VPR128.8H[80,16] = TMPQ2[80,16] << Imm_uimm_exact8:2;
+ Rd_VPR128.8H[96,16] = TMPQ2[96,16] << Imm_uimm_exact8:2;
+ Rd_VPR128.8H[112,16] = TMPQ2[112,16] << Imm_uimm_exact8:2;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.256 SHRN, SHRN2 page C7-2587 line 151244 MATCH x0f008400/mask=xbf80fc00
+# CONSTRUCT x0f208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 zext:8 $>>@8 =$zext@8:8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shrn/2@8
+# AUNIT --inst x0f208400/mask=xffe0fc00 --status pass --comment "ext"
+
+:shrn Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x10 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
+{
+ local tmp1:8 = zext(Imm_shr_imm32);
+ # simd infix TMPQ1 = Rn_VPR128.2D >> tmp1 on lane size 8
+ TMPQ1[0,64] = Rn_VPR128.2D[0,64] >> tmp1;
+ TMPQ1[64,64] = Rn_VPR128.2D[64,64] >> tmp1;
+ # simd resize Rd_VPR64.2S = zext(TMPQ1) (lane size 8 to 4)
+ Rd_VPR64.2S[0,32] = TMPQ1[0,32];
+ Rd_VPR64.2S[32,32] = TMPQ1[64,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.256 SHRN, SHRN2 page C7-2587 line 151244 MATCH x0f008400/mask=xbf80fc00
+# CONSTRUCT x0f108400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:4 $>>@4 =$zext@4:16
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shrn/2@4
+# AUNIT --inst x0f108400/mask=xfff0fc00 --status pass --comment "ext"
+
+:shrn Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x10 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.4S >> Imm_shr_imm16:4 on lane size 4
+ TMPQ1[0,32] = Rn_VPR128.4S[0,32] >> Imm_shr_imm16:4;
+ TMPQ1[32,32] = Rn_VPR128.4S[32,32] >> Imm_shr_imm16:4;
+ TMPQ1[64,32] = Rn_VPR128.4S[64,32] >> Imm_shr_imm16:4;
+ TMPQ1[96,32] = Rn_VPR128.4S[96,32] >> Imm_shr_imm16:4;
+ # simd resize Rd_VPR64.4H = zext(TMPQ1) (lane size 4 to 2)
+ Rd_VPR64.4H[0,16] = TMPQ1[0,16];
+ Rd_VPR64.4H[16,16] = TMPQ1[32,16];
+ Rd_VPR64.4H[32,16] = TMPQ1[64,16];
+ Rd_VPR64.4H[48,16] = TMPQ1[96,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.256 SHRN, SHRN2 page C7-2587 line 151244 MATCH x0f008400/mask=xbf80fc00
+# CONSTRUCT x0f088400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:2 $>>@2 =$zext@2:8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shrn/2@2
+# AUNIT --inst x0f088400/mask=xfff8fc00 --status pass --comment "ext"
+
+:shrn Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x10 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.8H >> Imm_shr_imm8:2 on lane size 2
+ TMPQ1[0,16] = Rn_VPR128.8H[0,16] >> Imm_shr_imm8:2;
+ TMPQ1[16,16] = Rn_VPR128.8H[16,16] >> Imm_shr_imm8:2;
+ TMPQ1[32,16] = Rn_VPR128.8H[32,16] >> Imm_shr_imm8:2;
+ TMPQ1[48,16] = Rn_VPR128.8H[48,16] >> Imm_shr_imm8:2;
+ TMPQ1[64,16] = Rn_VPR128.8H[64,16] >> Imm_shr_imm8:2;
+ TMPQ1[80,16] = Rn_VPR128.8H[80,16] >> Imm_shr_imm8:2;
+ TMPQ1[96,16] = Rn_VPR128.8H[96,16] >> Imm_shr_imm8:2;
+ TMPQ1[112,16] = Rn_VPR128.8H[112,16] >> Imm_shr_imm8:2;
+ # simd resize Rd_VPR64.8B = zext(TMPQ1) (lane size 2 to 1)
+ Rd_VPR64.8B[0,8] = TMPQ1[0,8];
+ Rd_VPR64.8B[8,8] = TMPQ1[16,8];
+ Rd_VPR64.8B[16,8] = TMPQ1[32,8];
+ Rd_VPR64.8B[24,8] = TMPQ1[48,8];
+ Rd_VPR64.8B[32,8] = TMPQ1[64,8];
+ Rd_VPR64.8B[40,8] = TMPQ1[80,8];
+ Rd_VPR64.8B[48,8] = TMPQ1[96,8];
+ Rd_VPR64.8B[56,8] = TMPQ1[112,8];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.256 SHRN, SHRN2 page C7-2587 line 151244 MATCH x0f008400/mask=xbf80fc00
+# CONSTRUCT x4f208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 zext:8 $>>@8 $zext@8:8 1:1 &=$copy
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shrn2/2@8
+# AUNIT --inst x4f208400/mask=xffe0fc00 --status pass --comment "ext"
+
+:shrn2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x10 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
+{
+ local tmp1:8 = zext(Imm_shr_imm32);
+ # simd infix TMPQ1 = Rn_VPR128.2D >> tmp1 on lane size 8
+ TMPQ1[0,64] = Rn_VPR128.2D[0,64] >> tmp1;
+ TMPQ1[64,64] = Rn_VPR128.2D[64,64] >> tmp1;
+ # simd resize TMPD2 = zext(TMPQ1) (lane size 8 to 4)
+ TMPD2[0,32] = TMPQ1[0,32];
+ TMPD2[32,32] = TMPQ1[64,32];
+ # simd copy Rd_VPR128.4S element 1:1 = TMPD2 (lane size 8)
+ Rd_VPR128.4S[64,64] = TMPD2;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.256 SHRN, SHRN2 page C7-2587 line 151244 MATCH x0f008400/mask=xbf80fc00
+# CONSTRUCT x4f108400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:4 $>>@4 $zext@4:8 1:1 &=$copy
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shrn2/2@4
+# AUNIT --inst x4f108400/mask=xfff0fc00 --status pass --comment "ext"
+
+:shrn2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x10 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.4S >> Imm_shr_imm16:4 on lane size 4
+ TMPQ1[0,32] = Rn_VPR128.4S[0,32] >> Imm_shr_imm16:4;
+ TMPQ1[32,32] = Rn_VPR128.4S[32,32] >> Imm_shr_imm16:4;
+ TMPQ1[64,32] = Rn_VPR128.4S[64,32] >> Imm_shr_imm16:4;
+ TMPQ1[96,32] = Rn_VPR128.4S[96,32] >> Imm_shr_imm16:4;
+ # simd resize TMPD2 = zext(TMPQ1) (lane size 4 to 2)
+ TMPD2[0,16] = TMPQ1[0,16];
+ TMPD2[16,16] = TMPQ1[32,16];
+ TMPD2[32,16] = TMPQ1[64,16];
+ TMPD2[48,16] = TMPQ1[96,16];
+ # simd copy Rd_VPR128.8H element 1:1 = TMPD2 (lane size 8)
+ Rd_VPR128.8H[64,64] = TMPD2;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.256 SHRN, SHRN2 page C7-2587 line 151244 MATCH x0f008400/mask=xbf80fc00
+# CONSTRUCT x4f088400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:2 $>>@2 $zext@2:8 1:1 &=$copy
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shrn2/2@2
+# AUNIT --inst x4f088400/mask=xfff8fc00 --status pass --comment "ext"
+
+:shrn2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x10 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.8H >> Imm_shr_imm8:2 on lane size 2
+ TMPQ1[0,16] = Rn_VPR128.8H[0,16] >> Imm_shr_imm8:2;
+ TMPQ1[16,16] = Rn_VPR128.8H[16,16] >> Imm_shr_imm8:2;
+ TMPQ1[32,16] = Rn_VPR128.8H[32,16] >> Imm_shr_imm8:2;
+ TMPQ1[48,16] = Rn_VPR128.8H[48,16] >> Imm_shr_imm8:2;
+ TMPQ1[64,16] = Rn_VPR128.8H[64,16] >> Imm_shr_imm8:2;
+ TMPQ1[80,16] = Rn_VPR128.8H[80,16] >> Imm_shr_imm8:2;
+ TMPQ1[96,16] = Rn_VPR128.8H[96,16] >> Imm_shr_imm8:2;
+ TMPQ1[112,16] = Rn_VPR128.8H[112,16] >> Imm_shr_imm8:2;
+ # simd resize TMPD2 = zext(TMPQ1) (lane size 2 to 1)
+ TMPD2[0,8] = TMPQ1[0,8];
+ TMPD2[8,8] = TMPQ1[16,8];
+ TMPD2[16,8] = TMPQ1[32,8];
+ TMPD2[24,8] = TMPQ1[48,8];
+ TMPD2[32,8] = TMPQ1[64,8];
+ TMPD2[40,8] = TMPQ1[80,8];
+ TMPD2[48,8] = TMPQ1[96,8];
+ TMPD2[56,8] = TMPQ1[112,8];
+ # simd copy Rd_VPR128.16B element 1:1 = TMPD2 (lane size 8)
+ Rd_VPR128.16B[64,64] = TMPD2;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.257 SHSUB page C7-2589 line 151368 MATCH x0e202400/mask=xbf20fc00
+# CONSTRUCT x4e202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shsub/2@1
+# AUNIT --inst x4e202400/mask=xffe0fc00 --status nopcodeop
+
+:shsub Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x4 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_shsub(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.257 SHSUB page C7-2589 line 151368 MATCH x0e202400/mask=xbf20fc00
+# CONSTRUCT x0ea02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shsub/2@4
+# AUNIT --inst x0ea02400/mask=xffe0fc00 --status nopcodeop
+
+:shsub Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x4 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_shsub(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.257 SHSUB page C7-2589 line 151368 MATCH x0e202400/mask=xbf20fc00
+# CONSTRUCT x0e602400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shsub/2@2
+# AUNIT --inst x0e602400/mask=xffe0fc00 --status nopcodeop
+
+:shsub Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x4 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_shsub(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.257 SHSUB page C7-2589 line 151368 MATCH x0e202400/mask=xbf20fc00
+# CONSTRUCT x4ea02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shsub/2@4
+# AUNIT --inst x4ea02400/mask=xffe0fc00 --status nopcodeop
+
+:shsub Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x4 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_shsub(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.257 SHSUB page C7-2589 line 151368 MATCH x0e202400/mask=xbf20fc00
+# CONSTRUCT x0e202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shsub/2@1
+# AUNIT --inst x0e202400/mask=xffe0fc00 --status nopcodeop
+
+:shsub Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x4 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_shsub(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.257 SHSUB page C7-2589 line 151368 MATCH x0e202400/mask=xbf20fc00
+# CONSTRUCT x4e602400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_shsub/2@2
+# AUNIT --inst x4e602400/mask=xffe0fc00 --status nopcodeop
+
+:shsub Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x4 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_shsub(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00
+# CONSTRUCT x6f085400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@1
+# AUNIT --inst x6f085400/mask=xfff8fc00 --status nopcodeop
+
+:sli Rd_VPR128.16B, Rn_VPR128.16B, Imm_uimm3
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xa & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_sli(Rd_VPR128.16B, Rn_VPR128.16B, Imm_uimm3:1, 1:1);
+}
+
+# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00
+# CONSTRUCT x6f405400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@8
+# AUNIT --inst x6f405400/mask=xffc0fc00 --status nopcodeop
+
+:sli Rd_VPR128.2D, Rn_VPR128.2D, Imm_imm0_63
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_imm0_63 & b_1115=0xa & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_sli(Rd_VPR128.2D, Rn_VPR128.2D, Imm_imm0_63:1, 8:1);
+}
+
+# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00
+# CONSTRUCT x2f205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@4
+# AUNIT --inst x2f205400/mask=xffe0fc00 --status nopcodeop
+
+:sli Rd_VPR64.2S, Rn_VPR64.2S, Imm_uimm5
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xa & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_sli(Rd_VPR64.2S, Rn_VPR64.2S, Imm_uimm5:1, 4:1);
+}
+
+# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00
+# CONSTRUCT x2f105400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@2
+# AUNIT --inst x2f105400/mask=xfff0fc00 --status nopcodeop
+
+:sli Rd_VPR64.4H, Rn_VPR64.4H, Imm_uimm4
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xa & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_sli(Rd_VPR64.4H, Rn_VPR64.4H, Imm_uimm4:1, 2:1);
+}
+
+# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00
+# CONSTRUCT x6f205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@4
+# AUNIT --inst x6f205400/mask=xffe0fc00 --status nopcodeop
+
+:sli Rd_VPR128.4S, Rn_VPR128.4S, Imm_uimm5
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xa & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sli(Rd_VPR128.4S, Rn_VPR128.4S, Imm_uimm5:1, 4:1);
+}
+
+# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00
+# CONSTRUCT x2f085400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@1
+# AUNIT --inst x2f085400/mask=xfff8fc00 --status nopcodeop
+
+:sli Rd_VPR64.8B, Rn_VPR64.8B, Imm_uimm3
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xa & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_sli(Rd_VPR64.8B, Rn_VPR64.8B, Imm_uimm3:1, 1:1);
+}
+
+# C7.2.258 SLI page C7-2591 line 151468 MATCH x2f005400/mask=xbf80fc00
+# CONSTRUCT x6f105400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3@2
+# AUNIT --inst x6f105400/mask=xfff0fc00 --status nopcodeop
+
+:sli Rd_VPR128.8H, Rn_VPR128.8H, Imm_uimm4
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xa & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_sli(Rd_VPR128.8H, Rn_VPR128.8H, Imm_uimm4:1, 2:1);
+}
+
+# C7.2.258 SLI page C7-2591 line 151468 MATCH x7f005400/mask=xff80fc00
+# CONSTRUCT x7f405400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sli/3
+# AUNIT --inst x7f405400/mask=xffc0fc00 --status nopcodeop
+
+:sli Rd_VPR64, Rn_VPR64, Imm_uimm5
+is b_2331=0b011111110 & b_22=1 & b_1015=0b010101 & Rd_VPR64 & Rn_VPR64 & Imm_uimm5 & Zd
+{
+ Rd_VPR64 = NEON_sli(Rd_VPR64, Rn_VPR64, Imm_uimm5:1);
+}
+
+# C7.2.259 SM3PARTW1 page C7-2594 line 151635 MATCH xce60c000/mask=xffe0fc00
+# CONSTRUCT xce60c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm3partw1/3@4
+# AUNIT --inst xce60c000/mask=xffe0fc00 --status noqemu
+
+:sm3partw1 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_2131=0b11001110011 & b_1015=0b110000 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sm3partw1(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.260 SM3PARTW2 page C7-2596 line 151723 MATCH xce60c400/mask=xffe0fc00
+# CONSTRUCT xce60c400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm3partw2/3@4
+# AUNIT --inst xce60c400/mask=xffe0fc00 --status noqemu
+
+:sm3partw2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_2131=0b11001110011 & b_1015=0b110001 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sm3partw2(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.261 SM3SS1 page C7-2598 line 151808 MATCH xce400000/mask=xffe08000
+# CONSTRUCT xce400000/mask=xffe08000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_sm3ss1/3@4
+# AUNIT --inst xce400000/mask=xffe08000 --status noqemu
+
+:sm3ss1 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, Ra_VPR128.4S
+is b_2131=0b11001110010 & b_15=0 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Ra_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sm3ss1(Rn_VPR128.4S, Rm_VPR128.4S, Ra_VPR128.4S, 4:1);
+}
+
+# C7.2.247 SM3TT1A page C7-1529 line 88534 KEEPWITH
+
+sm3imm2: b_1213 is b_1213 { export *[const]:4 b_1213; }
+Re_VPR128.S.sm3imm2: Re_VPR128.S^"["^sm3imm2^"]" is Re_VPR128.S & sm3imm2 { export Re_VPR128.S; }
+
+# C7.2.262 SM3TT1A page C7-2600 line 151893 MATCH xce408000/mask=xffe0cc00
+# CONSTRUCT xce408000/mask=xffe0cc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm3tt1a/3@4
+# AUNIT --inst xce408000/mask=xffe0cc00 --status noqemu
+
+:sm3tt1a Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.sm3imm2
+is b_2131=0b11001110010 & b_1415=0b10 & b_1011=0b00 & Rd_VPR128.4S & Rn_VPR128.4S & Re_VPR128.S.sm3imm2 & Re_VPR128.S & sm3imm2 & Zd
+{
+ local tmp1:4 = SIMD_PIECE(Re_VPR128.S, sm3imm2:1);
+ Rd_VPR128.4S = NEON_sm3tt1a(Rd_VPR128.4S, Rn_VPR128.4S, tmp1, 4:1);
+}
+
+# C7.2.263 SM3TT1B page C7-2602 line 151999 MATCH xce408400/mask=xffe0cc00
+# CONSTRUCT xce408400/mask=xffe0cc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm3tt1b/3@4
+# AUNIT --inst xce408400/mask=xffe0cc00 --status noqemu
+
+:sm3tt1b Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.sm3imm2
+is b_2131=0b11001110010 & b_1415=0b10 & b_1011=0b01 & Rd_VPR128.4S & Rn_VPR128.4S & Re_VPR128.S.sm3imm2 & Re_VPR128.S & sm3imm2 & Zd
+{
+ local tmp1:4 = SIMD_PIECE(Re_VPR128.S, sm3imm2:1);
+ Rd_VPR128.4S = NEON_sm3tt1b(Rd_VPR128.4S, Rn_VPR128.4S, tmp1, 4:1);
+}
+
+# C7.2.264 SM3TT2A page C7-2604 line 152105 MATCH xce408800/mask=xffe0cc00
+# CONSTRUCT xce408800/mask=xffe0cc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm3tt2a/3@4
+# AUNIT --inst xce408800/mask=xffe0cc00 --status noqemu
+
+:sm3tt2a Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.sm3imm2
+is b_2131=0b11001110010 & b_1415=0b10 & b_1011=0b10 & Rd_VPR128.4S & Rn_VPR128.4S & Re_VPR128.S.sm3imm2 & Re_VPR128.S & sm3imm2 & Zd
+{
+ local tmp1:4 = SIMD_PIECE(Re_VPR128.S, sm3imm2:1);
+ Rd_VPR128.4S = NEON_sm3tt2a(Rd_VPR128.4S, Rn_VPR128.4S, tmp1, 4:1);
+}
+
+# C7.2.265 SM3TT2B page C7-2606 line 152210 MATCH xce408c00/mask=xffe0cc00
+# CONSTRUCT xce408c00/mask=xffe0cc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm3tt2b/3@4
+# AUNIT --inst xce408c00/mask=xffe0cc00 --status noqemu
+
+:sm3tt2b Rd_VPR128.S, Rn_VPR128.S, Re_VPR128.S.sm3imm2
+is b_2131=0b11001110010 & b_1415=0b10 & b_1011=0b11 & Rd_VPR128.S & Rn_VPR128.S & Re_VPR128.S.sm3imm2 & Re_VPR128.S & sm3imm2 & Zd
+{
+ local tmp1:4 = SIMD_PIECE(Re_VPR128.S, sm3imm2:1);
+ Rd_VPR128.S = NEON_sm3tt2b(Rd_VPR128.S, Rn_VPR128.S, tmp1, 4:1);
+}
+
+# C7.2.266 SM4E page C7-2608 line 152315 MATCH xcec08400/mask=xfffffc00
+# CONSTRUCT xcec08400/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sm4e/2@4
+# AUNIT --inst xcec08400/mask=xfffffc00 --status noqemu
+
+:sm4e Rd_VPR128.4S, Rn_VPR128.4S
+is b_1031=0b1100111011000000100001 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sm4e(Rd_VPR128.4S, Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.267 SM4EKEY page C7-2610 line 152409 MATCH xce60c800/mask=xffe0fc00
+# CONSTRUCT xce60c800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sm4ekey/3@4
+# AUNIT --inst xce60c800/mask=xffe0fc00 --status noqemu
+
+:sm4ekey Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_2131=0b11001110011 & b_1015=0b110010 & Rd_VPR128.4S & Rn_VPR128.4S & Rm_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sm4ekey(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.268 SMAX page C7-2612 line 152509 MATCH x0e206400/mask=xbf20fc00
+# CONSTRUCT x4e206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@1
+# AUNIT --inst x4e206400/mask=xffe0fc00 --status nopcodeop
+
+:smax Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xc & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_smax(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.268 SMAX page C7-2612 line 152509 MATCH x0e206400/mask=xbf20fc00
+# CONSTRUCT x0ea06400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@4
+# AUNIT --inst x0ea06400/mask=xffe0fc00 --status nopcodeop
+
+:smax Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xc & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_smax(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.268 SMAX page C7-2612 line 152509 MATCH x0e206400/mask=xbf20fc00
+# CONSTRUCT x0e606400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@2
+# AUNIT --inst x0e606400/mask=xffe0fc00 --status nopcodeop
+
+:smax Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xc & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_smax(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.268 SMAX page C7-2612 line 152509 MATCH x0e206400/mask=xbf20fc00
+# CONSTRUCT x4ea06400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@4
+# AUNIT --inst x4ea06400/mask=xffe0fc00 --status nopcodeop
+
+:smax Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xc & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_smax(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.268 SMAX page C7-2612 line 152509 MATCH x0e206400/mask=xbf20fc00
+# CONSTRUCT x0e206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@1
+# AUNIT --inst x0e206400/mask=xffe0fc00 --status nopcodeop
+
+:smax Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xc & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_smax(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.268 SMAX page C7-2612 line 152509 MATCH x0e206400/mask=xbf20fc00
+# CONSTRUCT x4e606400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@2
+# AUNIT --inst x4e606400/mask=xffe0fc00 --status nopcodeop
+
+:smax Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xc & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_smax(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.269 SMAXP page C7-2614 line 152611 MATCH x0e20a400/mask=xbf20fc00
+# CONSTRUCT x4e20a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smax/2@1
+# AUNIT --inst x4e20a400/mask=xffe0fc00 --status nopcodeop
+
+:smaxp Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x14 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_smax(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.269 SMAXP page C7-2614 line 152611 MATCH x0e20a400/mask=xbf20fc00
+# CONSTRUCT x0ea0a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smaxp/2@4
+# AUNIT --inst x0ea0a400/mask=xffe0fc00 --status nopcodeop
+
+:smaxp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x14 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_smaxp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.269 SMAXP page C7-2614 line 152611 MATCH x0e20a400/mask=xbf20fc00
+# CONSTRUCT x0e60a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smaxp/2@2
+# AUNIT --inst x0e60a400/mask=xffe0fc00 --status nopcodeop
+
+:smaxp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x14 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_smaxp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.269 SMAXP page C7-2614 line 152611 MATCH x0e20a400/mask=xbf20fc00
+# CONSTRUCT x4ea0a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smaxp/2@4
+# AUNIT --inst x4ea0a400/mask=xffe0fc00 --status nopcodeop
+
+:smaxp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x14 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_smaxp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.269 SMAXP page C7-2614 line 152611 MATCH x0e20a400/mask=xbf20fc00
+# CONSTRUCT x0e20a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smaxp/2@1
+# AUNIT --inst x0e20a400/mask=xffe0fc00 --status nopcodeop
+
+:smaxp Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x14 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_smaxp(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.269 SMAXP page C7-2614 line 152611 MATCH x0e20a400/mask=xbf20fc00
+# CONSTRUCT x4e60a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smaxp/2@2
+# AUNIT --inst x4e60a400/mask=xffe0fc00 --status nopcodeop
+
+:smaxp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x14 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_smaxp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.270 SMAXV page C7-2616 line 152715 MATCH x0e30a800/mask=xbf3ffc00
+# CONSTRUCT x4e30a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_smaxv/1@1
+# AUNIT --inst x4e30a800/mask=xfffffc00 --status nopcodeop
+
+:smaxv Rd_FPR8, Rn_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.16B & Rd_FPR8 & Zd
+{
+ Rd_FPR8 = NEON_smaxv(Rn_VPR128.16B, 1:1);
+}
+
+# C7.2.270 SMAXV page C7-2616 line 152715 MATCH x0e30a800/mask=xbf3ffc00
+# CONSTRUCT x0e30a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_smaxv/1@1
+# AUNIT --inst x0e30a800/mask=xfffffc00 --status nopcodeop
+
+:smaxv Rd_FPR8, Rn_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR64.8B & Rd_FPR8 & Zd
+{
+ Rd_FPR8 = NEON_smaxv(Rn_VPR64.8B, 1:1);
+}
+
+# C7.2.270 SMAXV page C7-2616 line 152715 MATCH x0e30a800/mask=xbf3ffc00
+# CONSTRUCT x0e70a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_smaxv/1@2
+# AUNIT --inst x0e70a800/mask=xfffffc00 --status nopcodeop
+
+:smaxv Rd_FPR16, Rn_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR64.4H & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_smaxv(Rn_VPR64.4H, 2:1);
+}
+
+# C7.2.270 SMAXV page C7-2616 line 152715 MATCH x0e30a800/mask=xbf3ffc00
+# CONSTRUCT x4e70a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_smaxv/1@2
+# AUNIT --inst x4e70a800/mask=xfffffc00 --status nopcodeop
+
+:smaxv Rd_FPR16, Rn_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.8H & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_smaxv(Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.270 SMAXV page C7-2616 line 152715 MATCH x0e30a800/mask=xbf3ffc00
+# CONSTRUCT x4eb0a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_smaxv/1@4
+# AUNIT --inst x4eb0a800/mask=xfffffc00 --status nopcodeop
+
+:smaxv Rd_FPR32, Rn_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_smaxv(Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.271 SMIN page C7-2618 line 152818 MATCH x0e206c00/mask=xbf20fc00
+# CONSTRUCT x4e206c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smin/2@1
+# AUNIT --inst x4e206c00/mask=xffe0fc00 --status nopcodeop
+
+:smin Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xd & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_smin(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.271 SMIN page C7-2618 line 152818 MATCH x0e206c00/mask=xbf20fc00
+# CONSTRUCT x0ea06c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smin/2@4
+# AUNIT --inst x0ea06c00/mask=xffe0fc00 --status nopcodeop
+
+:smin Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xd & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_smin(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.271 SMIN page C7-2618 line 152818 MATCH x0e206c00/mask=xbf20fc00
+# CONSTRUCT x0e606c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smin/2@2
+# AUNIT --inst x0e606c00/mask=xffe0fc00 --status nopcodeop
+
+:smin Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xd & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_smin(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.271 SMIN page C7-2618 line 152818 MATCH x0e206c00/mask=xbf20fc00
+# CONSTRUCT x4ea06c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smin/2@4
+# AUNIT --inst x4ea06c00/mask=xffe0fc00 --status nopcodeop
+
+:smin Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xd & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_smin(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.271 SMIN page C7-2618 line 152818 MATCH x0e206c00/mask=xbf20fc00
+# CONSTRUCT x0e206c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smin/2@1
+# AUNIT --inst x0e206c00/mask=xffe0fc00 --status nopcodeop
+
+:smin Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xd & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_smin(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.271 SMIN page C7-2618 line 152818 MATCH x0e206c00/mask=xbf20fc00
+# CONSTRUCT x4e606c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smin/2@2
+# AUNIT --inst x4e606c00/mask=xffe0fc00 --status nopcodeop
+
+:smin Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xd & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_smin(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.272 SMINP page C7-2620 line 152920 MATCH x0e20ac00/mask=xbf20fc00
+# CONSTRUCT x4e20ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sminp/2@1
+# AUNIT --inst x4e20ac00/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:sminp Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x15 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_sminp(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.272 SMINP page C7-2620 line 152920 MATCH x0e20ac00/mask=xbf20fc00
+# CONSTRUCT x0ea0ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sminp/2@4
+# AUNIT --inst x0ea0ac00/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:sminp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x15 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_sminp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.272 SMINP page C7-2620 line 152920 MATCH x0e20ac00/mask=xbf20fc00
+# CONSTRUCT x0e60ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sminp/2@2
+# AUNIT --inst x0e60ac00/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:sminp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x15 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_sminp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.272 SMINP page C7-2620 line 152920 MATCH x0e20ac00/mask=xbf20fc00
+# CONSTRUCT x4ea0ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sminp/2@4
+# AUNIT --inst x4ea0ac00/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:sminp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x15 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sminp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.272 SMINP page C7-2620 line 152920 MATCH x0e20ac00/mask=xbf20fc00
+# CONSTRUCT x0e20ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sminp/2@1
+# AUNIT --inst x0e20ac00/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:sminp Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x15 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_sminp(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.272 SMINP page C7-2620 line 152920 MATCH x0e20ac00/mask=xbf20fc00
+# CONSTRUCT x4e60ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sminp/2@2
+# AUNIT --inst x4e60ac00/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:sminp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x15 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_sminp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.273 SMINV page C7-2622 line 153024 MATCH x0e31a800/mask=xbf3ffc00
+# CONSTRUCT x4e31a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sminv/1@1
+# AUNIT --inst x4e31a800/mask=xfffffc00 --status nopcodeop
+
+:sminv Rd_FPR8, Rn_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.16B & Rd_FPR8 & Zd
+{
+ Rd_FPR8 = NEON_sminv(Rn_VPR128.16B, 1:1);
+}
+
+# C7.2.273 SMINV page C7-2622 line 153024 MATCH x0e31a800/mask=xbf3ffc00
+# CONSTRUCT x0e31a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sminv/1@1
+# AUNIT --inst x0e31a800/mask=xfffffc00 --status nopcodeop
+
+:sminv Rd_FPR8, Rn_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR64.8B & Rd_FPR8 & Zd
+{
+ Rd_FPR8 = NEON_sminv(Rn_VPR64.8B, 1:1);
+}
+
+# C7.2.273 SMINV page C7-2622 line 153024 MATCH x0e31a800/mask=xbf3ffc00
+# CONSTRUCT x0e71a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sminv/1@2
+# AUNIT --inst x0e71a800/mask=xfffffc00 --status nopcodeop
+
+:sminv Rd_FPR16, Rn_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR64.4H & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_sminv(Rn_VPR64.4H, 2:1);
+}
+
+# C7.2.273 SMINV page C7-2622 line 153024 MATCH x0e31a800/mask=xbf3ffc00
+# CONSTRUCT x4e71a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sminv/1@2
+# AUNIT --inst x4e71a800/mask=xfffffc00 --status nopcodeop
+
+:sminv Rd_FPR16, Rn_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.8H & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_sminv(Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.273 SMINV page C7-2622 line 153024 MATCH x0e31a800/mask=xbf3ffc00
+# CONSTRUCT x4eb1a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sminv/1@4
+# AUNIT --inst x4eb1a800/mask=xfffffc00 --status nopcodeop
+
+:sminv Rd_FPR32, Rn_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_sminv(Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.274 SMLAL, SMLAL2 (by element) page C7-2624 line 153127 MATCH x0f002000/mask=xbf00f400
+# CONSTRUCT x0f802000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal/3@4
+# AUNIT --inst x0f802000/mask=xffc0f400 --status pass --comment "ext"
+
+:smlal Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x2 & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp2:4 = Re_VPR128.S.vIndex;
+ local tmp3:8 = sext(tmp2);
+ # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8
+ TMPQ2[0,64] = TMPQ1[0,64] * tmp3;
+ TMPQ2[64,64] = TMPQ1[64,64] * tmp3;
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ2 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ2[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ2[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.274 SMLAL, SMLAL2 (by element) page C7-2624 line 153127 MATCH x0f002000/mask=xbf00f400
+# CONSTRUCT x0f402000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal/3@2
+# AUNIT --inst x0f402000/mask=xffc0f400 --status pass --comment "ext"
+
+:smlal Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x2 & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp3:4 = sext(tmp2);
+ # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4
+ TMPQ2[0,32] = TMPQ1[0,32] * tmp3;
+ TMPQ2[32,32] = TMPQ1[32,32] * tmp3;
+ TMPQ2[64,32] = TMPQ1[64,32] * tmp3;
+ TMPQ2[96,32] = TMPQ1[96,32] * tmp3;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ2 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ2[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ2[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ2[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ2[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.274 SMLAL, SMLAL2 (by element) page C7-2624 line 153127 MATCH x0f002000/mask=xbf00f400
+# CONSTRUCT x4f802000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 sext:8 $* &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal2/3@4
+# AUNIT --inst x4f802000/mask=xffc0f400 --status pass --comment "ext"
+
+:smlal2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x2 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Rn_VPR128 & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(TMPD1[0,32]);
+ TMPQ2[64,64] = sext(TMPD1[32,32]);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp3:4 = Re_VPR128.S.vIndex;
+ local tmp4:8 = sext(tmp3);
+ # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8
+ TMPQ3[0,64] = TMPQ2[0,64] * tmp4;
+ TMPQ3[64,64] = TMPQ2[64,64] * tmp4;
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ3 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ3[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ3[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.274 SMLAL, SMLAL2 (by element) page C7-2624 line 153127 MATCH x0f002000/mask=xbf00f400
+# CONSTRUCT x4f402000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 sext:4 $* &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal2/3@2
+# AUNIT --inst x4f402000/mask=xffc0f400 --status pass --comment "ext"
+
+:smlal2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x2 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Rn_VPR128 & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(TMPD1[0,16]);
+ TMPQ2[32,32] = sext(TMPD1[16,16]);
+ TMPQ2[64,32] = sext(TMPD1[32,16]);
+ TMPQ2[96,32] = sext(TMPD1[48,16]);
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp3:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp4:4 = sext(tmp3);
+ # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4
+ TMPQ3[0,32] = TMPQ2[0,32] * tmp4;
+ TMPQ3[32,32] = TMPQ2[32,32] * tmp4;
+ TMPQ3[64,32] = TMPQ2[64,32] * tmp4;
+ TMPQ3[96,32] = TMPQ2[96,32] * tmp4;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.275 SMLAL, SMLAL2 (vector) page C7-2627 line 153291 MATCH x0e208000/mask=xbf20fc00
+# CONSTRUCT x0ea08000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 $*@8 &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal/3@4
+# AUNIT --inst x0ea08000/mask=xffe0fc00 --status pass --comment "ext"
+
+:smlal Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x8 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);
+ TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);
+ # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 8
+ TMPQ3[0,64] = TMPQ1[0,64] * TMPQ2[0,64];
+ TMPQ3[64,64] = TMPQ1[64,64] * TMPQ2[64,64];
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ3 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ3[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ3[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.275 SMLAL, SMLAL2 (vector) page C7-2627 line 153291 MATCH x0e208000/mask=xbf20fc00
+# CONSTRUCT x0e608000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 $*@4 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal/3@2
+# AUNIT --inst x0e608000/mask=xffe0fc00 --status pass --comment "ext"
+
+:smlal Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x8 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);
+ TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);
+ TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);
+ TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);
+ # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 4
+ TMPQ3[0,32] = TMPQ1[0,32] * TMPQ2[0,32];
+ TMPQ3[32,32] = TMPQ1[32,32] * TMPQ2[32,32];
+ TMPQ3[64,32] = TMPQ1[64,32] * TMPQ2[64,32];
+ TMPQ3[96,32] = TMPQ1[96,32] * TMPQ2[96,32];
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.275 SMLAL, SMLAL2 (vector) page C7-2627 line 153291 MATCH x0e208000/mask=xbf20fc00
+# CONSTRUCT x0e208000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 $*@2 &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal/3@1
+# AUNIT --inst x0e208000/mask=xffe0fc00 --status pass --comment "ext"
+
+:smlal Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x8 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)
+ TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);
+ TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);
+ TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);
+ TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);
+ TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);
+ TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);
+ TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);
+ TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2)
+ TMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]);
+ TMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]);
+ TMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]);
+ TMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]);
+ TMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]);
+ TMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]);
+ TMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]);
+ TMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]);
+ # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 2
+ TMPQ3[0,16] = TMPQ1[0,16] * TMPQ2[0,16];
+ TMPQ3[16,16] = TMPQ1[16,16] * TMPQ2[16,16];
+ TMPQ3[32,16] = TMPQ1[32,16] * TMPQ2[32,16];
+ TMPQ3[48,16] = TMPQ1[48,16] * TMPQ2[48,16];
+ TMPQ3[64,16] = TMPQ1[64,16] * TMPQ2[64,16];
+ TMPQ3[80,16] = TMPQ1[80,16] * TMPQ2[80,16];
+ TMPQ3[96,16] = TMPQ1[96,16] * TMPQ2[96,16];
+ TMPQ3[112,16] = TMPQ1[112,16] * TMPQ2[112,16];
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ3 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ3[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ3[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ3[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ3[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ3[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ3[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ3[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ3[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.275 SMLAL, SMLAL2 (vector) page C7-2627 line 153291 MATCH x0e208000/mask=xbf20fc00
+# CONSTRUCT x4ea08000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $*@8 &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal2/3@4
+# AUNIT --inst x4ea08000/mask=xffe0fc00 --status pass --comment "ext"
+
+:smlal2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x8 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(TMPD1[0,32]);
+ TMPQ2[64,64] = sext(TMPD1[32,32]);
+ TMPD3 = Rm_VPR128.4S[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)
+ TMPQ4[0,64] = sext(TMPD3[0,32]);
+ TMPQ4[64,64] = sext(TMPD3[32,32]);
+ # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8
+ TMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64];
+ TMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64];
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ5 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ5[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ5[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.275 SMLAL, SMLAL2 (vector) page C7-2627 line 153291 MATCH x0e208000/mask=xbf20fc00
+# CONSTRUCT x4e608000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $*@4 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal2/3@2
+# AUNIT --inst x4e608000/mask=xffe0fc00 --status pass --comment "ext"
+
+:smlal2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x8 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(TMPD1[0,16]);
+ TMPQ2[32,32] = sext(TMPD1[16,16]);
+ TMPQ2[64,32] = sext(TMPD1[32,16]);
+ TMPQ2[96,32] = sext(TMPD1[48,16]);
+ TMPD3 = Rm_VPR128.8H[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)
+ TMPQ4[0,32] = sext(TMPD3[0,16]);
+ TMPQ4[32,32] = sext(TMPD3[16,16]);
+ TMPQ4[64,32] = sext(TMPD3[32,16]);
+ TMPQ4[96,32] = sext(TMPD3[48,16]);
+ # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4
+ TMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32];
+ TMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32];
+ TMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32];
+ TMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32];
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ5 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ5[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ5[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ5[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ5[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.275 SMLAL, SMLAL2 (vector) page C7-2627 line 153291 MATCH x0e208000/mask=xbf20fc00
+# CONSTRUCT x4e208000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 $*@2 &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlal2/3@1
+# AUNIT --inst x4e208000/mask=xffe0fc00 --status pass --comment "ext"
+
+:smlal2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x8 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
+{
+ TMPD1 = Rn_VPR128.16B[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)
+ TMPQ2[0,16] = sext(TMPD1[0,8]);
+ TMPQ2[16,16] = sext(TMPD1[8,8]);
+ TMPQ2[32,16] = sext(TMPD1[16,8]);
+ TMPQ2[48,16] = sext(TMPD1[24,8]);
+ TMPQ2[64,16] = sext(TMPD1[32,8]);
+ TMPQ2[80,16] = sext(TMPD1[40,8]);
+ TMPQ2[96,16] = sext(TMPD1[48,8]);
+ TMPQ2[112,16] = sext(TMPD1[56,8]);
+ TMPD3 = Rm_VPR128.16B[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2)
+ TMPQ4[0,16] = sext(TMPD3[0,8]);
+ TMPQ4[16,16] = sext(TMPD3[8,8]);
+ TMPQ4[32,16] = sext(TMPD3[16,8]);
+ TMPQ4[48,16] = sext(TMPD3[24,8]);
+ TMPQ4[64,16] = sext(TMPD3[32,8]);
+ TMPQ4[80,16] = sext(TMPD3[40,8]);
+ TMPQ4[96,16] = sext(TMPD3[48,8]);
+ TMPQ4[112,16] = sext(TMPD3[56,8]);
+ # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 2
+ TMPQ5[0,16] = TMPQ2[0,16] * TMPQ4[0,16];
+ TMPQ5[16,16] = TMPQ2[16,16] * TMPQ4[16,16];
+ TMPQ5[32,16] = TMPQ2[32,16] * TMPQ4[32,16];
+ TMPQ5[48,16] = TMPQ2[48,16] * TMPQ4[48,16];
+ TMPQ5[64,16] = TMPQ2[64,16] * TMPQ4[64,16];
+ TMPQ5[80,16] = TMPQ2[80,16] * TMPQ4[80,16];
+ TMPQ5[96,16] = TMPQ2[96,16] * TMPQ4[96,16];
+ TMPQ5[112,16] = TMPQ2[112,16] * TMPQ4[112,16];
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ5 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ5[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ5[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ5[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ5[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ5[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ5[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ5[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ5[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.276 SMLSL, SMLSL2 (by element) page C7-2629 line 153415 MATCH x0f006000/mask=xbf00f400
+# CONSTRUCT x0f806000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* &=$-@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl/3@4
+# AUNIT --inst x0f806000/mask=xffc0f400 --status pass --comment "ext"
+
+:smlsl Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x6 & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp2:4 = Re_VPR128.S.vIndex;
+ local tmp3:8 = sext(tmp2);
+ # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8
+ TMPQ2[0,64] = TMPQ1[0,64] * tmp3;
+ TMPQ2[64,64] = TMPQ1[64,64] * tmp3;
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ2 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ2[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ2[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.276 SMLSL, SMLSL2 (by element) page C7-2629 line 153415 MATCH x0f006000/mask=xbf00f400
+# CONSTRUCT x0f406000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* &=$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl/3@2
+# AUNIT --inst x0f406000/mask=xffc0f400 --status pass --comment "ext"
+
+:smlsl Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x6 & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp3:4 = sext(tmp2);
+ # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4
+ TMPQ2[0,32] = TMPQ1[0,32] * tmp3;
+ TMPQ2[32,32] = TMPQ1[32,32] * tmp3;
+ TMPQ2[64,32] = TMPQ1[64,32] * tmp3;
+ TMPQ2[96,32] = TMPQ1[96,32] * tmp3;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ2 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ2[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ2[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ2[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ2[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.276 SMLSL, SMLSL2 (by element) page C7-2629 line 153415 MATCH x0f006000/mask=xbf00f400
+# CONSTRUCT x4f806000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 sext:8 $* &=$-@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl2/3@4
+# AUNIT --inst x4f806000/mask=xffc0f400 --status pass --comment "ext"
+
+:smlsl2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x6 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(TMPD1[0,32]);
+ TMPQ2[64,64] = sext(TMPD1[32,32]);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp3:4 = Re_VPR128.S.vIndex;
+ local tmp4:8 = sext(tmp3);
+ # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8
+ TMPQ3[0,64] = TMPQ2[0,64] * tmp4;
+ TMPQ3[64,64] = TMPQ2[64,64] * tmp4;
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ3 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ3[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ3[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.276 SMLSL, SMLSL2 (by element) page C7-2629 line 153415 MATCH x0f006000/mask=xbf00f400
+# CONSTRUCT x4f406000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 sext:4 $* &=$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl2/3@2
+# AUNIT --inst x4f406000/mask=xffc0f400 --status pass --comment "ext"
+
+:smlsl2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x6 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(TMPD1[0,16]);
+ TMPQ2[32,32] = sext(TMPD1[16,16]);
+ TMPQ2[64,32] = sext(TMPD1[32,16]);
+ TMPQ2[96,32] = sext(TMPD1[48,16]);
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp3:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp4:4 = sext(tmp3);
+ # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4
+ TMPQ3[0,32] = TMPQ2[0,32] * tmp4;
+ TMPQ3[32,32] = TMPQ2[32,32] * tmp4;
+ TMPQ3[64,32] = TMPQ2[64,32] * tmp4;
+ TMPQ3[96,32] = TMPQ2[96,32] * tmp4;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.277 SMLSL, SMLSL2 (vector) page C7-2632 line 153579 MATCH x0e20a000/mask=xbf20fc00
+# CONSTRUCT x0ea0a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 $*@8 &=$-@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl/3@4
+# AUNIT --inst x0ea0a000/mask=xffe0fc00 --status pass --comment "ext"
+
+:smlsl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0xa & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);
+ TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);
+ # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 8
+ TMPQ3[0,64] = TMPQ1[0,64] * TMPQ2[0,64];
+ TMPQ3[64,64] = TMPQ1[64,64] * TMPQ2[64,64];
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ3 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ3[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ3[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.277 SMLSL, SMLSL2 (vector) page C7-2632 line 153579 MATCH x0e20a000/mask=xbf20fc00
+# CONSTRUCT x0e60a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 $*@4 &=$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl/3@2
+# AUNIT --inst x0e60a000/mask=xffe0fc00 --status pass --comment "ext"
+
+:smlsl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0xa & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);
+ TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);
+ TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);
+ TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);
+ # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 4
+ TMPQ3[0,32] = TMPQ1[0,32] * TMPQ2[0,32];
+ TMPQ3[32,32] = TMPQ1[32,32] * TMPQ2[32,32];
+ TMPQ3[64,32] = TMPQ1[64,32] * TMPQ2[64,32];
+ TMPQ3[96,32] = TMPQ1[96,32] * TMPQ2[96,32];
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.277 SMLSL, SMLSL2 (vector) page C7-2632 line 153579 MATCH x0e20a000/mask=xbf20fc00
+# CONSTRUCT x0e20a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 $*@2 &=$-@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl/3@1
+# AUNIT --inst x0e20a000/mask=xffe0fc00 --status pass --comment "ext"
+
+:smlsl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0xa & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)
+ TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);
+ TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);
+ TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);
+ TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);
+ TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);
+ TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);
+ TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);
+ TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2)
+ TMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]);
+ TMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]);
+ TMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]);
+ TMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]);
+ TMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]);
+ TMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]);
+ TMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]);
+ TMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]);
+ # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 2
+ TMPQ3[0,16] = TMPQ1[0,16] * TMPQ2[0,16];
+ TMPQ3[16,16] = TMPQ1[16,16] * TMPQ2[16,16];
+ TMPQ3[32,16] = TMPQ1[32,16] * TMPQ2[32,16];
+ TMPQ3[48,16] = TMPQ1[48,16] * TMPQ2[48,16];
+ TMPQ3[64,16] = TMPQ1[64,16] * TMPQ2[64,16];
+ TMPQ3[80,16] = TMPQ1[80,16] * TMPQ2[80,16];
+ TMPQ3[96,16] = TMPQ1[96,16] * TMPQ2[96,16];
+ TMPQ3[112,16] = TMPQ1[112,16] * TMPQ2[112,16];
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H - TMPQ3 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] - TMPQ3[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] - TMPQ3[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] - TMPQ3[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] - TMPQ3[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] - TMPQ3[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] - TMPQ3[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] - TMPQ3[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] - TMPQ3[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.277 SMLSL, SMLSL2 (vector) page C7-2632 line 153579 MATCH x0e20a000/mask=xbf20fc00
+# CONSTRUCT x4ea0a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $*@8 &=$-@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl2/3@4
+# AUNIT --inst x4ea0a000/mask=xffe0fc00 --status pass --comment "ext"
+
+:smlsl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0xa & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(TMPD1[0,32]);
+ TMPQ2[64,64] = sext(TMPD1[32,32]);
+ TMPD3 = Rm_VPR128.4S[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)
+ TMPQ4[0,64] = sext(TMPD3[0,32]);
+ TMPQ4[64,64] = sext(TMPD3[32,32]);
+ # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8
+ TMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64];
+ TMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64];
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ5 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ5[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ5[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.277 SMLSL, SMLSL2 (vector) page C7-2632 line 153579 MATCH x0e20a000/mask=xbf20fc00
+# CONSTRUCT x4e60a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $*@4 &=$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl2/3@2
+# AUNIT --inst x4e60a000/mask=xffe0fc00 --status pass --comment "ext"
+
+:smlsl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0xa & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(TMPD1[0,16]);
+ TMPQ2[32,32] = sext(TMPD1[16,16]);
+ TMPQ2[64,32] = sext(TMPD1[32,16]);
+ TMPQ2[96,32] = sext(TMPD1[48,16]);
+ TMPD3 = Rm_VPR128.8H[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)
+ TMPQ4[0,32] = sext(TMPD3[0,16]);
+ TMPQ4[32,32] = sext(TMPD3[16,16]);
+ TMPQ4[64,32] = sext(TMPD3[32,16]);
+ TMPQ4[96,32] = sext(TMPD3[48,16]);
+ # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4
+ TMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32];
+ TMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32];
+ TMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32];
+ TMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32];
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ5 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ5[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ5[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ5[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ5[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.277 SMLSL, SMLSL2 (vector) page C7-2632 line 153579 MATCH x0e20a000/mask=xbf20fc00
+# CONSTRUCT x4e20a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 $*@2 &=$-@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_smlsl2/3@1
+# AUNIT --inst x4e20a000/mask=xffe0fc00 --status pass --comment "ext"
+
+:smlsl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0xa & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
+{
+ TMPD1 = Rn_VPR128.16B[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)
+ TMPQ2[0,16] = sext(TMPD1[0,8]);
+ TMPQ2[16,16] = sext(TMPD1[8,8]);
+ TMPQ2[32,16] = sext(TMPD1[16,8]);
+ TMPQ2[48,16] = sext(TMPD1[24,8]);
+ TMPQ2[64,16] = sext(TMPD1[32,8]);
+ TMPQ2[80,16] = sext(TMPD1[40,8]);
+ TMPQ2[96,16] = sext(TMPD1[48,8]);
+ TMPQ2[112,16] = sext(TMPD1[56,8]);
+ TMPD3 = Rm_VPR128.16B[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2)
+ TMPQ4[0,16] = sext(TMPD3[0,8]);
+ TMPQ4[16,16] = sext(TMPD3[8,8]);
+ TMPQ4[32,16] = sext(TMPD3[16,8]);
+ TMPQ4[48,16] = sext(TMPD3[24,8]);
+ TMPQ4[64,16] = sext(TMPD3[32,8]);
+ TMPQ4[80,16] = sext(TMPD3[40,8]);
+ TMPQ4[96,16] = sext(TMPD3[48,8]);
+ TMPQ4[112,16] = sext(TMPD3[56,8]);
+ # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 2
+ TMPQ5[0,16] = TMPQ2[0,16] * TMPQ4[0,16];
+ TMPQ5[16,16] = TMPQ2[16,16] * TMPQ4[16,16];
+ TMPQ5[32,16] = TMPQ2[32,16] * TMPQ4[32,16];
+ TMPQ5[48,16] = TMPQ2[48,16] * TMPQ4[48,16];
+ TMPQ5[64,16] = TMPQ2[64,16] * TMPQ4[64,16];
+ TMPQ5[80,16] = TMPQ2[80,16] * TMPQ4[80,16];
+ TMPQ5[96,16] = TMPQ2[96,16] * TMPQ4[96,16];
+ TMPQ5[112,16] = TMPQ2[112,16] * TMPQ4[112,16];
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H - TMPQ5 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] - TMPQ5[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] - TMPQ5[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] - TMPQ5[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] - TMPQ5[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] - TMPQ5[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] - TMPQ5[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] - TMPQ5[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] - TMPQ5[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.279 SMOV page C7-2635 line 153760 MATCH x0e002c00/mask=xbfe0fc00
+# CONSTRUCT x0e012c00/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =sext
+# SMACRO(pseudo) ARG1 ARG2 =NEON_smov/1
+# AUNIT --inst x0e012c00/mask=xffe1fc00 --status pass
+
+:smov Rd_GPR32, Rn_VPR128.B.imm_neon_uimm4
+is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x5 & b_1010=1 & Rn_VPR128 & Rd_GPR32 & Rd_GPR64
+{
+ # simd element Rn_VPR128[imm_neon_uimm4] lane size 1
+ local tmp1:1 = Rn_VPR128.B.imm_neon_uimm4;
+ Rd_GPR32 = sext(tmp1);
+ zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
+}
+
+# C7.2.279 SMOV page C7-2635 line 153760 MATCH x0e002c00/mask=xbfe0fc00
+# CONSTRUCT x0e022c00/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =sext
+# SMACRO(pseudo) ARG1 ARG2 =NEON_smov/1
+# AUNIT --inst x0e022c00/mask=xffe3fc00 --status pass
+
+:smov Rd_GPR32, Rn_VPR128.H.imm_neon_uimm3
+is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x5 & b_1010=1 & Rn_VPR128 & Rd_GPR32 & Rd_GPR64
+{
+ # simd element Rn_VPR128[imm_neon_uimm3] lane size 2
+ local tmp1:2 = Rn_VPR128.H.imm_neon_uimm3;
+ Rd_GPR32 = sext(tmp1);
+ zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
+}
+
+# C7.2.279 SMOV page C7-2635 line 153760 MATCH x0e002c00/mask=xbfe0fc00
+# CONSTRUCT x4e012c00/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =sext
+# SMACRO(pseudo) ARG1 ARG2 =NEON_smov/1
+# AUNIT --inst x4e012c00/mask=xffe1fc00 --status pass
+
+:smov Rd_GPR64, Rn_VPR128.B.imm_neon_uimm4
+is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x5 & b_1010=1 & Rn_VPR128 & Rd_GPR64
+{
+ # simd element Rn_VPR128[imm_neon_uimm4] lane size 1
+ local tmp1:1 = Rn_VPR128.B.imm_neon_uimm4;
+ Rd_GPR64 = sext(tmp1);
+}
+
+# C7.2.279 SMOV page C7-2635 line 153760 MATCH x0e002c00/mask=xbfe0fc00
+# CONSTRUCT x4e022c00/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =sext
+# SMACRO(pseudo) ARG1 ARG2 =NEON_smov/1
+# AUNIT --inst x4e022c00/mask=xffe3fc00 --status pass
+
+:smov Rd_GPR64, Rn_VPR128.H.imm_neon_uimm3
+is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x5 & b_1010=1 & Rn_VPR128 & Rd_GPR64
+{
+ # simd element Rn_VPR128[imm_neon_uimm3] lane size 2
+ local tmp1:2 = Rn_VPR128.H.imm_neon_uimm3;
+ Rd_GPR64 = sext(tmp1);
+}
+
+# C7.2.279 SMOV page C7-2635 line 153760 MATCH x0e002c00/mask=xbfe0fc00
+# CONSTRUCT x4e042c00/mask=xffe7fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =sext
+# SMACRO(pseudo) ARG1 ARG2 =NEON_smov/1
+# AUNIT --inst x4e042c00/mask=xffe7fc00 --status pass
+
+:smov Rd_GPR64, Rn_VPR128.S.imm_neon_uimm2
+is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.S.imm_neon_uimm2 & b_1618=4 & b_1515=0 & imm4=0x5 & b_1010=1 & Rn_VPR128 & Rd_GPR64
+{
+ # simd element Rn_VPR128[imm_neon_uimm2] lane size 4
+ local tmp1:4 = Rn_VPR128.S.imm_neon_uimm2;
+ Rd_GPR64 = sext(tmp1);
+}
+
+# C7.2.280 SMULL, SMULL2 (by element) page C7-2637 line 153881 MATCH x0f00a000/mask=xbf00f400
+# CONSTRUCT x0f80a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 =$*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull/2@4
+# AUNIT --inst x0f80a000/mask=xffc0f400 --status pass --comment "ext"
+
+:smull Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xa & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp2:4 = Re_VPR128.S.vIndex;
+ local tmp3:8 = sext(tmp2);
+ # simd infix Rd_VPR128.2D = TMPQ1 * tmp3 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ1[0,64] * tmp3;
+ Rd_VPR128.2D[64,64] = TMPQ1[64,64] * tmp3;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.280 SMULL, SMULL2 (by element) page C7-2637 line 153881 MATCH x0f00a000/mask=xbf00f400
+# CONSTRUCT x0f40a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 =$*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull/2@2
+# AUNIT --inst x0f40a000/mask=xffc0f400 --status pass --comment "ext"
+
+:smull Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xa & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp3:4 = sext(tmp2);
+ # simd infix Rd_VPR128.4S = TMPQ1 * tmp3 on lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ1[0,32] * tmp3;
+ Rd_VPR128.4S[32,32] = TMPQ1[32,32] * tmp3;
+ Rd_VPR128.4S[64,32] = TMPQ1[64,32] * tmp3;
+ Rd_VPR128.4S[96,32] = TMPQ1[96,32] * tmp3;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.280 SMULL, SMULL2 (by element) page C7-2637 line 153881 MATCH x0f00a000/mask=xbf00f400
+# CONSTRUCT x4f80a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 sext:8 =$*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull2/2@4
+# AUNIT --inst x4f80a000/mask=xffc0f400 --status pass --comment "ext"
+
+:smull2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xa & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Rn_VPR128 & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(TMPD1[0,32]);
+ TMPQ2[64,64] = sext(TMPD1[32,32]);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp3:4 = Re_VPR128.S.vIndex;
+ local tmp4:8 = sext(tmp3);
+ # simd infix Rd_VPR128.2D = TMPQ2 * tmp4 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ2[0,64] * tmp4;
+ Rd_VPR128.2D[64,64] = TMPQ2[64,64] * tmp4;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.280 SMULL, SMULL2 (by element) page C7-2637 line 153881 MATCH x0f00a000/mask=xbf00f400
+# CONSTRUCT x4f40a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 sext:4 =$*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull2/2@2
+# AUNIT --inst x4f40a000/mask=xffc0f400 --status pass --comment "ext"
+
+:smull2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xa & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Rn_VPR128 & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(TMPD1[0,16]);
+ TMPQ2[32,32] = sext(TMPD1[16,16]);
+ TMPQ2[64,32] = sext(TMPD1[32,16]);
+ TMPQ2[96,32] = sext(TMPD1[48,16]);
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp3:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp4:4 = sext(tmp3);
+ # simd infix Rd_VPR128.4S = TMPQ2 * tmp4 on lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ2[0,32] * tmp4;
+ Rd_VPR128.4S[32,32] = TMPQ2[32,32] * tmp4;
+ Rd_VPR128.4S[64,32] = TMPQ2[64,32] * tmp4;
+ Rd_VPR128.4S[96,32] = TMPQ2[96,32] * tmp4;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.281 SMULL, SMULL2 (vector) page C7-2640 line 154037 MATCH x0e20c000/mask=xbf20fc00
+# CONSTRUCT x0ea0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 =$*@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull/2@4
+# AUNIT --inst x0ea0c000/mask=xffe0fc00 --status pass --comment "ext"
+
+:smull Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0xc & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);
+ TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);
+ # simd infix Rd_VPR128.2D = TMPQ1 * TMPQ2 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ1[0,64] * TMPQ2[0,64];
+ Rd_VPR128.2D[64,64] = TMPQ1[64,64] * TMPQ2[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.281 SMULL, SMULL2 (vector) page C7-2640 line 154037 MATCH x0e20c000/mask=xbf20fc00
+# CONSTRUCT x0e60c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 =$*@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull/2@2
+# AUNIT --inst x0e60c000/mask=xffe0fc00 --status pass --comment "ext"
+
+:smull Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0xc & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);
+ TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);
+ TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);
+ TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);
+ # simd infix Rd_VPR128.4S = TMPQ1 * TMPQ2 on lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ1[0,32] * TMPQ2[0,32];
+ Rd_VPR128.4S[32,32] = TMPQ1[32,32] * TMPQ2[32,32];
+ Rd_VPR128.4S[64,32] = TMPQ1[64,32] * TMPQ2[64,32];
+ Rd_VPR128.4S[96,32] = TMPQ1[96,32] * TMPQ2[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.281 SMULL, SMULL2 (vector) page C7-2640 line 154037 MATCH x0e20c000/mask=xbf20fc00
+# CONSTRUCT x0e20c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 =$*@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull/2@1
+# AUNIT --inst x0e20c000/mask=xffe0fc00 --status pass --comment "ext"
+
+:smull Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0xc & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)
+ TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);
+ TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);
+ TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);
+ TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);
+ TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);
+ TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);
+ TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);
+ TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2)
+ TMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]);
+ TMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]);
+ TMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]);
+ TMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]);
+ TMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]);
+ TMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]);
+ TMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]);
+ TMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]);
+ # simd infix Rd_VPR128.8H = TMPQ1 * TMPQ2 on lane size 2
+ Rd_VPR128.8H[0,16] = TMPQ1[0,16] * TMPQ2[0,16];
+ Rd_VPR128.8H[16,16] = TMPQ1[16,16] * TMPQ2[16,16];
+ Rd_VPR128.8H[32,16] = TMPQ1[32,16] * TMPQ2[32,16];
+ Rd_VPR128.8H[48,16] = TMPQ1[48,16] * TMPQ2[48,16];
+ Rd_VPR128.8H[64,16] = TMPQ1[64,16] * TMPQ2[64,16];
+ Rd_VPR128.8H[80,16] = TMPQ1[80,16] * TMPQ2[80,16];
+ Rd_VPR128.8H[96,16] = TMPQ1[96,16] * TMPQ2[96,16];
+ Rd_VPR128.8H[112,16] = TMPQ1[112,16] * TMPQ2[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.281 SMULL, SMULL2 (vector) page C7-2640 line 154037 MATCH x0e20c000/mask=xbf20fc00
+# CONSTRUCT x4ea0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 =$*@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull2/2@4
+# AUNIT --inst x4ea0c000/mask=xffe0fc00 --status pass --comment "ext"
+
+:smull2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0xc & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Rn_VPR128 & Rm_VPR128 & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(TMPD1[0,32]);
+ TMPQ2[64,64] = sext(TMPD1[32,32]);
+ TMPD3 = Rm_VPR128.4S[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)
+ TMPQ4[0,64] = sext(TMPD3[0,32]);
+ TMPQ4[64,64] = sext(TMPD3[32,32]);
+ # simd infix Rd_VPR128.2D = TMPQ2 * TMPQ4 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ2[0,64] * TMPQ4[0,64];
+ Rd_VPR128.2D[64,64] = TMPQ2[64,64] * TMPQ4[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.281 SMULL, SMULL2 (vector) page C7-2640 line 154037 MATCH x0e20c000/mask=xbf20fc00
+# CONSTRUCT x4e60c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 =$*@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull2/2@2
+# AUNIT --inst x4e60c000/mask=xffe0fc00 --status pass --comment "ext"
+
+:smull2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0xc & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Rn_VPR128 & Rm_VPR128 & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(TMPD1[0,16]);
+ TMPQ2[32,32] = sext(TMPD1[16,16]);
+ TMPQ2[64,32] = sext(TMPD1[32,16]);
+ TMPQ2[96,32] = sext(TMPD1[48,16]);
+ TMPD3 = Rm_VPR128.8H[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)
+ TMPQ4[0,32] = sext(TMPD3[0,16]);
+ TMPQ4[32,32] = sext(TMPD3[16,16]);
+ TMPQ4[64,32] = sext(TMPD3[32,16]);
+ TMPQ4[96,32] = sext(TMPD3[48,16]);
+ # simd infix Rd_VPR128.4S = TMPQ2 * TMPQ4 on lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ2[0,32] * TMPQ4[0,32];
+ Rd_VPR128.4S[32,32] = TMPQ2[32,32] * TMPQ4[32,32];
+ Rd_VPR128.4S[64,32] = TMPQ2[64,32] * TMPQ4[64,32];
+ Rd_VPR128.4S[96,32] = TMPQ2[96,32] * TMPQ4[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.281 SMULL, SMULL2 (vector) page C7-2640 line 154037 MATCH x0e20c000/mask=xbf20fc00
+# CONSTRUCT x4e20c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 =$*@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_smull2/2@1
+# AUNIT --inst x4e20c000/mask=xffe0fc00 --status pass --comment "ext"
+
+:smull2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0xc & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Rn_VPR128 & Rm_VPR128 & Zd
+{
+ TMPD1 = Rn_VPR128.16B[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)
+ TMPQ2[0,16] = sext(TMPD1[0,8]);
+ TMPQ2[16,16] = sext(TMPD1[8,8]);
+ TMPQ2[32,16] = sext(TMPD1[16,8]);
+ TMPQ2[48,16] = sext(TMPD1[24,8]);
+ TMPQ2[64,16] = sext(TMPD1[32,8]);
+ TMPQ2[80,16] = sext(TMPD1[40,8]);
+ TMPQ2[96,16] = sext(TMPD1[48,8]);
+ TMPQ2[112,16] = sext(TMPD1[56,8]);
+ TMPD3 = Rm_VPR128.16B[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2)
+ TMPQ4[0,16] = sext(TMPD3[0,8]);
+ TMPQ4[16,16] = sext(TMPD3[8,8]);
+ TMPQ4[32,16] = sext(TMPD3[16,8]);
+ TMPQ4[48,16] = sext(TMPD3[24,8]);
+ TMPQ4[64,16] = sext(TMPD3[32,8]);
+ TMPQ4[80,16] = sext(TMPD3[40,8]);
+ TMPQ4[96,16] = sext(TMPD3[48,8]);
+ TMPQ4[112,16] = sext(TMPD3[56,8]);
+ # simd infix Rd_VPR128.8H = TMPQ2 * TMPQ4 on lane size 2
+ Rd_VPR128.8H[0,16] = TMPQ2[0,16] * TMPQ4[0,16];
+ Rd_VPR128.8H[16,16] = TMPQ2[16,16] * TMPQ4[16,16];
+ Rd_VPR128.8H[32,16] = TMPQ2[32,16] * TMPQ4[32,16];
+ Rd_VPR128.8H[48,16] = TMPQ2[48,16] * TMPQ4[48,16];
+ Rd_VPR128.8H[64,16] = TMPQ2[64,16] * TMPQ4[64,16];
+ Rd_VPR128.8H[80,16] = TMPQ2[80,16] * TMPQ4[80,16];
+ Rd_VPR128.8H[96,16] = TMPQ2[96,16] * TMPQ4[96,16];
+ Rd_VPR128.8H[112,16] = TMPQ2[112,16] * TMPQ4[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.282 SQABS page C7-2642 line 154155 MATCH x5e207800/mask=xff3ffc00
+# CONSTRUCT x5e207800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =abs
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1
+# AUNIT --inst x5e207800/mask=xfffffc00 --status pass --comment "nointsat"
+# Scalar variant when size = 00 Q = 1 aa=1 suf=FPR8
+# Note: in some implemented semantics that ignore saturation (where it
+# makes a difference), there is an error in about 50% of the lanes.
+
+:sqabs Rd_FPR8, Rn_FPR8
+is b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b00 & b_1021=0b100000011110 & Rd_FPR8 & Rn_FPR8 & Zd
+{
+ Rd_FPR8 = MP_INT_ABS(Rn_FPR8);
+ zext_zb(Zd); # zero upper 31 bytes of Zd
+}
+
+# C7.2.282 SQABS page C7-2642 line 154155 MATCH x5e207800/mask=xff3ffc00
+# CONSTRUCT x5e607800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =abs
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1
+# AUNIT --inst x5e607800/mask=xfffffc00 --status pass --comment "nointsat"
+# Scalar variant when size = 01 Q = 1 aa=1 suf=FPR16
+
+:sqabs Rd_FPR16, Rn_FPR16
+is b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b01 & b_1021=0b100000011110 & Rd_FPR16 & Rn_FPR16 & Zd
+{
+ Rd_FPR16 = MP_INT_ABS(Rn_FPR16);
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.282 SQABS page C7-2642 line 154155 MATCH x5e207800/mask=xff3ffc00
+# CONSTRUCT x5ea07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =abs
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1
+# AUNIT --inst x5ea07800/mask=xfffffc00 --status pass --comment "nointsat"
+# Scalar variant when size = 10 Q = 1 aa=1 suf=FPR32
+
+:sqabs Rd_FPR32, Rn_FPR32
+is b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b10 & b_1021=0b100000011110 & Rd_FPR32 & Rn_FPR32 & Zd
+{
+ Rd_FPR32 = MP_INT_ABS(Rn_FPR32);
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.282 SQABS page C7-2642 line 154155 MATCH x5e207800/mask=xff3ffc00
+# CONSTRUCT x5ee07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =abs
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1
+# AUNIT --inst x5ee07800/mask=xfffffc00 --status pass --comment "nointsat"
+# Scalar variant when size = 11 Q = 1 aa=1 suf=FPR64
+
+:sqabs Rd_FPR64, Rn_FPR64
+is b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b11 & b_1021=0b100000011110 & Rd_FPR64 & Rn_FPR64 & Zd
+{
+ Rd_FPR64 = MP_INT_ABS(Rn_FPR64);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.282 SQABS page C7-2642 line 154155 MATCH x0e207800/mask=xbf3ffc00
+# CONSTRUCT x0e207800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$abs@1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@1
+# AUNIT --inst x0e207800/mask=xfffffc00 --status fail --comment "nointsat"
+# Vector variant when size = 00 Q = 0 aa=0 esize=1 suf=VPR64.8B
+
+:sqabs Rd_VPR64.8B, Rn_VPR64.8B
+is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000011110 & Rd_VPR64.8B & Rn_VPR64.8B & Zd
+{
+ # simd unary Rd_VPR64.8B = MP_INT_ABS(Rn_VPR64.8B) on lane size 1
+ Rd_VPR64.8B[0,8] = MP_INT_ABS(Rn_VPR64.8B[0,8]);
+ Rd_VPR64.8B[8,8] = MP_INT_ABS(Rn_VPR64.8B[8,8]);
+ Rd_VPR64.8B[16,8] = MP_INT_ABS(Rn_VPR64.8B[16,8]);
+ Rd_VPR64.8B[24,8] = MP_INT_ABS(Rn_VPR64.8B[24,8]);
+ Rd_VPR64.8B[32,8] = MP_INT_ABS(Rn_VPR64.8B[32,8]);
+ Rd_VPR64.8B[40,8] = MP_INT_ABS(Rn_VPR64.8B[40,8]);
+ Rd_VPR64.8B[48,8] = MP_INT_ABS(Rn_VPR64.8B[48,8]);
+ Rd_VPR64.8B[56,8] = MP_INT_ABS(Rn_VPR64.8B[56,8]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.282 SQABS page C7-2642 line 154155 MATCH x0e207800/mask=xbf3ffc00
+# CONSTRUCT x4e207800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$abs@1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@1
+# AUNIT --inst x4e207800/mask=xfffffc00 --status fail --comment "nointsat"
+# Vector variant when size = 00 Q = 1 aa=0 esize=1 suf=VPR128.16B
+
+:sqabs Rd_VPR128.16B, Rn_VPR128.16B
+is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000011110 & Rd_VPR128.16B & Rn_VPR128.16B & Zd
+{
+ # simd unary Rd_VPR128.16B = MP_INT_ABS(Rn_VPR128.16B) on lane size 1
+ Rd_VPR128.16B[0,8] = MP_INT_ABS(Rn_VPR128.16B[0,8]);
+ Rd_VPR128.16B[8,8] = MP_INT_ABS(Rn_VPR128.16B[8,8]);
+ Rd_VPR128.16B[16,8] = MP_INT_ABS(Rn_VPR128.16B[16,8]);
+ Rd_VPR128.16B[24,8] = MP_INT_ABS(Rn_VPR128.16B[24,8]);
+ Rd_VPR128.16B[32,8] = MP_INT_ABS(Rn_VPR128.16B[32,8]);
+ Rd_VPR128.16B[40,8] = MP_INT_ABS(Rn_VPR128.16B[40,8]);
+ Rd_VPR128.16B[48,8] = MP_INT_ABS(Rn_VPR128.16B[48,8]);
+ Rd_VPR128.16B[56,8] = MP_INT_ABS(Rn_VPR128.16B[56,8]);
+ Rd_VPR128.16B[64,8] = MP_INT_ABS(Rn_VPR128.16B[64,8]);
+ Rd_VPR128.16B[72,8] = MP_INT_ABS(Rn_VPR128.16B[72,8]);
+ Rd_VPR128.16B[80,8] = MP_INT_ABS(Rn_VPR128.16B[80,8]);
+ Rd_VPR128.16B[88,8] = MP_INT_ABS(Rn_VPR128.16B[88,8]);
+ Rd_VPR128.16B[96,8] = MP_INT_ABS(Rn_VPR128.16B[96,8]);
+ Rd_VPR128.16B[104,8] = MP_INT_ABS(Rn_VPR128.16B[104,8]);
+ Rd_VPR128.16B[112,8] = MP_INT_ABS(Rn_VPR128.16B[112,8]);
+ Rd_VPR128.16B[120,8] = MP_INT_ABS(Rn_VPR128.16B[120,8]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.282 SQABS page C7-2642 line 154155 MATCH x0e207800/mask=xbf3ffc00
+# CONSTRUCT x0e607800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$abs@2
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@2
+# AUNIT --inst x0e607800/mask=xfffffc00 --status pass --comment "nointsat"
+# Vector variant when size = 01 Q = 0 aa=0 esize=2 suf=VPR64.4H
+
+:sqabs Rd_VPR64.4H, Rn_VPR64.4H
+is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000011110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
+{
+ # simd unary Rd_VPR64.4H = MP_INT_ABS(Rn_VPR64.4H) on lane size 2
+ Rd_VPR64.4H[0,16] = MP_INT_ABS(Rn_VPR64.4H[0,16]);
+ Rd_VPR64.4H[16,16] = MP_INT_ABS(Rn_VPR64.4H[16,16]);
+ Rd_VPR64.4H[32,16] = MP_INT_ABS(Rn_VPR64.4H[32,16]);
+ Rd_VPR64.4H[48,16] = MP_INT_ABS(Rn_VPR64.4H[48,16]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.282 SQABS page C7-2642 line 154155 MATCH x0e207800/mask=xbf3ffc00
+# CONSTRUCT x4e607800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$abs@2
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@2
+# AUNIT --inst x4e607800/mask=xfffffc00 --status pass --comment "nointsat"
+# Vector variant when size = 01 Q = 1 aa=0 esize=2 suf=VPR128.8H
+
+:sqabs Rd_VPR128.8H, Rn_VPR128.8H
+is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000011110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
+{
+ # simd unary Rd_VPR128.8H = MP_INT_ABS(Rn_VPR128.8H) on lane size 2
+ Rd_VPR128.8H[0,16] = MP_INT_ABS(Rn_VPR128.8H[0,16]);
+ Rd_VPR128.8H[16,16] = MP_INT_ABS(Rn_VPR128.8H[16,16]);
+ Rd_VPR128.8H[32,16] = MP_INT_ABS(Rn_VPR128.8H[32,16]);
+ Rd_VPR128.8H[48,16] = MP_INT_ABS(Rn_VPR128.8H[48,16]);
+ Rd_VPR128.8H[64,16] = MP_INT_ABS(Rn_VPR128.8H[64,16]);
+ Rd_VPR128.8H[80,16] = MP_INT_ABS(Rn_VPR128.8H[80,16]);
+ Rd_VPR128.8H[96,16] = MP_INT_ABS(Rn_VPR128.8H[96,16]);
+ Rd_VPR128.8H[112,16] = MP_INT_ABS(Rn_VPR128.8H[112,16]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.282 SQABS page C7-2642 line 154155 MATCH x0e207800/mask=xbf3ffc00
+# CONSTRUCT x0ea07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$abs@4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@4
+# AUNIT --inst x0ea07800/mask=xfffffc00 --status pass --comment "nointsat"
+# Vector variant when size = 10 Q = 0 aa=0 esize=4 suf=VPR64.2S
+
+:sqabs Rd_VPR64.2S, Rn_VPR64.2S
+is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000011110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd
+{
+ # simd unary Rd_VPR64.2S = MP_INT_ABS(Rn_VPR64.2S) on lane size 4
+ Rd_VPR64.2S[0,32] = MP_INT_ABS(Rn_VPR64.2S[0,32]);
+ Rd_VPR64.2S[32,32] = MP_INT_ABS(Rn_VPR64.2S[32,32]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.282 SQABS page C7-2642 line 154155 MATCH x0e207800/mask=xbf3ffc00
+# CONSTRUCT x4ea07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$abs@4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@4
+# AUNIT --inst x4ea07800/mask=xfffffc00 --status pass --comment "nointsat"
+# Vector variant when size = 10 Q = 1 aa=0 esize=4 suf=VPR128.4S
+
+:sqabs Rd_VPR128.4S, Rn_VPR128.4S
+is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000011110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
+{
+ # simd unary Rd_VPR128.4S = MP_INT_ABS(Rn_VPR128.4S) on lane size 4
+ Rd_VPR128.4S[0,32] = MP_INT_ABS(Rn_VPR128.4S[0,32]);
+ Rd_VPR128.4S[32,32] = MP_INT_ABS(Rn_VPR128.4S[32,32]);
+ Rd_VPR128.4S[64,32] = MP_INT_ABS(Rn_VPR128.4S[64,32]);
+ Rd_VPR128.4S[96,32] = MP_INT_ABS(Rn_VPR128.4S[96,32]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.282 SQABS page C7-2642 line 154155 MATCH x0e207800/mask=xbf3ffc00
+# CONSTRUCT x4ee07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$abs@8
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sqabs/1@8
+# AUNIT --inst x4ee07800/mask=xfffffc00 --status pass --comment "nointsat"
+# Vector variant when size = 11 Q = 1 aa=0 esize=8 suf=VPR128.2D
+
+:sqabs Rd_VPR128.2D, Rn_VPR128.2D
+is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b11 & b_1021=0b100000011110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd
+{
+ # simd unary Rd_VPR128.2D = MP_INT_ABS(Rn_VPR128.2D) on lane size 8
+ Rd_VPR128.2D[0,64] = MP_INT_ABS(Rn_VPR128.2D[0,64]);
+ Rd_VPR128.2D[64,64] = MP_INT_ABS(Rn_VPR128.2D[64,64]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.283 SQADD page C7-2644 line 154278 MATCH x5e200c00/mask=xff20fc00
+# CONSTRUCT x5e200c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2
+# AUNIT --inst x5e200c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqadd Rd_FPR8, Rn_FPR8, Rm_FPR8
+is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0x1 & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd
+{
+ Rd_FPR8 = NEON_sqadd(Rn_FPR8, Rm_FPR8);
+}
+
+# C7.2.283 SQADD page C7-2644 line 154278 MATCH x5e200c00/mask=xff20fc00
+# CONSTRUCT x5ee00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2
+# AUNIT --inst x5ee00c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqadd Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x1 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_sqadd(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.283 SQADD page C7-2644 line 154278 MATCH x5e200c00/mask=xff20fc00
+# CONSTRUCT x5e600c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2
+# AUNIT --inst x5e600c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqadd Rd_FPR16, Rn_FPR16, Rm_FPR16
+is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x1 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_sqadd(Rn_FPR16, Rm_FPR16);
+}
+
+# C7.2.283 SQADD page C7-2644 line 154278 MATCH x5e200c00/mask=xff20fc00
+# CONSTRUCT x5ea00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2
+# AUNIT --inst x5ea00c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqadd Rd_FPR32, Rn_FPR32, Rm_FPR32
+is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x1 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_sqadd(Rn_FPR32, Rm_FPR32);
+}
+
+# C7.2.283 SQADD page C7-2644 line 154278 MATCH x0e200c00/mask=xbf20fc00
+# CONSTRUCT x4e200c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@1
+# AUNIT --inst x4e200c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqadd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x1 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_sqadd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.283 SQADD page C7-2644 line 154278 MATCH x0e200c00/mask=xbf20fc00
+# CONSTRUCT x4ee00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@8
+# AUNIT --inst x4ee00c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqadd Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x1 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_sqadd(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.283 SQADD page C7-2644 line 154278 MATCH x0e200c00/mask=xbf20fc00
+# CONSTRUCT x0ea00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@4
+# AUNIT --inst x0ea00c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x1 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_sqadd(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.283 SQADD page C7-2644 line 154278 MATCH x0e200c00/mask=xbf20fc00
+# CONSTRUCT x0e600c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@2
+# AUNIT --inst x0e600c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x1 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_sqadd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.283 SQADD page C7-2644 line 154278 MATCH x0e200c00/mask=xbf20fc00
+# CONSTRUCT x4ea00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@4
+# AUNIT --inst x4ea00c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x1 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sqadd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.283 SQADD page C7-2644 line 154278 MATCH x0e200c00/mask=xbf20fc00
+# CONSTRUCT x0e200c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@1
+# AUNIT --inst x0e200c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqadd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x1 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_sqadd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.283 SQADD page C7-2644 line 154278 MATCH x0e200c00/mask=xbf20fc00
+# CONSTRUCT x4e600c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqadd/2@2
+# AUNIT --inst x4e600c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x1 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_sqadd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.284 SQDMLAL, SQDMLAL2 (by element) page C7-2646 line 154405 MATCH x5f003000/mask=xff00f400
+# CONSTRUCT x5f803000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 * &=+/2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3
+# AUNIT --inst x5f803000/mask=xffc0f400 --status fail --comment "nointsat"
+# scalar variant, size == 10 (always part == 0)
+
+:sqdmlal Rd_FPR64, Rn_FPR32, Re_VPR128.S.vIndex
+is b_2431=0b01011111 & b_2223=0b10 & b_1215=0b0011 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rd_FPR64 & Rn_FPR32 & Zd
+{
+ local tmp1:8 = sext(Rn_FPR32);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp2:4 = Re_VPR128.S.vIndex;
+ local tmp3:8 = sext(tmp2);
+ local tmp4:8 = tmp1 * tmp3;
+ local tmp5:8 = tmp4 * 2:8;
+ Rd_FPR64 = Rd_FPR64 + tmp5;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.284 SQDMLAL, SQDMLAL2 (by element) page C7-2646 line 154405 MATCH x5f003000/mask=xff00f400
+# CONSTRUCT x5f403000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG3 sext:4 ARG2 sext:4 * 2:4 * &=+
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3
+# AUNIT --inst x5f403000/mask=xffc0f400 --status fail --comment "nointsat"
+# scalar variant, size == 01 (always part == 0)
+
+:sqdmlal Rd_FPR32, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM
+is b_2431=0b01011111 & b_2223=0b01 & b_1215=0b0011 & b_10=0 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Rd_FPR32 & Rn_FPR16 & Zd
+{
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp1:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp2:4 = sext(tmp1);
+ local tmp3:4 = sext(Rn_FPR16);
+ local tmp4:4 = tmp2 * tmp3;
+ local tmp5:4 = tmp4 * 2:4;
+ Rd_FPR32 = Rd_FPR32 + tmp5;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.284 SQDMLAL, SQDMLAL2 (by element) page C7-2646 line 154405 MATCH x0f003000/mask=xbf00f400
+# CONSTRUCT x0f803000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* 2:8 $* &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3@4
+# AUNIT --inst x0f803000/mask=xffc0f400 --status fail --comment "ext nointsat"
+# vector variant, Q == 0, size == 10
+
+:sqdmlal Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex
+is b_31=0 & b_30=0 & b_2429=0b001111 & b_2223=0b10 & b_1215=0b0011 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp2:4 = Re_VPR128.S.vIndex;
+ local tmp3:8 = sext(tmp2);
+ # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8
+ TMPQ2[0,64] = TMPQ1[0,64] * tmp3;
+ TMPQ2[64,64] = TMPQ1[64,64] * tmp3;
+ # simd infix TMPQ3 = TMPQ2 * 2:8 on lane size 8
+ TMPQ3[0,64] = TMPQ2[0,64] * 2:8;
+ TMPQ3[64,64] = TMPQ2[64,64] * 2:8;
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ3 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ3[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ3[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.284 SQDMLAL, SQDMLAL2 (by element) page C7-2646 line 154405 MATCH x0f003000/mask=xbf00f400
+# CONSTRUCT x0f403000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* 2:4 $* &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3@2
+# AUNIT --inst x0f403000/mask=xffc0f400 --status fail --comment "ext nointsat"
+# vector variant, Q = 0, size == 01
+
+:sqdmlal Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
+is b_31=0 & b_30=0 & b_2429=0b001111 & b_2223=0b01 & b_1215=0b0011 & b_10=0 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp3:4 = sext(tmp2);
+ # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4
+ TMPQ2[0,32] = TMPQ1[0,32] * tmp3;
+ TMPQ2[32,32] = TMPQ1[32,32] * tmp3;
+ TMPQ2[64,32] = TMPQ1[64,32] * tmp3;
+ TMPQ2[96,32] = TMPQ1[96,32] * tmp3;
+ # simd infix TMPQ3 = TMPQ2 * 2:4 on lane size 4
+ TMPQ3[0,32] = TMPQ2[0,32] * 2:4;
+ TMPQ3[32,32] = TMPQ2[32,32] * 2:4;
+ TMPQ3[64,32] = TMPQ2[64,32] * 2:4;
+ TMPQ3[96,32] = TMPQ2[96,32] * 2:4;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.284 SQDMLAL, SQDMLAL2 (by element) page C7-2646 line 154405 MATCH x0f003000/mask=xbf00f400
+# CONSTRUCT x4f803000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 sext:8 $* 2:8 $* &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal2/3@4
+# AUNIT --inst x4f803000/mask=xffc0f400 --status fail --comment "ext nointsat"
+# vector variant, Q = 1, size == 10
+
+:sqdmlal2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex
+is b_31=0 & b_30=1 & b_2429=0b001111 & b_2223=0b10 & b_1215=0b0011 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(TMPD1[0,32]);
+ TMPQ2[64,64] = sext(TMPD1[32,32]);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp3:4 = Re_VPR128.S.vIndex;
+ local tmp4:8 = sext(tmp3);
+ # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8
+ TMPQ3[0,64] = TMPQ2[0,64] * tmp4;
+ TMPQ3[64,64] = TMPQ2[64,64] * tmp4;
+ # simd infix TMPQ4 = TMPQ3 * 2:8 on lane size 8
+ TMPQ4[0,64] = TMPQ3[0,64] * 2:8;
+ TMPQ4[64,64] = TMPQ3[64,64] * 2:8;
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ4 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ4[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ4[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.284 SQDMLAL, SQDMLAL2 (by element) page C7-2646 line 154405 MATCH x0f003000/mask=xbf00f400
+# CONSTRUCT x4f403000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 sext:4 $* 2:4 $* &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal2/3@2
+# AUNIT --inst x4f403000/mask=xffc0f400 --status fail --comment "ext nointsat"
+# vector variant, Q = 1, size == 01
+
+:sqdmlal2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
+is b_31=0 & b_30=1 & b_2429=0b001111 & b_2223=0b01 & b_1215=0b0011 & b_10=0 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(TMPD1[0,16]);
+ TMPQ2[32,32] = sext(TMPD1[16,16]);
+ TMPQ2[64,32] = sext(TMPD1[32,16]);
+ TMPQ2[96,32] = sext(TMPD1[48,16]);
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp3:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp4:4 = sext(tmp3);
+ # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4
+ TMPQ3[0,32] = TMPQ2[0,32] * tmp4;
+ TMPQ3[32,32] = TMPQ2[32,32] * tmp4;
+ TMPQ3[64,32] = TMPQ2[64,32] * tmp4;
+ TMPQ3[96,32] = TMPQ2[96,32] * tmp4;
+ # simd infix TMPQ4 = TMPQ3 * 2:4 on lane size 4
+ TMPQ4[0,32] = TMPQ3[0,32] * 2:4;
+ TMPQ4[32,32] = TMPQ3[32,32] * 2:4;
+ TMPQ4[64,32] = TMPQ3[64,32] * 2:4;
+ TMPQ4[96,32] = TMPQ3[96,32] * 2:4;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ4 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ4[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ4[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ4[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ4[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.285 SQDMLAL, SQDMLAL2 (vector) page C7-2650 line 154623 MATCH x5e209000/mask=xff20fc00
+# CONSTRUCT x5ea09000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 * &=+
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3
+# AUNIT --inst x5ea09000/mask=xffe0fc00 --status fail --comment "nointsat"
+# scalar variant, size == 10 (always part == 0)
+
+:sqdmlal Rd_FPR64, Rn_FPR32, Rm_FPR32
+is b_2431=0b01011110 & b_2223=0b10 & b_21=1 & b_1015=0b100100 & Rd_FPR64 & Rn_FPR32 & Rm_FPR32 & Zd
+{
+ local tmp1:8 = sext(Rn_FPR32);
+ local tmp2:8 = sext(Rm_FPR32);
+ local tmp3:8 = tmp1 * tmp2;
+ local tmp4:8 = tmp3 * 2:8;
+ Rd_FPR64 = Rd_FPR64 + tmp4;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.285 SQDMLAL, SQDMLAL2 (vector) page C7-2650 line 154623 MATCH x5e209000/mask=xff20fc00
+# CONSTRUCT x5e609000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 * &=+
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3
+# AUNIT --inst x5e609000/mask=xffe0fc00 --status fail --comment "nointsat"
+# scalar variant, size == 01 (always part == 0)
+
+:sqdmlal Rd_FPR32, Rn_FPR16, Rm_FPR16
+is b_2431=0b01011110 & b_2223=0b01 & b_21=1 & b_1015=0b100100 & Rd_FPR32 & Rn_FPR16 & Rm_FPR16 & Zd
+{
+ local tmp1:4 = sext(Rn_FPR16);
+ local tmp2:4 = sext(Rm_FPR16);
+ local tmp3:4 = tmp1 * tmp2;
+ local tmp4:4 = tmp3 * 2:4;
+ Rd_FPR32 = Rd_FPR32 + tmp4;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.285 SQDMLAL, SQDMLAL2 (vector) page C7-2650 line 154623 MATCH x0e209000/mask=xbf20fc00
+# CONSTRUCT x0ea09000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 $*@8 2:8 $* &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3@4
+# AUNIT --inst x0ea09000/mask=xffe0fc00 --status fail --comment "ext nointsat"
+# vector variant, Q == 0, size == 10
+
+:sqdmlal Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
+is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_21=1 & b_1015=0b100100 & Rn_VPR64.2S & Rd_VPR128.2D & Rm_VPR64.2S & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);
+ TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);
+ # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 8
+ TMPQ3[0,64] = TMPQ1[0,64] * TMPQ2[0,64];
+ TMPQ3[64,64] = TMPQ1[64,64] * TMPQ2[64,64];
+ # simd infix TMPQ4 = TMPQ3 * 2:8 on lane size 8
+ TMPQ4[0,64] = TMPQ3[0,64] * 2:8;
+ TMPQ4[64,64] = TMPQ3[64,64] * 2:8;
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ4 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ4[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ4[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.285 SQDMLAL, SQDMLAL2 (vector) page C7-2650 line 154623 MATCH x0e209000/mask=xbf20fc00
+# CONSTRUCT x0e609000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 $*@4 2:4 $* &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal/3@2
+# AUNIT --inst x0e609000/mask=xffe0fc00 --status fail --comment "ext nointsat"
+# vector variant, Q = 0, size == 01
+
+:sqdmlal Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_21=1 & b_1015=0b100100 & Rn_VPR64.4H & Rd_VPR128.4S & Rm_VPR64.4H & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);
+ TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);
+ TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);
+ TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);
+ # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 4
+ TMPQ3[0,32] = TMPQ1[0,32] * TMPQ2[0,32];
+ TMPQ3[32,32] = TMPQ1[32,32] * TMPQ2[32,32];
+ TMPQ3[64,32] = TMPQ1[64,32] * TMPQ2[64,32];
+ TMPQ3[96,32] = TMPQ1[96,32] * TMPQ2[96,32];
+ # simd infix TMPQ4 = TMPQ3 * 2:4 on lane size 4
+ TMPQ4[0,32] = TMPQ3[0,32] * 2:4;
+ TMPQ4[32,32] = TMPQ3[32,32] * 2:4;
+ TMPQ4[64,32] = TMPQ3[64,32] * 2:4;
+ TMPQ4[96,32] = TMPQ3[96,32] * 2:4;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ4 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ4[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ4[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ4[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ4[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.285 SQDMLAL, SQDMLAL2 (vector) page C7-2650 line 154623 MATCH x0e209000/mask=xbf20fc00
+# CONSTRUCT x4ea09000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $*@8 2:8 $* &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal2/3@4
+# AUNIT --inst x4ea09000/mask=xffe0fc00 --status fail --comment "ext nointsat"
+# vector variant, Q = 1, size == 10
+
+:sqdmlal2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
+is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_21=1 & b_1015=0b100100 & Rn_VPR128.4S & Rd_VPR128.2D & Rm_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(TMPD1[0,32]);
+ TMPQ2[64,64] = sext(TMPD1[32,32]);
+ TMPD3 = Rm_VPR128.4S[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)
+ TMPQ4[0,64] = sext(TMPD3[0,32]);
+ TMPQ4[64,64] = sext(TMPD3[32,32]);
+ # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8
+ TMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64];
+ TMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64];
+ # simd infix TMPQ6 = TMPQ5 * 2:8 on lane size 8
+ TMPQ6[0,64] = TMPQ5[0,64] * 2:8;
+ TMPQ6[64,64] = TMPQ5[64,64] * 2:8;
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ6 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ6[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ6[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.285 SQDMLAL, SQDMLAL2 (vector) page C7-2650 line 154623 MATCH x0e209000/mask=xbf20fc00
+# CONSTRUCT x4e609000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $*@4 2:4 $* &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlal2/3@2
+# AUNIT --inst x4e609000/mask=xffe0fc00 --status fail --comment "ext nointsat"
+# vector variant, Q = 1, size == 01
+
+:sqdmlal2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_21=1 & b_1015=0b100100 & Rn_VPR128.8H & Rd_VPR128.4S & Rm_VPR128.8H & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(TMPD1[0,16]);
+ TMPQ2[32,32] = sext(TMPD1[16,16]);
+ TMPQ2[64,32] = sext(TMPD1[32,16]);
+ TMPQ2[96,32] = sext(TMPD1[48,16]);
+ TMPD3 = Rm_VPR128.8H[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)
+ TMPQ4[0,32] = sext(TMPD3[0,16]);
+ TMPQ4[32,32] = sext(TMPD3[16,16]);
+ TMPQ4[64,32] = sext(TMPD3[32,16]);
+ TMPQ4[96,32] = sext(TMPD3[48,16]);
+ # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4
+ TMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32];
+ TMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32];
+ TMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32];
+ TMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32];
+ # simd infix TMPQ6 = TMPQ5 * 2:4 on lane size 4
+ TMPQ6[0,32] = TMPQ5[0,32] * 2:4;
+ TMPQ6[32,32] = TMPQ5[32,32] * 2:4;
+ TMPQ6[64,32] = TMPQ5[64,32] * 2:4;
+ TMPQ6[96,32] = TMPQ5[96,32] * 2:4;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ6 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ6[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ6[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ6[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ6[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.286 SQDMLSL, SQDMLSL2 (by element) page C7-2653 line 154796 MATCH x5f007000/mask=xff00f400
+# CONSTRUCT x5f807000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 * &=-
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3
+# AUNIT --inst x5f807000/mask=xffc0f400 --status fail --comment "nointsat"
+# scalar variant, size == 10 (always part == 0)
+
+:sqdmlsl Rd_FPR64, Rn_FPR32, Re_VPR128.S.vIndex
+is b_2431=0b01011111 & b_2223=0b10 & b_1215=0b0111 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rd_FPR64 & Rn_FPR32 & Zd
+{
+ local tmp1:8 = sext(Rn_FPR32);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp2:4 = Re_VPR128.S.vIndex;
+ local tmp3:8 = sext(tmp2);
+ local tmp4:8 = tmp1 * tmp3;
+ local tmp5:8 = tmp4 * 2:8;
+ Rd_FPR64 = Rd_FPR64 - tmp5;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.286 SQDMLSL, SQDMLSL2 (by element) page C7-2653 line 154796 MATCH x5f007000/mask=xff00f400
+# CONSTRUCT x5f407000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 * &=-
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3
+# AUNIT --inst x5f407000/mask=xffc0f400 --status fail --comment "nointsat"
+# scalar variant, size == 01 (always part == 0)
+
+:sqdmlsl Rd_FPR32, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM
+is b_2431=0b01011111 & b_2223=0b01 & b_1215=0b0111 & b_10=0 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Rd_FPR32 & Rn_FPR16 & Zd
+{
+ local tmp1:4 = sext(Rn_FPR16);
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp3:4 = sext(tmp2);
+ local tmp4:4 = tmp1 * tmp3;
+ local tmp5:4 = tmp4 * 2:4;
+ Rd_FPR32 = Rd_FPR32 - tmp5;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.286 SQDMLSL, SQDMLSL2 (by element) page C7-2653 line 154796 MATCH x0f007000/mask=xbf00f400
+# CONSTRUCT x0f807000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* 2:8 $* &=$-@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3@4
+# AUNIT --inst x0f807000/mask=xffc0f400 --status fail --comment "ext nointsat"
+# vector variant, Q == 0, size == 10
+
+:sqdmlsl Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex
+is b_31=0 & b_30=0 & b_2429=0b001111 & b_2223=0b10 & b_1215=0b0111 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp2:4 = Re_VPR128.S.vIndex;
+ local tmp3:8 = sext(tmp2);
+ # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8
+ TMPQ2[0,64] = TMPQ1[0,64] * tmp3;
+ TMPQ2[64,64] = TMPQ1[64,64] * tmp3;
+ # simd infix TMPQ3 = TMPQ2 * 2:8 on lane size 8
+ TMPQ3[0,64] = TMPQ2[0,64] * 2:8;
+ TMPQ3[64,64] = TMPQ2[64,64] * 2:8;
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ3 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ3[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ3[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.286 SQDMLSL, SQDMLSL2 (by element) page C7-2653 line 154796 MATCH x0f007000/mask=xbf00f400
+# CONSTRUCT x0f407000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* 2:4 $* &=$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3@2
+# AUNIT --inst x0f407000/mask=xffc0f400 --status fail --comment "ext nointsat"
+# vector variant, Q = 0, size == 01
+
+:sqdmlsl Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
+is b_31=0 & b_30=0 & b_2429=0b001111 & b_2223=0b01 & b_1215=0b0111 & b_10=0 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp3:4 = sext(tmp2);
+ # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4
+ TMPQ2[0,32] = TMPQ1[0,32] * tmp3;
+ TMPQ2[32,32] = TMPQ1[32,32] * tmp3;
+ TMPQ2[64,32] = TMPQ1[64,32] * tmp3;
+ TMPQ2[96,32] = TMPQ1[96,32] * tmp3;
+ # simd infix TMPQ3 = TMPQ2 * 2:4 on lane size 4
+ TMPQ3[0,32] = TMPQ2[0,32] * 2:4;
+ TMPQ3[32,32] = TMPQ2[32,32] * 2:4;
+ TMPQ3[64,32] = TMPQ2[64,32] * 2:4;
+ TMPQ3[96,32] = TMPQ2[96,32] * 2:4;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.286 SQDMLSL, SQDMLSL2 (by element) page C7-2653 line 154796 MATCH x0f007000/mask=xbf00f400
+# CONSTRUCT x4f807000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 sext:8 $* 2:8 $* &=$-@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl2/3@4
+# AUNIT --inst x4f807000/mask=xffc0f400 --status fail --comment "ext nointsat"
+# vector variant, Q = 1, size == 10
+
+:sqdmlsl2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex
+is b_31=0 & b_30=1 & b_2429=0b001111 & b_2223=0b10 & b_1215=0b0111 & b_10=0 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(TMPD1[0,32]);
+ TMPQ2[64,64] = sext(TMPD1[32,32]);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp3:4 = Re_VPR128.S.vIndex;
+ local tmp4:8 = sext(tmp3);
+ # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8
+ TMPQ3[0,64] = TMPQ2[0,64] * tmp4;
+ TMPQ3[64,64] = TMPQ2[64,64] * tmp4;
+ # simd infix TMPQ4 = TMPQ3 * 2:8 on lane size 8
+ TMPQ4[0,64] = TMPQ3[0,64] * 2:8;
+ TMPQ4[64,64] = TMPQ3[64,64] * 2:8;
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ4 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ4[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ4[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.286 SQDMLSL, SQDMLSL2 (by element) page C7-2653 line 154796 MATCH x0f007000/mask=xbf00f400
+# CONSTRUCT x4f407000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 sext:4 $* 2:4 $* &=$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl2/3@2
+# AUNIT --inst x4f407000/mask=xffc0f400 --status fail --comment "ext nointsat"
+# vector variant, Q = 1, size == 01
+
+:sqdmlsl2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
+is b_31=0 & b_30=1 & b_2429=0b001111 & b_2223=0b01 & b_1215=0b0111 & b_10=0 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(TMPD1[0,16]);
+ TMPQ2[32,32] = sext(TMPD1[16,16]);
+ TMPQ2[64,32] = sext(TMPD1[32,16]);
+ TMPQ2[96,32] = sext(TMPD1[48,16]);
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp3:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp4:4 = sext(tmp3);
+ # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4
+ TMPQ3[0,32] = TMPQ2[0,32] * tmp4;
+ TMPQ3[32,32] = TMPQ2[32,32] * tmp4;
+ TMPQ3[64,32] = TMPQ2[64,32] * tmp4;
+ TMPQ3[96,32] = TMPQ2[96,32] * tmp4;
+ # simd infix TMPQ4 = TMPQ3 * 2:4 on lane size 4
+ TMPQ4[0,32] = TMPQ3[0,32] * 2:4;
+ TMPQ4[32,32] = TMPQ3[32,32] * 2:4;
+ TMPQ4[64,32] = TMPQ3[64,32] * 2:4;
+ TMPQ4[96,32] = TMPQ3[96,32] * 2:4;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ4 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ4[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ4[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ4[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ4[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.287 SQDMLSL, SQDMLSL2 (vector) page C7-2657 line 155015 MATCH x5e20b000/mask=xff20fc00
+# CONSTRUCT x5ea0b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 * &=-
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3
+# AUNIT --inst x5ea0b000/mask=xffe0fc00 --status fail --comment "nointsat"
+# scalar variant, size == 10 (always part == 0)
+
+:sqdmlsl Rd_FPR64, Rn_FPR32, Rm_FPR32
+is b_2431=0b01011110 & b_2223=0b10 & b_21=1 & b_1015=0b101100 & Rd_FPR64 & Rn_FPR32 & Rm_FPR32 & Zd
+{
+ local tmp1:8 = sext(Rn_FPR32);
+ local tmp2:8 = sext(Rm_FPR32);
+ local tmp3:8 = tmp1 * tmp2;
+ local tmp4:8 = tmp3 * 2:8;
+ Rd_FPR64 = Rd_FPR64 - tmp4;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.287 SQDMLSL, SQDMLSL2 (vector) page C7-2657 line 155015 MATCH x5e20b000/mask=xff20fc00
+# CONSTRUCT x5e60b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 * &=-
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3
+# AUNIT --inst x5e60b000/mask=xffe0fc00 --status fail --comment "nointsat"
+# scalar variant, size == 01 (always part == 0)
+
+:sqdmlsl Rd_FPR32, Rn_FPR16, Rm_FPR16
+is b_2431=0b01011110 & b_2223=0b01 & b_21=1 & b_1015=0b101100 & Rd_FPR32 & Rn_FPR16 & Rm_FPR16 & Zd
+{
+ local tmp1:4 = sext(Rn_FPR16);
+ local tmp2:4 = sext(Rm_FPR16);
+ local tmp3:4 = tmp1 * tmp2;
+ local tmp4:4 = tmp3 * 2:4;
+ Rd_FPR32 = Rd_FPR32 - tmp4;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.287 SQDMLSL, SQDMLSL2 (vector) page C7-2657 line 155015 MATCH x0e20b000/mask=xbf20fc00
+# CONSTRUCT x0ea0b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 $*@8 2:8 $* &=$-@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3
+# AUNIT --inst x0ea0b000/mask=xffe0fc00 --status fail --comment "ext nointsat"
+# vector variant, Q == 0, size == 10
+
+:sqdmlsl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
+is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_21=1 & b_1015=0b101100 & Rn_VPR64.2S & Rd_VPR128.2D & Rm_VPR64.2S & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);
+ TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);
+ # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 8
+ TMPQ3[0,64] = TMPQ1[0,64] * TMPQ2[0,64];
+ TMPQ3[64,64] = TMPQ1[64,64] * TMPQ2[64,64];
+ # simd infix TMPQ4 = TMPQ3 * 2:8 on lane size 8
+ TMPQ4[0,64] = TMPQ3[0,64] * 2:8;
+ TMPQ4[64,64] = TMPQ3[64,64] * 2:8;
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ4 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ4[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ4[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.287 SQDMLSL, SQDMLSL2 (vector) page C7-2657 line 155015 MATCH x0e20b000/mask=xbf20fc00
+# CONSTRUCT x0e60b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 $*@4 2:4 $* &=$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3@2
+# AUNIT --inst x0e60b000/mask=xffe0fc00 --status fail --comment "ext nointsat"
+# vector variant, Q = 0, size == 01
+
+:sqdmlsl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
+is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_21=1 & b_1015=0b101100 & Rn_VPR64.4H & Rd_VPR128.4S & Rm_VPR64.4H & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);
+ TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);
+ TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);
+ TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);
+ # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 4
+ TMPQ3[0,32] = TMPQ1[0,32] * TMPQ2[0,32];
+ TMPQ3[32,32] = TMPQ1[32,32] * TMPQ2[32,32];
+ TMPQ3[64,32] = TMPQ1[64,32] * TMPQ2[64,32];
+ TMPQ3[96,32] = TMPQ1[96,32] * TMPQ2[96,32];
+ # simd infix TMPQ4 = TMPQ3 * 2:4 on lane size 4
+ TMPQ4[0,32] = TMPQ3[0,32] * 2:4;
+ TMPQ4[32,32] = TMPQ3[32,32] * 2:4;
+ TMPQ4[64,32] = TMPQ3[64,32] * 2:4;
+ TMPQ4[96,32] = TMPQ3[96,32] * 2:4;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ4 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ4[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ4[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ4[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ4[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.287 SQDMLSL, SQDMLSL2 (vector) page C7-2657 line 155015 MATCH x0e20b000/mask=xbf20fc00
+# CONSTRUCT x4ea0b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $*@8 2:8 $* &=$-@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl2/3@4
+# AUNIT --inst x4ea0b000/mask=xffe0fc00 --status fail --comment "ext nointsat"
+# vector variant, Q = 1, size == 10
+
+:sqdmlsl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
+is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_21=1 & b_1015=0b101100 & Rn_VPR128.4S & Rd_VPR128.2D & Rm_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(TMPD1[0,32]);
+ TMPQ2[64,64] = sext(TMPD1[32,32]);
+ TMPD3 = Rm_VPR128.4S[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)
+ TMPQ4[0,64] = sext(TMPD3[0,32]);
+ TMPQ4[64,64] = sext(TMPD3[32,32]);
+ # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8
+ TMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64];
+ TMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64];
+ # simd infix TMPQ6 = TMPQ5 * 2:8 on lane size 8
+ TMPQ6[0,64] = TMPQ5[0,64] * 2:8;
+ TMPQ6[64,64] = TMPQ5[64,64] * 2:8;
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ6 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ6[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ6[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.287 SQDMLSL, SQDMLSL2 (vector) page C7-2657 line 155015 MATCH x0e20b000/mask=xbf20fc00
+# CONSTRUCT x4e60b000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $*@4 2:4 $* &=$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl2/3@2
+# AUNIT --inst x4e60b000/mask=xffe0fc00 --status fail --comment "ext nointsat"
+# vector variant, Q = 1, size == 01
+
+:sqdmlsl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
+is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_21=1 & b_1015=0b101100 & Rn_VPR128.8H & Rd_VPR128.4S & Rm_VPR128.8H & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(TMPD1[0,16]);
+ TMPQ2[32,32] = sext(TMPD1[16,16]);
+ TMPQ2[64,32] = sext(TMPD1[32,16]);
+ TMPQ2[96,32] = sext(TMPD1[48,16]);
+ TMPD3 = Rm_VPR128.8H[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)
+ TMPQ4[0,32] = sext(TMPD3[0,16]);
+ TMPQ4[32,32] = sext(TMPD3[16,16]);
+ TMPQ4[64,32] = sext(TMPD3[32,16]);
+ TMPQ4[96,32] = sext(TMPD3[48,16]);
+ # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4
+ TMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32];
+ TMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32];
+ TMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32];
+ TMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32];
+ # simd infix TMPQ6 = TMPQ5 * 2:4 on lane size 4
+ TMPQ6[0,32] = TMPQ5[0,32] * 2:4;
+ TMPQ6[32,32] = TMPQ5[32,32] * 2:4;
+ TMPQ6[64,32] = TMPQ5[64,32] * 2:4;
+ TMPQ6[96,32] = TMPQ5[96,32] * 2:4;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ6 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ6[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ6[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ6[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ6[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.288 SQDMULH (by element) page C7-2660 line 155188 MATCH x0f00c000/mask=xbf00f400
+# CONSTRUCT x0f80c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* 2:8 $* &=$shuffle@1-0@3-1:4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_sqdmlsl/3@4
+# AUNIT --inst x0f80c000/mask=xffc0f400 --status pass --comment "ext nointsat"
+
+:sqdmulh Rd_VPR64.2S, Rn_VPR64.2S, Re_VPR128.S.vIndex
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xc & b_1010=0 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp2:4 = Re_VPR128.S.vIndex;
+ local tmp3:8 = sext(tmp2);
+ # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8
+ TMPQ2[0,64] = TMPQ1[0,64] * tmp3;
+ TMPQ2[64,64] = TMPQ1[64,64] * tmp3;
+ # simd infix TMPQ3 = TMPQ2 * 2:8 on lane size 8
+ TMPQ3[0,64] = TMPQ2[0,64] * 2:8;
+ TMPQ3[64,64] = TMPQ2[64,64] * 2:8;
+ # simd shuffle Rd_VPR64.2S = TMPQ3 (@1-0@3-1) lane size 4
+ Rd_VPR64.2S[0,32] = TMPQ3[32,32];
+ Rd_VPR64.2S[32,32] = TMPQ3[96,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.288 SQDMULH (by element) page C7-2660 line 155188 MATCH x0f00c000/mask=xbf00f400
+# CONSTRUCT x0f40c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* 2:4 $* &=$shuffle@1-0@3-1@5-2@7-3:2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@2
+# AUNIT --inst x0f40c000/mask=xffc0f400 --status pass --comment "ext nointsat"
+
+:sqdmulh Rd_VPR64.4H, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xc & b_1010=0 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp3:4 = sext(tmp2);
+ # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4
+ TMPQ2[0,32] = TMPQ1[0,32] * tmp3;
+ TMPQ2[32,32] = TMPQ1[32,32] * tmp3;
+ TMPQ2[64,32] = TMPQ1[64,32] * tmp3;
+ TMPQ2[96,32] = TMPQ1[96,32] * tmp3;
+ # simd infix TMPQ3 = TMPQ2 * 2:4 on lane size 4
+ TMPQ3[0,32] = TMPQ2[0,32] * 2:4;
+ TMPQ3[32,32] = TMPQ2[32,32] * 2:4;
+ TMPQ3[64,32] = TMPQ2[64,32] * 2:4;
+ TMPQ3[96,32] = TMPQ2[96,32] * 2:4;
+ # simd shuffle Rd_VPR64.4H = TMPQ3 (@1-0@3-1@5-2@7-3) lane size 2
+ Rd_VPR64.4H[0,16] = TMPQ3[16,16];
+ Rd_VPR64.4H[16,16] = TMPQ3[48,16];
+ Rd_VPR64.4H[32,16] = TMPQ3[80,16];
+ Rd_VPR64.4H[48,16] = TMPQ3[112,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.288 SQDMULH (by element) page C7-2660 line 155188 MATCH x0f00c000/mask=xbf00f400
+# CONSTRUCT x4f80c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@4:32 ARG3 sext:8 $* 2:8 $* &=$shuffle@1-0@3-1@5-2@7-3:4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@4
+# AUNIT --inst x4f80c000/mask=xffc0f400 --status pass --comment "ext nointsat"
+
+:sqdmulh Rd_VPR128.4S, Rn_VPR128.4S, Re_VPR128.S.vIndex
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xc & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPZ1 = sext(Rn_VPR128.4S) (lane size 4 to 8)
+ TMPZ1[0,64] = sext(Rn_VPR128.4S[0,32]);
+ TMPZ1[64,64] = sext(Rn_VPR128.4S[32,32]);
+ TMPZ1[128,64] = sext(Rn_VPR128.4S[64,32]);
+ TMPZ1[192,64] = sext(Rn_VPR128.4S[96,32]);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp2:4 = Re_VPR128.S.vIndex;
+ local tmp3:8 = sext(tmp2);
+ # simd infix TMPZ2 = TMPZ1 * tmp3 on lane size 8
+ TMPZ2[0,64] = TMPZ1[0,64] * tmp3;
+ TMPZ2[64,64] = TMPZ1[64,64] * tmp3;
+ TMPZ2[128,64] = TMPZ1[128,64] * tmp3;
+ TMPZ2[192,64] = TMPZ1[192,64] * tmp3;
+ # simd infix TMPZ3 = TMPZ2 * 2:8 on lane size 8
+ TMPZ3[0,64] = TMPZ2[0,64] * 2:8;
+ TMPZ3[64,64] = TMPZ2[64,64] * 2:8;
+ TMPZ3[128,64] = TMPZ2[128,64] * 2:8;
+ TMPZ3[192,64] = TMPZ2[192,64] * 2:8;
+ # simd shuffle Rd_VPR128.4S = TMPZ3 (@1-0@3-1@5-2@7-3) lane size 4
+ Rd_VPR128.4S[0,32] = TMPZ3[32,32];
+ Rd_VPR128.4S[32,32] = TMPZ3[96,32];
+ Rd_VPR128.4S[64,32] = TMPZ3[160,32];
+ Rd_VPR128.4S[96,32] = TMPZ3[224,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.288 SQDMULH (by element) page C7-2660 line 155188 MATCH x0f00c000/mask=xbf00f400
+# CONSTRUCT x4f40c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@2:32 ARG3 sext:4 $* 2:4 $* &=$shuffle@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7:2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@2
+# AUNIT --inst x4f40c000/mask=xffc0f400 --status pass --comment "ext nointsat"
+
+:sqdmulh Rd_VPR128.8H, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xc & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ # simd resize TMPZ1 = sext(Rn_VPR128.8H) (lane size 2 to 4)
+ TMPZ1[0,32] = sext(Rn_VPR128.8H[0,16]);
+ TMPZ1[32,32] = sext(Rn_VPR128.8H[16,16]);
+ TMPZ1[64,32] = sext(Rn_VPR128.8H[32,16]);
+ TMPZ1[96,32] = sext(Rn_VPR128.8H[48,16]);
+ TMPZ1[128,32] = sext(Rn_VPR128.8H[64,16]);
+ TMPZ1[160,32] = sext(Rn_VPR128.8H[80,16]);
+ TMPZ1[192,32] = sext(Rn_VPR128.8H[96,16]);
+ TMPZ1[224,32] = sext(Rn_VPR128.8H[112,16]);
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp3:4 = sext(tmp2);
+ # simd infix TMPZ2 = TMPZ1 * tmp3 on lane size 4
+ TMPZ2[0,32] = TMPZ1[0,32] * tmp3;
+ TMPZ2[32,32] = TMPZ1[32,32] * tmp3;
+ TMPZ2[64,32] = TMPZ1[64,32] * tmp3;
+ TMPZ2[96,32] = TMPZ1[96,32] * tmp3;
+ TMPZ2[128,32] = TMPZ1[128,32] * tmp3;
+ TMPZ2[160,32] = TMPZ1[160,32] * tmp3;
+ TMPZ2[192,32] = TMPZ1[192,32] * tmp3;
+ TMPZ2[224,32] = TMPZ1[224,32] * tmp3;
+ # simd infix TMPZ3 = TMPZ2 * 2:4 on lane size 4
+ TMPZ3[0,32] = TMPZ2[0,32] * 2:4;
+ TMPZ3[32,32] = TMPZ2[32,32] * 2:4;
+ TMPZ3[64,32] = TMPZ2[64,32] * 2:4;
+ TMPZ3[96,32] = TMPZ2[96,32] * 2:4;
+ TMPZ3[128,32] = TMPZ2[128,32] * 2:4;
+ TMPZ3[160,32] = TMPZ2[160,32] * 2:4;
+ TMPZ3[192,32] = TMPZ2[192,32] * 2:4;
+ TMPZ3[224,32] = TMPZ2[224,32] * 2:4;
+ # simd shuffle Rd_VPR128.8H = TMPZ3 (@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7) lane size 2
+ Rd_VPR128.8H[0,16] = TMPZ3[16,16];
+ Rd_VPR128.8H[16,16] = TMPZ3[48,16];
+ Rd_VPR128.8H[32,16] = TMPZ3[80,16];
+ Rd_VPR128.8H[48,16] = TMPZ3[112,16];
+ Rd_VPR128.8H[64,16] = TMPZ3[144,16];
+ Rd_VPR128.8H[80,16] = TMPZ3[176,16];
+ Rd_VPR128.8H[96,16] = TMPZ3[208,16];
+ Rd_VPR128.8H[112,16] = TMPZ3[240,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.288 SQDMULH (by element) page C7-2660 line 155188 MATCH x5f00c000/mask=xff00f400
+# CONSTRUCT x5f40c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 * 16:1 >>:4 =
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2
+# AUNIT --inst x5f40c000/mask=xffc0f400 --status pass --comment "nointsat"
+# Scalar variant when size=01 suf=FPR16 elem=Re_VPR128Lo.H.vIndexHLM p1=Re_VPR128Lo.H p2=vIndexHLM
+
+:sqdmulh Rd_FPR16, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM
+is b_2431=0b01011111 & b_2223=0b01 & b_1215=0b1100 & b_10=0 & Rd_FPR16 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd
+{
+ local tmp1:4 = sext(Rn_FPR16);
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp3:4 = sext(tmp2);
+ local tmp4:4 = tmp1 * tmp3;
+ local tmp5:4 = tmp4 * 2:4;
+ local tmp6:4 = tmp5 >> 16:1;
+ Rd_FPR16 = tmp6:2;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.288 SQDMULH (by element) page C7-2660 line 155188 MATCH x5f00c000/mask=xff00f400
+# CONSTRUCT x5f80c000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 * 32:1 >>:8 =
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2
+# AUNIT --inst x5f80c000/mask=xffc0f400 --status pass --comment "nointsat"
+# Scalar variant when size=10 suf=FPR32 elem=Re_VPR128.S.vIndex p1=Re_VPR128.S p2=vIndex
+
+:sqdmulh Rd_FPR32, Rn_FPR32, Re_VPR128.S.vIndex
+is b_2431=0b01011111 & b_2223=0b10 & b_1215=0b1100 & b_10=0 & Rd_FPR32 & Rn_FPR32 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Zd
+{
+ local tmp1:8 = sext(Rn_FPR32);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp2:4 = Re_VPR128.S.vIndex;
+ local tmp3:8 = sext(tmp2);
+ local tmp4:8 = tmp1 * tmp3;
+ local tmp5:8 = tmp4 * 2:8;
+ local tmp6:8 = tmp5 >> 32:1;
+ Rd_FPR32 = tmp6:4;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.289 SQDMULH (vector) page C7-2663 line 155365 MATCH x5e20b400/mask=xff20fc00
+# CONSTRUCT x5e60b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2
+# AUNIT --inst x5e60b400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqdmulh Rd_FPR16, Rn_FPR16, Rm_FPR16
+is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x16 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_sqdmulh(Rn_FPR16, Rm_FPR16);
+}
+
+# C7.2.289 SQDMULH (vector) page C7-2663 line 155365 MATCH x5e20b400/mask=xff20fc00
+# CONSTRUCT x5ea0b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2
+# AUNIT --inst x5ea0b400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqdmulh Rd_FPR32, Rn_FPR32, Rm_FPR32
+is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x16 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_sqdmulh(Rn_FPR32, Rm_FPR32);
+}
+
+# C7.2.289 SQDMULH (vector) page C7-2663 line 155365 MATCH x0e20b400/mask=xbf20fc00
+# CONSTRUCT x0ea0b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@4
+# AUNIT --inst x0ea0b400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqdmulh Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x16 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_sqdmulh(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.289 SQDMULH (vector) page C7-2663 line 155365 MATCH x0e20b400/mask=xbf20fc00
+# CONSTRUCT x0e60b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@2
+# AUNIT --inst x0e60b400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqdmulh Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x16 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_sqdmulh(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.289 SQDMULH (vector) page C7-2663 line 155365 MATCH x0e20b400/mask=xbf20fc00
+# CONSTRUCT x4ea0b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@4
+# AUNIT --inst x4ea0b400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqdmulh Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x16 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sqdmulh(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.289 SQDMULH (vector) page C7-2663 line 155365 MATCH x0e20b400/mask=xbf20fc00
+# CONSTRUCT x4e60b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmulh/2@2
+# AUNIT --inst x4e60b400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqdmulh Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x16 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_sqdmulh(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.290 SQDMULL, SQDMULL2 (by element) page C7-2665 line 155494 MATCH x0f00b000/mask=xbf00f400
+# CONSTRUCT x0f80b000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@4:16 ARG3 sext:8 $* 2:8 =$*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2@4
+# AUNIT --inst x0f80b000/mask=xffc0f400 --status pass --comment "ext nointsat"
+
+:sqdmull Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xb & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp2:4 = Re_VPR128.S.vIndex;
+ local tmp3:8 = sext(tmp2);
+ # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8
+ TMPQ2[0,64] = TMPQ1[0,64] * tmp3;
+ TMPQ2[64,64] = TMPQ1[64,64] * tmp3;
+ # simd infix Rd_VPR128.2D = TMPQ2 * 2:8 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ2[0,64] * 2:8;
+ Rd_VPR128.2D[64,64] = TMPQ2[64,64] * 2:8;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.290 SQDMULL, SQDMULL2 (by element) page C7-2665 line 155494 MATCH x0f00b000/mask=xbf00f400
+# CONSTRUCT x4f80b000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 sext:8 $* 2:8 =$*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull2/2@4
+# AUNIT --inst x4f80b000/mask=xffc0f400 --status pass --comment "ext nointsat"
+
+:sqdmull2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xb & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(TMPD1[0,32]);
+ TMPQ2[64,64] = sext(TMPD1[32,32]);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp3:4 = Re_VPR128.S.vIndex;
+ local tmp4:8 = sext(tmp3);
+ # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8
+ TMPQ3[0,64] = TMPQ2[0,64] * tmp4;
+ TMPQ3[64,64] = TMPQ2[64,64] * tmp4;
+ # simd infix Rd_VPR128.2D = TMPQ3 * 2:8 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ3[0,64] * 2:8;
+ Rd_VPR128.2D[64,64] = TMPQ3[64,64] * 2:8;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.290 SQDMULL, SQDMULL2 (by element) page C7-2665 line 155494 MATCH x0f00b000/mask=xbf00f400
+# CONSTRUCT x0f40b000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@2:16 ARG3 sext:4 $* 2:4 =$*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull2/2@2
+# AUNIT --inst x0f40b000/mask=xffc0f400 --status pass --comment "ext nointsat"
+
+:sqdmull Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xb & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp3:4 = sext(tmp2);
+ # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4
+ TMPQ2[0,32] = TMPQ1[0,32] * tmp3;
+ TMPQ2[32,32] = TMPQ1[32,32] * tmp3;
+ TMPQ2[64,32] = TMPQ1[64,32] * tmp3;
+ TMPQ2[96,32] = TMPQ1[96,32] * tmp3;
+ # simd infix Rd_VPR128.4S = TMPQ2 * 2:4 on lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ2[0,32] * 2:4;
+ Rd_VPR128.4S[32,32] = TMPQ2[32,32] * 2:4;
+ Rd_VPR128.4S[64,32] = TMPQ2[64,32] * 2:4;
+ Rd_VPR128.4S[96,32] = TMPQ2[96,32] * 2:4;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.290 SQDMULL, SQDMULL2 (by element) page C7-2665 line 155494 MATCH x0f00b000/mask=xbf00f400
+# CONSTRUCT x4f40b000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 sext:4 $* 2:4 =$*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull2/2@2
+# AUNIT --inst x4f40b000/mask=xffc0f400 --status pass --comment "ext nointsat"
+
+:sqdmull2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xb & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(TMPD1[0,16]);
+ TMPQ2[32,32] = sext(TMPD1[16,16]);
+ TMPQ2[64,32] = sext(TMPD1[32,16]);
+ TMPQ2[96,32] = sext(TMPD1[48,16]);
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp3:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp4:4 = sext(tmp3);
+ # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4
+ TMPQ3[0,32] = TMPQ2[0,32] * tmp4;
+ TMPQ3[32,32] = TMPQ2[32,32] * tmp4;
+ TMPQ3[64,32] = TMPQ2[64,32] * tmp4;
+ TMPQ3[96,32] = TMPQ2[96,32] * tmp4;
+ # simd infix Rd_VPR128.4S = TMPQ3 * 2:4 on lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ3[0,32] * 2:4;
+ Rd_VPR128.4S[32,32] = TMPQ3[32,32] * 2:4;
+ Rd_VPR128.4S[64,32] = TMPQ3[64,32] * 2:4;
+ Rd_VPR128.4S[96,32] = TMPQ3[96,32] * 2:4;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.290 SQDMULL, SQDMULL2 (by element) page C7-2665 line 155494 MATCH x5f00b000/mask=xff00f400
+# CONSTRUCT x5f40b000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 =*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2
+# AUNIT --inst x5f40b000/mask=xffc0f400 --status pass --comment "nointsat"
+# Scalar variant when size=01 Va=FPR32 Vb=FPR16 elem=Re_VPR128Lo.H.vIndexHLM p1=Re_VPR128Lo.H p2=vIndexHLM
+
+:sqdmull Rd_FPR32, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM
+is b_2431=0b01011111 & b_2223=0b01 & b_1215=0b1011 & b_10=0 & Rd_FPR32 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd
+{
+ local tmp1:4 = sext(Rn_FPR16);
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp3:4 = sext(tmp2);
+ local tmp4:4 = tmp1 * tmp3;
+ Rd_FPR32 = tmp4 * 2:4;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.290 SQDMULL, SQDMULL2 (by element) page C7-2665 line 155494 MATCH x5f00b000/mask=xff00f400
+# CONSTRUCT x5f80b000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 =*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2
+# AUNIT --inst x5f80b000/mask=xffc0f400 --status pass --comment "nointsat"
+# Scalar variant when size=10 Va=FPR64 Vb=FPR32 elem=Re_VPR128.S.vIndex p1=Re_VPR128.S p2=vIndex
+
+:sqdmull Rd_FPR64, Rn_FPR32, Re_VPR128.S.vIndex
+is b_2431=0b01011111 & b_2223=0b10 & b_1215=0b1011 & b_10=0 & Rd_FPR64 & Rn_FPR32 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Zd
+{
+ local tmp1:8 = sext(Rn_FPR32);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp2:4 = Re_VPR128.S.vIndex;
+ local tmp3:8 = sext(tmp2);
+ local tmp4:8 = tmp1 * tmp3;
+ Rd_FPR64 = tmp4 * 2:8;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.291 SQDMULL, SQDMULL2 (vector) page C7-2668 line 155694 MATCH x0e20d000/mask=xbf20fc00
+# CONSTRUCT x4ea0d000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 $*@8 2:8 =$*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull2/2@4
+# AUNIT --inst x4ea0d000/mask=xffe0fc00 --status pass --comment "ext nointsat"
+
+:sqdmull2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0xd & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(TMPD1[0,32]);
+ TMPQ2[64,64] = sext(TMPD1[32,32]);
+ TMPD3 = Rm_VPR128.4S[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)
+ TMPQ4[0,64] = sext(TMPD3[0,32]);
+ TMPQ4[64,64] = sext(TMPD3[32,32]);
+ # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8
+ TMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64];
+ TMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64];
+ # simd infix Rd_VPR128.2D = TMPQ5 * 2:8 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ5[0,64] * 2:8;
+ Rd_VPR128.2D[64,64] = TMPQ5[64,64] * 2:8;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.291 SQDMULL, SQDMULL2 (vector) page C7-2668 line 155694 MATCH x0e20d000/mask=xbf20fc00
+# CONSTRUCT x4e60d000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 $*@4 2:4 =$*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull2/2@2
+# AUNIT --inst x4e60d000/mask=xffe0fc00 --status pass --comment "ext nointsat"
+
+:sqdmull2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0xd & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(TMPD1[0,16]);
+ TMPQ2[32,32] = sext(TMPD1[16,16]);
+ TMPQ2[64,32] = sext(TMPD1[32,16]);
+ TMPQ2[96,32] = sext(TMPD1[48,16]);
+ TMPD3 = Rm_VPR128.8H[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)
+ TMPQ4[0,32] = sext(TMPD3[0,16]);
+ TMPQ4[32,32] = sext(TMPD3[16,16]);
+ TMPQ4[64,32] = sext(TMPD3[32,16]);
+ TMPQ4[96,32] = sext(TMPD3[48,16]);
+ # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4
+ TMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32];
+ TMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32];
+ TMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32];
+ TMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32];
+ # simd infix Rd_VPR128.4S = TMPQ5 * 2:4 on lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ5[0,32] * 2:4;
+ Rd_VPR128.4S[32,32] = TMPQ5[32,32] * 2:4;
+ Rd_VPR128.4S[64,32] = TMPQ5[64,32] * 2:4;
+ Rd_VPR128.4S[96,32] = TMPQ5[96,32] * 2:4;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.291 SQDMULL, SQDMULL2 (vector) page C7-2668 line 155694 MATCH x0e20d000/mask=xbf20fc00
+# CONSTRUCT x0ea0d000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2@4
+# AUNIT --inst x0ea0d000/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqdmull Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0xd & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_sqdmull(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.291 SQDMULL, SQDMULL2 (vector) page C7-2668 line 155694 MATCH x0e20d000/mask=xbf20fc00
+# CONSTRUCT x0e60d000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2@2
+# AUNIT --inst x0e60d000/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqdmull Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0xd & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sqdmull(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.291 SQDMULL, SQDMULL2 (vector) page C7-2668 line 155694 MATCH x5e20d000/mask=xff20fc00
+# CONSTRUCT x5e60d000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 sext:4 ARG3 sext:4 * 2:4 =*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2
+# AUNIT --inst x5e60d000/mask=xffe0fc00 --status pass --comment "nointsat"
+# Scalar variant when size=01 Va=FPR32 Vb=FPR16
+
+:sqdmull Rd_FPR32, Rn_FPR16, Rm_FPR16
+is b_2431=0b01011110 & b_2223=0b01 & b_21=1 & b_1015=0b110100 & Rd_FPR32 & Rn_FPR16 & Rm_FPR16 & Zd
+{
+ local tmp1:4 = sext(Rn_FPR16);
+ local tmp2:4 = sext(Rm_FPR16);
+ local tmp3:4 = tmp1 * tmp2;
+ Rd_FPR32 = tmp3 * 2:4;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.291 SQDMULL, SQDMULL2 (vector) page C7-2668 line 155694 MATCH x5e20d000/mask=xff20fc00
+# CONSTRUCT x5ea0d000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 =*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqdmull/2
+# AUNIT --inst x5ea0d000/mask=xffe0fc00 --status pass --comment "nointsat"
+# Scalar variant when size=10 Va=FPR64 Vb=FPR32
+
+:sqdmull Rd_FPR64, Rn_FPR32, Rm_FPR32
+is b_2431=0b01011110 & b_2223=0b10 & b_21=1 & b_1015=0b110100 & Rd_FPR64 & Rn_FPR32 & Rm_FPR32 & Zd
+{
+ local tmp1:8 = sext(Rn_FPR32);
+ local tmp2:8 = sext(Rm_FPR32);
+ local tmp3:8 = tmp1 * tmp2;
+ Rd_FPR64 = tmp3 * 2:8;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x7e207800/mask=xff3ffc00
+# CONSTRUCT x7e207800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =2comp
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1
+# AUNIT --inst x7e207800/mask=xfffffc00 --status pass --comment "nointsat"
+# Scalar variant when size=00 Q=1 aa=1 suf=FPR8
+
+:sqneg Rd_FPR8, Rn_FPR8
+is b_31=0 & Q=1 & b_2429=0b111110 & b_2223=0b00 & b_1021=0b100000011110 & Rd_FPR8 & Rn_FPR8 & Zd
+{
+ Rd_FPR8 = - Rn_FPR8;
+ zext_zb(Zd); # zero upper 31 bytes of Zd
+}
+
+# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x7e207800/mask=xff3ffc00
+# CONSTRUCT x7e607800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =2comp
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1
+# AUNIT --inst x7e607800/mask=xfffffc00 --status pass --comment "nointsat"
+# Scalar variant when size=01 Q=1 aa=1 suf=FPR16
+
+:sqneg Rd_FPR16, Rn_FPR16
+is b_31=0 & Q=1 & b_2429=0b111110 & b_2223=0b01 & b_1021=0b100000011110 & Rd_FPR16 & Rn_FPR16 & Zd
+{
+ Rd_FPR16 = - Rn_FPR16;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x7e207800/mask=xff3ffc00
+# CONSTRUCT x7ea07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =2comp
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1
+# AUNIT --inst x7ea07800/mask=xfffffc00 --status pass --comment "nointsat"
+# Scalar variant when size=10 Q=1 aa=1 suf=FPR32
+
+:sqneg Rd_FPR32, Rn_FPR32
+is b_31=0 & Q=1 & b_2429=0b111110 & b_2223=0b10 & b_1021=0b100000011110 & Rd_FPR32 & Rn_FPR32 & Zd
+{
+ Rd_FPR32 = - Rn_FPR32;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x7e207800/mask=xff3ffc00
+# CONSTRUCT x7ee07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =2comp
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1
+# AUNIT --inst x7ee07800/mask=xfffffc00 --status pass --comment "nointsat"
+# Scalar variant when size=11 Q=1 aa=1 suf=FPR64
+
+:sqneg Rd_FPR64, Rn_FPR64
+is b_31=0 & Q=1 & b_2429=0b111110 & b_2223=0b11 & b_1021=0b100000011110 & Rd_FPR64 & Rn_FPR64 & Zd
+{
+ Rd_FPR64 = - Rn_FPR64;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x2e207800/mask=xbf3ffc00
+# CONSTRUCT x2e207800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$2comp@1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@1
+# AUNIT --inst x2e207800/mask=xfffffc00 --status fail --comment "nointsat"
+# Vector variant when when size = 00 , Q = 0 aa=0 esize=1 suf=VPR64.8B
+
+:sqneg Rd_VPR64.8B, Rn_VPR64.8B
+is b_31=0 & Q=0 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000011110 & Rd_VPR64.8B & Rn_VPR64.8B & Zd
+{
+ # simd unary Rd_VPR64.8B = -(Rn_VPR64.8B) on lane size 1
+ Rd_VPR64.8B[0,8] = -(Rn_VPR64.8B[0,8]);
+ Rd_VPR64.8B[8,8] = -(Rn_VPR64.8B[8,8]);
+ Rd_VPR64.8B[16,8] = -(Rn_VPR64.8B[16,8]);
+ Rd_VPR64.8B[24,8] = -(Rn_VPR64.8B[24,8]);
+ Rd_VPR64.8B[32,8] = -(Rn_VPR64.8B[32,8]);
+ Rd_VPR64.8B[40,8] = -(Rn_VPR64.8B[40,8]);
+ Rd_VPR64.8B[48,8] = -(Rn_VPR64.8B[48,8]);
+ Rd_VPR64.8B[56,8] = -(Rn_VPR64.8B[56,8]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x2e207800/mask=xbf3ffc00
+# CONSTRUCT x6e207800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$2comp@1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@1
+# AUNIT --inst x6e207800/mask=xfffffc00 --status fail --comment "nointsat"
+# Vector variant when when size = 00 , Q = 1 aa=0 esize=1 suf=VPR128.16B
+
+:sqneg Rd_VPR128.16B, Rn_VPR128.16B
+is b_31=0 & Q=1 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000011110 & Rd_VPR128.16B & Rn_VPR128.16B & Zd
+{
+ # simd unary Rd_VPR128.16B = -(Rn_VPR128.16B) on lane size 1
+ Rd_VPR128.16B[0,8] = -(Rn_VPR128.16B[0,8]);
+ Rd_VPR128.16B[8,8] = -(Rn_VPR128.16B[8,8]);
+ Rd_VPR128.16B[16,8] = -(Rn_VPR128.16B[16,8]);
+ Rd_VPR128.16B[24,8] = -(Rn_VPR128.16B[24,8]);
+ Rd_VPR128.16B[32,8] = -(Rn_VPR128.16B[32,8]);
+ Rd_VPR128.16B[40,8] = -(Rn_VPR128.16B[40,8]);
+ Rd_VPR128.16B[48,8] = -(Rn_VPR128.16B[48,8]);
+ Rd_VPR128.16B[56,8] = -(Rn_VPR128.16B[56,8]);
+ Rd_VPR128.16B[64,8] = -(Rn_VPR128.16B[64,8]);
+ Rd_VPR128.16B[72,8] = -(Rn_VPR128.16B[72,8]);
+ Rd_VPR128.16B[80,8] = -(Rn_VPR128.16B[80,8]);
+ Rd_VPR128.16B[88,8] = -(Rn_VPR128.16B[88,8]);
+ Rd_VPR128.16B[96,8] = -(Rn_VPR128.16B[96,8]);
+ Rd_VPR128.16B[104,8] = -(Rn_VPR128.16B[104,8]);
+ Rd_VPR128.16B[112,8] = -(Rn_VPR128.16B[112,8]);
+ Rd_VPR128.16B[120,8] = -(Rn_VPR128.16B[120,8]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x2e207800/mask=xbf3ffc00
+# CONSTRUCT x2e607800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$2comp@2
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@2
+# AUNIT --inst x2e607800/mask=xfffffc00 --status pass --comment "nointsat"
+# Vector variant when when size = 01 , Q = 0 aa=0 esize=2 suf=VPR64.4H
+
+:sqneg Rd_VPR64.4H, Rn_VPR64.4H
+is b_31=0 & Q=0 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000011110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
+{
+ # simd unary Rd_VPR64.4H = -(Rn_VPR64.4H) on lane size 2
+ Rd_VPR64.4H[0,16] = -(Rn_VPR64.4H[0,16]);
+ Rd_VPR64.4H[16,16] = -(Rn_VPR64.4H[16,16]);
+ Rd_VPR64.4H[32,16] = -(Rn_VPR64.4H[32,16]);
+ Rd_VPR64.4H[48,16] = -(Rn_VPR64.4H[48,16]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x2e207800/mask=xbf3ffc00
+# CONSTRUCT x6e607800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$2comp@2
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@2
+# AUNIT --inst x6e607800/mask=xfffffc00 --status pass --comment "nointsat"
+# Vector variant when when size = 01 , Q = 1 aa=0 esize=2 suf=VPR128.8H
+
+:sqneg Rd_VPR128.8H, Rn_VPR128.8H
+is b_31=0 & Q=1 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000011110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
+{
+ # simd unary Rd_VPR128.8H = -(Rn_VPR128.8H) on lane size 2
+ Rd_VPR128.8H[0,16] = -(Rn_VPR128.8H[0,16]);
+ Rd_VPR128.8H[16,16] = -(Rn_VPR128.8H[16,16]);
+ Rd_VPR128.8H[32,16] = -(Rn_VPR128.8H[32,16]);
+ Rd_VPR128.8H[48,16] = -(Rn_VPR128.8H[48,16]);
+ Rd_VPR128.8H[64,16] = -(Rn_VPR128.8H[64,16]);
+ Rd_VPR128.8H[80,16] = -(Rn_VPR128.8H[80,16]);
+ Rd_VPR128.8H[96,16] = -(Rn_VPR128.8H[96,16]);
+ Rd_VPR128.8H[112,16] = -(Rn_VPR128.8H[112,16]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x2e207800/mask=xbf3ffc00
+# CONSTRUCT x2ea07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$2comp@4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@4
+# AUNIT --inst x2ea07800/mask=xfffffc00 --status pass --comment "nointsat"
+# Vector variant when when size = 10 , Q = 0 aa=0 esize=4 suf=VPR64.2S
+
+:sqneg Rd_VPR64.2S, Rn_VPR64.2S
+is b_31=0 & Q=0 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000011110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd
+{
+ # simd unary Rd_VPR64.2S = -(Rn_VPR64.2S) on lane size 4
+ Rd_VPR64.2S[0,32] = -(Rn_VPR64.2S[0,32]);
+ Rd_VPR64.2S[32,32] = -(Rn_VPR64.2S[32,32]);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x2e207800/mask=xbf3ffc00
+# CONSTRUCT x6ea07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$2comp@4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@4
+# AUNIT --inst x6ea07800/mask=xfffffc00 --status pass --comment "nointsat"
+# Vector variant when when size = 10 , Q = 1 aa=0 esize=4 suf=VPR128.4S
+
+:sqneg Rd_VPR128.4S, Rn_VPR128.4S
+is b_31=0 & Q=1 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000011110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
+{
+ # simd unary Rd_VPR128.4S = -(Rn_VPR128.4S) on lane size 4
+ Rd_VPR128.4S[0,32] = -(Rn_VPR128.4S[0,32]);
+ Rd_VPR128.4S[32,32] = -(Rn_VPR128.4S[32,32]);
+ Rd_VPR128.4S[64,32] = -(Rn_VPR128.4S[64,32]);
+ Rd_VPR128.4S[96,32] = -(Rn_VPR128.4S[96,32]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.292 SQNEG page C7-2671 line 155857 MATCH x2e207800/mask=xbf3ffc00
+# CONSTRUCT x6ee07800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =$2comp@8
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sqneg/1@8
+# AUNIT --inst x6ee07800/mask=xfffffc00 --status pass --comment "nointsat"
+# Vector variant when when size = 11 , Q = 1 aa=0 esize=8 suf=VPR128.2D
+
+:sqneg Rd_VPR128.2D, Rn_VPR128.2D
+is b_31=0 & Q=1 & b_2429=0b101110 & b_2223=0b11 & b_1021=0b100000011110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd
+{
+ # simd unary Rd_VPR128.2D = -(Rn_VPR128.2D) on lane size 8
+ Rd_VPR128.2D[0,64] = -(Rn_VPR128.2D[0,64]);
+ Rd_VPR128.2D[64,64] = -(Rn_VPR128.2D[64,64]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.277 SQRDMLAH (by element) page C7-1598 line 92254 KEEPWITH
+# Integer saturating instruction (not implemented)
+
+sqrdml_subop: "ah" is b_24=0 & b_11=0 { export 0:1; }
+sqrdml_subop: "ah" is b_24=1 & b_13=0 { export 0:1; }
+sqrdml_subop: "sh" is b_24=0 & b_11=1 { export 1:1; }
+sqrdml_subop: "sh" is b_24=1 & b_13=1 { export 1:1; }
+
+sqrdml_esize: "h" is b_2223=0b01 { export 16:1; }
+sqrdml_esize: "s" is b_2223=0b10 { export 32:1; }
+
+sqrdml_elements: "4h" is b_2223=0b01 & b_30=0 { export 4:1; }
+sqrdml_elements: "8h" is b_2223=0b01 & b_30=1 { export 8:1; }
+sqrdml_elements: "2s" is b_2223=0b10 & b_30=0 { export 2:1; }
+sqrdml_elements: "4s" is b_2223=0b10 & b_30=1 { export 4:1; }
+
+sqrdml_index: val is b_2223=0b01 & b_21 & b_20 & b_11 [ val = b_11 * 4 + b_21 * 2 + b_20; ] { export * [const]:1 val; }
+sqrdml_index: val is b_2223=0b10 & b_21 & b_11 [ val = b_11 * 2 + b_21; ] { export * [const]:1 val; }
+
+# We could be more specific about the size of the register, which
+# depends on the variant and Q (b_30). For now, I've just made them
+# all 128 bits.
+
+sqrdml_vd: Rd_FPR16 is b_28=1 & b_2223=0b01 & Rd_FPR16 & Rd_VPR128 { export Rd_VPR128; }
+sqrdml_vd: Rd_FPR32 is b_28=1 & b_2223=0b10 & Rd_FPR32 & Rd_VPR128 { export Rd_VPR128; }
+sqrdml_vd: vRd_VPR128^"."^sqrdml_elements is b_28=0 & vRd_VPR128 & Rd_VPR128 & sqrdml_elements { export Rd_VPR128; }
+
+sqrdml_vn: Rn_FPR16 is b_28=1 & b_2223=0b01 & Rn_FPR16 & Rn_VPR128 { export Rn_VPR128; }
+sqrdml_vn: Rn_FPR32 is b_28=1 & b_2223=0b10 & Rn_FPR32 & Rn_VPR128 { export Rn_VPR128; }
+sqrdml_vn: vRn_VPR128^"."^sqrdml_elements is b_28=0 & vRn_VPR128 & Rn_VPR128 & sqrdml_elements { export Rn_VPR128; }
+
+# Decode Vm (in some cases) depending on size
+
+# cases 34.1, 36.1
+sqrdml_vm: Rm_FPR16 is b_28=1 & b_24=0 & b_2223=0b01 & Rm_FPR16 & Rm_VPR128 { export Rm_VPR128; }
+sqrdml_vm: Rm_FPR32 is b_28=1 & b_24=0 & b_2223=0b10 & Rm_FPR32 & Rm_VPR128 { export Rm_VPR128; }
+
+# cases 34.2, 36.2
+sqrdml_vm: vRm_VPR128^"."^sqrdml_elements is b_28=0 & b_24=0 & vRm_VPR128 & sqrdml_elements & Rm_VPR128 { export Rm_VPR128; }
+
+sqrdml_vmlo: vRm_VPR128Lo is b_2223=0b01 & vRm_VPR128Lo & Rm_VPR128Lo { export Rm_VPR128Lo; }
+sqrdml_vmlo: vRm_VPR128 is b_2223=0b10 & vRm_VPR128 & Rm_VPR128 { export Rm_VPR128; }
+
+# cases 33, 35
+sqrdml_vm: sqrdml_vmlo^"."^sqrdml_esize[sqrdml_index] is b_24=1 & sqrdml_vmlo & sqrdml_esize & sqrdml_index { export sqrdml_vmlo; }
+
+# SQRDML(Vd, Vn, Vm, esize, elements, subop[, index])
+#
+# performs the SQRDML operation
+#
+# Vd[e] = SignedSatQ(Vd[e]<>:4 =
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2
+# AUNIT --inst x5f40d000/mask=xffc0f400 --status fail --comment "nointround nointsat"
+# Scalar variant when size=01 suf=FPR16 elem elem=Re_VPR128Lo.H.vIndexHLM p1=Re_VPR128Lo.H p2=vIndexHLM
+
+:sqrdmulh Rd_FPR16, Rn_FPR16, Re_VPR128Lo.H.vIndexHLM
+is b_2431=0b01011111 & b_2223=0b01 & b_1215=0b1101 & b_10=0 & Rd_FPR16 & Rn_FPR16 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & Zd
+{
+ local tmp1:4 = sext(Rn_FPR16);
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp3:4 = sext(tmp2);
+ local tmp4:4 = tmp1 * tmp3;
+ local tmp5:4 = tmp4 * 2:4;
+ local tmp6:4 = tmp5 >> 16:4;
+ Rd_FPR16 = tmp6:2;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.297 SQRDMULH (by element) page C7-2685 line 156680 MATCH x5f00d000/mask=xff00f400
+# CONSTRUCT x5f80d000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 sext:8 ARG3 sext:8 * 2:8 * 32:8 >>:8 =
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2
+# AUNIT --inst x5f80d000/mask=xffc0f400 --status fail --comment "nointround nointsat"
+# Scalar variant when size=10 suf=FPR32 elem=Re_VPR128.S.vIndex p1=Re_VPR128.S p2=vIndex
+
+:sqrdmulh Rd_FPR32, Rn_FPR32, Re_VPR128.S.vIndex
+is b_2431=0b01011111 & b_2223=0b10 & b_1215=0b1101 & b_10=0 & Rd_FPR32 & Rn_FPR32 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & Zd
+{
+ local tmp1:8 = sext(Rn_FPR32);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp2:4 = Re_VPR128.S.vIndex;
+ local tmp3:8 = sext(tmp2);
+ local tmp4:8 = tmp1 * tmp3;
+ local tmp5:8 = tmp4 * 2:8;
+ local tmp6:8 = tmp5 >> 32:8;
+ Rd_FPR32 = tmp6:4;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.298 SQRDMULH (vector) page C7-2688 line 156859 MATCH x7e20b400/mask=xff20fc00
+# CONSTRUCT x7e60b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2
+# AUNIT --inst x7e60b400/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrdmulh Rd_FPR16, Rn_FPR16, Rm_FPR16
+is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x16 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_sqrdmulh(Rn_FPR16, Rm_FPR16);
+}
+
+# C7.2.298 SQRDMULH (vector) page C7-2688 line 156859 MATCH x7e20b400/mask=xff20fc00
+# CONSTRUCT x7ea0b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2
+# AUNIT --inst x7ea0b400/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrdmulh Rd_FPR32, Rn_FPR32, Rm_FPR32
+is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x16 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_sqrdmulh(Rn_FPR32, Rm_FPR32);
+}
+
+# C7.2.298 SQRDMULH (vector) page C7-2688 line 156859 MATCH x2e20b400/mask=xbf20fc00
+# CONSTRUCT x2ea0b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2@4
+# AUNIT --inst x2ea0b400/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrdmulh Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x16 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_sqrdmulh(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.298 SQRDMULH (vector) page C7-2688 line 156859 MATCH x2e20b400/mask=xbf20fc00
+# CONSTRUCT x2e60b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2@2
+# AUNIT --inst x2e60b400/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrdmulh Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x16 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_sqrdmulh(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.298 SQRDMULH (vector) page C7-2688 line 156859 MATCH x2e20b400/mask=xbf20fc00
+# CONSTRUCT x6ea0b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2@4
+# AUNIT --inst x6ea0b400/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrdmulh Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x16 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sqrdmulh(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.298 SQRDMULH (vector) page C7-2688 line 156859 MATCH x2e20b400/mask=xbf20fc00
+# CONSTRUCT x6e60b400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrdmulh/2@2
+# AUNIT --inst x6e60b400/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrdmulh Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x16 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_sqrdmulh(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x5e205c00/mask=xff20fc00
+# CONSTRUCT x5e205c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2
+# AUNIT --inst x5e205c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrshl Rd_FPR8, Rn_FPR8, Rm_FPR8
+is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0xb & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd
+{
+ Rd_FPR8 = NEON_sqrshl(Rn_FPR8, Rm_FPR8);
+}
+
+# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x5e205c00/mask=xff20fc00
+# CONSTRUCT x5ee05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2
+# AUNIT --inst x5ee05c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrshl Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0xb & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_sqrshl(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x5e205c00/mask=xff20fc00
+# CONSTRUCT x5e605c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2
+# AUNIT --inst x5e605c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrshl Rd_FPR16, Rn_FPR16, Rm_FPR16
+is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0xb & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_sqrshl(Rn_FPR16, Rm_FPR16);
+}
+
+# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x5e205c00/mask=xff20fc00
+# CONSTRUCT x5ea05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2
+# AUNIT --inst x5ea05c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrshl Rd_FPR32, Rn_FPR32, Rm_FPR32
+is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0xb & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_sqrshl(Rn_FPR32, Rm_FPR32);
+}
+
+# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x0e205c00/mask=xbf20fc00
+# CONSTRUCT x4e205c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@1
+# AUNIT --inst x4e205c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xb & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_sqrshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x0e205c00/mask=xbf20fc00
+# CONSTRUCT x4ee05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@8
+# AUNIT --inst x4ee05c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0xb & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_sqrshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x0e205c00/mask=xbf20fc00
+# CONSTRUCT x0ea05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@4
+# AUNIT --inst x0ea05c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xb & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_sqrshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x0e205c00/mask=xbf20fc00
+# CONSTRUCT x0e605c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@2
+# AUNIT --inst x0e605c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xb & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_sqrshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x0e205c00/mask=xbf20fc00
+# CONSTRUCT x4ea05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@4
+# AUNIT --inst x4ea05c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xb & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sqrshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x0e205c00/mask=xbf20fc00
+# CONSTRUCT x0e205c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@1
+# AUNIT --inst x0e205c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xb & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_sqrshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.299 SQRSHL page C7-2690 line 156988 MATCH x0e205c00/mask=xbf20fc00
+# CONSTRUCT x4e605c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqrshl/2@2
+# AUNIT --inst x4e605c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xb & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_sqrshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x0f009c00/mask=xbf80fc00
+# CONSTRUCT x4f089c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn2/3@2
+# AUNIT --inst x4f089c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrshrn2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x13 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_sqrshrn2(Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
+}
+
+# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x0f009c00/mask=xbf80fc00
+# CONSTRUCT x0f209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn/3@8
+# AUNIT --inst x0f209c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrshrn Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x13 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_sqrshrn(Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
+}
+
+# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x0f009c00/mask=xbf80fc00
+# CONSTRUCT x0f109c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn/3@4
+# AUNIT --inst x0f109c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrshrn Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x13 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_sqrshrn(Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
+}
+
+# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x0f009c00/mask=xbf80fc00
+# CONSTRUCT x4f209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn2/3@8
+# AUNIT --inst x4f209c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrshrn2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x13 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sqrshrn2(Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
+}
+
+# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x0f009c00/mask=xbf80fc00
+# CONSTRUCT x0f089c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn2/3@2
+# AUNIT --inst x0f089c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrshrn Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x13 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_sqrshrn2(Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
+}
+
+# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x0f009c00/mask=xbf80fc00
+# CONSTRUCT x4f109c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn2/3@4
+# AUNIT --inst x4f109c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrshrn2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x13 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_sqrshrn2(Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
+}
+
+# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x5f009c00/mask=xff80fc00
+# CONSTRUCT x5f089c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn/3
+# AUNIT --inst x5f089c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat"
+# Scalar variant when immh=0001 Va=FPR16 Vb=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001
+
+:sqrshrn Rd_FPR8, Rn_FPR16, Imm_shr_imm8
+is b_2331=0b010111110 & b_1922=0b0001 & b_1015=0b100111 & Rd_FPR8 & Rn_FPR16 & Imm_shr_imm8 & Zd
+{
+ Rd_FPR8 = NEON_sqrshrn(Rd_FPR8, Rn_FPR16, Imm_shr_imm8:1);
+}
+
+# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x5f009c00/mask=xff80fc00
+# CONSTRUCT x5f109c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn/3
+# AUNIT --inst x5f109c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat"
+# Scalar variant when immh=001x Va=FPR32 Vb=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001
+
+:sqrshrn Rd_FPR16, Rn_FPR32, Imm_shr_imm16
+is b_2331=0b010111110 & b_2022=0b001 & b_1015=0b100111 & Rd_FPR16 & Rn_FPR32 & Imm_shr_imm16 & Zd
+{
+ Rd_FPR16 = NEON_sqrshrn(Rd_FPR16, Rn_FPR32, Imm_shr_imm16:1);
+}
+
+# C7.2.300 SQRSHRN, SQRSHRN2 page C7-2692 line 157131 MATCH x5f009c00/mask=xff80fc00
+# CONSTRUCT x5f209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrn/3
+# AUNIT --inst x5f209c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+# Scalar variant when immh=01xx Va=FPR64 Vb=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01
+
+:sqrshrn Rd_FPR32, Rn_FPR64, Imm_shr_imm32
+is b_2331=0b010111110 & b_2122=0b01 & b_1015=0b100111 & Rd_FPR32 & Rn_FPR64 & Imm_shr_imm32 & Zd
+{
+ Rd_FPR32 = NEON_sqrshrn(Rd_FPR32, Rn_FPR64, Imm_shr_imm32:1);
+}
+
+# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x2f008c00/mask=xbf80fc00
+# CONSTRUCT x6f088c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun2/3@2
+# AUNIT --inst x6f088c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrshrun2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x11 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_sqrshrun2(Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
+}
+
+# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x2f008c00/mask=xbf80fc00
+# CONSTRUCT x2f208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun/3@8
+# AUNIT --inst x2f208c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrshrun Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x11 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_sqrshrun(Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
+}
+
+# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x2f008c00/mask=xbf80fc00
+# CONSTRUCT x2f108c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun/3@4
+# AUNIT --inst x2f108c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrshrun Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x11 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_sqrshrun(Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
+}
+
+# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x2f008c00/mask=xbf80fc00
+# CONSTRUCT x6f208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun2/3@8
+# AUNIT --inst x6f208c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrshrun2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x11 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sqrshrun2(Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
+}
+
+# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x2f008c00/mask=xbf80fc00
+# CONSTRUCT x2f088c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun/3@2
+# AUNIT --inst x2f088c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrshrun Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x11 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_sqrshrun(Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
+}
+
+# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x2f008c00/mask=xbf80fc00
+# CONSTRUCT x6f108c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun2/3@4
+# AUNIT --inst x6f108c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:sqrshrun2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x11 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_sqrshrun2(Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
+}
+
+# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x7f008c00/mask=xff80fc00
+# CONSTRUCT x7f088c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun/3
+# AUNIT --inst x7f088c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat"
+# Scalar variant when immh=0001 Va=FPR16 Vb=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001
+
+:sqrshrun Rd_FPR8, Rn_FPR16, Imm_shr_imm8
+is b_2331=0b011111110 & b_1922=0b0001 & b_1015=0b100011 & Rd_FPR8 & Rn_FPR16 & Imm_shr_imm8 & Zd
+{
+ Rd_FPR8 = NEON_sqrshrun(Rd_FPR8, Rn_FPR16, Imm_shr_imm8:1);
+}
+
+# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x7f008c00/mask=xff80fc00
+# CONSTRUCT x7f108c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun/3
+# AUNIT --inst x7f108c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat"
+# Scalar variant when immh=001x Va=FPR32 Vb=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001
+
+:sqrshrun Rd_FPR16, Rn_FPR32, Imm_shr_imm16
+is b_2331=0b011111110 & b_2022=0b001 & b_1015=0b100011 & Rd_FPR16 & Rn_FPR32 & Imm_shr_imm16 & Zd
+{
+ Rd_FPR16 = NEON_sqrshrun(Rd_FPR16, Rn_FPR32, Imm_shr_imm16:1);
+}
+
+# C7.2.301 SQRSHRUN, SQRSHRUN2 page C7-2695 line 157316 MATCH x7f008c00/mask=xff80fc00
+# CONSTRUCT x7f208c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqrshrun/3
+# AUNIT --inst x7f208c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+# Scalar variant when immh=01xx Va=FPR64 Vb=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01
+
+:sqrshrun Rd_FPR32, Rn_FPR64, Imm_shr_imm32
+is b_2331=0b011111110 & b_2122=0b01 & b_1015=0b100011 & Rd_FPR32 & Rn_FPR64 & Imm_shr_imm32 & Zd
+{
+ Rd_FPR32 = NEON_sqrshrun(Rd_FPR32, Rn_FPR64, Imm_shr_imm32:1);
+}
+
+# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00
+# CONSTRUCT x4f087400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@1
+# AUNIT --inst x4f087400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
+
+:sqshl Rd_VPR128.16B, Rn_VPR128.16B, Imm_uimm3
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xe & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_sqshl(Rn_VPR128.16B, Imm_uimm3:1, 1:1);
+}
+
+# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00
+# CONSTRUCT x4f407400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@8
+# AUNIT --inst x4f407400/mask=xffc0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshl Rd_VPR128.2D, Rn_VPR128.2D, Imm_imm0_63
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_imm0_63 & b_1115=0xe & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_sqshl(Rn_VPR128.2D, Imm_imm0_63:1, 8:1);
+}
+
+# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00
+# CONSTRUCT x0f207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@4
+# AUNIT --inst x0f207400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshl Rd_VPR64.2S, Rn_VPR64.2S, Imm_uimm5
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xe & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_sqshl(Rn_VPR64.2S, Imm_uimm5:1, 4:1);
+}
+
+# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00
+# CONSTRUCT x0f107400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@2
+# AUNIT --inst x0f107400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshl Rd_VPR64.4H, Rn_VPR64.4H, Imm_uimm4
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xe & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_sqshl(Rn_VPR64.4H, Imm_uimm4:1, 2:1);
+}
+
+# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00
+# CONSTRUCT x4f207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@4
+# AUNIT --inst x4f207400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshl Rd_VPR128.4S, Rn_VPR128.4S, Imm_uimm5
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xe & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sqshl(Rn_VPR128.4S, Imm_uimm5:1, 4:1);
+}
+
+# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00
+# CONSTRUCT x0f087400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@1
+# AUNIT --inst x0f087400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
+
+:sqshl Rd_VPR64.8B, Rn_VPR64.8B, Imm_uimm3
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xe & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_sqshl(Rn_VPR64.8B, Imm_uimm3:1, 1:1);
+}
+
+# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x0f007400/mask=xbf80fc00
+# CONSTRUCT x4f107400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2@2
+# AUNIT --inst x4f107400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshl Rd_VPR128.8H, Rn_VPR128.8H, Imm_uimm4
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xe & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_sqshl(Rn_VPR128.8H, Imm_uimm4:1, 2:1);
+}
+
+# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x5f007400/mask=xff80fc00
+# CONSTRUCT x5f087400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2
+# AUNIT --inst x5f087400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when immh=0001 V=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001
+
+:sqshl Rd_FPR8, Rn_FPR8, Imm_shr_imm8
+is b_2331=0b010111110 & b_1922=0b0001 & b_1015=0b011101 & Rd_FPR8 & Rn_FPR8 & Imm_shr_imm8 & Zd
+{
+ Rd_FPR8 = NEON_sqshl(Rn_FPR8, Imm_shr_imm8:1);
+}
+
+# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x5f007400/mask=xff80fc00
+# CONSTRUCT x5f107400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2
+# AUNIT --inst x5f107400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when immh=001x V=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001
+
+:sqshl Rd_FPR16, Rn_FPR16, Imm_shr_imm16
+is b_2331=0b010111110 & b_2022=0b001 & b_1015=0b011101 & Rd_FPR16 & Rn_FPR16 & Imm_shr_imm16 & Zd
+{
+ Rd_FPR16 = NEON_sqshl(Rn_FPR16, Imm_shr_imm16:1);
+}
+
+# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x5f007400/mask=xff80fc00
+# CONSTRUCT x5f207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2
+# AUNIT --inst x5f207400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when immh=01xx V=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01
+
+:sqshl Rd_FPR32, Rn_FPR32, Imm_shr_imm32
+is b_2331=0b010111110 & b_2122=0b01 & b_1015=0b011101 & Rd_FPR32 & Rn_FPR32 & Imm_shr_imm32 & Zd
+{
+ Rd_FPR32 = NEON_sqshl(Rn_FPR32, Imm_shr_imm32:1);
+}
+
+# C7.2.302 SQSHL (immediate) page C7-2698 line 157500 MATCH x5f007400/mask=xff80fc00
+# CONSTRUCT x5f407400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshl/2
+# AUNIT --inst x5f407400/mask=xffc0fc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when immh=1xxx V=FPR64 imm=Imm_shr_imm64 bb=b_22 aa=1
+
+:sqshl Rd_FPR64, Rn_FPR64, Imm_shr_imm64
+is b_2331=0b010111110 & b_22=1 & b_1015=0b011101 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd
+{
+ Rd_FPR64 = NEON_sqshl(Rn_FPR64, Imm_shr_imm64:1);
+}
+
+# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x5e204c00/mask=xff20fc00
+# CONSTRUCT x5e204c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2
+# AUNIT --inst x5e204c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshl Rd_FPR8, Rn_FPR8, Rm_FPR8
+is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0x9 & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd
+{
+ Rd_FPR8 = NEON_sqshl(Rn_FPR8, Rm_FPR8);
+}
+
+# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x5e204c00/mask=xff20fc00
+# CONSTRUCT x5ee04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2
+# AUNIT --inst x5ee04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshl Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x9 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_sqshl(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x5e204c00/mask=xff20fc00
+# CONSTRUCT x5e604c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2
+# AUNIT --inst x5e604c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshl Rd_FPR16, Rn_FPR16, Rm_FPR16
+is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x9 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_sqshl(Rn_FPR16, Rm_FPR16);
+}
+
+# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x5e204c00/mask=xff20fc00
+# CONSTRUCT x5ea04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2
+# AUNIT --inst x5ea04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshl Rd_FPR32, Rn_FPR32, Rm_FPR32
+is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x9 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_sqshl(Rn_FPR32, Rm_FPR32);
+}
+
+# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x0e204c00/mask=xbf20fc00
+# CONSTRUCT x4e204c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@1
+# AUNIT --inst x4e204c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x9 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_sqshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x0e204c00/mask=xbf20fc00
+# CONSTRUCT x4ee04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@8
+# AUNIT --inst x4ee04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x9 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_sqshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x0e204c00/mask=xbf20fc00
+# CONSTRUCT x0ea04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@4
+# AUNIT --inst x0ea04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x9 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_sqshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x0e204c00/mask=xbf20fc00
+# CONSTRUCT x0e604c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@2
+# AUNIT --inst x0e604c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x9 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_sqshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x0e204c00/mask=xbf20fc00
+# CONSTRUCT x4ea04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@4
+# AUNIT --inst x4ea04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x9 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sqshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x0e204c00/mask=xbf20fc00
+# CONSTRUCT x0e204c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@1
+# AUNIT --inst x0e204c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x9 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_sqshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.303 SQSHL (register) page C7-2701 line 157665 MATCH x0e204c00/mask=xbf20fc00
+# CONSTRUCT x4e604c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqshl/2@2
+# AUNIT --inst x4e604c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x9 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_sqshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00
+# CONSTRUCT x6f086400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@1
+# AUNIT --inst x6f086400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
+
+:sqshlu Rd_VPR128.16B, Rn_VPR128.16B, Imm_uimm3
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xc & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_sqshlu(Rn_VPR128.16B, Imm_uimm3:1, 1:1);
+}
+
+# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00
+# CONSTRUCT x6f406400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@8
+# AUNIT --inst x6f406400/mask=xffc0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshlu Rd_VPR128.2D, Rn_VPR128.2D, Imm_imm0_63
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_imm0_63 & b_1115=0xc & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_sqshlu(Rn_VPR128.2D, Imm_imm0_63:1, 8:1);
+}
+
+# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00
+# CONSTRUCT x2f206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@4
+# AUNIT --inst x2f206400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshlu Rd_VPR64.2S, Rn_VPR64.2S, Imm_uimm5
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xc & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_sqshlu(Rn_VPR64.2S, Imm_uimm5:1, 4:1);
+}
+
+# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00
+# CONSTRUCT x2f106400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@2
+# AUNIT --inst x2f106400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshlu Rd_VPR64.4H, Rn_VPR64.4H, Imm_uimm4
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xc & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_sqshlu(Rn_VPR64.4H, Imm_uimm4:1, 2:1);
+}
+
+# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00
+# CONSTRUCT x6f206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@4
+# AUNIT --inst x6f206400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshlu Rd_VPR128.4S, Rn_VPR128.4S, Imm_uimm5
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xc & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sqshlu(Rn_VPR128.4S, Imm_uimm5:1, 4:1);
+}
+
+# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00
+# CONSTRUCT x2f086400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@1
+# AUNIT --inst x2f086400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
+
+:sqshlu Rd_VPR64.8B, Rn_VPR64.8B, Imm_uimm3
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xc & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_sqshlu(Rn_VPR64.8B, Imm_uimm3:1, 1:1);
+}
+
+# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x2f006400/mask=xbf80fc00
+# CONSTRUCT x6f106400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2@2
+# AUNIT --inst x6f106400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshlu Rd_VPR128.8H, Rn_VPR128.8H, Imm_uimm4
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xc & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_sqshlu(Rn_VPR128.8H, Imm_uimm4:1, 2:1);
+}
+
+# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x7f006400/mask=xff80fc00
+# CONSTRUCT x7f086400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2
+# AUNIT --inst x7f086400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when immh=0001 V=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001
+
+:sqshlu Rd_FPR8, Rn_FPR8, Imm_shr_imm8
+is b_2331=0b011111110 & b_1922=0b0001 & b_1015=0b011001 & Rd_FPR8 & Rn_FPR8 & Imm_shr_imm8 & Zd
+{
+ Rd_FPR8 = NEON_sqshlu(Rn_FPR8, Imm_shr_imm8:1);
+}
+
+# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x7f006400/mask=xff80fc00
+# CONSTRUCT x7f106400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2
+# AUNIT --inst x7f106400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when immh=001x V=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001
+
+:sqshlu Rd_FPR16, Rn_FPR16, Imm_shr_imm16
+is b_2331=0b011111110 & b_2022=0b001 & b_1015=0b011001 & Rd_FPR16 & Rn_FPR16 & Imm_shr_imm16 & Zd
+{
+ Rd_FPR16 = NEON_sqshlu(Rn_FPR16, Imm_shr_imm16:1);
+}
+
+# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x7f006400/mask=xff80fc00
+# CONSTRUCT x7f206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2
+# AUNIT --inst x7f206400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when immh=01xx V=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01
+
+:sqshlu Rd_FPR32, Rn_FPR32, Imm_shr_imm32
+is b_2331=0b011111110 & b_2122=0b01 & b_1015=0b011001 & Rd_FPR32 & Rn_FPR32 & Imm_shr_imm32 & Zd
+{
+ Rd_FPR32 = NEON_sqshlu(Rn_FPR32, Imm_shr_imm32:1);
+}
+
+# C7.2.304 SQSHLU page C7-2703 line 157807 MATCH x7f006400/mask=xff80fc00
+# CONSTRUCT x7f406400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sqshlu/2
+# AUNIT --inst x7f406400/mask=xffc0fc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when immh=1xxx V=FPR64 imm=Imm_shr_imm64 bb=b_22 aa=1
+
+:sqshlu Rd_FPR64, Rn_FPR64, Imm_shr_imm64
+is b_2331=0b011111110 & b_22=1 & b_1015=0b011001 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd
+{
+ Rd_FPR64 = NEON_sqshlu(Rn_FPR64, Imm_shr_imm64:1);
+}
+
+# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x0f009400/mask=xbf80fc00
+# CONSTRUCT x4f089400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn2/3@2
+# AUNIT --inst x4f089400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
+
+:sqshrn2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x12 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_sqshrn2(Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
+}
+
+# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x0f009400/mask=xbf80fc00
+# CONSTRUCT x0f209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn/3@8
+# AUNIT --inst x0f209400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshrn Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x12 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_sqshrn(Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
+}
+
+# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x0f009400/mask=xbf80fc00
+# CONSTRUCT x0f109400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn/3@4
+# AUNIT --inst x0f109400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshrn Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x12 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_sqshrn(Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
+}
+
+# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x0f009400/mask=xbf80fc00
+# CONSTRUCT x4f209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn2/3@8
+# AUNIT --inst x4f209400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshrn2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x12 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sqshrn2(Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
+}
+
+# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x0f009400/mask=xbf80fc00
+# CONSTRUCT x0f089400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn/3@2
+# AUNIT --inst x0f089400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
+
+:sqshrn Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x12 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_sqshrn(Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
+}
+
+# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x0f009400/mask=xbf80fc00
+# CONSTRUCT x4f109400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn2/3@4
+# AUNIT --inst x4f109400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshrn2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x12 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_sqshrn2(Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
+}
+
+# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x5f009400/mask=xff80fc00
+# CONSTRUCT x5f089400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn/3
+# AUNIT --inst x5f089400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when immh=0001 Va=FPR16 Vb=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001
+
+:sqshrn Rd_FPR8, Rd_FPR16, Imm_shr_imm8
+is b_2331=0b010111110 & b_1922=0b0001 & b_1015=0b100101 & Rd_FPR8 & Rd_FPR16 & Imm_shr_imm8 & Zd
+{
+ Rd_FPR8 = NEON_sqshrn(Rd_FPR8, Rd_FPR16, Imm_shr_imm8:1);
+}
+
+# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x5f009400/mask=xff80fc00
+# CONSTRUCT x5f109400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn/3
+# AUNIT --inst x5f109400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when immh=001x Va=FPR32 Vb=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001
+
+:sqshrn Rd_FPR16, Rd_FPR32, Imm_shr_imm16
+is b_2331=0b010111110 & b_2022=0b001 & b_1015=0b100101 & Rd_FPR16 & Rd_FPR32 & Imm_shr_imm16 & Zd
+{
+ Rd_FPR16 = NEON_sqshrn(Rd_FPR16, Rd_FPR32, Imm_shr_imm16:1);
+}
+
+# C7.2.305 SQSHRN, SQSHRN2 page C7-2706 line 157972 MATCH x5f009400/mask=xff80fc00
+# CONSTRUCT x5f209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrn/3
+# AUNIT --inst x5f209400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when immh=01xx Va=FPR64 Vb=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01
+
+:sqshrn Rd_FPR32, Rd_FPR64, Imm_shr_imm32
+is b_2331=0b010111110 & b_2122=0b01 & b_1015=0b100101 & Rd_FPR32 & Rd_FPR64 & Imm_shr_imm32 & Zd
+{
+ Rd_FPR32 = NEON_sqshrn(Rd_FPR32, Rd_FPR64, Imm_shr_imm32:1);
+}
+
+# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x2f008400/mask=xbf80fc00
+# CONSTRUCT x6f088400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun2/3@2
+# AUNIT --inst x6f088400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
+
+:sqshrun2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x10 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_sqshrun2(Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
+}
+
+# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x2f008400/mask=xbf80fc00
+# CONSTRUCT x2f208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun/3@8
+# AUNIT --inst x2f208400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshrun Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x10 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_sqshrun(Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
+}
+
+# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x2f008400/mask=xbf80fc00
+# CONSTRUCT x2f108400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun/3@4
+# AUNIT --inst x2f108400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshrun Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x10 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_sqshrun(Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
+}
+
+# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x2f008400/mask=xbf80fc00
+# CONSTRUCT x6f208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun2/3@8
+# AUNIT --inst x6f208400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshrun2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x10 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sqshrun2(Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
+}
+
+# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x2f008400/mask=xbf80fc00
+# CONSTRUCT x2f088400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun/3@2
+# AUNIT --inst x2f088400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
+
+:sqshrun Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x10 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_sqshrun(Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
+}
+
+# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x2f008400/mask=xbf80fc00
+# CONSTRUCT x6f108400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun2/3@4
+# AUNIT --inst x6f108400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
+
+:sqshrun2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x10 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_sqshrun2(Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
+}
+
+# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x7f008400/mask=xff80fc00
+# CONSTRUCT x7f088400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun/3
+# AUNIT --inst x7f088400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when immh=0001 Va=FPR16 Vb=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001
+
+:sqshrun Rd_FPR8, Rd_FPR16, Imm_shr_imm8
+is b_2331=0b011111110 & b_1922=0b0001 & b_1015=0b100001 & Rd_FPR8 & Rd_FPR16 & Imm_shr_imm8 & Zd
+{
+ Rd_FPR8 = NEON_sqshrun(Rd_FPR8, Rd_FPR16, Imm_shr_imm8:1);
+}
+
+# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x7f008400/mask=xff80fc00
+# CONSTRUCT x7f108400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun/3
+# AUNIT --inst x7f108400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when immh=001x Va=FPR32 Vb=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001
+
+:sqshrun Rd_FPR16, Rd_FPR32, Imm_shr_imm16
+is b_2331=0b011111110 & b_2022=0b001 & b_1015=0b100001 & Rd_FPR16 & Rd_FPR32 & Imm_shr_imm16 & Zd
+{
+ Rd_FPR16 = NEON_sqshrun(Rd_FPR16, Rd_FPR32, Imm_shr_imm16:1);
+}
+
+# C7.2.306 SQSHRUN, SQSHRUN2 page C7-2709 line 158157 MATCH x7f008400/mask=xff80fc00
+# CONSTRUCT x7f208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sqshrun/3
+# AUNIT --inst x7f208400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when immh=01xx Va=FPR64 Vb=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01
+
+:sqshrun Rd_FPR32, Rd_FPR64, Imm_shr_imm32
+is b_2331=0b011111110 & b_2122=0b01 & b_1015=0b100001 & Rd_FPR32 & Rd_FPR64 & Imm_shr_imm32 & Zd
+{
+ Rd_FPR32 = NEON_sqshrun(Rd_FPR32, Rd_FPR64, Imm_shr_imm32:1);
+}
+
+# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x5e202c00/mask=xff20fc00
+# CONSTRUCT x5e202c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2
+# AUNIT --inst x5e202c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqsub Rd_FPR8, Rn_FPR8, Rm_FPR8
+is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0x5 & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd
+{
+ Rd_FPR8 = NEON_sqsub(Rn_FPR8, Rm_FPR8);
+}
+
+# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x5e202c00/mask=xff20fc00
+# CONSTRUCT x5ee02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2
+# AUNIT --inst x5ee02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqsub Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x5 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_sqsub(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x5e202c00/mask=xff20fc00
+# CONSTRUCT x5e602c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2
+# AUNIT --inst x5e602c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqsub Rd_FPR16, Rn_FPR16, Rm_FPR16
+is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x5 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_sqsub(Rn_FPR16, Rm_FPR16);
+}
+
+# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x5e202c00/mask=xff20fc00
+# CONSTRUCT x5ea02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2
+# AUNIT --inst x5ea02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqsub Rd_FPR32, Rn_FPR32, Rm_FPR32
+is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x5 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_sqsub(Rn_FPR32, Rm_FPR32);
+}
+
+# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x0e202c00/mask=xbf20fc00
+# CONSTRUCT x4e202c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@1
+# AUNIT --inst x4e202c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqsub Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x5 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_sqsub(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x0e202c00/mask=xbf20fc00
+# CONSTRUCT x4ee02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@8
+# AUNIT --inst x4ee02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqsub Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x5 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_sqsub(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x0e202c00/mask=xbf20fc00
+# CONSTRUCT x0ea02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@4
+# AUNIT --inst x0ea02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqsub Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x5 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_sqsub(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x0e202c00/mask=xbf20fc00
+# CONSTRUCT x0e602c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@2
+# AUNIT --inst x0e602c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqsub Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x5 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_sqsub(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x0e202c00/mask=xbf20fc00
+# CONSTRUCT x4ea02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@4
+# AUNIT --inst x4ea02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqsub Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x5 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sqsub(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x0e202c00/mask=xbf20fc00
+# CONSTRUCT x0e202c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@1
+# AUNIT --inst x0e202c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqsub Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x5 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_sqsub(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.307 SQSUB page C7-2712 line 158339 MATCH x0e202c00/mask=xbf20fc00
+# CONSTRUCT x4e602c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sqsub/2@2
+# AUNIT --inst x4e602c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:sqsub Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x5 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_sqsub(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x5e214800/mask=xff3ffc00
+# CONSTRUCT x5e214800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn/2
+# AUNIT --inst x5e214800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+
+:sqxtn Rd_FPR8, Rn_FPR16
+is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_FPR16 & Rd_FPR8 & Zd
+{
+ Rd_FPR8 = NEON_sqxtn(Rd_FPR8, Rn_FPR16);
+}
+
+# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x5e214800/mask=xff3ffc00
+# CONSTRUCT x5e614800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn/2
+# AUNIT --inst x5e614800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+
+:sqxtn Rd_FPR16, Rn_FPR32
+is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_FPR32 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_sqxtn(Rd_FPR16, Rn_FPR32);
+}
+
+# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x5e214800/mask=xff3ffc00
+# CONSTRUCT x5ea14800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn/2
+# AUNIT --inst x5ea14800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+
+:sqxtn Rd_FPR32, Rn_FPR64
+is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_FPR64 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_sqxtn(Rd_FPR32, Rn_FPR64);
+}
+
+# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x0e214800/mask=xbf3ffc00
+# CONSTRUCT x4e214800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn2/2@2
+# AUNIT --inst x4e214800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+
+:sqxtn2 Rd_VPR128.16B, Rn_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_sqxtn2(Rd_VPR128.16B, Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x0e214800/mask=xbf3ffc00
+# CONSTRUCT x4e614800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn2/2@4
+# AUNIT --inst x4e614800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+
+:sqxtn2 Rd_VPR128.8H, Rn_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_sqxtn2(Rd_VPR128.8H, Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x0e214800/mask=xbf3ffc00
+# CONSTRUCT x4ea14800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn2/2@8
+# AUNIT --inst x4ea14800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+
+:sqxtn2 Rd_VPR128.4S, Rn_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sqxtn2(Rd_VPR128.4S, Rn_VPR128.2D, 8:1);
+}
+
+# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x0e214800/mask=xbf3ffc00
+# CONSTRUCT x0ea14800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn/2@8
+# AUNIT --inst x0ea14800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+
+:sqxtn Rd_VPR64.2S, Rn_VPR128.2D
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_sqxtn(Rd_VPR64.2S, Rn_VPR128.2D, 8:1);
+}
+
+# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x0e214800/mask=xbf3ffc00
+# CONSTRUCT x0e614800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn/2@4
+# AUNIT --inst x0e614800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+
+:sqxtn Rd_VPR64.4H, Rn_VPR128.4S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_sqxtn(Rd_VPR64.4H, Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.308 SQXTN, SQXTN2 page C7-2714 line 158467 MATCH x0e214800/mask=xbf3ffc00
+# CONSTRUCT x0e214800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtn/2@2
+# AUNIT --inst x0e214800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+
+:sqxtn Rd_VPR64.8B, Rn_VPR128.8H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x14 & b_1011=2 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_sqxtn(Rd_VPR64.8B, Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x7e212800/mask=xff3ffc00
+# CONSTRUCT x7e212800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun/2
+# AUNIT --inst x7e212800/mask=xfffffc00 --status noqemu --comment "nointsat"
+# Scalar variant when size=00 Q=1 bb=1 Ta=FPR16 Tb=FPR8
+
+:sqxtun Rd_FPR8, Rn_FPR16
+is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b00 & b_1021=0b100001001010 & Rd_FPR8 & Rn_FPR16 & Zd
+{
+ Rd_FPR8 = NEON_sqxtun(Rd_FPR8, Rn_FPR16);
+}
+
+# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x7e212800/mask=xff3ffc00
+# CONSTRUCT x7e612800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun/2
+# AUNIT --inst x7e612800/mask=xfffffc00 --status noqemu --comment "nointsat"
+# Scalar variant when size=01 Q=1 bb=1 Ta=FPR32 Tb=FPR16
+
+:sqxtun Rd_FPR16, Rn_FPR32
+is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b01 & b_1021=0b100001001010 & Rd_FPR16 & Rn_FPR32 & Zd
+{
+ Rd_FPR16 = NEON_sqxtun(Rd_FPR16, Rn_FPR32);
+}
+
+# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x7e212800/mask=xff3ffc00
+# CONSTRUCT x7ea12800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun/2
+# AUNIT --inst x7ea12800/mask=xfffffc00 --status noqemu --comment "nointsat"
+# Scalar variant when size=10 Q=1 bb=1 Ta=FPR64 Tb=FPR32
+
+:sqxtun Rd_FPR32, Rn_FPR64
+is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b10 & b_1021=0b100001001010 & Rd_FPR32 & Rn_FPR64 & Zd
+{
+ Rd_FPR32 = NEON_sqxtun(Rd_FPR32, Rn_FPR64);
+}
+
+# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x2e212800/mask=xbf3ffc00
+# CONSTRUCT x2e212800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun/2@2
+# AUNIT --inst x2e212800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Vector variant when size=00 Q=0 bb=0 Ta=VPR128.8H Tb=VPR64.8B esize=2
+
+:sqxtun Rd_VPR64.8B, Rn_VPR128.8H
+is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100001001010 & Rd_VPR64.8B & Rn_VPR128.8H & Zd
+{
+ Rd_VPR64.8B = NEON_sqxtun(Rd_VPR64.8B, Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x2e212800/mask=xbf3ffc00
+# CONSTRUCT x6e212800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun2/2@2
+# AUNIT --inst x6e212800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Vector variant when size=00 Q=1 bb=0 Ta=VPR128.8H Tb=VPR128.16B esize=2
+
+:sqxtun2 Rd_VPR128.16B, Rn_VPR128.8H
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100001001010 & Rd_VPR128.16B & Rn_VPR128.8H & Zd
+{
+ Rd_VPR128.16B = NEON_sqxtun2(Rd_VPR128.16B, Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x2e212800/mask=xbf3ffc00
+# CONSTRUCT x2e612800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun/2@4
+# AUNIT --inst x2e612800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Vector variant when size=01 Q=0 bb=0 Ta=VPR128.4S Tb=VPR64.4H esize=4
+
+:sqxtun Rd_VPR64.4H, Rn_VPR128.4S
+is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100001001010 & Rd_VPR64.4H & Rn_VPR128.4S & Zd
+{
+ Rd_VPR64.4H = NEON_sqxtun(Rd_VPR64.4H, Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x2e212800/mask=xbf3ffc00
+# CONSTRUCT x6e612800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun2/2@4
+# AUNIT --inst x6e612800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Vector variant when size=01 Q=1 bb=0 Ta=VPR128.4S Tb=VPR128.8H esize=4
+
+:sqxtun2 Rd_VPR128.8H, Rn_VPR128.4S
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100001001010 & Rd_VPR128.8H & Rn_VPR128.4S & Zd
+{
+ Rd_VPR128.8H = NEON_sqxtun2(Rd_VPR128.8H, Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x2e212800/mask=xbf3ffc00
+# CONSTRUCT x2ea12800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun/2@8
+# AUNIT --inst x2ea12800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Vector variant when size=10 Q=0 bb=0 Ta=VPR128.2D Tb=VPR64.2S esize=8
+
+:sqxtun Rd_VPR64.2S, Rn_VPR128.2D
+is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100001001010 & Rd_VPR64.2S & Rn_VPR128.2D & Zd
+{
+ Rd_VPR64.2S = NEON_sqxtun(Rd_VPR64.2S, Rn_VPR128.2D, 8:1);
+}
+
+# C7.2.309 SQXTUN, SQXTUN2 page C7-2717 line 158622 MATCH x2e212800/mask=xbf3ffc00
+# CONSTRUCT x6ea12800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_sqxtun2/2@8
+# AUNIT --inst x6ea12800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Vector variant when size=10 Q=1 bb=0 Ta=VPR128.2D Tb=VPR128.4S esize=8
+
+:sqxtun2 Rd_VPR128.4S, Rn_VPR128.2D
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100001001010 & Rd_VPR128.4S & Rn_VPR128.2D & Zd
+{
+ Rd_VPR128.4S = NEON_sqxtun2(Rd_VPR128.4S, Rn_VPR128.2D, 8:1);
+}
+
+# C7.2.310 SRHADD page C7-2720 line 158773 MATCH x0e201400/mask=xbf20fc00
+# CONSTRUCT x4e201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_srhadd/2@1
+# AUNIT --inst x4e201400/mask=xffe0fc00 --status nopcodeop
+
+:srhadd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x2 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rn_VPR128.16B = NEON_srhadd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.310 SRHADD page C7-2720 line 158773 MATCH x0e201400/mask=xbf20fc00
+# CONSTRUCT x0ea01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_srhadd/2@4
+# AUNIT --inst x0ea01400/mask=xffe0fc00 --status nopcodeop
+
+:srhadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x2 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rn_VPR64.2S = NEON_srhadd(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.310 SRHADD page C7-2720 line 158773 MATCH x0e201400/mask=xbf20fc00
+# CONSTRUCT x0e601400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_srhadd/2@2
+# AUNIT --inst x0e601400/mask=xffe0fc00 --status nopcodeop
+
+:srhadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x2 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rn_VPR64.4H = NEON_srhadd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.310 SRHADD page C7-2720 line 158773 MATCH x0e201400/mask=xbf20fc00
+# CONSTRUCT x4ea01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_srhadd/2@4
+# AUNIT --inst x4ea01400/mask=xffe0fc00 --status nopcodeop
+
+:srhadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x2 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rn_VPR128.4S = NEON_srhadd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.310 SRHADD page C7-2720 line 158773 MATCH x0e201400/mask=xbf20fc00
+# CONSTRUCT x0e201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_srhadd/2@1
+# AUNIT --inst x0e201400/mask=xffe0fc00 --status nopcodeop
+
+:srhadd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x2 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rn_VPR64.8B = NEON_srhadd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.310 SRHADD page C7-2720 line 158773 MATCH x0e201400/mask=xbf20fc00
+# CONSTRUCT x4e601400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_srhadd/2@2
+# AUNIT --inst x4e601400/mask=xffe0fc00 --status nopcodeop
+
+:srhadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x2 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rn_VPR128.8H = NEON_srhadd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00
+# CONSTRUCT x6f084400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@1
+# AUNIT --inst x6f084400/mask=xfff8fc00 --status nopcodeop
+
+:sri Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x8 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_sri(Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8:4, 1:1);
+}
+
+# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00
+# CONSTRUCT x6f404400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@8
+# AUNIT --inst x6f404400/mask=xffc0fc00 --status nopcodeop
+
+:sri Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x8 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_sri(Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64:4, 8:1);
+}
+
+# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00
+# CONSTRUCT x2f204400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@4
+# AUNIT --inst x2f204400/mask=xffe0fc00 --status nopcodeop
+
+:sri Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x8 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_sri(Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32:4, 4:1);
+}
+
+# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00
+# CONSTRUCT x2f104400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@2
+# AUNIT --inst x2f104400/mask=xfff0fc00 --status nopcodeop
+
+:sri Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x8 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_sri(Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16:4, 2:1);
+}
+
+# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00
+# CONSTRUCT x6f204400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@4
+# AUNIT --inst x6f204400/mask=xffe0fc00 --status nopcodeop
+
+:sri Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x8 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sri(Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32:4, 4:1);
+}
+
+# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00
+# CONSTRUCT x2f084400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@1
+# AUNIT --inst x2f084400/mask=xfff8fc00 --status nopcodeop
+
+:sri Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x8 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_sri(Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8:4, 1:1);
+}
+
+# C7.2.311 SRI page C7-2722 line 158861 MATCH x2f004400/mask=xbf80fc00
+# CONSTRUCT x6f104400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:4 &=NEON_sri/3@2
+# AUNIT --inst x6f104400/mask=xfff0fc00 --status nopcodeop
+
+:sri Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x8 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_sri(Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16:4, 2:1);
+}
+
+# C7.2.311 SRI page C7-2722 line 158861 MATCH x7f004400/mask=xff80fc00
+# CONSTRUCT x7f404400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_sri/3
+# AUNIT --inst x7f404400/mask=xffc0fc00 --status nopcodeop
+
+:sri Rd_FPR64, Rn_FPR64, Imm_shr_imm64
+is b_2331=0b011111110 & b_22=1 & b_1015=0b010001 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd
+{
+ Rd_FPR64 = NEON_sri(Rd_FPR64, Rn_FPR64, Imm_shr_imm64:1);
+}
+
+# C7.2.312 SRSHL page C7-2725 line 159028 MATCH x5e205400/mask=xff20fc00
+# CONSTRUCT x5ee05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2
+# AUNIT --inst x5ee05400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:srshl Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0xa & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_srshl(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.312 SRSHL page C7-2725 line 159028 MATCH x0e205400/mask=xbf20fc00
+# CONSTRUCT x4e205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@1
+# AUNIT --inst x4e205400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:srshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xa & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_srshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.312 SRSHL page C7-2725 line 159028 MATCH x0e205400/mask=xbf20fc00
+# CONSTRUCT x4ee05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@8
+# AUNIT --inst x4ee05400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:srshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0xa & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_srshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.312 SRSHL page C7-2725 line 159028 MATCH x0e205400/mask=xbf20fc00
+# CONSTRUCT x0ea05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@4
+# AUNIT --inst x0ea05400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:srshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xa & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_srshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.312 SRSHL page C7-2725 line 159028 MATCH x0e205400/mask=xbf20fc00
+# CONSTRUCT x0e605400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@2
+# AUNIT --inst x0e605400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:srshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xa & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_srshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.312 SRSHL page C7-2725 line 159028 MATCH x0e205400/mask=xbf20fc00
+# CONSTRUCT x4ea05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@4
+# AUNIT --inst x4ea05400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:srshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xa & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_srshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.312 SRSHL page C7-2725 line 159028 MATCH x0e205400/mask=xbf20fc00
+# CONSTRUCT x0e205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@1
+# AUNIT --inst x0e205400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:srshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xa & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_srshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.312 SRSHL page C7-2725 line 159028 MATCH x0e205400/mask=xbf20fc00
+# CONSTRUCT x4e605400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_srshl/2@2
+# AUNIT --inst x4e605400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:srshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xa & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_srshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00
+# CONSTRUCT x4f082400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@1
+# AUNIT --inst x4f082400/mask=xfff8fc00 --status nopcodeop --comment "nointround"
+
+:srshr Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x4 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_srshr(Rn_VPR128.16B, Imm_shr_imm8:1, 1:1);
+}
+
+# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00
+# CONSTRUCT x4f402400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@8
+# AUNIT --inst x4f402400/mask=xffc0fc00 --status nopcodeop --comment "nointround"
+
+:srshr Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x4 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_srshr(Rn_VPR128.2D, Imm_shr_imm64:1, 8:1);
+}
+
+# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00
+# CONSTRUCT x0f202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@4
+# AUNIT --inst x0f202400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:srshr Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x4 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_srshr(Rn_VPR64.2S, Imm_shr_imm32:1, 4:1);
+}
+
+# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00
+# CONSTRUCT x0f102400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@2
+# AUNIT --inst x0f102400/mask=xfff0fc00 --status nopcodeop --comment "nointround"
+
+:srshr Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x4 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_srshr(Rn_VPR64.4H, Imm_shr_imm16:1, 2:1);
+}
+
+# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00
+# CONSTRUCT x4f202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@4
+# AUNIT --inst x4f202400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:srshr Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x4 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_srshr(Rn_VPR128.4S, Imm_shr_imm32:1, 4:1);
+}
+
+# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00
+# CONSTRUCT x0f082400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@1
+# AUNIT --inst x0f082400/mask=xfff8fc00 --status nopcodeop --comment "nointround"
+
+:srshr Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x4 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_srshr(Rn_VPR64.8B, Imm_shr_imm8:1, 1:1);
+}
+
+# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x0f002400/mask=xbf80fc00
+# CONSTRUCT x4f102400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2@2
+# AUNIT --inst x4f102400/mask=xfff0fc00 --status nopcodeop --comment "nointround"
+
+:srshr Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x4 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_srshr(Rn_VPR128.8H, Imm_shr_imm16:1, 2:1);
+}
+
+# C7.2.313 SRSHR page C7-2727 line 159165 MATCH x5f002400/mask=xff80fc00
+# CONSTRUCT x5f402400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_srshr/2
+# AUNIT --inst x5f402400/mask=xffc0fc00 --status nopcodeop --comment "nointround"
+
+:srshr Rd_FPR64, Rn_FPR64, Imm_shr_imm64
+is b_2331=0b010111110 & b_22=1 & b_1015=0b001001 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd
+{
+ Rd_FPR64 = NEON_srshr(Rn_FPR64, Imm_shr_imm64:1);
+}
+
+# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00
+# CONSTRUCT x4f083400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:1 $s>>@1 &=$+@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@1
+# AUNIT --inst x4f083400/mask=xfff8fc00 --status fail --comment "nointround"
+
+:srsra Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x6 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.16B s>> Imm_shr_imm8:1 on lane size 1
+ TMPQ1[0,8] = Rn_VPR128.16B[0,8] s>> Imm_shr_imm8:1;
+ TMPQ1[8,8] = Rn_VPR128.16B[8,8] s>> Imm_shr_imm8:1;
+ TMPQ1[16,8] = Rn_VPR128.16B[16,8] s>> Imm_shr_imm8:1;
+ TMPQ1[24,8] = Rn_VPR128.16B[24,8] s>> Imm_shr_imm8:1;
+ TMPQ1[32,8] = Rn_VPR128.16B[32,8] s>> Imm_shr_imm8:1;
+ TMPQ1[40,8] = Rn_VPR128.16B[40,8] s>> Imm_shr_imm8:1;
+ TMPQ1[48,8] = Rn_VPR128.16B[48,8] s>> Imm_shr_imm8:1;
+ TMPQ1[56,8] = Rn_VPR128.16B[56,8] s>> Imm_shr_imm8:1;
+ TMPQ1[64,8] = Rn_VPR128.16B[64,8] s>> Imm_shr_imm8:1;
+ TMPQ1[72,8] = Rn_VPR128.16B[72,8] s>> Imm_shr_imm8:1;
+ TMPQ1[80,8] = Rn_VPR128.16B[80,8] s>> Imm_shr_imm8:1;
+ TMPQ1[88,8] = Rn_VPR128.16B[88,8] s>> Imm_shr_imm8:1;
+ TMPQ1[96,8] = Rn_VPR128.16B[96,8] s>> Imm_shr_imm8:1;
+ TMPQ1[104,8] = Rn_VPR128.16B[104,8] s>> Imm_shr_imm8:1;
+ TMPQ1[112,8] = Rn_VPR128.16B[112,8] s>> Imm_shr_imm8:1;
+ TMPQ1[120,8] = Rn_VPR128.16B[120,8] s>> Imm_shr_imm8:1;
+ # simd infix Rd_VPR128.16B = Rd_VPR128.16B + TMPQ1 on lane size 1
+ Rd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] + TMPQ1[0,8];
+ Rd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] + TMPQ1[8,8];
+ Rd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] + TMPQ1[16,8];
+ Rd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] + TMPQ1[24,8];
+ Rd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] + TMPQ1[32,8];
+ Rd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] + TMPQ1[40,8];
+ Rd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] + TMPQ1[48,8];
+ Rd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] + TMPQ1[56,8];
+ Rd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] + TMPQ1[64,8];
+ Rd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] + TMPQ1[72,8];
+ Rd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] + TMPQ1[80,8];
+ Rd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] + TMPQ1[88,8];
+ Rd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] + TMPQ1[96,8];
+ Rd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] + TMPQ1[104,8];
+ Rd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] + TMPQ1[112,8];
+ Rd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] + TMPQ1[120,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00
+# CONSTRUCT x4f403400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 zext:8 $s>>@8 &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@8
+# AUNIT --inst x4f403400/mask=xffc0fc00 --status fail --comment "nointround"
+
+:srsra Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x6 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ local tmp1:8 = zext(Imm_shr_imm64);
+ # simd infix TMPQ1 = Rn_VPR128.2D s>> tmp1 on lane size 8
+ TMPQ1[0,64] = Rn_VPR128.2D[0,64] s>> tmp1;
+ TMPQ1[64,64] = Rn_VPR128.2D[64,64] s>> tmp1;
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ1 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ1[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ1[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00
+# CONSTRUCT x0f203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:4 $s>>@4 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@4
+# AUNIT --inst x0f203400/mask=xffe0fc00 --status fail --comment "nointround"
+
+:srsra Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x6 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ # simd infix TMPD1 = Rn_VPR64.2S s>> Imm_shr_imm32:4 on lane size 4
+ TMPD1[0,32] = Rn_VPR64.2S[0,32] s>> Imm_shr_imm32:4;
+ TMPD1[32,32] = Rn_VPR64.2S[32,32] s>> Imm_shr_imm32:4;
+ # simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4
+ Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32];
+ Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00
+# CONSTRUCT x0f103400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:2 $s>>@2 &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@2
+# AUNIT --inst x0f103400/mask=xfff0fc00 --status fail --comment "nointround"
+
+:srsra Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x6 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ # simd infix TMPD1 = Rn_VPR64.4H s>> Imm_shr_imm16:2 on lane size 2
+ TMPD1[0,16] = Rn_VPR64.4H[0,16] s>> Imm_shr_imm16:2;
+ TMPD1[16,16] = Rn_VPR64.4H[16,16] s>> Imm_shr_imm16:2;
+ TMPD1[32,16] = Rn_VPR64.4H[32,16] s>> Imm_shr_imm16:2;
+ TMPD1[48,16] = Rn_VPR64.4H[48,16] s>> Imm_shr_imm16:2;
+ # simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2
+ Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16];
+ Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16];
+ Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16];
+ Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00
+# CONSTRUCT x4f203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:4 $s>>@4 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@4
+# AUNIT --inst x4f203400/mask=xffe0fc00 --status fail --comment "nointround"
+
+:srsra Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x6 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.4S s>> Imm_shr_imm32:4 on lane size 4
+ TMPQ1[0,32] = Rn_VPR128.4S[0,32] s>> Imm_shr_imm32:4;
+ TMPQ1[32,32] = Rn_VPR128.4S[32,32] s>> Imm_shr_imm32:4;
+ TMPQ1[64,32] = Rn_VPR128.4S[64,32] s>> Imm_shr_imm32:4;
+ TMPQ1[96,32] = Rn_VPR128.4S[96,32] s>> Imm_shr_imm32:4;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00
+# CONSTRUCT x0f083400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:1 $s>>@1 &=$+@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@1
+# AUNIT --inst x0f083400/mask=xfff8fc00 --status fail --comment "nointround"
+
+:srsra Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x6 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ # simd infix TMPD1 = Rn_VPR64.8B s>> Imm_shr_imm8:1 on lane size 1
+ TMPD1[0,8] = Rn_VPR64.8B[0,8] s>> Imm_shr_imm8:1;
+ TMPD1[8,8] = Rn_VPR64.8B[8,8] s>> Imm_shr_imm8:1;
+ TMPD1[16,8] = Rn_VPR64.8B[16,8] s>> Imm_shr_imm8:1;
+ TMPD1[24,8] = Rn_VPR64.8B[24,8] s>> Imm_shr_imm8:1;
+ TMPD1[32,8] = Rn_VPR64.8B[32,8] s>> Imm_shr_imm8:1;
+ TMPD1[40,8] = Rn_VPR64.8B[40,8] s>> Imm_shr_imm8:1;
+ TMPD1[48,8] = Rn_VPR64.8B[48,8] s>> Imm_shr_imm8:1;
+ TMPD1[56,8] = Rn_VPR64.8B[56,8] s>> Imm_shr_imm8:1;
+ # simd infix Rd_VPR64.8B = Rd_VPR64.8B + TMPD1 on lane size 1
+ Rd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] + TMPD1[0,8];
+ Rd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] + TMPD1[8,8];
+ Rd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] + TMPD1[16,8];
+ Rd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] + TMPD1[24,8];
+ Rd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] + TMPD1[32,8];
+ Rd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] + TMPD1[40,8];
+ Rd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] + TMPD1[48,8];
+ Rd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] + TMPD1[56,8];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x0f003400/mask=xbf80fc00
+# CONSTRUCT x4f103400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:2 $s>>@2 &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3@2
+# AUNIT --inst x4f103400/mask=xfff0fc00 --status fail --comment "nointround"
+
+:srsra Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x6 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.8H s>> Imm_shr_imm16:2 on lane size 2
+ TMPQ1[0,16] = Rn_VPR128.8H[0,16] s>> Imm_shr_imm16:2;
+ TMPQ1[16,16] = Rn_VPR128.8H[16,16] s>> Imm_shr_imm16:2;
+ TMPQ1[32,16] = Rn_VPR128.8H[32,16] s>> Imm_shr_imm16:2;
+ TMPQ1[48,16] = Rn_VPR128.8H[48,16] s>> Imm_shr_imm16:2;
+ TMPQ1[64,16] = Rn_VPR128.8H[64,16] s>> Imm_shr_imm16:2;
+ TMPQ1[80,16] = Rn_VPR128.8H[80,16] s>> Imm_shr_imm16:2;
+ TMPQ1[96,16] = Rn_VPR128.8H[96,16] s>> Imm_shr_imm16:2;
+ TMPQ1[112,16] = Rn_VPR128.8H[112,16] s>> Imm_shr_imm16:2;
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.314 SRSRA page C7-2730 line 159316 MATCH x5f003400/mask=xff80fc00
+# CONSTRUCT x5f403400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 zext:8 s>> &=+
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_srsra/3
+# AUNIT --inst x5f403400/mask=xffc0fc00 --status fail --comment "nointround"
+
+:srsra Rd_FPR64, Rn_FPR64, Imm_shr_imm64
+is b_2331=0b010111110 & b_22=1 & b_1015=0b001101 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd
+{
+ local tmp1:8 = zext(Imm_shr_imm64);
+ local tmp2:8 = Rn_FPR64 s>> tmp1;
+ Rd_FPR64 = Rd_FPR64 + tmp2;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.315 SSHL page C7-2733 line 159467 MATCH x5e204400/mask=xff20fc00
+# CONSTRUCT x5ee04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2
+# AUNIT --inst x5ee04400/mask=xffe0fc00 --status nopcodeop
+
+:sshl Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_3031=1 & u=0 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x8 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_sshl(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.315 SSHL page C7-2733 line 159467 MATCH x0e204400/mask=xbf20fc00
+# CONSTRUCT x4e204400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@1
+# AUNIT --inst x4e204400/mask=xffe0fc00 --status nopcodeop
+
+:sshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x8 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_sshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.315 SSHL page C7-2733 line 159467 MATCH x0e204400/mask=xbf20fc00
+# CONSTRUCT x4ee04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@8
+# AUNIT --inst x4ee04400/mask=xffe0fc00 --status nopcodeop
+
+:sshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x8 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_sshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.315 SSHL page C7-2733 line 159467 MATCH x0e204400/mask=xbf20fc00
+# CONSTRUCT x0ea04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@4
+# AUNIT --inst x0ea04400/mask=xffe0fc00 --status nopcodeop
+
+:sshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x8 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_sshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.315 SSHL page C7-2733 line 159467 MATCH x0e204400/mask=xbf20fc00
+# CONSTRUCT x0e604400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@2
+# AUNIT --inst x0e604400/mask=xffe0fc00 --status nopcodeop
+
+:sshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x8 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_sshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.315 SSHL page C7-2733 line 159467 MATCH x0e204400/mask=xbf20fc00
+# CONSTRUCT x4ea04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@4
+# AUNIT --inst x4ea04400/mask=xffe0fc00 --status nopcodeop
+
+:sshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x8 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_sshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.315 SSHL page C7-2733 line 159467 MATCH x0e204400/mask=xbf20fc00
+# CONSTRUCT x0e204400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@1
+# AUNIT --inst x0e204400/mask=xffe0fc00 --status nopcodeop
+
+:sshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x8 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_sshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.315 SSHL page C7-2733 line 159467 MATCH x0e204400/mask=xbf20fc00
+# CONSTRUCT x4e604400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sshl/2@2
+# AUNIT --inst x4e604400/mask=xffe0fc00 --status nopcodeop
+
+:sshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x8 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_sshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00
+# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00
+# CONSTRUCT x4f08a400/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3 =var:2 =$<<@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshll2/2@1
+# AUNIT --inst x4f08a400/mask=xfff8fc00 --status pass --comment "ext"
+
+:sshll2 Rd_VPR128.8H, Rn_VPR128.16B, Imm_uimm3
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0x14 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
+{
+ TMPD1 = Rn_VPR128.16B[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)
+ TMPQ2[0,16] = sext(TMPD1[0,8]);
+ TMPQ2[16,16] = sext(TMPD1[8,8]);
+ TMPQ2[32,16] = sext(TMPD1[16,8]);
+ TMPQ2[48,16] = sext(TMPD1[24,8]);
+ TMPQ2[64,16] = sext(TMPD1[32,8]);
+ TMPQ2[80,16] = sext(TMPD1[40,8]);
+ TMPQ2[96,16] = sext(TMPD1[48,8]);
+ TMPQ2[112,16] = sext(TMPD1[56,8]);
+ local tmp3:2 = Imm_uimm3;
+ # simd infix Rd_VPR128.8H = TMPQ2 << tmp3 on lane size 2
+ Rd_VPR128.8H[0,16] = TMPQ2[0,16] << tmp3;
+ Rd_VPR128.8H[16,16] = TMPQ2[16,16] << tmp3;
+ Rd_VPR128.8H[32,16] = TMPQ2[32,16] << tmp3;
+ Rd_VPR128.8H[48,16] = TMPQ2[48,16] << tmp3;
+ Rd_VPR128.8H[64,16] = TMPQ2[64,16] << tmp3;
+ Rd_VPR128.8H[80,16] = TMPQ2[80,16] << tmp3;
+ Rd_VPR128.8H[96,16] = TMPQ2[96,16] << tmp3;
+ Rd_VPR128.8H[112,16] = TMPQ2[112,16] << tmp3;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00
+# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00
+# CONSTRUCT x0f20a400/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@4:16 ARG3 =var:8 =$<<@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshll/2@4
+# AUNIT --inst x0f20a400/mask=xffe0fc00 --status pass --comment "ext"
+
+:sshll Rd_VPR128.2D, Rn_VPR64.2S, Imm_uimm5
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0x14 & b_1010=1 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
+ local tmp2:8 = Imm_uimm5;
+ # simd infix Rd_VPR128.2D = TMPQ1 << tmp2 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ1[0,64] << tmp2;
+ Rd_VPR128.2D[64,64] = TMPQ1[64,64] << tmp2;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00
+# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00
+# CONSTRUCT x0f10a400/mask=xfff0fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@2:16 ARG3 =var:4 =$<<@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshll/2@2
+# AUNIT --inst x0f10a400/mask=xfff0fc00 --status pass --comment "ext"
+
+:sshll Rd_VPR128.4S, Rn_VPR64.4H, Imm_uimm4
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0x14 & b_1010=1 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
+ local tmp2:4 = Imm_uimm4;
+ # simd infix Rd_VPR128.4S = TMPQ1 << tmp2 on lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ1[0,32] << tmp2;
+ Rd_VPR128.4S[32,32] = TMPQ1[32,32] << tmp2;
+ Rd_VPR128.4S[64,32] = TMPQ1[64,32] << tmp2;
+ Rd_VPR128.4S[96,32] = TMPQ1[96,32] << tmp2;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00
+# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00
+# CONSTRUCT x4f20a400/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3 =var:8 =$<<@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshll2/2@4
+# AUNIT --inst x4f20a400/mask=xffe0fc00 --status pass --comment "ext"
+
+:sshll2 Rd_VPR128.2D, Rn_VPR128.4S, Imm_uimm5
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0x14 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(TMPD1[0,32]);
+ TMPQ2[64,64] = sext(TMPD1[32,32]);
+ local tmp3:8 = Imm_uimm5;
+ # simd infix Rd_VPR128.2D = TMPQ2 << tmp3 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ2[0,64] << tmp3;
+ Rd_VPR128.2D[64,64] = TMPQ2[64,64] << tmp3;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00
+# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00
+# CONSTRUCT x0f08a400/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@1:16 ARG3 =var:2 =$<<@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshll/2@1
+# AUNIT --inst x0f08a400/mask=xfff8fc00 --status pass --comment "ext"
+
+:sshll Rd_VPR128.8H, Rn_VPR64.8B, Imm_uimm3
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0x14 & b_1010=1 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)
+ TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);
+ TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);
+ TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);
+ TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);
+ TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);
+ TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);
+ TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);
+ TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);
+ local tmp2:2 = Imm_uimm3;
+ # simd infix Rd_VPR128.8H = TMPQ1 << tmp2 on lane size 2
+ Rd_VPR128.8H[0,16] = TMPQ1[0,16] << tmp2;
+ Rd_VPR128.8H[16,16] = TMPQ1[16,16] << tmp2;
+ Rd_VPR128.8H[32,16] = TMPQ1[32,16] << tmp2;
+ Rd_VPR128.8H[48,16] = TMPQ1[48,16] << tmp2;
+ Rd_VPR128.8H[64,16] = TMPQ1[64,16] << tmp2;
+ Rd_VPR128.8H[80,16] = TMPQ1[80,16] << tmp2;
+ Rd_VPR128.8H[96,16] = TMPQ1[96,16] << tmp2;
+ Rd_VPR128.8H[112,16] = TMPQ1[112,16] << tmp2;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00
+# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00
+# CONSTRUCT x4f10a400/mask=xfff0fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3 =var:4 =$<<@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshll2/2@2
+# AUNIT --inst x4f10a400/mask=xfff0fc00 --status pass --comment "ext"
+
+:sshll2 Rd_VPR128.4S, Rn_VPR128.8H, Imm_uimm4
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0x14 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(TMPD1[0,16]);
+ TMPQ2[32,32] = sext(TMPD1[16,16]);
+ TMPQ2[64,32] = sext(TMPD1[32,16]);
+ TMPQ2[96,32] = sext(TMPD1[48,16]);
+ local tmp3:4 = Imm_uimm4;
+ # simd infix Rd_VPR128.4S = TMPQ2 << tmp3 on lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ2[0,32] << tmp3;
+ Rd_VPR128.4S[32,32] = TMPQ2[32,32] << tmp3;
+ Rd_VPR128.4S[64,32] = TMPQ2[64,32] << tmp3;
+ Rd_VPR128.4S[96,32] = TMPQ2[96,32] << tmp3;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.317 SSHR page C7-2738 line 159757 MATCH x5f000400/mask=xff80fc00
+# CONSTRUCT x5f400400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2
+# AUNIT --inst x5f400400/mask=xffc0fc00 --status nopcodeop
+
+:sshr Rd_FPR64, Rn_FPR64, Imm_shr_imm64
+is b_3031=1 & u=0 & b_2428=0x1f & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x0 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_sshr(Rn_FPR64, Imm_shr_imm64:1);
+}
+
+# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00
+# CONSTRUCT x4f080400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:1 =$s>>@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@1
+# AUNIT --inst x4f080400/mask=xfff8fc00 --status pass
+
+:sshr Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x0 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ # simd infix Rd_VPR128.16B = Rn_VPR128.16B s>> Imm_shr_imm8:1 on lane size 1
+ Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] s>> Imm_shr_imm8:1;
+ Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] s>> Imm_shr_imm8:1;
+ Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] s>> Imm_shr_imm8:1;
+ Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] s>> Imm_shr_imm8:1;
+ Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] s>> Imm_shr_imm8:1;
+ Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] s>> Imm_shr_imm8:1;
+ Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] s>> Imm_shr_imm8:1;
+ Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] s>> Imm_shr_imm8:1;
+ Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] s>> Imm_shr_imm8:1;
+ Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] s>> Imm_shr_imm8:1;
+ Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] s>> Imm_shr_imm8:1;
+ Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] s>> Imm_shr_imm8:1;
+ Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] s>> Imm_shr_imm8:1;
+ Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] s>> Imm_shr_imm8:1;
+ Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] s>> Imm_shr_imm8:1;
+ Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] s>> Imm_shr_imm8:1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00
+# CONSTRUCT x4f400400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 zext:8 =$s>>@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@8
+# AUNIT --inst x4f400400/mask=xffc0fc00 --status pass
+
+:sshr Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x0 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ local tmp1:8 = zext(Imm_shr_imm64);
+ # simd infix Rd_VPR128.2D = Rn_VPR128.2D s>> tmp1 on lane size 8
+ Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] s>> tmp1;
+ Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] s>> tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00
+# CONSTRUCT x0f200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =var:4 =$s>>@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@4
+# AUNIT --inst x0f200400/mask=xffe0fc00 --status pass
+
+:sshr Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x0 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ local tmp1:4 = Imm_shr_imm32;
+ # simd infix Rd_VPR64.2S = Rn_VPR64.2S s>> tmp1 on lane size 4
+ Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] s>> tmp1;
+ Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] s>> tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00
+# CONSTRUCT x0f100400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:2 =$s>>@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@2
+# AUNIT --inst x0f100400/mask=xfff0fc00 --status pass
+
+:sshr Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x0 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ # simd infix Rd_VPR64.4H = Rn_VPR64.4H s>> Imm_shr_imm16:2 on lane size 2
+ Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] s>> Imm_shr_imm16:2;
+ Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] s>> Imm_shr_imm16:2;
+ Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] s>> Imm_shr_imm16:2;
+ Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] s>> Imm_shr_imm16:2;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00
+# CONSTRUCT x4f200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =var:4 =$s>>@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@4
+# AUNIT --inst x4f200400/mask=xffe0fc00 --status pass
+
+:sshr Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x0 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ local tmp1:4 = Imm_shr_imm32;
+ # simd infix Rd_VPR128.4S = Rn_VPR128.4S s>> tmp1 on lane size 4
+ Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] s>> tmp1;
+ Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] s>> tmp1;
+ Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] s>> tmp1;
+ Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] s>> tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00
+# CONSTRUCT x0f080400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:1 =$s>>@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@1
+# AUNIT --inst x0f080400/mask=xfff8fc00 --status pass
+
+:sshr Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x0 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ # simd infix Rd_VPR64.8B = Rn_VPR64.8B s>> Imm_shr_imm8:1 on lane size 1
+ Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] s>> Imm_shr_imm8:1;
+ Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] s>> Imm_shr_imm8:1;
+ Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] s>> Imm_shr_imm8:1;
+ Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] s>> Imm_shr_imm8:1;
+ Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] s>> Imm_shr_imm8:1;
+ Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] s>> Imm_shr_imm8:1;
+ Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] s>> Imm_shr_imm8:1;
+ Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] s>> Imm_shr_imm8:1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.317 SSHR page C7-2738 line 159757 MATCH x0f000400/mask=xbf80fc00
+# CONSTRUCT x4f100400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:2 =$s>>@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_sshr/2@2
+# AUNIT --inst x4f100400/mask=xfff0fc00 --status pass
+
+:sshr Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x0 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ # simd infix Rd_VPR128.8H = Rn_VPR128.8H s>> Imm_shr_imm16:2 on lane size 2
+ Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] s>> Imm_shr_imm16:2;
+ Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] s>> Imm_shr_imm16:2;
+ Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] s>> Imm_shr_imm16:2;
+ Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] s>> Imm_shr_imm16:2;
+ Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] s>> Imm_shr_imm16:2;
+ Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] s>> Imm_shr_imm16:2;
+ Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] s>> Imm_shr_imm16:2;
+ Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] s>> Imm_shr_imm16:2;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00
+# CONSTRUCT x4f081400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:1 $s>>@1 &=$+@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@1
+# AUNIT --inst x4f081400/mask=xfff8fc00 --status pass
+
+:ssra Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x2 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.16B s>> Imm_shr_imm8:1 on lane size 1
+ TMPQ1[0,8] = Rn_VPR128.16B[0,8] s>> Imm_shr_imm8:1;
+ TMPQ1[8,8] = Rn_VPR128.16B[8,8] s>> Imm_shr_imm8:1;
+ TMPQ1[16,8] = Rn_VPR128.16B[16,8] s>> Imm_shr_imm8:1;
+ TMPQ1[24,8] = Rn_VPR128.16B[24,8] s>> Imm_shr_imm8:1;
+ TMPQ1[32,8] = Rn_VPR128.16B[32,8] s>> Imm_shr_imm8:1;
+ TMPQ1[40,8] = Rn_VPR128.16B[40,8] s>> Imm_shr_imm8:1;
+ TMPQ1[48,8] = Rn_VPR128.16B[48,8] s>> Imm_shr_imm8:1;
+ TMPQ1[56,8] = Rn_VPR128.16B[56,8] s>> Imm_shr_imm8:1;
+ TMPQ1[64,8] = Rn_VPR128.16B[64,8] s>> Imm_shr_imm8:1;
+ TMPQ1[72,8] = Rn_VPR128.16B[72,8] s>> Imm_shr_imm8:1;
+ TMPQ1[80,8] = Rn_VPR128.16B[80,8] s>> Imm_shr_imm8:1;
+ TMPQ1[88,8] = Rn_VPR128.16B[88,8] s>> Imm_shr_imm8:1;
+ TMPQ1[96,8] = Rn_VPR128.16B[96,8] s>> Imm_shr_imm8:1;
+ TMPQ1[104,8] = Rn_VPR128.16B[104,8] s>> Imm_shr_imm8:1;
+ TMPQ1[112,8] = Rn_VPR128.16B[112,8] s>> Imm_shr_imm8:1;
+ TMPQ1[120,8] = Rn_VPR128.16B[120,8] s>> Imm_shr_imm8:1;
+ # simd infix Rd_VPR128.16B = Rd_VPR128.16B + TMPQ1 on lane size 1
+ Rd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] + TMPQ1[0,8];
+ Rd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] + TMPQ1[8,8];
+ Rd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] + TMPQ1[16,8];
+ Rd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] + TMPQ1[24,8];
+ Rd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] + TMPQ1[32,8];
+ Rd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] + TMPQ1[40,8];
+ Rd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] + TMPQ1[48,8];
+ Rd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] + TMPQ1[56,8];
+ Rd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] + TMPQ1[64,8];
+ Rd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] + TMPQ1[72,8];
+ Rd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] + TMPQ1[80,8];
+ Rd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] + TMPQ1[88,8];
+ Rd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] + TMPQ1[96,8];
+ Rd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] + TMPQ1[104,8];
+ Rd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] + TMPQ1[112,8];
+ Rd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] + TMPQ1[120,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00
+# CONSTRUCT x4f401400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 zext:8 $s>>@8 &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@8
+# AUNIT --inst x4f401400/mask=xffc0fc00 --status pass
+
+:ssra Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x2 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ local tmp1:8 = zext(Imm_shr_imm64);
+ # simd infix TMPQ1 = Rn_VPR128.2D s>> tmp1 on lane size 8
+ TMPQ1[0,64] = Rn_VPR128.2D[0,64] s>> tmp1;
+ TMPQ1[64,64] = Rn_VPR128.2D[64,64] s>> tmp1;
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ1 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ1[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ1[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00
+# CONSTRUCT x0f201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =var:4 $s>>@4 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@4
+# AUNIT --inst x0f201400/mask=xffe0fc00 --status pass
+
+:ssra Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x2 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ local tmp1:4 = Imm_shr_imm32;
+ # simd infix TMPD1 = Rn_VPR64.2S s>> tmp1 on lane size 4
+ TMPD1[0,32] = Rn_VPR64.2S[0,32] s>> tmp1;
+ TMPD1[32,32] = Rn_VPR64.2S[32,32] s>> tmp1;
+ # simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4
+ Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32];
+ Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00
+# CONSTRUCT x0f101400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:2 $s>>@2 &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@2
+# AUNIT --inst x0f101400/mask=xfff0fc00 --status pass
+
+:ssra Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x2 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ # simd infix TMPD1 = Rn_VPR64.4H s>> Imm_shr_imm16:2 on lane size 2
+ TMPD1[0,16] = Rn_VPR64.4H[0,16] s>> Imm_shr_imm16:2;
+ TMPD1[16,16] = Rn_VPR64.4H[16,16] s>> Imm_shr_imm16:2;
+ TMPD1[32,16] = Rn_VPR64.4H[32,16] s>> Imm_shr_imm16:2;
+ TMPD1[48,16] = Rn_VPR64.4H[48,16] s>> Imm_shr_imm16:2;
+ # simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2
+ Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16];
+ Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16];
+ Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16];
+ Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00
+# CONSTRUCT x4f201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =var:4 $s>>@4 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@4
+# AUNIT --inst x4f201400/mask=xffe0fc00 --status pass
+
+:ssra Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x2 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ local tmp1:4 = Imm_shr_imm32;
+ # simd infix TMPQ1 = Rn_VPR128.4S s>> tmp1 on lane size 4
+ TMPQ1[0,32] = Rn_VPR128.4S[0,32] s>> tmp1;
+ TMPQ1[32,32] = Rn_VPR128.4S[32,32] s>> tmp1;
+ TMPQ1[64,32] = Rn_VPR128.4S[64,32] s>> tmp1;
+ TMPQ1[96,32] = Rn_VPR128.4S[96,32] s>> tmp1;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00
+# CONSTRUCT x0f081400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:1 $s>>@1 &=$+@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@1
+# AUNIT --inst x0f081400/mask=xfff8fc00 --status pass
+
+:ssra Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x2 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ # simd infix TMPD1 = Rn_VPR64.8B s>> Imm_shr_imm8:1 on lane size 1
+ TMPD1[0,8] = Rn_VPR64.8B[0,8] s>> Imm_shr_imm8:1;
+ TMPD1[8,8] = Rn_VPR64.8B[8,8] s>> Imm_shr_imm8:1;
+ TMPD1[16,8] = Rn_VPR64.8B[16,8] s>> Imm_shr_imm8:1;
+ TMPD1[24,8] = Rn_VPR64.8B[24,8] s>> Imm_shr_imm8:1;
+ TMPD1[32,8] = Rn_VPR64.8B[32,8] s>> Imm_shr_imm8:1;
+ TMPD1[40,8] = Rn_VPR64.8B[40,8] s>> Imm_shr_imm8:1;
+ TMPD1[48,8] = Rn_VPR64.8B[48,8] s>> Imm_shr_imm8:1;
+ TMPD1[56,8] = Rn_VPR64.8B[56,8] s>> Imm_shr_imm8:1;
+ # simd infix Rd_VPR64.8B = Rd_VPR64.8B + TMPD1 on lane size 1
+ Rd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] + TMPD1[0,8];
+ Rd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] + TMPD1[8,8];
+ Rd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] + TMPD1[16,8];
+ Rd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] + TMPD1[24,8];
+ Rd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] + TMPD1[32,8];
+ Rd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] + TMPD1[40,8];
+ Rd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] + TMPD1[48,8];
+ Rd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] + TMPD1[56,8];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.318 SSRA page C7-2741 line 159921 MATCH x0f001400/mask=xbf80fc00
+# CONSTRUCT x4f101400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:2 $s>>@2 &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3@2
+# AUNIT --inst x4f101400/mask=xfff0fc00 --status pass
+
+:ssra Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x2 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.8H s>> Imm_shr_imm16:2 on lane size 2
+ TMPQ1[0,16] = Rn_VPR128.8H[0,16] s>> Imm_shr_imm16:2;
+ TMPQ1[16,16] = Rn_VPR128.8H[16,16] s>> Imm_shr_imm16:2;
+ TMPQ1[32,16] = Rn_VPR128.8H[32,16] s>> Imm_shr_imm16:2;
+ TMPQ1[48,16] = Rn_VPR128.8H[48,16] s>> Imm_shr_imm16:2;
+ TMPQ1[64,16] = Rn_VPR128.8H[64,16] s>> Imm_shr_imm16:2;
+ TMPQ1[80,16] = Rn_VPR128.8H[80,16] s>> Imm_shr_imm16:2;
+ TMPQ1[96,16] = Rn_VPR128.8H[96,16] s>> Imm_shr_imm16:2;
+ TMPQ1[112,16] = Rn_VPR128.8H[112,16] s>> Imm_shr_imm16:2;
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.318 SSRA page C7-2741 line 159921 MATCH x5f001400/mask=xff80fc00
+# CONSTRUCT x5f401400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 zext:8 s>> &=+
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ssra/3
+# AUNIT --inst x5f401400/mask=xffc0fc00 --status pass
+
+:ssra Rd_FPR64, Rn_FPR64, Imm_shr_imm64
+is b_2331=0b010111110 & b_22=1 & b_1015=0b000101 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd
+{
+ local tmp1:8 = zext(Imm_shr_imm64);
+ local tmp2:8 = Rn_FPR64 s>> tmp1;
+ Rd_FPR64 = Rd_FPR64 + tmp2;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.319 SSUBL, SSUBL2 page C7-2744 line 160085 MATCH x0e202000/mask=xbf20fc00
+# CONSTRUCT x4ea02000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@4:16 ARG3[1]:8 $sext@4:16 =$-@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubl2/2@4
+# AUNIT --inst x4ea02000/mask=xffe0fc00 --status pass --comment "ext"
+
+:ssubl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x2 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(TMPD1[0,32]);
+ TMPQ2[64,64] = sext(TMPD1[32,32]);
+ TMPD3 = Rm_VPR128.4S[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 4 to 8)
+ TMPQ4[0,64] = sext(TMPD3[0,32]);
+ TMPQ4[64,64] = sext(TMPD3[32,32]);
+ # simd infix Rd_VPR128.2D = TMPQ2 - TMPQ4 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ2[0,64] - TMPQ4[0,64];
+ Rd_VPR128.2D[64,64] = TMPQ2[64,64] - TMPQ4[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.319 SSUBL, SSUBL2 page C7-2744 line 160085 MATCH x0e202000/mask=xbf20fc00
+# CONSTRUCT x4e602000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@2:16 ARG3[1]:8 $sext@2:16 =$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubl2/2@2
+# AUNIT --inst x4e602000/mask=xffe0fc00 --status pass --comment "ext"
+
+:ssubl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x2 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(TMPD1[0,16]);
+ TMPQ2[32,32] = sext(TMPD1[16,16]);
+ TMPQ2[64,32] = sext(TMPD1[32,16]);
+ TMPQ2[96,32] = sext(TMPD1[48,16]);
+ TMPD3 = Rm_VPR128.8H[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 2 to 4)
+ TMPQ4[0,32] = sext(TMPD3[0,16]);
+ TMPQ4[32,32] = sext(TMPD3[16,16]);
+ TMPQ4[64,32] = sext(TMPD3[32,16]);
+ TMPQ4[96,32] = sext(TMPD3[48,16]);
+ # simd infix Rd_VPR128.4S = TMPQ2 - TMPQ4 on lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ2[0,32] - TMPQ4[0,32];
+ Rd_VPR128.4S[32,32] = TMPQ2[32,32] - TMPQ4[32,32];
+ Rd_VPR128.4S[64,32] = TMPQ2[64,32] - TMPQ4[64,32];
+ Rd_VPR128.4S[96,32] = TMPQ2[96,32] - TMPQ4[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.319 SSUBL, SSUBL2 page C7-2744 line 160085 MATCH x0e202000/mask=xbf20fc00
+# CONSTRUCT x4e202000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $sext@1:16 ARG3[1]:8 $sext@1:16 =$-@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubl2/2@1
+# AUNIT --inst x4e202000/mask=xffe0fc00 --status pass --comment "ext"
+
+:ssubl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x2 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
+{
+ TMPD1 = Rn_VPR128.16B[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)
+ TMPQ2[0,16] = sext(TMPD1[0,8]);
+ TMPQ2[16,16] = sext(TMPD1[8,8]);
+ TMPQ2[32,16] = sext(TMPD1[16,8]);
+ TMPQ2[48,16] = sext(TMPD1[24,8]);
+ TMPQ2[64,16] = sext(TMPD1[32,8]);
+ TMPQ2[80,16] = sext(TMPD1[40,8]);
+ TMPQ2[96,16] = sext(TMPD1[48,8]);
+ TMPQ2[112,16] = sext(TMPD1[56,8]);
+ TMPD3 = Rm_VPR128.16B[64,64];
+ # simd resize TMPQ4 = sext(TMPD3) (lane size 1 to 2)
+ TMPQ4[0,16] = sext(TMPD3[0,8]);
+ TMPQ4[16,16] = sext(TMPD3[8,8]);
+ TMPQ4[32,16] = sext(TMPD3[16,8]);
+ TMPQ4[48,16] = sext(TMPD3[24,8]);
+ TMPQ4[64,16] = sext(TMPD3[32,8]);
+ TMPQ4[80,16] = sext(TMPD3[40,8]);
+ TMPQ4[96,16] = sext(TMPD3[48,8]);
+ TMPQ4[112,16] = sext(TMPD3[56,8]);
+ # simd infix Rd_VPR128.8H = TMPQ2 - TMPQ4 on lane size 2
+ Rd_VPR128.8H[0,16] = TMPQ2[0,16] - TMPQ4[0,16];
+ Rd_VPR128.8H[16,16] = TMPQ2[16,16] - TMPQ4[16,16];
+ Rd_VPR128.8H[32,16] = TMPQ2[32,16] - TMPQ4[32,16];
+ Rd_VPR128.8H[48,16] = TMPQ2[48,16] - TMPQ4[48,16];
+ Rd_VPR128.8H[64,16] = TMPQ2[64,16] - TMPQ4[64,16];
+ Rd_VPR128.8H[80,16] = TMPQ2[80,16] - TMPQ4[80,16];
+ Rd_VPR128.8H[96,16] = TMPQ2[96,16] - TMPQ4[96,16];
+ Rd_VPR128.8H[112,16] = TMPQ2[112,16] - TMPQ4[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.319 SSUBL, SSUBL2 page C7-2744 line 160085 MATCH x0e202000/mask=xbf20fc00
+# CONSTRUCT x0ea02000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@4:16 ARG3 $sext@4:16 =$-@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubl/2@4
+# AUNIT --inst x0ea02000/mask=xffe0fc00 --status pass --comment "ext"
+
+:ssubl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x2 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = sext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = sext(Rn_VPR64.2S[32,32]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.2S) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(Rm_VPR64.2S[0,32]);
+ TMPQ2[64,64] = sext(Rm_VPR64.2S[32,32]);
+ # simd infix Rd_VPR128.2D = TMPQ1 - TMPQ2 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ1[0,64] - TMPQ2[0,64];
+ Rd_VPR128.2D[64,64] = TMPQ1[64,64] - TMPQ2[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.319 SSUBL, SSUBL2 page C7-2744 line 160085 MATCH x0e202000/mask=xbf20fc00
+# CONSTRUCT x0e602000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@2:16 ARG3 $sext@2:16 =$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubl/2@2
+# AUNIT --inst x0e602000/mask=xffe0fc00 --status pass --comment "ext"
+
+:ssubl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x2 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = sext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = sext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = sext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = sext(Rn_VPR64.4H[48,16]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.4H) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(Rm_VPR64.4H[0,16]);
+ TMPQ2[32,32] = sext(Rm_VPR64.4H[16,16]);
+ TMPQ2[64,32] = sext(Rm_VPR64.4H[32,16]);
+ TMPQ2[96,32] = sext(Rm_VPR64.4H[48,16]);
+ # simd infix Rd_VPR128.4S = TMPQ1 - TMPQ2 on lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ1[0,32] - TMPQ2[0,32];
+ Rd_VPR128.4S[32,32] = TMPQ1[32,32] - TMPQ2[32,32];
+ Rd_VPR128.4S[64,32] = TMPQ1[64,32] - TMPQ2[64,32];
+ Rd_VPR128.4S[96,32] = TMPQ1[96,32] - TMPQ2[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.319 SSUBL, SSUBL2 page C7-2744 line 160085 MATCH x0e202000/mask=xbf20fc00
+# CONSTRUCT x0e202000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $sext@1:16 ARG3 $sext@1:16 =$-@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubl/2@1
+# AUNIT --inst x0e202000/mask=xffe0fc00 --status pass --comment "ext"
+
+:ssubl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x2 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
+{
+ # simd resize TMPQ1 = sext(Rn_VPR64.8B) (lane size 1 to 2)
+ TMPQ1[0,16] = sext(Rn_VPR64.8B[0,8]);
+ TMPQ1[16,16] = sext(Rn_VPR64.8B[8,8]);
+ TMPQ1[32,16] = sext(Rn_VPR64.8B[16,8]);
+ TMPQ1[48,16] = sext(Rn_VPR64.8B[24,8]);
+ TMPQ1[64,16] = sext(Rn_VPR64.8B[32,8]);
+ TMPQ1[80,16] = sext(Rn_VPR64.8B[40,8]);
+ TMPQ1[96,16] = sext(Rn_VPR64.8B[48,8]);
+ TMPQ1[112,16] = sext(Rn_VPR64.8B[56,8]);
+ # simd resize TMPQ2 = sext(Rm_VPR64.8B) (lane size 1 to 2)
+ TMPQ2[0,16] = sext(Rm_VPR64.8B[0,8]);
+ TMPQ2[16,16] = sext(Rm_VPR64.8B[8,8]);
+ TMPQ2[32,16] = sext(Rm_VPR64.8B[16,8]);
+ TMPQ2[48,16] = sext(Rm_VPR64.8B[24,8]);
+ TMPQ2[64,16] = sext(Rm_VPR64.8B[32,8]);
+ TMPQ2[80,16] = sext(Rm_VPR64.8B[40,8]);
+ TMPQ2[96,16] = sext(Rm_VPR64.8B[48,8]);
+ TMPQ2[112,16] = sext(Rm_VPR64.8B[56,8]);
+ # simd infix Rd_VPR128.8H = TMPQ1 - TMPQ2 on lane size 2
+ Rd_VPR128.8H[0,16] = TMPQ1[0,16] - TMPQ2[0,16];
+ Rd_VPR128.8H[16,16] = TMPQ1[16,16] - TMPQ2[16,16];
+ Rd_VPR128.8H[32,16] = TMPQ1[32,16] - TMPQ2[32,16];
+ Rd_VPR128.8H[48,16] = TMPQ1[48,16] - TMPQ2[48,16];
+ Rd_VPR128.8H[64,16] = TMPQ1[64,16] - TMPQ2[64,16];
+ Rd_VPR128.8H[80,16] = TMPQ1[80,16] - TMPQ2[80,16];
+ Rd_VPR128.8H[96,16] = TMPQ1[96,16] - TMPQ2[96,16];
+ Rd_VPR128.8H[112,16] = TMPQ1[112,16] - TMPQ2[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.320 SSUBW, SSUBW2 page C7-2746 line 160208 MATCH x0e203000/mask=xbf20fc00
+# CONSTRUCT x4ea03000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3[1]:8 $sext@4:16 =$-@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubw2/2@4
+# AUNIT --inst x4ea03000/mask=xffe0fc00 --status pass --comment "ext"
+
+:ssubw2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x3 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Rm_VPR128 & Zd
+{
+ TMPD1 = Rm_VPR128.4S[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = sext(TMPD1[0,32]);
+ TMPQ2[64,64] = sext(TMPD1[32,32]);
+ # simd infix Rd_VPR128.2D = Rn_VPR128.2D - TMPQ2 on lane size 8
+ Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] - TMPQ2[0,64];
+ Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] - TMPQ2[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.320 SSUBW, SSUBW2 page C7-2746 line 160208 MATCH x0e203000/mask=xbf20fc00
+# CONSTRUCT x4e603000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3[1]:8 $sext@2:16 =$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubw2/2@2
+# AUNIT --inst x4e603000/mask=xffe0fc00 --status pass --comment "ext"
+
+:ssubw2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x3 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rm_VPR128.8H[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = sext(TMPD1[0,16]);
+ TMPQ2[32,32] = sext(TMPD1[16,16]);
+ TMPQ2[64,32] = sext(TMPD1[32,16]);
+ TMPQ2[96,32] = sext(TMPD1[48,16]);
+ # simd infix Rd_VPR128.4S = Rn_VPR128.4S - TMPQ2 on lane size 4
+ Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] - TMPQ2[0,32];
+ Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] - TMPQ2[32,32];
+ Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] - TMPQ2[64,32];
+ Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] - TMPQ2[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.320 SSUBW, SSUBW2 page C7-2746 line 160208 MATCH x0e203000/mask=xbf20fc00
+# CONSTRUCT x4e203000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3[1]:8 $sext@1:16 =$-@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubw2/2@1
+# AUNIT --inst x4e203000/mask=xffe0fc00 --status pass --comment "ext"
+
+:ssubw2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x3 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ TMPD1 = Rm_VPR128.16B[64,64];
+ # simd resize TMPQ2 = sext(TMPD1) (lane size 1 to 2)
+ TMPQ2[0,16] = sext(TMPD1[0,8]);
+ TMPQ2[16,16] = sext(TMPD1[8,8]);
+ TMPQ2[32,16] = sext(TMPD1[16,8]);
+ TMPQ2[48,16] = sext(TMPD1[24,8]);
+ TMPQ2[64,16] = sext(TMPD1[32,8]);
+ TMPQ2[80,16] = sext(TMPD1[40,8]);
+ TMPQ2[96,16] = sext(TMPD1[48,8]);
+ TMPQ2[112,16] = sext(TMPD1[56,8]);
+ # simd infix Rd_VPR128.8H = Rn_VPR128.8H - TMPQ2 on lane size 2
+ Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] - TMPQ2[0,16];
+ Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] - TMPQ2[16,16];
+ Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] - TMPQ2[32,16];
+ Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] - TMPQ2[48,16];
+ Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] - TMPQ2[64,16];
+ Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] - TMPQ2[80,16];
+ Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] - TMPQ2[96,16];
+ Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] - TMPQ2[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.320 SSUBW, SSUBW2 page C7-2746 line 160208 MATCH x0e203000/mask=xbf20fc00
+# CONSTRUCT x0ea03000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $sext@4:16 =$-@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubw/2@4
+# AUNIT --inst x0ea03000/mask=xffe0fc00 --status pass --comment "ext"
+
+:ssubw Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x3 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = sext(Rm_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = sext(Rm_VPR64.2S[0,32]);
+ TMPQ1[64,64] = sext(Rm_VPR64.2S[32,32]);
+ # simd infix Rd_VPR128.2D = Rn_VPR128.2D - TMPQ1 on lane size 8
+ Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] - TMPQ1[0,64];
+ Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] - TMPQ1[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.320 SSUBW, SSUBW2 page C7-2746 line 160208 MATCH x0e203000/mask=xbf20fc00
+# CONSTRUCT x0e603000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $sext@2:16 =$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubw/2@2
+# AUNIT --inst x0e603000/mask=xffe0fc00 --status pass --comment "ext"
+
+:ssubw Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x3 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = sext(Rm_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = sext(Rm_VPR64.4H[0,16]);
+ TMPQ1[32,32] = sext(Rm_VPR64.4H[16,16]);
+ TMPQ1[64,32] = sext(Rm_VPR64.4H[32,16]);
+ TMPQ1[96,32] = sext(Rm_VPR64.4H[48,16]);
+ # simd infix Rd_VPR128.4S = Rn_VPR128.4S - TMPQ1 on lane size 4
+ Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] - TMPQ1[0,32];
+ Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] - TMPQ1[32,32];
+ Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] - TMPQ1[64,32];
+ Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] - TMPQ1[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.320 SSUBW, SSUBW2 page C7-2746 line 160208 MATCH x0e203000/mask=xbf20fc00
+# CONSTRUCT x0e203000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $sext@1:16 =$-@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ssubw/2@1
+# AUNIT --inst x0e203000/mask=xffe0fc00 --status pass --comment "ext"
+
+:ssubw Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x3 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ # simd resize TMPQ1 = sext(Rm_VPR64.8B) (lane size 1 to 2)
+ TMPQ1[0,16] = sext(Rm_VPR64.8B[0,8]);
+ TMPQ1[16,16] = sext(Rm_VPR64.8B[8,8]);
+ TMPQ1[32,16] = sext(Rm_VPR64.8B[16,8]);
+ TMPQ1[48,16] = sext(Rm_VPR64.8B[24,8]);
+ TMPQ1[64,16] = sext(Rm_VPR64.8B[32,8]);
+ TMPQ1[80,16] = sext(Rm_VPR64.8B[40,8]);
+ TMPQ1[96,16] = sext(Rm_VPR64.8B[48,8]);
+ TMPQ1[112,16] = sext(Rm_VPR64.8B[56,8]);
+ # simd infix Rd_VPR128.8H = Rn_VPR128.8H - TMPQ1 on lane size 2
+ Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] - TMPQ1[0,16];
+ Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] - TMPQ1[16,16];
+ Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] - TMPQ1[32,16];
+ Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] - TMPQ1[48,16];
+ Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] - TMPQ1[64,16];
+ Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] - TMPQ1[80,16];
+ Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] - TMPQ1[96,16];
+ Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] - TMPQ1[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.329 STNP (SIMD&FP) page C7-2777 line 162166 MATCH x2c000000/mask=x3fc00000
+# CONSTRUCT x2c000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG3 =store pop ARG2 ARG3 4 +:8 =store pop
+# SMACRO(pseudo) null ARG1 ARG3 =NEON_stnp1/2 null ARG2 ARG3 =NEON_stnp2/2
+# AUNIT --inst x2c000000/mask=xffc00000 --status nomem
+
+:stnp Rt_FPR32, Rt2_FPR32, addrPairIndexed
+is b_3031=0b00 & b_2229=0b10110000 & Rt2_FPR32 & addrPairIndexed & Rt_FPR32
+{
+ * addrPairIndexed = Rt_FPR32;
+ local tmp1:8 = addrPairIndexed + 4;
+ * tmp1 = Rt2_FPR32;
+}
+
+# C7.2.329 STNP (SIMD&FP) page C7-2777 line 162166 MATCH x2c000000/mask=x3fc00000
+# CONSTRUCT x6c000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG3 =store pop ARG2 ARG3 8 +:8 =store pop
+# SMACRO(pseudo) null ARG1 ARG3 =NEON_stnp1/2 null ARG2 ARG3 =NEON_stnp2/2
+# AUNIT --inst x6c000000/mask=xffc00000 --status nomem
+
+:stnp Rt_FPR64, Rt2_FPR64, addrPairIndexed
+is b_3031=0b01 & b_2229=0b10110000 & Rt2_FPR64 & addrPairIndexed & Rt_FPR64
+{
+ * addrPairIndexed = Rt_FPR64;
+ local tmp1:8 = addrPairIndexed + 8;
+ * tmp1 = Rt2_FPR64;
+}
+
+# C7.2.329 STNP (SIMD&FP) page C7-2777 line 162166 MATCH x2c000000/mask=x3fc00000
+# CONSTRUCT xac000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG3 =store pop ARG2 ARG3 16 +:8 =store pop
+# SMACRO(pseudo) null ARG1 ARG3 =NEON_stnp1/2 null ARG2 ARG3 =NEON_stnp2/2
+# AUNIT --inst xac000000/mask=xffc00000 --status nomem
+
+:stnp Rt_FPR128, Rt2_FPR128, addrPairIndexed
+is b_3031=0b10 & b_2229=0b10110000 & Rt2_FPR64 & Rt2_FPR128 & addrPairIndexed & Rt_FPR128
+{
+ * addrPairIndexed = Rt_FPR128;
+ local tmp1:8 = addrPairIndexed + 16;
+ * tmp1 = Rt2_FPR128;
+}
+
+# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2c800000/mask=x3fc00000
+# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2d800000/mask=x3fc00000
+# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2d000000/mask=x3fc00000
+# C7.2.329 STNP (SIMD&FP) page C7-2777 line 162166 MATCH x2c000000/mask=x3fc00000
+# CONSTRUCT xac000000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG3 =store pop ARG2 ARG3 16 +:8 =store pop
+# SMACRO(pseudo) null ARG1 ARG3 =NEON_stp1/2 null ARG2 ARG3 =NEON_stp2/2
+# AUNIT --inst xac000000/mask=xfe400000 --status nomem
+# 128-bit variant (post-index, pre-index, and signed offset)
+
+:stp Rt_FPR128, Rt2_FPR128, addrPairIndexed
+is b_3031=0b10 & b_2529=0b10110 & b_22=0 & Rt2_FPR128 & addrPairIndexed & Rt_FPR128
+{
+ * addrPairIndexed = Rt_FPR128;
+ local tmp1:8 = addrPairIndexed + 16;
+ * tmp1 = Rt2_FPR128;
+}
+
+# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2c800000/mask=x3fc00000
+# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2d800000/mask=x3fc00000
+# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2d000000/mask=x3fc00000
+# C7.2.329 STNP (SIMD&FP) page C7-2777 line 162166 MATCH x2c000000/mask=x3fc00000
+# CONSTRUCT x2c000000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG3 =store pop ARG2 ARG3 4 +:8 =store pop
+# SMACRO(pseudo) null ARG1 ARG3 =NEON_stp1/2 null ARG2 ARG3 =NEON_stp2/2
+# AUNIT --inst x2c000000/mask=xfe400000 --status nomem
+# 32-bit variant (post-index, pre-index, and signed offset)
+
+:stp Rt_FPR32, Rt2_FPR32, addrPairIndexed
+is b_3031=0b00 & b_2529=0b10110 & b_22=0 & Rt2_FPR32 & addrPairIndexed & Rt_FPR32
+{
+ * addrPairIndexed = Rt_FPR32;
+ local tmp1:8 = addrPairIndexed + 4;
+ * tmp1 = Rt2_FPR32;
+}
+
+# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2c800000/mask=x3fc00000
+# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2d800000/mask=x3fc00000
+# C7.2.330 STP (SIMD&FP) page C7-2779 line 162288 MATCH x2d000000/mask=x3fc00000
+# C7.2.329 STNP (SIMD&FP) page C7-2777 line 162166 MATCH x2c000000/mask=x3fc00000
+# CONSTRUCT x6c000000/mask=xfe400000 MATCHED 4 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG3 =store pop ARG2 ARG3 8 +:8 =store pop
+# SMACRO(pseudo) null ARG1 ARG3 =NEON_stp1/2 null ARG2 ARG3 =NEON_stp2/2
+# AUNIT --inst x6c000000/mask=xfe400000 --status nomem
+# 64-bit variant (post-index, pre-index, and signed offset)
+
+:stp Rt_FPR64, Rt2_FPR64, addrPairIndexed
+is b_3031=0b01 & b_2529=0b10110 & b_22=0 & Rt2_FPR64 & addrPairIndexed & Rt_FPR64
+{
+ * addrPairIndexed = Rt_FPR64;
+ local tmp1:8 = addrPairIndexed + 8;
+ * tmp1 = Rt2_FPR64;
+}
+
+# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000400/mask=x3f600c00
+# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000c00/mask=x3f600c00
+# CONSTRUCT x3c000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =store pop
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2
+# AUNIT --inst x3c000400/mask=xffe00400 --status nomem
+# Post- and Pre-offset 8-bit variant when size == 00 && opc == 00 F=FPR8
+
+:str Rt_FPR8, addrIndexed
+is b_3031=0b00 & b_2429=0b111100 & b_2223=0b00 & b_21=0 & b_10=1 & Rt_FPR8 & addrIndexed & Zt
+{
+ * addrIndexed = Rt_FPR8;
+}
+
+# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000400/mask=x3f600c00
+# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000c00/mask=x3f600c00
+# CONSTRUCT x7c000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =store pop
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2
+# AUNIT --inst x7c000400/mask=xffe00400 --status nomem
+# Post- and Pre-offset 16-bit variant when size == 01 && opc == 00 F=FPR16
+
+:str Rt_FPR16, addrIndexed
+is b_3031=0b01 & b_2429=0b111100 & b_2223=0b00 & b_21=0 & b_10=1 & Rt_FPR16 & addrIndexed & Zt
+{
+ * addrIndexed = Rt_FPR16;
+}
+
+# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000400/mask=x3f600c00
+# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000c00/mask=x3f600c00
+# CONSTRUCT xbc000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =store pop
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2
+# AUNIT --inst xbc000400/mask=xffe00400 --status nomem
+# Post- and Pre-offset 32-bit variant when size == 10 && opc == 00 F=FPR32
+
+:str Rt_FPR32, addrIndexed
+is b_3031=0b10 & b_2429=0b111100 & b_2223=0b00 & b_21=0 & b_10=1 & Rt_FPR32 & addrIndexed & Zt
+{
+ * addrIndexed = Rt_FPR32;
+}
+
+# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000400/mask=x3f600c00
+# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000c00/mask=x3f600c00
+# CONSTRUCT xfc000400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =store pop
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2
+# AUNIT --inst xfc000400/mask=xffe00400 --status nomem
+# Post- and Pre-offset 64-bit variant when size == 11 && opc == 00 F=FPR64
+
+:str Rt_FPR64, addrIndexed
+is b_3031=0b11 & b_2429=0b111100 & b_2223=0b00 & b_21=0 & b_10=1 & Rt_FPR64 & addrIndexed & Zt
+{
+ * addrIndexed = Rt_FPR64;
+}
+
+# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000400/mask=x3f600c00
+# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3c000c00/mask=x3f600c00
+# CONSTRUCT x3c800400/mask=xffe00400 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =store pop
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2
+# AUNIT --inst x3c800400/mask=xffe00400 --status nomem
+# Post- and Pre-offset 128-bit variant when size == 00 && opc == 10 F=FPR128
+
+:str Rt_FPR128, addrIndexed
+is b_3031=0b00 & b_2429=0b111100 & b_2223=0b10 & b_21=0 & b_10=1 & Rt_FPR128 & addrIndexed & Zt
+{
+ * addrIndexed = Rt_FPR128;
+}
+
+# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3d000000/mask=x3f400000
+# CONSTRUCT x3d000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =store pop
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2
+# AUNIT --inst x3d000000/mask=xffc00000 --status nomem
+# Unsigned offset 8-bit variant when size == 00 && opc == 00 F=FPR8
+
+:str Rt_FPR8, addrUIMM
+is b_3031=0b00 & b_2429=0b111101 & b_2223=0b00 & Rt_FPR8 & addrUIMM & Zt
+{
+ * addrUIMM = Rt_FPR8;
+}
+
+# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3d000000/mask=x3f400000
+# CONSTRUCT x7d000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =store pop
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2
+# AUNIT --inst x7d000000/mask=xffc00000 --status nomem
+# Unsigned offset 16-bit variant when size == 01 && opc == 00 F=FPR16
+
+:str Rt_FPR16, addrUIMM
+is b_3031=0b01 & b_2429=0b111101 & b_2223=0b00 & Rt_FPR16 & addrUIMM & Zt
+{
+ * addrUIMM = Rt_FPR16;
+}
+
+# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3d000000/mask=x3f400000
+# CONSTRUCT xbd000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =store pop
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2
+# AUNIT --inst xbd000000/mask=xffc00000 --status nomem
+# Unsigned offset 32-bit variant when size == 10 && opc == 00 F=FPR32
+
+:str Rt_FPR32, addrUIMM
+is b_3031=0b10 & b_2429=0b111101 & b_2223=0b00 & Rt_FPR32 & addrUIMM & Zt
+{
+ * addrUIMM = Rt_FPR32;
+}
+
+# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3d000000/mask=x3f400000
+# CONSTRUCT xfd000000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =store pop
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2
+# AUNIT --inst xfd000000/mask=xffc00000 --status nomem
+# Unsigned offset 64-bit variant when size == 11 && opc == 00 F=FPR64
+
+:str Rt_FPR64, addrUIMM
+is b_3031=0b11 & b_2429=0b111101 & b_2223=0b00 & Rt_FPR64 & addrUIMM & Zt
+{
+ * addrUIMM = Rt_FPR64;
+}
+
+# C7.2.331 STR (immediate, SIMD&FP) page C7-2782 line 162501 MATCH x3d000000/mask=x3f400000
+# CONSTRUCT x3d800000/mask=xffc00000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =store pop
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_str/2
+# AUNIT --inst x3d800000/mask=xffc00000 --status nomem
+# Unsigned offset 128-bit variant when size == 00 && opc == 10 F=FPR128
+
+:str Rt_FPR128, addrUIMM
+is b_3031=0b00 & b_2429=0b111101 & b_2223=0b10 & Rt_FPR128 & addrUIMM & Zt
+{
+ * addrUIMM = Rt_FPR128;
+}
+
+# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00
+# CONSTRUCT x3c200800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop
+# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4
+# AUNIT --inst x3c200800/mask=xffe02c00 --status nomem
+# 8-fsreg,STR-8-fsreg variant when size == 00 && opc == 00 && option is not 011 bb=b_13 option=0 F=FPR8 G=GPR32
+
+:str Rt_FPR8, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]
+is b_3031=0b00 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR8 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zd
+{
+ local tmp1:8 = extend_spec << extend_amount;
+ local tmp2:8 = Rn_GPR64xsp + tmp1;
+ * tmp2 = Rt_FPR8;
+}
+
+# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00
+# CONSTRUCT x3c202800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop
+# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4
+# AUNIT --inst x3c202800/mask=xffe02c00 --status nomem
+# 8-fsreg,STR-8-fsreg variant when size == 00 && opc == 00 && option is not 011 bb=b_13 option=1 F=FPR8 G=GPR64
+
+:str Rt_FPR8, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]
+is b_3031=0b00 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR8 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zd
+{
+ local tmp1:8 = extend_spec << extend_amount;
+ local tmp2:8 = Rn_GPR64xsp + tmp1;
+ * tmp2 = Rt_FPR8;
+}
+
+# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00
+# CONSTRUCT x3c206800/mask=xffe0ec00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop
+# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4
+# AUNIT --inst x3c206800/mask=xffe0ec00 --status nomem
+# 8-fsreg,STR-8-fsreg variant when size == 00 && opc == 00 && option is 011 bb=b_1315 option=0b011 F=FPR8 G=GPR64
+
+:str Rt_FPR8, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]
+is b_3031=0b00 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_1315=0b011 & b_1011=0b10 & Rt_FPR8 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zd
+{
+ local tmp1:8 = extend_spec << extend_amount;
+ local tmp2:8 = Rn_GPR64xsp + tmp1;
+ * tmp2 = Rt_FPR8;
+}
+
+# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00
+# CONSTRUCT x7c200800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop
+# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4
+# AUNIT --inst x7c200800/mask=xffe02c00 --status nomem
+# 16-fsreg,STR-16-fsreg variant when size == 01 && opc == 00 bb=b_13 option=0 F=FPR16 G=GPR32
+
+:str Rt_FPR16, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]
+is b_3031=0b01 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR16 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zd
+{
+ local tmp1:8 = extend_spec << extend_amount;
+ local tmp2:8 = Rn_GPR64xsp + tmp1;
+ * tmp2 = Rt_FPR16;
+}
+
+# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00
+# CONSTRUCT x7c202800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop
+# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4
+# AUNIT --inst x7c202800/mask=xffe02c00 --status nomem
+# 16-fsreg,STR-16-fsreg variant when size == 01 && opc == 00 bb=b_13 option=1 F=FPR16 G=GPR64
+
+:str Rt_FPR16, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]
+is b_3031=0b01 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR16 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zd
+{
+ local tmp1:8 = extend_spec << extend_amount;
+ local tmp2:8 = Rn_GPR64xsp + tmp1;
+ * tmp2 = Rt_FPR16;
+}
+
+# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00
+# CONSTRUCT xbc200800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop
+# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4
+# AUNIT --inst xbc200800/mask=xffe02c00 --status nomem
+# 32-fsreg,STR-32-fsreg variant when size == 10 && opc == 00 bb=b_13 option=0 F=FPR32 G=GPR32
+
+:str Rt_FPR32, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]
+is b_3031=0b10 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR32 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zd
+{
+ local tmp1:8 = extend_spec << extend_amount;
+ local tmp2:8 = Rn_GPR64xsp + tmp1;
+ * tmp2 = Rt_FPR32;
+}
+
+# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00
+# CONSTRUCT xbc202800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop
+# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4
+# AUNIT --inst xbc202800/mask=xffe02c00 --status nomem
+# 32-fsreg,STR-32-fsreg variant when size == 10 && opc == 00 bb=b_13 option=1 F=FPR32 G=GPR64
+
+:str Rt_FPR32, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]
+is b_3031=0b10 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR32 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zd
+{
+ local tmp1:8 = extend_spec << extend_amount;
+ local tmp2:8 = Rn_GPR64xsp + tmp1;
+ * tmp2 = Rt_FPR32;
+}
+
+# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00
+# CONSTRUCT xfc200800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop
+# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4
+# AUNIT --inst xfc200800/mask=xffe02c00 --status nomem
+# 64-fsreg,STR-64-fsreg variant when size == 11 && opc == 00 bb=b_13 option=0 F=FPR64 G=GPR32
+
+:str Rt_FPR64, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]
+is b_3031=0b11 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR64 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zd
+{
+ local tmp1:8 = extend_spec << extend_amount;
+ local tmp2:8 = Rn_GPR64xsp + tmp1;
+ * tmp2 = Rt_FPR64;
+}
+
+# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00
+# CONSTRUCT xfc202800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop
+# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4
+# AUNIT --inst xfc202800/mask=xffe02c00 --status nomem
+# 64-fsreg,STR-64-fsreg variant when size == 11 && opc == 00 bb=b_13 option=1 F=FPR64 G=GPR64
+
+:str Rt_FPR64, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]
+is b_3031=0b11 & b_2429=0b111100 & b_2223=0b00 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR64 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zd
+{
+ local tmp1:8 = extend_spec << extend_amount;
+ local tmp2:8 = Rn_GPR64xsp + tmp1;
+ * tmp2 = Rt_FPR64;
+}
+
+# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00
+# CONSTRUCT x3ca00800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop
+# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4
+# AUNIT --inst x3ca00800/mask=xffe02c00 --status nomem
+# 128-fsreg,STR-128-fsreg variant when size == 00 && opc == 10 bb=b_13 option=0 F=FPR128 G=GPR32
+
+:str Rt_FPR128, [Rn_GPR64xsp, Rm_GPR32^extend_spec^extend_amount]
+is b_3031=0b00 & b_2429=0b111100 & b_2223=0b10 & b_21=1 & b_13=0 & b_1011=0b10 & Rt_FPR128 & Rn_GPR64xsp & Rm_GPR32 & extend_spec & extend_amount & Zd
+{
+ local tmp1:8 = extend_spec << extend_amount;
+ local tmp2:8 = Rn_GPR64xsp + tmp1;
+ * tmp2 = Rt_FPR128;
+}
+
+# C7.2.332 STR (register, SIMD&FP) page C7-2786 line 162762 MATCH x3c200800/mask=x3f600c00
+# CONSTRUCT x3ca02800/mask=xffe02c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 Rn_GPR64xsp extend_spec extend_amount <<:8 + =store pop
+# SMACRO(pseudo) null ARG1 Rn_GPR64xsp extend_spec extend_amount =NEON_str/4
+# AUNIT --inst x3ca02800/mask=xffe02c00 --status nomem
+# 128-fsreg,STR-128-fsreg variant when size == 00 && opc == 10 bb=b_13 option=1 F=FPR128 G=GPR64
+
+:str Rt_FPR128, [Rn_GPR64xsp, Rm_GPR64^extend_spec^extend_amount]
+is b_3031=0b00 & b_2429=0b111100 & b_2223=0b10 & b_21=1 & b_13=1 & b_1011=0b10 & Rt_FPR128 & Rn_GPR64xsp & Rm_GPR64 & extend_spec & extend_amount & Zd
+{
+ local tmp1:8 = extend_spec << extend_amount;
+ local tmp2:8 = Rn_GPR64xsp + tmp1;
+ * tmp2 = Rt_FPR128;
+}
+
+# C7.2.333 STUR (SIMD&FP) page C7-2789 line 162949 MATCH x3c000000/mask=x3f600c00
+# CONSTRUCT x3c800000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =store pop
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_stur/2
+# AUNIT --inst x3c800000/mask=xffe00c00 --status nomem
+
+:stur Rt_FPR128, addrIndexed
+is size.ldstr=0 & b_2729=7 & v=1 & b_2425=0 & b_23=1 & b_2222=0 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR128
+{
+ * addrIndexed = Rt_FPR128;
+}
+
+# C7.2.333 STUR (SIMD&FP) page C7-2789 line 162949 MATCH x3c000000/mask=x3f600c00
+# CONSTRUCT x7c000000/mask=xffc00c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =store pop
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_stur/2
+# AUNIT --inst x7c000000/mask=xffc00c00 --status nomem
+
+:stur Rt_FPR16, addrIndexed
+is size.ldstr=1 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=0 & b_1011=0 & addrIndexed & Rt_FPR16
+{
+ * addrIndexed = Rt_FPR16;
+}
+
+# C7.2.333 STUR (SIMD&FP) page C7-2789 line 162949 MATCH x3c000000/mask=x3f600c00
+# CONSTRUCT xbc000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =store pop
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_stur/2
+# AUNIT --inst xbc000000/mask=xffe00c00 --status nomem
+
+:stur Rt_FPR32, addrIndexed
+is size.ldstr=2 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR32
+{
+ * addrIndexed = Rt_FPR32;
+}
+
+# C7.2.333 STUR (SIMD&FP) page C7-2789 line 162949 MATCH x3c000000/mask=x3f600c00
+# CONSTRUCT xfc000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =store pop
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_stur/2
+# AUNIT --inst xfc000000/mask=xffe00c00 --status nomem
+
+:stur Rt_FPR64, addrIndexed
+is size.ldstr=3 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR64
+{
+ * addrIndexed = Rt_FPR64;
+}
+
+# C7.2.333 STUR (SIMD&FP) page C7-2789 line 162949 MATCH x3c000000/mask=x3f600c00
+# CONSTRUCT x3c000000/mask=xffe00c00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =store pop
+# SMACRO(pseudo) null ARG1 ARG2 =NEON_stur/2
+# AUNIT --inst x3c000000/mask=xffe00c00 --status nomem
+
+:stur Rt_FPR8, addrIndexed
+is size.ldstr=0 & b_2729=7 & v=1 & b_2425=0 & b_23=0 & b_2222=0 & b_2121=0 & b_1011=0 & addrIndexed & Rt_FPR8
+{
+ * addrIndexed = Rt_FPR8;
+}
+
+# C7.2.334 SUB (vector) page C7-2791 line 163076 MATCH x7e208400/mask=xff20fc00
+# CONSTRUCT x7ee08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =-
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2
+# AUNIT --inst x7ee08400/mask=xffe0fc00 --status pass
+
+:sub Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x10 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = Rn_FPR64 - Rm_FPR64;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.334 SUB (vector) page C7-2791 line 163076 MATCH x2e208400/mask=xbf20fc00
+# CONSTRUCT x6e208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$-@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@1
+# AUNIT --inst x6e208400/mask=xffe0fc00 --status pass
+
+:sub Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x10 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ # simd infix Rd_VPR128.16B = Rn_VPR128.16B - Rm_VPR128.16B on lane size 1
+ Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] - Rm_VPR128.16B[0,8];
+ Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] - Rm_VPR128.16B[8,8];
+ Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] - Rm_VPR128.16B[16,8];
+ Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] - Rm_VPR128.16B[24,8];
+ Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] - Rm_VPR128.16B[32,8];
+ Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] - Rm_VPR128.16B[40,8];
+ Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] - Rm_VPR128.16B[48,8];
+ Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] - Rm_VPR128.16B[56,8];
+ Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] - Rm_VPR128.16B[64,8];
+ Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] - Rm_VPR128.16B[72,8];
+ Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] - Rm_VPR128.16B[80,8];
+ Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] - Rm_VPR128.16B[88,8];
+ Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] - Rm_VPR128.16B[96,8];
+ Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] - Rm_VPR128.16B[104,8];
+ Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] - Rm_VPR128.16B[112,8];
+ Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] - Rm_VPR128.16B[120,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.334 SUB (vector) page C7-2791 line 163076 MATCH x2e208400/mask=xbf20fc00
+# CONSTRUCT x6ee08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$-@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@8
+# AUNIT --inst x6ee08400/mask=xffe0fc00 --status pass
+
+:sub Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x10 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ # simd infix Rd_VPR128.2D = Rn_VPR128.2D - Rm_VPR128.2D on lane size 8
+ Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] - Rm_VPR128.2D[0,64];
+ Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] - Rm_VPR128.2D[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.334 SUB (vector) page C7-2791 line 163076 MATCH x2e208400/mask=xbf20fc00
+# CONSTRUCT x2ea08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@4
+# AUNIT --inst x2ea08400/mask=xffe0fc00 --status pass
+
+:sub Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x10 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ # simd infix Rd_VPR64.2S = Rn_VPR64.2S - Rm_VPR64.2S on lane size 4
+ Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] - Rm_VPR64.2S[0,32];
+ Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] - Rm_VPR64.2S[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.334 SUB (vector) page C7-2791 line 163076 MATCH x2e208400/mask=xbf20fc00
+# CONSTRUCT x2e608400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$-@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@2
+# AUNIT --inst x2e608400/mask=xffe0fc00 --status pass
+
+:sub Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x10 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ # simd infix Rd_VPR64.4H = Rn_VPR64.4H - Rm_VPR64.4H on lane size 2
+ Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] - Rm_VPR64.4H[0,16];
+ Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] - Rm_VPR64.4H[16,16];
+ Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] - Rm_VPR64.4H[32,16];
+ Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] - Rm_VPR64.4H[48,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.334 SUB (vector) page C7-2791 line 163076 MATCH x2e208400/mask=xbf20fc00
+# CONSTRUCT x6ea08400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@4
+# AUNIT --inst x6ea08400/mask=xffe0fc00 --status pass
+
+:sub Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x10 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd infix Rd_VPR128.4S = Rn_VPR128.4S - Rm_VPR128.4S on lane size 4
+ Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] - Rm_VPR128.4S[0,32];
+ Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] - Rm_VPR128.4S[32,32];
+ Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] - Rm_VPR128.4S[64,32];
+ Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] - Rm_VPR128.4S[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.334 SUB (vector) page C7-2791 line 163076 MATCH x2e208400/mask=xbf20fc00
+# CONSTRUCT x2e208400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$-@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@1
+# AUNIT --inst x2e208400/mask=xffe0fc00 --status pass
+
+:sub Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x10 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ # simd infix Rd_VPR64.8B = Rn_VPR64.8B - Rm_VPR64.8B on lane size 1
+ Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] - Rm_VPR64.8B[0,8];
+ Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] - Rm_VPR64.8B[8,8];
+ Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] - Rm_VPR64.8B[16,8];
+ Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] - Rm_VPR64.8B[24,8];
+ Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] - Rm_VPR64.8B[32,8];
+ Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] - Rm_VPR64.8B[40,8];
+ Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] - Rm_VPR64.8B[48,8];
+ Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] - Rm_VPR64.8B[56,8];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.334 SUB (vector) page C7-2791 line 163076 MATCH x2e208400/mask=xbf20fc00
+# CONSTRUCT x6e608400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =$-@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@2
+# AUNIT --inst x6e608400/mask=xffe0fc00 --status pass
+
+:sub Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x10 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ # simd infix Rd_VPR128.8H = Rn_VPR128.8H - Rm_VPR128.8H on lane size 2
+ Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] - Rm_VPR128.8H[0,16];
+ Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] - Rm_VPR128.8H[16,16];
+ Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] - Rm_VPR128.8H[32,16];
+ Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] - Rm_VPR128.8H[48,16];
+ Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] - Rm_VPR128.8H[64,16];
+ Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] - Rm_VPR128.8H[80,16];
+ Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] - Rm_VPR128.8H[96,16];
+ Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] - Rm_VPR128.8H[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.335 SUBHN, SUBHN2 page C7-2793 line 163214 MATCH x0e206000/mask=xbf20fc00
+# CONSTRUCT x4e206000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $-@2 &=$shuffle@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15:1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@2
+# AUNIT --inst x4e206000/mask=xffe0fc00 --status pass
+
+:subhn2 Rd_VPR128.16B, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x6 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.8H - Rm_VPR128.8H on lane size 2
+ TMPQ1[0,16] = Rn_VPR128.8H[0,16] - Rm_VPR128.8H[0,16];
+ TMPQ1[16,16] = Rn_VPR128.8H[16,16] - Rm_VPR128.8H[16,16];
+ TMPQ1[32,16] = Rn_VPR128.8H[32,16] - Rm_VPR128.8H[32,16];
+ TMPQ1[48,16] = Rn_VPR128.8H[48,16] - Rm_VPR128.8H[48,16];
+ TMPQ1[64,16] = Rn_VPR128.8H[64,16] - Rm_VPR128.8H[64,16];
+ TMPQ1[80,16] = Rn_VPR128.8H[80,16] - Rm_VPR128.8H[80,16];
+ TMPQ1[96,16] = Rn_VPR128.8H[96,16] - Rm_VPR128.8H[96,16];
+ TMPQ1[112,16] = Rn_VPR128.8H[112,16] - Rm_VPR128.8H[112,16];
+ # simd shuffle Rd_VPR128.16B = TMPQ1 (@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15) lane size 1
+ Rd_VPR128.16B[64,8] = TMPQ1[8,8];
+ Rd_VPR128.16B[72,8] = TMPQ1[24,8];
+ Rd_VPR128.16B[80,8] = TMPQ1[40,8];
+ Rd_VPR128.16B[88,8] = TMPQ1[56,8];
+ Rd_VPR128.16B[96,8] = TMPQ1[72,8];
+ Rd_VPR128.16B[104,8] = TMPQ1[88,8];
+ Rd_VPR128.16B[112,8] = TMPQ1[104,8];
+ Rd_VPR128.16B[120,8] = TMPQ1[120,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.335 SUBHN, SUBHN2 page C7-2793 line 163214 MATCH x0e206000/mask=xbf20fc00
+# CONSTRUCT x4ea06000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $-@8 &=$shuffle@1-2@3-3:4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_sub/2@8
+# AUNIT --inst x4ea06000/mask=xffe0fc00 --status pass
+
+:subhn2 Rd_VPR128.4S, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x6 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.2D - Rm_VPR128.2D on lane size 8
+ TMPQ1[0,64] = Rn_VPR128.2D[0,64] - Rm_VPR128.2D[0,64];
+ TMPQ1[64,64] = Rn_VPR128.2D[64,64] - Rm_VPR128.2D[64,64];
+ # simd shuffle Rd_VPR128.4S = TMPQ1 (@1-2@3-3) lane size 4
+ Rd_VPR128.4S[64,32] = TMPQ1[32,32];
+ Rd_VPR128.4S[96,32] = TMPQ1[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.335 SUBHN, SUBHN2 page C7-2793 line 163214 MATCH x0e206000/mask=xbf20fc00
+# CONSTRUCT x4e606000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $-@4 &=$shuffle@1-4@3-5@5-6@7-7:2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_subhn2/3@4
+# AUNIT --inst x4e606000/mask=xffe0fc00 --status pass
+
+:subhn2 Rd_VPR128.8H, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x6 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.4S - Rm_VPR128.4S on lane size 4
+ TMPQ1[0,32] = Rn_VPR128.4S[0,32] - Rm_VPR128.4S[0,32];
+ TMPQ1[32,32] = Rn_VPR128.4S[32,32] - Rm_VPR128.4S[32,32];
+ TMPQ1[64,32] = Rn_VPR128.4S[64,32] - Rm_VPR128.4S[64,32];
+ TMPQ1[96,32] = Rn_VPR128.4S[96,32] - Rm_VPR128.4S[96,32];
+ # simd shuffle Rd_VPR128.8H = TMPQ1 (@1-4@3-5@5-6@7-7) lane size 2
+ Rd_VPR128.8H[64,16] = TMPQ1[16,16];
+ Rd_VPR128.8H[80,16] = TMPQ1[48,16];
+ Rd_VPR128.8H[96,16] = TMPQ1[80,16];
+ Rd_VPR128.8H[112,16] = TMPQ1[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.335 SUBHN, SUBHN2 page C7-2793 line 163214 MATCH x0e206000/mask=xbf20fc00
+# CONSTRUCT x0ea06000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $-@8 &=$shuffle@1-0@3-1:4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_subhn/3@8
+# AUNIT --inst x0ea06000/mask=xffe0fc00 --status pass
+
+:subhn Rd_VPR64.2S, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.2D & b_1215=0x6 & b_1011=0 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.2D - Rm_VPR128.2D on lane size 8
+ TMPQ1[0,64] = Rn_VPR128.2D[0,64] - Rm_VPR128.2D[0,64];
+ TMPQ1[64,64] = Rn_VPR128.2D[64,64] - Rm_VPR128.2D[64,64];
+ # simd shuffle Rd_VPR64.2S = TMPQ1 (@1-0@3-1) lane size 4
+ Rd_VPR64.2S[0,32] = TMPQ1[32,32];
+ Rd_VPR64.2S[32,32] = TMPQ1[96,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.335 SUBHN, SUBHN2 page C7-2793 line 163214 MATCH x0e206000/mask=xbf20fc00
+# CONSTRUCT x0e606000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $-@4 &=$shuffle@1-0@3-1@5-2@7-3:2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_subhn/3@4
+# AUNIT --inst x0e606000/mask=xffe0fc00 --status pass
+
+:subhn Rd_VPR64.4H, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.4S & b_1215=0x6 & b_1011=0 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.4S - Rm_VPR128.4S on lane size 4
+ TMPQ1[0,32] = Rn_VPR128.4S[0,32] - Rm_VPR128.4S[0,32];
+ TMPQ1[32,32] = Rn_VPR128.4S[32,32] - Rm_VPR128.4S[32,32];
+ TMPQ1[64,32] = Rn_VPR128.4S[64,32] - Rm_VPR128.4S[64,32];
+ TMPQ1[96,32] = Rn_VPR128.4S[96,32] - Rm_VPR128.4S[96,32];
+ # simd shuffle Rd_VPR64.4H = TMPQ1 (@1-0@3-1@5-2@7-3) lane size 2
+ Rd_VPR64.4H[0,16] = TMPQ1[16,16];
+ Rd_VPR64.4H[16,16] = TMPQ1[48,16];
+ Rd_VPR64.4H[32,16] = TMPQ1[80,16];
+ Rd_VPR64.4H[48,16] = TMPQ1[112,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.335 SUBHN, SUBHN2 page C7-2793 line 163214 MATCH x0e206000/mask=xbf20fc00
+# CONSTRUCT x0e206000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $-@2 &=$shuffle@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7:1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_subhn/3@2
+# AUNIT --inst x0e206000/mask=xffe0fc00 --status pass
+
+:subhn Rd_VPR64.8B, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.8H & b_1215=0x6 & b_1011=0 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.8H - Rm_VPR128.8H on lane size 2
+ TMPQ1[0,16] = Rn_VPR128.8H[0,16] - Rm_VPR128.8H[0,16];
+ TMPQ1[16,16] = Rn_VPR128.8H[16,16] - Rm_VPR128.8H[16,16];
+ TMPQ1[32,16] = Rn_VPR128.8H[32,16] - Rm_VPR128.8H[32,16];
+ TMPQ1[48,16] = Rn_VPR128.8H[48,16] - Rm_VPR128.8H[48,16];
+ TMPQ1[64,16] = Rn_VPR128.8H[64,16] - Rm_VPR128.8H[64,16];
+ TMPQ1[80,16] = Rn_VPR128.8H[80,16] - Rm_VPR128.8H[80,16];
+ TMPQ1[96,16] = Rn_VPR128.8H[96,16] - Rm_VPR128.8H[96,16];
+ TMPQ1[112,16] = Rn_VPR128.8H[112,16] - Rm_VPR128.8H[112,16];
+ # simd shuffle Rd_VPR64.8B = TMPQ1 (@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7) lane size 1
+ Rd_VPR64.8B[0,8] = TMPQ1[8,8];
+ Rd_VPR64.8B[8,8] = TMPQ1[24,8];
+ Rd_VPR64.8B[16,8] = TMPQ1[40,8];
+ Rd_VPR64.8B[24,8] = TMPQ1[56,8];
+ Rd_VPR64.8B[32,8] = TMPQ1[72,8];
+ Rd_VPR64.8B[40,8] = TMPQ1[88,8];
+ Rd_VPR64.8B[48,8] = TMPQ1[104,8];
+ Rd_VPR64.8B[56,8] = TMPQ1[120,8];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x5e203800/mask=xff3ffc00
+# CONSTRUCT x5e203800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 &=+
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2
+# AUNIT --inst x5e203800/mask=xfffffc00 --status fail --comment "nointsat"
+# Scalar variant when size=00 Q=1 bb=1 V=FPR8 s2=2
+
+:suqadd Rd_FPR8, Rn_FPR8
+is b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b00 & b_1021=0b100000001110 & Rd_FPR8 & Rn_FPR8 & Zd
+{
+ Rd_FPR8 = Rd_FPR8 + Rn_FPR8;
+ zext_zb(Zd); # zero upper 31 bytes of Zd
+}
+
+# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x5e203800/mask=xff3ffc00
+# CONSTRUCT x5e603800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 &=+
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2
+# AUNIT --inst x5e603800/mask=xfffffc00 --status fail --comment "nointsat"
+# Scalar variant when size=01 Q=1 bb=1 V=FPR16 s2=4
+
+:suqadd Rd_FPR16, Rn_FPR16
+is b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b01 & b_1021=0b100000001110 & Rd_FPR16 & Rn_FPR16 & Zd
+{
+ Rd_FPR16 = Rd_FPR16 + Rn_FPR16;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x5e203800/mask=xff3ffc00
+# CONSTRUCT x5ea03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 &=+
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2
+# AUNIT --inst x5ea03800/mask=xfffffc00 --status fail --comment "nointsat"
+# Scalar variant when size=10 Q=1 bb=1 V=FPR32 s2=8
+
+:suqadd Rd_FPR32, Rn_FPR32
+is b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b10 & b_1021=0b100000001110 & Rd_FPR32 & Rn_FPR32 & Zd
+{
+ Rd_FPR32 = Rd_FPR32 + Rn_FPR32;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x5e203800/mask=xff3ffc00
+# CONSTRUCT x5ee03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 &=+
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2
+# AUNIT --inst x5ee03800/mask=xfffffc00 --status fail --comment "nointsat"
+# Scalar variant when size=11 Q=1 bb=1 V=FPR64 s2=16
+
+:suqadd Rd_FPR64, Rn_FPR64
+is b_31=0 & b_30=1 & b_2429=0b011110 & b_2223=0b11 & b_1021=0b100000001110 & Rd_FPR64 & Rn_FPR64 & Zd
+{
+ Rd_FPR64 = Rd_FPR64 + Rn_FPR64;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x0e203800/mask=xbf3ffc00
+# CONSTRUCT x0e203800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 &=$+@1
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@1
+# AUNIT --inst x0e203800/mask=xfffffc00 --status fail --comment "nointsat"
+# Vector variant when size=00 Q=0 bb=0 V=VPR64.8B e1=1 s2=16
+
+:suqadd Rd_VPR64.8B, Rn_VPR64.8B
+is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000001110 & Rd_VPR64.8B & Rn_VPR64.8B & Zd
+{
+ # simd infix Rd_VPR64.8B = Rd_VPR64.8B + Rn_VPR64.8B on lane size 1
+ Rd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] + Rn_VPR64.8B[0,8];
+ Rd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] + Rn_VPR64.8B[8,8];
+ Rd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] + Rn_VPR64.8B[16,8];
+ Rd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] + Rn_VPR64.8B[24,8];
+ Rd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] + Rn_VPR64.8B[32,8];
+ Rd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] + Rn_VPR64.8B[40,8];
+ Rd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] + Rn_VPR64.8B[48,8];
+ Rd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] + Rn_VPR64.8B[56,8];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x0e203800/mask=xbf3ffc00
+# CONSTRUCT x4e203800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 &=$+@1
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@1
+# AUNIT --inst x4e203800/mask=xfffffc00 --status fail --comment "nointsat"
+# Vector variant when size=00 Q=1 bb=0 V=VPR128.16B e1=1 s2=32
+
+:suqadd Rd_VPR128.16B, Rn_VPR128.16B
+is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b00 & b_1021=0b100000001110 & Rd_VPR128.16B & Rn_VPR128.16B & Zd
+{
+ # simd infix Rd_VPR128.16B = Rd_VPR128.16B + Rn_VPR128.16B on lane size 1
+ Rd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] + Rn_VPR128.16B[0,8];
+ Rd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] + Rn_VPR128.16B[8,8];
+ Rd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] + Rn_VPR128.16B[16,8];
+ Rd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] + Rn_VPR128.16B[24,8];
+ Rd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] + Rn_VPR128.16B[32,8];
+ Rd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] + Rn_VPR128.16B[40,8];
+ Rd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] + Rn_VPR128.16B[48,8];
+ Rd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] + Rn_VPR128.16B[56,8];
+ Rd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] + Rn_VPR128.16B[64,8];
+ Rd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] + Rn_VPR128.16B[72,8];
+ Rd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] + Rn_VPR128.16B[80,8];
+ Rd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] + Rn_VPR128.16B[88,8];
+ Rd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] + Rn_VPR128.16B[96,8];
+ Rd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] + Rn_VPR128.16B[104,8];
+ Rd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] + Rn_VPR128.16B[112,8];
+ Rd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] + Rn_VPR128.16B[120,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x0e203800/mask=xbf3ffc00
+# CONSTRUCT x0e603800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@2
+# AUNIT --inst x0e603800/mask=xfffffc00 --status fail --comment "nointsat"
+# Vector variant when size=01 Q=0 bb=0 V=VPR64.4H e1=2 s2=16
+
+:suqadd Rd_VPR64.4H, Rn_VPR64.4H
+is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000001110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
+{
+ # simd infix Rd_VPR64.4H = Rd_VPR64.4H + Rn_VPR64.4H on lane size 2
+ Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + Rn_VPR64.4H[0,16];
+ Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + Rn_VPR64.4H[16,16];
+ Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + Rn_VPR64.4H[32,16];
+ Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + Rn_VPR64.4H[48,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x0e203800/mask=xbf3ffc00
+# CONSTRUCT x4e603800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@2
+# AUNIT --inst x4e603800/mask=xfffffc00 --status fail --comment "nointsat"
+# Vector variant when size=01 Q=1 bb=0 V=VPR128.8H e1=2 s2=32
+
+:suqadd Rd_VPR128.8H, Rn_VPR128.8H
+is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b01 & b_1021=0b100000001110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
+{
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H + Rn_VPR128.8H on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + Rn_VPR128.8H[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + Rn_VPR128.8H[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + Rn_VPR128.8H[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + Rn_VPR128.8H[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + Rn_VPR128.8H[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + Rn_VPR128.8H[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + Rn_VPR128.8H[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + Rn_VPR128.8H[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x0e203800/mask=xbf3ffc00
+# CONSTRUCT x0ea03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@4
+# AUNIT --inst x0ea03800/mask=xfffffc00 --status fail --comment "nointsat"
+# Vector variant when size=10 Q=0 bb=0 V=VPR64.2S e1=4 s2=16
+
+:suqadd Rd_VPR64.2S, Rn_VPR64.2S
+is b_31=0 & b_30=0 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000001110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd
+{
+ # simd infix Rd_VPR64.2S = Rd_VPR64.2S + Rn_VPR64.2S on lane size 4
+ Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + Rn_VPR64.2S[0,32];
+ Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + Rn_VPR64.2S[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x0e203800/mask=xbf3ffc00
+# CONSTRUCT x4ea03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@4
+# AUNIT --inst x4ea03800/mask=xfffffc00 --status fail --comment "nointsat"
+# Vector variant when size=10 Q=1 bb=0 V=VPR128.4S e1=4 s2=32
+
+:suqadd Rd_VPR128.4S, Rn_VPR128.4S
+is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b10 & b_1021=0b100000001110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
+{
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + Rn_VPR128.4S on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + Rn_VPR128.4S[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + Rn_VPR128.4S[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + Rn_VPR128.4S[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + Rn_VPR128.4S[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.337 SUQADD page C7-2797 line 163431 MATCH x0e203800/mask=xbf3ffc00
+# CONSTRUCT x4ee03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_suqadd/2@8
+# AUNIT --inst x4ee03800/mask=xfffffc00 --status fail --comment "nointsat"
+# Vector variant when size=11 Q=1 bb=0 V=VPR128.2D e1=8 s2=32
+
+:suqadd Rd_VPR128.2D, Rn_VPR128.2D
+is b_31=0 & b_30=1 & b_2429=0b001110 & b_2223=0b11 & b_1021=0b100000001110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd
+{
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D + Rn_VPR128.2D on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + Rn_VPR128.2D[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + Rn_VPR128.2D[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00
+# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00
+# CONSTRUCT x4f08a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 =$sext@1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sxtl2/1@1
+# AUNIT --inst x4f08a400/mask=xfffffc00 --status pass --comment "ext"
+
+:sxtl2 Rd_VPR128.8H, Rn_VPR128.16B
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3=0 & b_1115=0x14 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
+{
+ TMPD1 = Rn_VPR128.16B[64,64];
+ # simd resize Rd_VPR128.8H = sext(TMPD1) (lane size 1 to 2)
+ Rd_VPR128.8H[0,16] = sext(TMPD1[0,8]);
+ Rd_VPR128.8H[16,16] = sext(TMPD1[8,8]);
+ Rd_VPR128.8H[32,16] = sext(TMPD1[16,8]);
+ Rd_VPR128.8H[48,16] = sext(TMPD1[24,8]);
+ Rd_VPR128.8H[64,16] = sext(TMPD1[32,8]);
+ Rd_VPR128.8H[80,16] = sext(TMPD1[40,8]);
+ Rd_VPR128.8H[96,16] = sext(TMPD1[48,8]);
+ Rd_VPR128.8H[112,16] = sext(TMPD1[56,8]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00
+# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00
+# CONSTRUCT x0f20a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =var =$sext@4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sxtl/1@4
+# AUNIT --inst x0f20a400/mask=xfffffc00 --status pass --comment "ext"
+
+:sxtl Rd_VPR128.2D, Rn_VPR64.2S
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5=0 & b_1115=0x14 & b_1010=1 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR64.2S;
+ # simd resize Rd_VPR128.2D = sext(TMPD1) (lane size 4 to 8)
+ Rd_VPR128.2D[0,64] = sext(TMPD1[0,32]);
+ Rd_VPR128.2D[64,64] = sext(TMPD1[32,32]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00
+# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00
+# CONSTRUCT x0f10a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =var =$sext@2
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sxtl/1@2
+# AUNIT --inst x0f10a400/mask=xfffffc00 --status pass --comment "ext"
+
+:sxtl Rd_VPR128.4S, Rn_VPR64.4H
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4=0 & b_1115=0x14 & b_1010=1 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR64.4H;
+ # simd resize Rd_VPR128.4S = sext(TMPD1) (lane size 2 to 4)
+ Rd_VPR128.4S[0,32] = sext(TMPD1[0,16]);
+ Rd_VPR128.4S[32,32] = sext(TMPD1[16,16]);
+ Rd_VPR128.4S[64,32] = sext(TMPD1[32,16]);
+ Rd_VPR128.4S[96,32] = sext(TMPD1[48,16]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00
+# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00
+# CONSTRUCT x4f20a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 =$sext@4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sxtl2/1@4
+# AUNIT --inst x4f20a400/mask=xfffffc00 --status pass --comment "ext"
+
+:sxtl2 Rd_VPR128.2D, Rn_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2123=1 & Imm_uimm5=0 & b_1115=0x14 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize Rd_VPR128.2D = sext(TMPD1) (lane size 4 to 8)
+ Rd_VPR128.2D[0,64] = sext(TMPD1[0,32]);
+ Rd_VPR128.2D[64,64] = sext(TMPD1[32,32]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00
+# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00
+# CONSTRUCT x0f08a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =var =$sext@1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sxtl/1@1
+# AUNIT --inst x0f08a400/mask=xfffffc00 --status pass --comment "ext"
+
+:sxtl Rd_VPR128.8H, Rn_VPR64.8B
+is b_3131=0 & q=0 & u=0 & b_2428=0xf & b_1923=0x1 & Imm_uimm3=0 & b_1115=0x14 & b_1010=1 & Rn_VPR64.8B & Rd_VPR128.8H & Rn_VPR128 & Zd
+{
+ TMPD1 = Rn_VPR64.8B;
+ # simd resize Rd_VPR128.8H = sext(TMPD1) (lane size 1 to 2)
+ Rd_VPR128.8H[0,16] = sext(TMPD1[0,8]);
+ Rd_VPR128.8H[16,16] = sext(TMPD1[8,8]);
+ Rd_VPR128.8H[32,16] = sext(TMPD1[16,8]);
+ Rd_VPR128.8H[48,16] = sext(TMPD1[24,8]);
+ Rd_VPR128.8H[64,16] = sext(TMPD1[32,8]);
+ Rd_VPR128.8H[80,16] = sext(TMPD1[40,8]);
+ Rd_VPR128.8H[96,16] = sext(TMPD1[48,8]);
+ Rd_VPR128.8H[112,16] = sext(TMPD1[56,8]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.338 SXTL, SXTL2 page C7-2799 line 163553 MATCH x0f00a400/mask=xbf87fc00
+# C7.2.316 SSHLL, SSHLL2 page C7-2736 line 159625 MATCH x0f00a400/mask=xbf80fc00
+# CONSTRUCT x4f10a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 =$sext@2
+# SMACRO(pseudo) ARG1 ARG2 =NEON_sxtl2/1@2
+# AUNIT --inst x4f10a400/mask=xfffffc00 --status pass --comment "ext"
+
+:sxtl2 Rd_VPR128.4S, Rn_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xf & b_2023=0x1 & Imm_uimm4=0 & b_1115=0x14 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize Rd_VPR128.4S = sext(TMPD1) (lane size 2 to 4)
+ Rd_VPR128.4S[0,32] = sext(TMPD1[0,16]);
+ Rd_VPR128.4S[32,32] = sext(TMPD1[16,16]);
+ Rd_VPR128.4S[64,32] = sext(TMPD1[32,16]);
+ Rd_VPR128.4S[96,32] = sext(TMPD1[48,16]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.322 TBL page C7-1717 line 99409 KEEPWITH
+
+tblx: "tbl" is b_12=0 { local tmp:16 = zext(0:8); export tmp; }
+tblx: "tbx" is b_12=1 & Rd_VPR128 { export Rd_VPR128; }
+
+# C7.2.339 TBL page C7-2801 line 163652 MATCH x0e000000/mask=xbfe09c00
+# C7.2.340 TBX page C7-2803 line 163781 MATCH x0e001000/mask=xbfe09c00
+# CONSTRUCT x0e000000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 tblx Rn_VPR128.16B ARG3 =a64_TBL/3
+# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B ARG3 =NEON_tblx/3@1
+# AUNIT --inst x0e000000/mask=xffe0ec00 --status pass
+# Q == 0 && len == 00 8B, Single register table variant
+
+:^tblx Rd_VPR64.8B, "{"^Rn_VPR128.16B^"}", Rm_VPR64.8B
+is b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=0 & b_1314=0b00 & Rm_VPR64.8B & Rn_VPR128.16B & Rd_VPR64.8B & tblx & Zd
+{
+ Rd_VPR64.8B = a64_TBL(tblx, Rn_VPR128.16B, Rm_VPR64.8B);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.339 TBL page C7-2801 line 163652 MATCH x0e000000/mask=xbfe09c00
+# C7.2.340 TBX page C7-2803 line 163781 MATCH x0e001000/mask=xbfe09c00
+# CONSTRUCT x4e000000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 tblx Rn_VPR128.16B ARG3 =a64_TBL/3
+# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B ARG3 =NEON_tblx/3@1
+# AUNIT --inst x4e000000/mask=xffe0ec00 --status pass
+# Q == 1 && len == 00 16B, Single register table variant
+
+:^tblx Rd_VPR128.16B, "{"^Rn_VPR128.16B^"}", Rm_VPR128.16B
+is b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=1 & b_1314=0b00 & Rm_VPR128.16B & Rn_VPR128.16B & Rd_VPR128.16B & tblx & Zd
+{
+ Rd_VPR128.16B = a64_TBL(tblx, Rn_VPR128.16B, Rm_VPR128.16B);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.339 TBL page C7-2801 line 163652 MATCH x0e000000/mask=xbfe09c00
+# C7.2.340 TBX page C7-2803 line 163781 MATCH x0e001000/mask=xbfe09c00
+# CONSTRUCT x0e002000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B ARG4 =a64_TBL/4
+# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B ARG4 =NEON_tblx/4
+# AUNIT --inst x0e002000/mask=xffe0ec00 --status pass
+# Q == 0 && len == 01 8B, Two register table variant
+
+:^tblx Rd_VPR64.8B, "{"^Rn_VPR128.16B^", "^Rnn_VPR128.16B^"}", Rm_VPR64.8B
+is b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=0 & b_1314=0b01 & Rm_VPR64.8B & Rn_VPR128.16B & Rnn_VPR128.16B & Rd_VPR64.8B & tblx & Zd
+{
+ Rd_VPR64.8B = a64_TBL(tblx, Rn_VPR128.16B, Rnn_VPR128.16B, Rm_VPR64.8B);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.339 TBL page C7-2801 line 163652 MATCH x0e000000/mask=xbfe09c00
+# C7.2.340 TBX page C7-2803 line 163781 MATCH x0e001000/mask=xbfe09c00
+# CONSTRUCT x4e002000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B ARG4 =a64_TBL/4
+# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B ARG4 =NEON_tblx/4
+# AUNIT --inst x4e002000/mask=xffe0ec00 --status pass
+# Q == 1 && len == 01 16B, Two register table variant
+
+:^tblx Rd_VPR128.16B, "{"^Rn_VPR128.16B^", "^Rnn_VPR128.16B^"}", Rm_VPR128.16B
+is b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=1 & b_1314=0b01 & Rm_VPR128.16B & Rn_VPR128.16B & Rnn_VPR128.16B & Rd_VPR128.16B & tblx & Zd
+{
+ Rd_VPR128.16B = a64_TBL(tblx, Rn_VPR128.16B, Rnn_VPR128.16B, Rm_VPR128.16B);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.339 TBL page C7-2801 line 163652 MATCH x0e000000/mask=xbfe09c00
+# C7.2.340 TBX page C7-2803 line 163781 MATCH x0e001000/mask=xbfe09c00
+# CONSTRUCT x0e004000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B ARG5 =a64_TBL/5
+# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B ARG5 =NEON_tblx/5
+# AUNIT --inst x0e004000/mask=xffe0ec00 --status pass
+# Q == 0 && len == 10 8B, Three register table variant
+
+:^tblx Rd_VPR64.8B, "{"^Rn_VPR128.16B^", "^Rnn_VPR128.16B^", "^Rnnn_VPR128.16B^"}", Rm_VPR64.8B
+is b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=0 & b_1314=0b10 & Rm_VPR64.8B & Rn_VPR128.16B & Rnn_VPR128.16B & Rnnn_VPR128.16B & Rd_VPR64.8B & tblx & Zd
+{
+ Rd_VPR64.8B = a64_TBL(tblx, Rn_VPR128.16B, Rnn_VPR128.16B, Rnnn_VPR128.16B, Rm_VPR64.8B);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.339 TBL page C7-2801 line 163652 MATCH x0e000000/mask=xbfe09c00
+# C7.2.340 TBX page C7-2803 line 163781 MATCH x0e001000/mask=xbfe09c00
+# CONSTRUCT x4e004000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B ARG5 =a64_TBL/5
+# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B ARG5 =NEON_tblx/5
+# AUNIT --inst x4e004000/mask=xffe0ec00 --status pass
+# Q == 1 && len == 10 16B, Three register table variant
+
+:^tblx Rd_VPR128.16B, "{"^Rn_VPR128.16B^", "^Rnn_VPR128.16B^", "^Rnnn_VPR128.16B^"}", Rm_VPR128.16B
+is b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=1 & b_1314=0b10 & Rm_VPR128.16B & Rn_VPR128.16B & Rnn_VPR128.16B & Rnnn_VPR128.16B & Rd_VPR128.16B & tblx & Zd
+{
+ Rd_VPR128.16B = a64_TBL(tblx, Rn_VPR128.16B, Rnn_VPR128.16B, Rnnn_VPR128.16B, Rm_VPR128.16B);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.339 TBL page C7-2801 line 163652 MATCH x0e000000/mask=xbfe09c00
+# C7.2.340 TBX page C7-2803 line 163781 MATCH x0e001000/mask=xbfe09c00
+# CONSTRUCT x0e006000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B Rnnnn_VPR128.16B ARG6 =a64_TBL/6
+# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B Rnnnn_VPR128.16B ARG6 =NEON_tblx/6
+# AUNIT --inst x0e006000/mask=xffe0ec00 --status pass
+# Q == 0 && len == 11 8B, Four register table variant
+
+:^tblx Rd_VPR64.8B, "{"^Rn_VPR128.16B^", "^Rnn_VPR128.16B^", "^Rnnn_VPR128.16B^", "^Rnnnn_VPR128.16B^"}", Rm_VPR64.8B
+is b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=0 & b_1314=0b11 & Rm_VPR64.8B & Rn_VPR128.16B & Rnn_VPR128.16B & Rnnn_VPR128.16B & Rnnnn_VPR128.16B & Rd_VPR64.8B & tblx & Zd
+{
+ Rd_VPR64.8B = a64_TBL(tblx, Rn_VPR128.16B, Rnn_VPR128.16B, Rnnn_VPR128.16B, Rnnnn_VPR128.16B, Rm_VPR64.8B);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.339 TBL page C7-2801 line 163652 MATCH x0e000000/mask=xbfe09c00
+# C7.2.340 TBX page C7-2803 line 163781 MATCH x0e001000/mask=xbfe09c00
+# CONSTRUCT x4e006000/mask=xffe0ec00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B Rnnnn_VPR128.16B ARG6 =a64_TBL/6
+# SMACRO(pseudo) ARG1 tblx Rn_VPR128.16B Rnn_VPR128.16B Rnnn_VPR128.16B Rnnnn_VPR128.16B ARG6 =NEON_tblx/6
+# AUNIT --inst x4e006000/mask=xffe0ec00 --status pass
+# Q == 1 && len == 11 16B, Four register table variant
+
+:^tblx Rd_VPR128.16B, "{"^Rn_VPR128.16B^", "^Rnn_VPR128.16B^", "^Rnnn_VPR128.16B^", "^Rnnnn_VPR128.16B^"}", Rm_VPR128.16B
+is b_31=0 & b_2129=0b001110000 & b_15=0 & b_1011=0b00 & b_30=1 & b_1314=0b11 & Rm_VPR128.16B & Rn_VPR128.16B & Rnn_VPR128.16B & Rnnn_VPR128.16B & Rnnnn_VPR128.16B & Rd_VPR128.16B & tblx & Zd
+{
+ Rd_VPR128.16B = a64_TBL(tblx, Rn_VPR128.16B, Rnn_VPR128.16B, Rnnn_VPR128.16B, Rnnnn_VPR128.16B, Rm_VPR128.16B);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.341 TRN1 page C7-2805 line 163910 MATCH x0e002800/mask=xbf20fc00
+# CONSTRUCT x4e002800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-2@4-4@6-6@8-8@10-10@12-12@14-14:1 swap &=$shuffle@0-1@2-3@4-5@6-7@8-9@10-11@12-13@14-15:1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@1
+# AUNIT --inst x4e002800/mask=xffe0fc00 --status pass
+
+:trn1 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ TMPQ2 = Rm_VPR128.16B;
+ TMPQ1 = Rn_VPR128.16B;
+ # simd shuffle Rd_VPR128.16B = TMPQ1 (@0-0@2-2@4-4@6-6@8-8@10-10@12-12@14-14) lane size 1
+ Rd_VPR128.16B[0,8] = TMPQ1[0,8];
+ Rd_VPR128.16B[16,8] = TMPQ1[16,8];
+ Rd_VPR128.16B[32,8] = TMPQ1[32,8];
+ Rd_VPR128.16B[48,8] = TMPQ1[48,8];
+ Rd_VPR128.16B[64,8] = TMPQ1[64,8];
+ Rd_VPR128.16B[80,8] = TMPQ1[80,8];
+ Rd_VPR128.16B[96,8] = TMPQ1[96,8];
+ Rd_VPR128.16B[112,8] = TMPQ1[112,8];
+ # simd shuffle Rd_VPR128.16B = TMPQ2 (@0-1@2-3@4-5@6-7@8-9@10-11@12-13@14-15) lane size 1
+ Rd_VPR128.16B[8,8] = TMPQ2[0,8];
+ Rd_VPR128.16B[24,8] = TMPQ2[16,8];
+ Rd_VPR128.16B[40,8] = TMPQ2[32,8];
+ Rd_VPR128.16B[56,8] = TMPQ2[48,8];
+ Rd_VPR128.16B[72,8] = TMPQ2[64,8];
+ Rd_VPR128.16B[88,8] = TMPQ2[80,8];
+ Rd_VPR128.16B[104,8] = TMPQ2[96,8];
+ Rd_VPR128.16B[120,8] = TMPQ2[112,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.341 TRN1 page C7-2805 line 163910 MATCH x0e002800/mask=xbf20fc00
+# CONSTRUCT x4ec02800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0:8 swap &=$shuffle@0-1:8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@8
+# AUNIT --inst x4ec02800/mask=xffe0fc00 --status pass
+
+:trn1 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=3 & b_2121=0 & Rm_VPR128.2D & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ TMPQ2 = Rm_VPR128.2D;
+ TMPQ1 = Rn_VPR128.2D;
+ # simd shuffle Rd_VPR128.2D = TMPQ1 (@0-0) lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ1[0,64];
+ # simd shuffle Rd_VPR128.2D = TMPQ2 (@0-1) lane size 8
+ Rd_VPR128.2D[64,64] = TMPQ2[0,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.341 TRN1 page C7-2805 line 163910 MATCH x0e002800/mask=xbf20fc00
+# CONSTRUCT x0e802800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0:4 swap &=$shuffle@0-1:4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@4
+# AUNIT --inst x0e802800/mask=xffe0fc00 --status pass
+
+:trn1 Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR64.2S & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ TMPD2 = Rm_VPR64.2S;
+ TMPD1 = Rn_VPR64.2S;
+ # simd shuffle Rd_VPR64.2S = TMPD1 (@0-0) lane size 4
+ Rd_VPR64.2S[0,32] = TMPD1[0,32];
+ # simd shuffle Rd_VPR64.2S = TMPD2 (@0-1) lane size 4
+ Rd_VPR64.2S[32,32] = TMPD2[0,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.341 TRN1 page C7-2805 line 163910 MATCH x0e002800/mask=xbf20fc00
+# CONSTRUCT x0e402800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-2:2 swap &=$shuffle@0-1@2-3:2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@2
+# AUNIT --inst x0e402800/mask=xffe0fc00 --status pass
+
+:trn1 Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR64.4H & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ TMPD2 = Rm_VPR64.4H;
+ TMPD1 = Rn_VPR64.4H;
+ # simd shuffle Rd_VPR64.4H = TMPD1 (@0-0@2-2) lane size 2
+ Rd_VPR64.4H[0,16] = TMPD1[0,16];
+ Rd_VPR64.4H[32,16] = TMPD1[32,16];
+ # simd shuffle Rd_VPR64.4H = TMPD2 (@0-1@2-3) lane size 2
+ Rd_VPR64.4H[16,16] = TMPD2[0,16];
+ Rd_VPR64.4H[48,16] = TMPD2[32,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.341 TRN1 page C7-2805 line 163910 MATCH x0e002800/mask=xbf20fc00
+# CONSTRUCT x4e802800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-2:4 swap &=$shuffle@0-1@2-3:4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@4
+# AUNIT --inst x4e802800/mask=xffe0fc00 --status pass
+
+:trn1 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR128.4S & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ TMPQ2 = Rm_VPR128.4S;
+ TMPQ1 = Rn_VPR128.4S;
+ # simd shuffle Rd_VPR128.4S = TMPQ1 (@0-0@2-2) lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ1[0,32];
+ Rd_VPR128.4S[64,32] = TMPQ1[64,32];
+ # simd shuffle Rd_VPR128.4S = TMPQ2 (@0-1@2-3) lane size 4
+ Rd_VPR128.4S[32,32] = TMPQ2[0,32];
+ Rd_VPR128.4S[96,32] = TMPQ2[64,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.341 TRN1 page C7-2805 line 163910 MATCH x0e002800/mask=xbf20fc00
+# CONSTRUCT x0e002800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-2@4-4@6-6:1 swap &=$shuffle@0-1@2-3@4-5@6-7:1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@1
+# AUNIT --inst x0e002800/mask=xffe0fc00 --status pass
+
+:trn1 Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR64.8B & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ TMPD2 = Rm_VPR64.8B;
+ TMPD1 = Rn_VPR64.8B;
+ # simd shuffle Rd_VPR64.8B = TMPD1 (@0-0@2-2@4-4@6-6) lane size 1
+ Rd_VPR64.8B[0,8] = TMPD1[0,8];
+ Rd_VPR64.8B[16,8] = TMPD1[16,8];
+ Rd_VPR64.8B[32,8] = TMPD1[32,8];
+ Rd_VPR64.8B[48,8] = TMPD1[48,8];
+ # simd shuffle Rd_VPR64.8B = TMPD2 (@0-1@2-3@4-5@6-7) lane size 1
+ Rd_VPR64.8B[8,8] = TMPD2[0,8];
+ Rd_VPR64.8B[24,8] = TMPD2[16,8];
+ Rd_VPR64.8B[40,8] = TMPD2[32,8];
+ Rd_VPR64.8B[56,8] = TMPD2[48,8];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.341 TRN1 page C7-2805 line 163910 MATCH x0e002800/mask=xbf20fc00
+# CONSTRUCT x4e402800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-2@4-4@6-6:2 swap &=$shuffle@0-1@2-3@4-5@6-7:2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn1/3@2
+# AUNIT --inst x4e402800/mask=xffe0fc00 --status pass
+
+:trn1 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR128.8H & b_1515=0 & b_1214=2 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ TMPQ2 = Rm_VPR128.8H;
+ TMPQ1 = Rn_VPR128.8H;
+ # simd shuffle Rd_VPR128.8H = TMPQ1 (@0-0@2-2@4-4@6-6) lane size 2
+ Rd_VPR128.8H[0,16] = TMPQ1[0,16];
+ Rd_VPR128.8H[32,16] = TMPQ1[32,16];
+ Rd_VPR128.8H[64,16] = TMPQ1[64,16];
+ Rd_VPR128.8H[96,16] = TMPQ1[96,16];
+ # simd shuffle Rd_VPR128.8H = TMPQ2 (@0-1@2-3@4-5@6-7) lane size 2
+ Rd_VPR128.8H[16,16] = TMPQ2[0,16];
+ Rd_VPR128.8H[48,16] = TMPQ2[32,16];
+ Rd_VPR128.8H[80,16] = TMPQ2[64,16];
+ Rd_VPR128.8H[112,16] = TMPQ2[96,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.342 TRN2 page C7-2807 line 164028 MATCH x0e006800/mask=xbf20fc00
+# CONSTRUCT x4e006800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-2@5-4@7-6@9-8@11-10@13-12@15-14:1 swap &=$shuffle@1-1@3-3@5-5@7-7@9-9@11-11@13-13@15-15:1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@1
+# AUNIT --inst x4e006800/mask=xffe0fc00 --status pass
+
+:trn2 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ TMPQ2 = Rm_VPR128.16B;
+ TMPQ1 = Rn_VPR128.16B;
+ # simd shuffle Rd_VPR128.16B = TMPQ1 (@1-0@3-2@5-4@7-6@9-8@11-10@13-12@15-14) lane size 1
+ Rd_VPR128.16B[0,8] = TMPQ1[8,8];
+ Rd_VPR128.16B[16,8] = TMPQ1[24,8];
+ Rd_VPR128.16B[32,8] = TMPQ1[40,8];
+ Rd_VPR128.16B[48,8] = TMPQ1[56,8];
+ Rd_VPR128.16B[64,8] = TMPQ1[72,8];
+ Rd_VPR128.16B[80,8] = TMPQ1[88,8];
+ Rd_VPR128.16B[96,8] = TMPQ1[104,8];
+ Rd_VPR128.16B[112,8] = TMPQ1[120,8];
+ # simd shuffle Rd_VPR128.16B = TMPQ2 (@1-1@3-3@5-5@7-7@9-9@11-11@13-13@15-15) lane size 1
+ Rd_VPR128.16B[8,8] = TMPQ2[8,8];
+ Rd_VPR128.16B[24,8] = TMPQ2[24,8];
+ Rd_VPR128.16B[40,8] = TMPQ2[40,8];
+ Rd_VPR128.16B[56,8] = TMPQ2[56,8];
+ Rd_VPR128.16B[72,8] = TMPQ2[72,8];
+ Rd_VPR128.16B[88,8] = TMPQ2[88,8];
+ Rd_VPR128.16B[104,8] = TMPQ2[104,8];
+ Rd_VPR128.16B[120,8] = TMPQ2[120,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.342 TRN2 page C7-2807 line 164028 MATCH x0e006800/mask=xbf20fc00
+# CONSTRUCT x4ec06800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0:8 swap &=$shuffle@1-1:8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@8
+# AUNIT --inst x4ec06800/mask=xffe0fc00 --status pass
+
+:trn2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=3 & b_2121=0 & Rm_VPR128.2D & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ TMPQ2 = Rm_VPR128.2D;
+ TMPQ1 = Rn_VPR128.2D;
+ # simd shuffle Rd_VPR128.2D = TMPQ1 (@1-0) lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ1[64,64];
+ # simd shuffle Rd_VPR128.2D = TMPQ2 (@1-1) lane size 8
+ Rd_VPR128.2D[64,64] = TMPQ2[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.342 TRN2 page C7-2807 line 164028 MATCH x0e006800/mask=xbf20fc00
+# CONSTRUCT x0e806800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0:4 swap &=$shuffle@1-1:4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@4
+# AUNIT --inst x0e806800/mask=xffe0fc00 --status pass
+
+:trn2 Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR64.2S & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ TMPD2 = Rm_VPR64.2S;
+ TMPD1 = Rn_VPR64.2S;
+ # simd shuffle Rd_VPR64.2S = TMPD1 (@1-0) lane size 4
+ Rd_VPR64.2S[0,32] = TMPD1[32,32];
+ # simd shuffle Rd_VPR64.2S = TMPD2 (@1-1) lane size 4
+ Rd_VPR64.2S[32,32] = TMPD2[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.342 TRN2 page C7-2807 line 164028 MATCH x0e006800/mask=xbf20fc00
+# CONSTRUCT x0e406800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-2:2 swap &=$shuffle@1-1@3-3:2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@2
+# AUNIT --inst x0e406800/mask=xffe0fc00 --status pass
+
+:trn2 Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR64.4H & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ TMPD2 = Rm_VPR64.4H;
+ TMPD1 = Rn_VPR64.4H;
+ # simd shuffle Rd_VPR64.4H = TMPD1 (@1-0@3-2) lane size 2
+ Rd_VPR64.4H[0,16] = TMPD1[16,16];
+ Rd_VPR64.4H[32,16] = TMPD1[48,16];
+ # simd shuffle Rd_VPR64.4H = TMPD2 (@1-1@3-3) lane size 2
+ Rd_VPR64.4H[16,16] = TMPD2[16,16];
+ Rd_VPR64.4H[48,16] = TMPD2[48,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.342 TRN2 page C7-2807 line 164028 MATCH x0e006800/mask=xbf20fc00
+# CONSTRUCT x4e806800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-2:4 swap &=$shuffle@1-1@3-3:4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@4
+# AUNIT --inst x4e806800/mask=xffe0fc00 --status pass
+
+:trn2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR128.4S & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ TMPQ2 = Rm_VPR128.4S;
+ TMPQ1 = Rn_VPR128.4S;
+ # simd shuffle Rd_VPR128.4S = TMPQ1 (@1-0@3-2) lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ1[32,32];
+ Rd_VPR128.4S[64,32] = TMPQ1[96,32];
+ # simd shuffle Rd_VPR128.4S = TMPQ2 (@1-1@3-3) lane size 4
+ Rd_VPR128.4S[32,32] = TMPQ2[32,32];
+ Rd_VPR128.4S[96,32] = TMPQ2[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.342 TRN2 page C7-2807 line 164028 MATCH x0e006800/mask=xbf20fc00
+# CONSTRUCT x0e006800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-2@5-4@7-6:1 swap &=$shuffle@1-1@3-3@5-5@7-7:1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@1
+# AUNIT --inst x0e006800/mask=xffe0fc00 --status pass
+
+:trn2 Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR64.8B & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ TMPD2 = Rm_VPR64.8B;
+ TMPD1 = Rn_VPR64.8B;
+ # simd shuffle Rd_VPR64.8B = TMPD1 (@1-0@3-2@5-4@7-6) lane size 1
+ Rd_VPR64.8B[0,8] = TMPD1[8,8];
+ Rd_VPR64.8B[16,8] = TMPD1[24,8];
+ Rd_VPR64.8B[32,8] = TMPD1[40,8];
+ Rd_VPR64.8B[48,8] = TMPD1[56,8];
+ # simd shuffle Rd_VPR64.8B = TMPD2 (@1-1@3-3@5-5@7-7) lane size 1
+ Rd_VPR64.8B[8,8] = TMPD2[8,8];
+ Rd_VPR64.8B[24,8] = TMPD2[24,8];
+ Rd_VPR64.8B[40,8] = TMPD2[40,8];
+ Rd_VPR64.8B[56,8] = TMPD2[56,8];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.342 TRN2 page C7-2807 line 164028 MATCH x0e006800/mask=xbf20fc00
+# CONSTRUCT x4e406800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-2@5-4@7-6:2 swap &=$shuffle@1-1@3-3@5-5@7-7:2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_trn2/3@2
+# AUNIT --inst x4e406800/mask=xffe0fc00 --status pass
+
+:trn2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR128.8H & b_1515=0 & b_1214=6 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ TMPQ2 = Rm_VPR128.8H;
+ TMPQ1 = Rn_VPR128.8H;
+ # simd shuffle Rd_VPR128.8H = TMPQ1 (@1-0@3-2@5-4@7-6) lane size 2
+ Rd_VPR128.8H[0,16] = TMPQ1[16,16];
+ Rd_VPR128.8H[32,16] = TMPQ1[48,16];
+ Rd_VPR128.8H[64,16] = TMPQ1[80,16];
+ Rd_VPR128.8H[96,16] = TMPQ1[112,16];
+ # simd shuffle Rd_VPR128.8H = TMPQ2 (@1-1@3-3@5-5@7-7) lane size 2
+ Rd_VPR128.8H[16,16] = TMPQ2[16,16];
+ Rd_VPR128.8H[48,16] = TMPQ2[48,16];
+ Rd_VPR128.8H[80,16] = TMPQ2[80,16];
+ Rd_VPR128.8H[112,16] = TMPQ2[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.343 UABA page C7-2809 line 164146 MATCH x2e207c00/mask=xbf20fc00
+# CONSTRUCT x6e207c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uaba/3@1
+# AUNIT --inst x6e207c00/mask=xffe0fc00 --status nopcodeop --comment "abd"
+
+:uaba Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xf & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_uaba(Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.343 UABA page C7-2809 line 164146 MATCH x2e207c00/mask=xbf20fc00
+# CONSTRUCT x2ea07c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uaba/3@4
+# AUNIT --inst x2ea07c00/mask=xffe0fc00 --status nopcodeop --comment "abd"
+
+:uaba Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xf & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_uaba(Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.343 UABA page C7-2809 line 164146 MATCH x2e207c00/mask=xbf20fc00
+# CONSTRUCT x2e607c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uaba/3@2
+# AUNIT --inst x2e607c00/mask=xffe0fc00 --status nopcodeop --comment "abd"
+
+:uaba Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xf & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_uaba(Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.343 UABA page C7-2809 line 164146 MATCH x2e207c00/mask=xbf20fc00
+# CONSTRUCT x6ea07c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uaba/3@4
+# AUNIT --inst x6ea07c00/mask=xffe0fc00 --status nopcodeop --comment "abd"
+
+:uaba Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xf & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_uaba(Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.343 UABA page C7-2809 line 164146 MATCH x2e207c00/mask=xbf20fc00
+# CONSTRUCT x2e207c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uaba/3@1
+# AUNIT --inst x2e207c00/mask=xffe0fc00 --status nopcodeop --comment "abd"
+
+:uaba Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xf & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_uaba(Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.343 UABA page C7-2809 line 164146 MATCH x2e207c00/mask=xbf20fc00
+# CONSTRUCT x6e607c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uaba/3@2
+# AUNIT --inst x6e607c00/mask=xffe0fc00 --status nopcodeop --comment "abd"
+
+:uaba Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xf & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_uaba(Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.344 UABAL, UABAL2 page C7-2811 line 164248 MATCH x2e205000/mask=xbf20fc00
+# CONSTRUCT x6ea05000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 $-@8 $abs@8 &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uabal2/3@4
+# AUNIT --inst x6ea05000/mask=xffe0fc00 --status pass --comment "ext abd"
+
+:uabal2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x5 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = zext(TMPD1[0,32]);
+ TMPQ2[64,64] = zext(TMPD1[32,32]);
+ TMPD3 = Rm_VPR128.4S[64,64];
+ # simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8)
+ TMPQ4[0,64] = zext(TMPD3[0,32]);
+ TMPQ4[64,64] = zext(TMPD3[32,32]);
+ # simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 8
+ TMPQ5[0,64] = TMPQ2[0,64] - TMPQ4[0,64];
+ TMPQ5[64,64] = TMPQ2[64,64] - TMPQ4[64,64];
+ # simd unary TMPQ6 = MP_INT_ABS(TMPQ5) on lane size 8
+ TMPQ6[0,64] = MP_INT_ABS(TMPQ5[0,64]);
+ TMPQ6[64,64] = MP_INT_ABS(TMPQ5[64,64]);
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ6 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ6[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ6[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.344 UABAL, UABAL2 page C7-2811 line 164248 MATCH x2e205000/mask=xbf20fc00
+# CONSTRUCT x6e605000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 $-@4 $abs@4 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uabal2/3@2
+# AUNIT --inst x6e605000/mask=xffe0fc00 --status pass --comment "ext abd"
+
+:uabal2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x5 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = zext(TMPD1[0,16]);
+ TMPQ2[32,32] = zext(TMPD1[16,16]);
+ TMPQ2[64,32] = zext(TMPD1[32,16]);
+ TMPQ2[96,32] = zext(TMPD1[48,16]);
+ TMPD3 = Rm_VPR128.8H[64,64];
+ # simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4)
+ TMPQ4[0,32] = zext(TMPD3[0,16]);
+ TMPQ4[32,32] = zext(TMPD3[16,16]);
+ TMPQ4[64,32] = zext(TMPD3[32,16]);
+ TMPQ4[96,32] = zext(TMPD3[48,16]);
+ # simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 4
+ TMPQ5[0,32] = TMPQ2[0,32] - TMPQ4[0,32];
+ TMPQ5[32,32] = TMPQ2[32,32] - TMPQ4[32,32];
+ TMPQ5[64,32] = TMPQ2[64,32] - TMPQ4[64,32];
+ TMPQ5[96,32] = TMPQ2[96,32] - TMPQ4[96,32];
+ # simd unary TMPQ6 = MP_INT_ABS(TMPQ5) on lane size 4
+ TMPQ6[0,32] = MP_INT_ABS(TMPQ5[0,32]);
+ TMPQ6[32,32] = MP_INT_ABS(TMPQ5[32,32]);
+ TMPQ6[64,32] = MP_INT_ABS(TMPQ5[64,32]);
+ TMPQ6[96,32] = MP_INT_ABS(TMPQ5[96,32]);
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ6 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ6[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ6[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ6[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ6[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.344 UABAL, UABAL2 page C7-2811 line 164248 MATCH x2e205000/mask=xbf20fc00
+# CONSTRUCT x6e205000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 $-@2 $abs@2 &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uabal2/3@1
+# AUNIT --inst x6e205000/mask=xffe0fc00 --status pass --comment "ext abd"
+
+:uabal2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x5 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
+{
+ TMPD1 = Rn_VPR128.16B[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)
+ TMPQ2[0,16] = zext(TMPD1[0,8]);
+ TMPQ2[16,16] = zext(TMPD1[8,8]);
+ TMPQ2[32,16] = zext(TMPD1[16,8]);
+ TMPQ2[48,16] = zext(TMPD1[24,8]);
+ TMPQ2[64,16] = zext(TMPD1[32,8]);
+ TMPQ2[80,16] = zext(TMPD1[40,8]);
+ TMPQ2[96,16] = zext(TMPD1[48,8]);
+ TMPQ2[112,16] = zext(TMPD1[56,8]);
+ TMPD3 = Rm_VPR128.16B[64,64];
+ # simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2)
+ TMPQ4[0,16] = zext(TMPD3[0,8]);
+ TMPQ4[16,16] = zext(TMPD3[8,8]);
+ TMPQ4[32,16] = zext(TMPD3[16,8]);
+ TMPQ4[48,16] = zext(TMPD3[24,8]);
+ TMPQ4[64,16] = zext(TMPD3[32,8]);
+ TMPQ4[80,16] = zext(TMPD3[40,8]);
+ TMPQ4[96,16] = zext(TMPD3[48,8]);
+ TMPQ4[112,16] = zext(TMPD3[56,8]);
+ # simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 2
+ TMPQ5[0,16] = TMPQ2[0,16] - TMPQ4[0,16];
+ TMPQ5[16,16] = TMPQ2[16,16] - TMPQ4[16,16];
+ TMPQ5[32,16] = TMPQ2[32,16] - TMPQ4[32,16];
+ TMPQ5[48,16] = TMPQ2[48,16] - TMPQ4[48,16];
+ TMPQ5[64,16] = TMPQ2[64,16] - TMPQ4[64,16];
+ TMPQ5[80,16] = TMPQ2[80,16] - TMPQ4[80,16];
+ TMPQ5[96,16] = TMPQ2[96,16] - TMPQ4[96,16];
+ TMPQ5[112,16] = TMPQ2[112,16] - TMPQ4[112,16];
+ # simd unary TMPQ6 = MP_INT_ABS(TMPQ5) on lane size 2
+ TMPQ6[0,16] = MP_INT_ABS(TMPQ5[0,16]);
+ TMPQ6[16,16] = MP_INT_ABS(TMPQ5[16,16]);
+ TMPQ6[32,16] = MP_INT_ABS(TMPQ5[32,16]);
+ TMPQ6[48,16] = MP_INT_ABS(TMPQ5[48,16]);
+ TMPQ6[64,16] = MP_INT_ABS(TMPQ5[64,16]);
+ TMPQ6[80,16] = MP_INT_ABS(TMPQ5[80,16]);
+ TMPQ6[96,16] = MP_INT_ABS(TMPQ5[96,16]);
+ TMPQ6[112,16] = MP_INT_ABS(TMPQ5[112,16]);
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ6 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ6[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ6[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ6[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ6[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ6[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ6[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ6[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ6[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.344 UABAL, UABAL2 page C7-2811 line 164248 MATCH x2e205000/mask=xbf20fc00
+# CONSTRUCT x2ea05000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@4:16 ARG3 $zext@4:16 $-@8 $abs@8 &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uabal/3@4
+# AUNIT --inst x2ea05000/mask=xffe0fc00 --status pass --comment "ext abd"
+
+:uabal Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x5 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);
+ # simd resize TMPQ2 = zext(Rm_VPR64.2S) (lane size 4 to 8)
+ TMPQ2[0,64] = zext(Rm_VPR64.2S[0,32]);
+ TMPQ2[64,64] = zext(Rm_VPR64.2S[32,32]);
+ # simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 8
+ TMPQ3[0,64] = TMPQ1[0,64] - TMPQ2[0,64];
+ TMPQ3[64,64] = TMPQ1[64,64] - TMPQ2[64,64];
+ # simd unary TMPQ4 = MP_INT_ABS(TMPQ3) on lane size 8
+ TMPQ4[0,64] = MP_INT_ABS(TMPQ3[0,64]);
+ TMPQ4[64,64] = MP_INT_ABS(TMPQ3[64,64]);
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ4 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ4[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ4[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.344 UABAL, UABAL2 page C7-2811 line 164248 MATCH x2e205000/mask=xbf20fc00
+# CONSTRUCT x2e605000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@2:16 ARG3 $zext@2:16 $-@4 $abs@4 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uabal/3@2
+# AUNIT --inst x2e605000/mask=xffe0fc00 --status pass --comment "ext abd"
+
+:uabal Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x5 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);
+ # simd resize TMPQ2 = zext(Rm_VPR64.4H) (lane size 2 to 4)
+ TMPQ2[0,32] = zext(Rm_VPR64.4H[0,16]);
+ TMPQ2[32,32] = zext(Rm_VPR64.4H[16,16]);
+ TMPQ2[64,32] = zext(Rm_VPR64.4H[32,16]);
+ TMPQ2[96,32] = zext(Rm_VPR64.4H[48,16]);
+ # simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 4
+ TMPQ3[0,32] = TMPQ1[0,32] - TMPQ2[0,32];
+ TMPQ3[32,32] = TMPQ1[32,32] - TMPQ2[32,32];
+ TMPQ3[64,32] = TMPQ1[64,32] - TMPQ2[64,32];
+ TMPQ3[96,32] = TMPQ1[96,32] - TMPQ2[96,32];
+ # simd unary TMPQ4 = MP_INT_ABS(TMPQ3) on lane size 4
+ TMPQ4[0,32] = MP_INT_ABS(TMPQ3[0,32]);
+ TMPQ4[32,32] = MP_INT_ABS(TMPQ3[32,32]);
+ TMPQ4[64,32] = MP_INT_ABS(TMPQ3[64,32]);
+ TMPQ4[96,32] = MP_INT_ABS(TMPQ3[96,32]);
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ4 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ4[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ4[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ4[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ4[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.344 UABAL, UABAL2 page C7-2811 line 164248 MATCH x2e205000/mask=xbf20fc00
+# CONSTRUCT x2e205000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@1:16 ARG3 $zext@1:16 $-@2 $abs@2 &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_uabal/3@1
+# AUNIT --inst x2e205000/mask=xffe0fc00 --status pass --comment "ext abd"
+
+:uabal Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x5 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2)
+ TMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]);
+ TMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]);
+ TMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]);
+ TMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]);
+ TMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]);
+ TMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]);
+ TMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]);
+ TMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]);
+ # simd resize TMPQ2 = zext(Rm_VPR64.8B) (lane size 1 to 2)
+ TMPQ2[0,16] = zext(Rm_VPR64.8B[0,8]);
+ TMPQ2[16,16] = zext(Rm_VPR64.8B[8,8]);
+ TMPQ2[32,16] = zext(Rm_VPR64.8B[16,8]);
+ TMPQ2[48,16] = zext(Rm_VPR64.8B[24,8]);
+ TMPQ2[64,16] = zext(Rm_VPR64.8B[32,8]);
+ TMPQ2[80,16] = zext(Rm_VPR64.8B[40,8]);
+ TMPQ2[96,16] = zext(Rm_VPR64.8B[48,8]);
+ TMPQ2[112,16] = zext(Rm_VPR64.8B[56,8]);
+ # simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 2
+ TMPQ3[0,16] = TMPQ1[0,16] - TMPQ2[0,16];
+ TMPQ3[16,16] = TMPQ1[16,16] - TMPQ2[16,16];
+ TMPQ3[32,16] = TMPQ1[32,16] - TMPQ2[32,16];
+ TMPQ3[48,16] = TMPQ1[48,16] - TMPQ2[48,16];
+ TMPQ3[64,16] = TMPQ1[64,16] - TMPQ2[64,16];
+ TMPQ3[80,16] = TMPQ1[80,16] - TMPQ2[80,16];
+ TMPQ3[96,16] = TMPQ1[96,16] - TMPQ2[96,16];
+ TMPQ3[112,16] = TMPQ1[112,16] - TMPQ2[112,16];
+ # simd unary TMPQ4 = MP_INT_ABS(TMPQ3) on lane size 2
+ TMPQ4[0,16] = MP_INT_ABS(TMPQ3[0,16]);
+ TMPQ4[16,16] = MP_INT_ABS(TMPQ3[16,16]);
+ TMPQ4[32,16] = MP_INT_ABS(TMPQ3[32,16]);
+ TMPQ4[48,16] = MP_INT_ABS(TMPQ3[48,16]);
+ TMPQ4[64,16] = MP_INT_ABS(TMPQ3[64,16]);
+ TMPQ4[80,16] = MP_INT_ABS(TMPQ3[80,16]);
+ TMPQ4[96,16] = MP_INT_ABS(TMPQ3[96,16]);
+ TMPQ4[112,16] = MP_INT_ABS(TMPQ3[112,16]);
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ4 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ4[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ4[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ4[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ4[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ4[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ4[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ4[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ4[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.345 UABD page C7-2813 line 164369 MATCH x2e207400/mask=xbf20fc00
+# CONSTRUCT x6e207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabd/2@1
+# AUNIT --inst x6e207400/mask=xffe0fc00 --status nopcodeop --comment "abd"
+
+:uabd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xe & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_uabd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.345 UABD page C7-2813 line 164369 MATCH x2e207400/mask=xbf20fc00
+# CONSTRUCT x2ea07400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $-@4 ARG3 ARG2 $-@4 2:4 &=$* ARG2 ARG3 $less@4 &=$*@4 =$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabd/2@4
+# AUNIT --inst x2ea07400/mask=xffe0fc00 --status pass --comment "abd"
+# This abd instruction is implemented correctly to document a correct
+# way to implement the unsigned absolute difference semantic.
+
+:uabd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xe & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ # simd infix TMPD1 = Rn_VPR64.2S - Rm_VPR64.2S on lane size 4
+ TMPD1[0,32] = Rn_VPR64.2S[0,32] - Rm_VPR64.2S[0,32];
+ TMPD1[32,32] = Rn_VPR64.2S[32,32] - Rm_VPR64.2S[32,32];
+ # simd infix TMPD2 = Rm_VPR64.2S - Rn_VPR64.2S on lane size 4
+ TMPD2[0,32] = Rm_VPR64.2S[0,32] - Rn_VPR64.2S[0,32];
+ TMPD2[32,32] = Rm_VPR64.2S[32,32] - Rn_VPR64.2S[32,32];
+ # simd infix TMPD2 = TMPD2 * 2:4 on lane size 4
+ TMPD2[0,32] = TMPD2[0,32] * 2:4;
+ TMPD2[32,32] = TMPD2[32,32] * 2:4;
+ # simd infix TMPD3 = Rn_VPR64.2S < Rm_VPR64.2S on lane size 4
+ TMPD3[0,32] = zext(Rn_VPR64.2S[0,32] < Rm_VPR64.2S[0,32]);
+ TMPD3[32,32] = zext(Rn_VPR64.2S[32,32] < Rm_VPR64.2S[32,32]);
+ # simd infix TMPD2 = TMPD2 * TMPD3 on lane size 4
+ TMPD2[0,32] = TMPD2[0,32] * TMPD3[0,32];
+ TMPD2[32,32] = TMPD2[32,32] * TMPD3[32,32];
+ # simd infix Rd_VPR64.2S = TMPD1 + TMPD2 on lane size 4
+ Rd_VPR64.2S[0,32] = TMPD1[0,32] + TMPD2[0,32];
+ Rd_VPR64.2S[32,32] = TMPD1[32,32] + TMPD2[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.345 UABD page C7-2813 line 164369 MATCH x2e207400/mask=xbf20fc00
+# CONSTRUCT x2e607400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabd/2@2
+# AUNIT --inst x2e607400/mask=xffe0fc00 --status nopcodeop --comment "abd"
+
+:uabd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xe & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_uabd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.345 UABD page C7-2813 line 164369 MATCH x2e207400/mask=xbf20fc00
+# CONSTRUCT x6ea07400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabd/2@4
+# AUNIT --inst x6ea07400/mask=xffe0fc00 --status nopcodeop --comment "abd"
+
+:uabd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xe & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_uabd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.345 UABD page C7-2813 line 164369 MATCH x2e207400/mask=xbf20fc00
+# CONSTRUCT x2e207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabd/2@1
+# AUNIT --inst x2e207400/mask=xffe0fc00 --status nopcodeop --comment "abd"
+
+:uabd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xe & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_uabd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.345 UABD page C7-2813 line 164369 MATCH x2e207400/mask=xbf20fc00
+# CONSTRUCT x6e607400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabd/2@2
+# AUNIT --inst x6e607400/mask=xffe0fc00 --status nopcodeop --comment "abd"
+
+:uabd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xe & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_uabd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.346 UABDL, UABDL2 page C7-2815 line 164471 MATCH x2e207000/mask=xbf20fc00
+# CONSTRUCT x6ea07000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 $-@8 =$abs@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabdl2/2@4
+# AUNIT --inst x6ea07000/mask=xffe0fc00 --status pass --comment "ext abd"
+
+:uabdl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x7 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = zext(TMPD1[0,32]);
+ TMPQ2[64,64] = zext(TMPD1[32,32]);
+ TMPD3 = Rm_VPR128.4S[64,64];
+ # simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8)
+ TMPQ4[0,64] = zext(TMPD3[0,32]);
+ TMPQ4[64,64] = zext(TMPD3[32,32]);
+ # simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 8
+ TMPQ5[0,64] = TMPQ2[0,64] - TMPQ4[0,64];
+ TMPQ5[64,64] = TMPQ2[64,64] - TMPQ4[64,64];
+ # simd unary Rd_VPR128.2D = MP_INT_ABS(TMPQ5) on lane size 8
+ Rd_VPR128.2D[0,64] = MP_INT_ABS(TMPQ5[0,64]);
+ Rd_VPR128.2D[64,64] = MP_INT_ABS(TMPQ5[64,64]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.346 UABDL, UABDL2 page C7-2815 line 164471 MATCH x2e207000/mask=xbf20fc00
+# CONSTRUCT x6e607000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 $-@4 =$abs@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabdl2/2@2
+# AUNIT --inst x6e607000/mask=xffe0fc00 --status pass --comment "ext abd"
+
+:uabdl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x7 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = zext(TMPD1[0,16]);
+ TMPQ2[32,32] = zext(TMPD1[16,16]);
+ TMPQ2[64,32] = zext(TMPD1[32,16]);
+ TMPQ2[96,32] = zext(TMPD1[48,16]);
+ TMPD3 = Rm_VPR128.8H[64,64];
+ # simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4)
+ TMPQ4[0,32] = zext(TMPD3[0,16]);
+ TMPQ4[32,32] = zext(TMPD3[16,16]);
+ TMPQ4[64,32] = zext(TMPD3[32,16]);
+ TMPQ4[96,32] = zext(TMPD3[48,16]);
+ # simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 4
+ TMPQ5[0,32] = TMPQ2[0,32] - TMPQ4[0,32];
+ TMPQ5[32,32] = TMPQ2[32,32] - TMPQ4[32,32];
+ TMPQ5[64,32] = TMPQ2[64,32] - TMPQ4[64,32];
+ TMPQ5[96,32] = TMPQ2[96,32] - TMPQ4[96,32];
+ # simd unary Rd_VPR128.4S = MP_INT_ABS(TMPQ5) on lane size 4
+ Rd_VPR128.4S[0,32] = MP_INT_ABS(TMPQ5[0,32]);
+ Rd_VPR128.4S[32,32] = MP_INT_ABS(TMPQ5[32,32]);
+ Rd_VPR128.4S[64,32] = MP_INT_ABS(TMPQ5[64,32]);
+ Rd_VPR128.4S[96,32] = MP_INT_ABS(TMPQ5[96,32]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.346 UABDL, UABDL2 page C7-2815 line 164471 MATCH x2e207000/mask=xbf20fc00
+# CONSTRUCT x6e207000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 $-@2 =$abs@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabdl2/2@1
+# AUNIT --inst x6e207000/mask=xffe0fc00 --status pass --comment "ext abd"
+
+:uabdl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x7 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
+{
+ TMPD1 = Rn_VPR128.16B[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)
+ TMPQ2[0,16] = zext(TMPD1[0,8]);
+ TMPQ2[16,16] = zext(TMPD1[8,8]);
+ TMPQ2[32,16] = zext(TMPD1[16,8]);
+ TMPQ2[48,16] = zext(TMPD1[24,8]);
+ TMPQ2[64,16] = zext(TMPD1[32,8]);
+ TMPQ2[80,16] = zext(TMPD1[40,8]);
+ TMPQ2[96,16] = zext(TMPD1[48,8]);
+ TMPQ2[112,16] = zext(TMPD1[56,8]);
+ TMPD3 = Rm_VPR128.16B[64,64];
+ # simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2)
+ TMPQ4[0,16] = zext(TMPD3[0,8]);
+ TMPQ4[16,16] = zext(TMPD3[8,8]);
+ TMPQ4[32,16] = zext(TMPD3[16,8]);
+ TMPQ4[48,16] = zext(TMPD3[24,8]);
+ TMPQ4[64,16] = zext(TMPD3[32,8]);
+ TMPQ4[80,16] = zext(TMPD3[40,8]);
+ TMPQ4[96,16] = zext(TMPD3[48,8]);
+ TMPQ4[112,16] = zext(TMPD3[56,8]);
+ # simd infix TMPQ5 = TMPQ2 - TMPQ4 on lane size 2
+ TMPQ5[0,16] = TMPQ2[0,16] - TMPQ4[0,16];
+ TMPQ5[16,16] = TMPQ2[16,16] - TMPQ4[16,16];
+ TMPQ5[32,16] = TMPQ2[32,16] - TMPQ4[32,16];
+ TMPQ5[48,16] = TMPQ2[48,16] - TMPQ4[48,16];
+ TMPQ5[64,16] = TMPQ2[64,16] - TMPQ4[64,16];
+ TMPQ5[80,16] = TMPQ2[80,16] - TMPQ4[80,16];
+ TMPQ5[96,16] = TMPQ2[96,16] - TMPQ4[96,16];
+ TMPQ5[112,16] = TMPQ2[112,16] - TMPQ4[112,16];
+ # simd unary Rd_VPR128.8H = MP_INT_ABS(TMPQ5) on lane size 2
+ Rd_VPR128.8H[0,16] = MP_INT_ABS(TMPQ5[0,16]);
+ Rd_VPR128.8H[16,16] = MP_INT_ABS(TMPQ5[16,16]);
+ Rd_VPR128.8H[32,16] = MP_INT_ABS(TMPQ5[32,16]);
+ Rd_VPR128.8H[48,16] = MP_INT_ABS(TMPQ5[48,16]);
+ Rd_VPR128.8H[64,16] = MP_INT_ABS(TMPQ5[64,16]);
+ Rd_VPR128.8H[80,16] = MP_INT_ABS(TMPQ5[80,16]);
+ Rd_VPR128.8H[96,16] = MP_INT_ABS(TMPQ5[96,16]);
+ Rd_VPR128.8H[112,16] = MP_INT_ABS(TMPQ5[112,16]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.346 UABDL, UABDL2 page C7-2815 line 164471 MATCH x2e207000/mask=xbf20fc00
+# CONSTRUCT x2ea07000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@4:16 ARG3 $zext@4:16 $-@8 =$abs@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabdl/2@4
+# AUNIT --inst x2ea07000/mask=xffe0fc00 --status pass --comment "ext abd"
+
+:uabdl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x7 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);
+ # simd resize TMPQ2 = zext(Rm_VPR64.2S) (lane size 4 to 8)
+ TMPQ2[0,64] = zext(Rm_VPR64.2S[0,32]);
+ TMPQ2[64,64] = zext(Rm_VPR64.2S[32,32]);
+ # simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 8
+ TMPQ3[0,64] = TMPQ1[0,64] - TMPQ2[0,64];
+ TMPQ3[64,64] = TMPQ1[64,64] - TMPQ2[64,64];
+ # simd unary Rd_VPR128.2D = MP_INT_ABS(TMPQ3) on lane size 8
+ Rd_VPR128.2D[0,64] = MP_INT_ABS(TMPQ3[0,64]);
+ Rd_VPR128.2D[64,64] = MP_INT_ABS(TMPQ3[64,64]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.346 UABDL, UABDL2 page C7-2815 line 164471 MATCH x2e207000/mask=xbf20fc00
+# CONSTRUCT x2e607000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@2:16 ARG3 $zext@2:16 $-@4 =$abs@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabdl/2@2
+# AUNIT --inst x2e607000/mask=xffe0fc00 --status pass --comment "ext abd"
+
+:uabdl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x7 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Rn_VPR128 & Rm_VPR128 & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);
+ # simd resize TMPQ2 = zext(Rm_VPR64.4H) (lane size 2 to 4)
+ TMPQ2[0,32] = zext(Rm_VPR64.4H[0,16]);
+ TMPQ2[32,32] = zext(Rm_VPR64.4H[16,16]);
+ TMPQ2[64,32] = zext(Rm_VPR64.4H[32,16]);
+ TMPQ2[96,32] = zext(Rm_VPR64.4H[48,16]);
+ # simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 4
+ TMPQ3[0,32] = TMPQ1[0,32] - TMPQ2[0,32];
+ TMPQ3[32,32] = TMPQ1[32,32] - TMPQ2[32,32];
+ TMPQ3[64,32] = TMPQ1[64,32] - TMPQ2[64,32];
+ TMPQ3[96,32] = TMPQ1[96,32] - TMPQ2[96,32];
+ # simd unary Rd_VPR128.4S = MP_INT_ABS(TMPQ3) on lane size 4
+ Rd_VPR128.4S[0,32] = MP_INT_ABS(TMPQ3[0,32]);
+ Rd_VPR128.4S[32,32] = MP_INT_ABS(TMPQ3[32,32]);
+ Rd_VPR128.4S[64,32] = MP_INT_ABS(TMPQ3[64,32]);
+ Rd_VPR128.4S[96,32] = MP_INT_ABS(TMPQ3[96,32]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.346 UABDL, UABDL2 page C7-2815 line 164471 MATCH x2e207000/mask=xbf20fc00
+# CONSTRUCT x2e207000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@1:16 ARG3 $zext@1:16 $-@2 =$abs@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uabdl/2@1
+# AUNIT --inst x2e207000/mask=xffe0fc00 --status pass --comment "ext abd"
+
+:uabdl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x7 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Rn_VPR128 & Rm_VPR128 & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2)
+ TMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]);
+ TMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]);
+ TMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]);
+ TMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]);
+ TMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]);
+ TMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]);
+ TMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]);
+ TMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]);
+ # simd resize TMPQ2 = zext(Rm_VPR64.8B) (lane size 1 to 2)
+ TMPQ2[0,16] = zext(Rm_VPR64.8B[0,8]);
+ TMPQ2[16,16] = zext(Rm_VPR64.8B[8,8]);
+ TMPQ2[32,16] = zext(Rm_VPR64.8B[16,8]);
+ TMPQ2[48,16] = zext(Rm_VPR64.8B[24,8]);
+ TMPQ2[64,16] = zext(Rm_VPR64.8B[32,8]);
+ TMPQ2[80,16] = zext(Rm_VPR64.8B[40,8]);
+ TMPQ2[96,16] = zext(Rm_VPR64.8B[48,8]);
+ TMPQ2[112,16] = zext(Rm_VPR64.8B[56,8]);
+ # simd infix TMPQ3 = TMPQ1 - TMPQ2 on lane size 2
+ TMPQ3[0,16] = TMPQ1[0,16] - TMPQ2[0,16];
+ TMPQ3[16,16] = TMPQ1[16,16] - TMPQ2[16,16];
+ TMPQ3[32,16] = TMPQ1[32,16] - TMPQ2[32,16];
+ TMPQ3[48,16] = TMPQ1[48,16] - TMPQ2[48,16];
+ TMPQ3[64,16] = TMPQ1[64,16] - TMPQ2[64,16];
+ TMPQ3[80,16] = TMPQ1[80,16] - TMPQ2[80,16];
+ TMPQ3[96,16] = TMPQ1[96,16] - TMPQ2[96,16];
+ TMPQ3[112,16] = TMPQ1[112,16] - TMPQ2[112,16];
+ # simd unary Rd_VPR128.8H = MP_INT_ABS(TMPQ3) on lane size 2
+ Rd_VPR128.8H[0,16] = MP_INT_ABS(TMPQ3[0,16]);
+ Rd_VPR128.8H[16,16] = MP_INT_ABS(TMPQ3[16,16]);
+ Rd_VPR128.8H[32,16] = MP_INT_ABS(TMPQ3[32,16]);
+ Rd_VPR128.8H[48,16] = MP_INT_ABS(TMPQ3[48,16]);
+ Rd_VPR128.8H[64,16] = MP_INT_ABS(TMPQ3[64,16]);
+ Rd_VPR128.8H[80,16] = MP_INT_ABS(TMPQ3[80,16]);
+ Rd_VPR128.8H[96,16] = MP_INT_ABS(TMPQ3[96,16]);
+ Rd_VPR128.8H[112,16] = MP_INT_ABS(TMPQ3[112,16]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.347 UADALP page C7-2817 line 164592 MATCH x2e206800/mask=xbf3ffc00
+# CONSTRUCT x6e206800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 var:16 ARG2 =#u+ &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_uadalp/2@1
+# AUNIT --inst x6e206800/mask=xfffffc00 --status pass --comment "ext"
+
+:uadalp Rd_VPR128.8H, Rn_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x6 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
+{
+ TMPQ1 = 0;
+ # sipd infix TMPQ1 = +(Rn_VPR128.16B) on pairs lane size (1 to 2)
+ local tmp2 = Rn_VPR128.16B[0,8];
+ local tmp4 = zext(tmp2);
+ local tmp3 = Rn_VPR128.16B[8,8];
+ local tmp5 = zext(tmp3);
+ TMPQ1[0,16] = tmp4 + tmp5;
+ tmp2 = Rn_VPR128.16B[16,8];
+ tmp4 = zext(tmp2);
+ tmp3 = Rn_VPR128.16B[24,8];
+ tmp5 = zext(tmp3);
+ TMPQ1[16,16] = tmp4 + tmp5;
+ tmp2 = Rn_VPR128.16B[32,8];
+ tmp4 = zext(tmp2);
+ tmp3 = Rn_VPR128.16B[40,8];
+ tmp5 = zext(tmp3);
+ TMPQ1[32,16] = tmp4 + tmp5;
+ tmp2 = Rn_VPR128.16B[48,8];
+ tmp4 = zext(tmp2);
+ tmp3 = Rn_VPR128.16B[56,8];
+ tmp5 = zext(tmp3);
+ TMPQ1[48,16] = tmp4 + tmp5;
+ tmp2 = Rn_VPR128.16B[64,8];
+ tmp4 = zext(tmp2);
+ tmp3 = Rn_VPR128.16B[72,8];
+ tmp5 = zext(tmp3);
+ TMPQ1[64,16] = tmp4 + tmp5;
+ tmp2 = Rn_VPR128.16B[80,8];
+ tmp4 = zext(tmp2);
+ tmp3 = Rn_VPR128.16B[88,8];
+ tmp5 = zext(tmp3);
+ TMPQ1[80,16] = tmp4 + tmp5;
+ tmp2 = Rn_VPR128.16B[96,8];
+ tmp4 = zext(tmp2);
+ tmp3 = Rn_VPR128.16B[104,8];
+ tmp5 = zext(tmp3);
+ TMPQ1[96,16] = tmp4 + tmp5;
+ tmp2 = Rn_VPR128.16B[112,8];
+ tmp4 = zext(tmp2);
+ tmp3 = Rn_VPR128.16B[120,8];
+ tmp5 = zext(tmp3);
+ TMPQ1[112,16] = tmp4 + tmp5;
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.347 UADALP page C7-2817 line 164592 MATCH x2e206800/mask=xbf3ffc00
+# CONSTRUCT x2ea06800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 var:8 ARG2 =#u+ &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_uadalp/2@4
+# AUNIT --inst x2ea06800/mask=xfffffc00 --status pass --comment "ext"
+
+:uadalp Rd_VPR64.1D, Rn_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x6 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.1D & Zd
+{
+ TMPD1 = 0;
+ # sipd infix TMPD1 = +(Rn_VPR64.2S) on pairs lane size (4 to 8)
+ local tmp2 = Rn_VPR64.2S[0,32];
+ local tmp4 = zext(tmp2);
+ local tmp3 = Rn_VPR64.2S[32,32];
+ local tmp5 = zext(tmp3);
+ TMPD1 = tmp4 + tmp5;
+ # simd infix Rd_VPR64.1D = Rd_VPR64.1D + TMPD1 on lane size 8
+ Rd_VPR64.1D = Rd_VPR64.1D + TMPD1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.347 UADALP page C7-2817 line 164592 MATCH x2e206800/mask=xbf3ffc00
+# CONSTRUCT x2e606800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 var:8 ARG2 =#u+ &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_uadalp/2@2
+# AUNIT --inst x2e606800/mask=xfffffc00 --status pass --comment "ext"
+
+:uadalp Rd_VPR64.2S, Rn_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x6 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.2S & Zd
+{
+ TMPD1 = 0;
+ # sipd infix TMPD1 = +(Rn_VPR64.4H) on pairs lane size (2 to 4)
+ local tmp2 = Rn_VPR64.4H[0,16];
+ local tmp4 = zext(tmp2);
+ local tmp3 = Rn_VPR64.4H[16,16];
+ local tmp5 = zext(tmp3);
+ TMPD1[0,32] = tmp4 + tmp5;
+ tmp2 = Rn_VPR64.4H[32,16];
+ tmp4 = zext(tmp2);
+ tmp3 = Rn_VPR64.4H[48,16];
+ tmp5 = zext(tmp3);
+ TMPD1[32,32] = tmp4 + tmp5;
+ # simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4
+ Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32];
+ Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.347 UADALP page C7-2817 line 164592 MATCH x2e206800/mask=xbf3ffc00
+# CONSTRUCT x6ea06800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 var:16 ARG2 =#u+ &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_uadalp/2@4
+# AUNIT --inst x6ea06800/mask=xfffffc00 --status pass --comment "ext"
+
+:uadalp Rd_VPR128.2D, Rn_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x6 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPQ1 = 0;
+ # sipd infix TMPQ1 = +(Rn_VPR128.4S) on pairs lane size (4 to 8)
+ local tmp2 = Rn_VPR128.4S[0,32];
+ local tmp4 = zext(tmp2);
+ local tmp3 = Rn_VPR128.4S[32,32];
+ local tmp5 = zext(tmp3);
+ TMPQ1[0,64] = tmp4 + tmp5;
+ tmp2 = Rn_VPR128.4S[64,32];
+ tmp4 = zext(tmp2);
+ tmp3 = Rn_VPR128.4S[96,32];
+ tmp5 = zext(tmp3);
+ TMPQ1[64,64] = tmp4 + tmp5;
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ1 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ1[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ1[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.347 UADALP page C7-2817 line 164592 MATCH x2e206800/mask=xbf3ffc00
+# CONSTRUCT x2e206800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 var:8 ARG2 =#u+ &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_uadalp/2@1
+# AUNIT --inst x2e206800/mask=xfffffc00 --status pass --comment "ext"
+
+:uadalp Rd_VPR64.4H, Rn_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x6 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.4H & Zd
+{
+ TMPD1 = 0;
+ # sipd infix TMPD1 = +(Rn_VPR64.8B) on pairs lane size (1 to 2)
+ local tmp2 = Rn_VPR64.8B[0,8];
+ local tmp4 = zext(tmp2);
+ local tmp3 = Rn_VPR64.8B[8,8];
+ local tmp5 = zext(tmp3);
+ TMPD1[0,16] = tmp4 + tmp5;
+ tmp2 = Rn_VPR64.8B[16,8];
+ tmp4 = zext(tmp2);
+ tmp3 = Rn_VPR64.8B[24,8];
+ tmp5 = zext(tmp3);
+ TMPD1[16,16] = tmp4 + tmp5;
+ tmp2 = Rn_VPR64.8B[32,8];
+ tmp4 = zext(tmp2);
+ tmp3 = Rn_VPR64.8B[40,8];
+ tmp5 = zext(tmp3);
+ TMPD1[32,16] = tmp4 + tmp5;
+ tmp2 = Rn_VPR64.8B[48,8];
+ tmp4 = zext(tmp2);
+ tmp3 = Rn_VPR64.8B[56,8];
+ tmp5 = zext(tmp3);
+ TMPD1[48,16] = tmp4 + tmp5;
+ # simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2
+ Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16];
+ Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16];
+ Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16];
+ Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.347 UADALP page C7-2817 line 164592 MATCH x2e206800/mask=xbf3ffc00
+# CONSTRUCT x6e606800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 var:16 ARG2 =#u+ &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_uadalp/2@2
+# AUNIT --inst x6e606800/mask=xfffffc00 --status pass --comment "ext"
+
+:uadalp Rd_VPR128.4S, Rn_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x6 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPQ1 = 0;
+ # sipd infix TMPQ1 = +(Rn_VPR128.8H) on pairs lane size (2 to 4)
+ local tmp2 = Rn_VPR128.8H[0,16];
+ local tmp4 = zext(tmp2);
+ local tmp3 = Rn_VPR128.8H[16,16];
+ local tmp5 = zext(tmp3);
+ TMPQ1[0,32] = tmp4 + tmp5;
+ tmp2 = Rn_VPR128.8H[32,16];
+ tmp4 = zext(tmp2);
+ tmp3 = Rn_VPR128.8H[48,16];
+ tmp5 = zext(tmp3);
+ TMPQ1[32,32] = tmp4 + tmp5;
+ tmp2 = Rn_VPR128.8H[64,16];
+ tmp4 = zext(tmp2);
+ tmp3 = Rn_VPR128.8H[80,16];
+ tmp5 = zext(tmp3);
+ TMPQ1[64,32] = tmp4 + tmp5;
+ tmp2 = Rn_VPR128.8H[96,16];
+ tmp4 = zext(tmp2);
+ tmp3 = Rn_VPR128.8H[112,16];
+ tmp5 = zext(tmp3);
+ TMPQ1[96,32] = tmp4 + tmp5;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.348 UADDL, UADDL2 page C7-2819 line 164702 MATCH x2e200000/mask=xbf20fc00
+# CONSTRUCT x6ea00000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 =$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddl2/2@4
+# AUNIT --inst x6ea00000/mask=xffe0fc00 --status pass --comment "ext"
+
+:uaddl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x0 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = zext(TMPD1[0,32]);
+ TMPQ2[64,64] = zext(TMPD1[32,32]);
+ TMPD3 = Rm_VPR128.4S[64,64];
+ # simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8)
+ TMPQ4[0,64] = zext(TMPD3[0,32]);
+ TMPQ4[64,64] = zext(TMPD3[32,32]);
+ # simd infix Rd_VPR128.2D = TMPQ2 + TMPQ4 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ2[0,64] + TMPQ4[0,64];
+ Rd_VPR128.2D[64,64] = TMPQ2[64,64] + TMPQ4[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.348 UADDL, UADDL2 page C7-2819 line 164702 MATCH x2e200000/mask=xbf20fc00
+# CONSTRUCT x6e600000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 =$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddl2/2@2
+# AUNIT --inst x6e600000/mask=xffe0fc00 --status pass --comment "ext"
+
+:uaddl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x0 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = zext(TMPD1[0,16]);
+ TMPQ2[32,32] = zext(TMPD1[16,16]);
+ TMPQ2[64,32] = zext(TMPD1[32,16]);
+ TMPQ2[96,32] = zext(TMPD1[48,16]);
+ TMPD3 = Rm_VPR128.8H[64,64];
+ # simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4)
+ TMPQ4[0,32] = zext(TMPD3[0,16]);
+ TMPQ4[32,32] = zext(TMPD3[16,16]);
+ TMPQ4[64,32] = zext(TMPD3[32,16]);
+ TMPQ4[96,32] = zext(TMPD3[48,16]);
+ # simd infix Rd_VPR128.4S = TMPQ2 + TMPQ4 on lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ2[0,32] + TMPQ4[0,32];
+ Rd_VPR128.4S[32,32] = TMPQ2[32,32] + TMPQ4[32,32];
+ Rd_VPR128.4S[64,32] = TMPQ2[64,32] + TMPQ4[64,32];
+ Rd_VPR128.4S[96,32] = TMPQ2[96,32] + TMPQ4[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.348 UADDL, UADDL2 page C7-2819 line 164702 MATCH x2e200000/mask=xbf20fc00
+# CONSTRUCT x6e200000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 =$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddl2/2@1
+# AUNIT --inst x6e200000/mask=xffe0fc00 --status pass --comment "ext"
+
+:uaddl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x0 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
+{
+ TMPD1 = Rn_VPR128.16B[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)
+ TMPQ2[0,16] = zext(TMPD1[0,8]);
+ TMPQ2[16,16] = zext(TMPD1[8,8]);
+ TMPQ2[32,16] = zext(TMPD1[16,8]);
+ TMPQ2[48,16] = zext(TMPD1[24,8]);
+ TMPQ2[64,16] = zext(TMPD1[32,8]);
+ TMPQ2[80,16] = zext(TMPD1[40,8]);
+ TMPQ2[96,16] = zext(TMPD1[48,8]);
+ TMPQ2[112,16] = zext(TMPD1[56,8]);
+ TMPD3 = Rm_VPR128.16B[64,64];
+ # simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2)
+ TMPQ4[0,16] = zext(TMPD3[0,8]);
+ TMPQ4[16,16] = zext(TMPD3[8,8]);
+ TMPQ4[32,16] = zext(TMPD3[16,8]);
+ TMPQ4[48,16] = zext(TMPD3[24,8]);
+ TMPQ4[64,16] = zext(TMPD3[32,8]);
+ TMPQ4[80,16] = zext(TMPD3[40,8]);
+ TMPQ4[96,16] = zext(TMPD3[48,8]);
+ TMPQ4[112,16] = zext(TMPD3[56,8]);
+ # simd infix Rd_VPR128.8H = TMPQ2 + TMPQ4 on lane size 2
+ Rd_VPR128.8H[0,16] = TMPQ2[0,16] + TMPQ4[0,16];
+ Rd_VPR128.8H[16,16] = TMPQ2[16,16] + TMPQ4[16,16];
+ Rd_VPR128.8H[32,16] = TMPQ2[32,16] + TMPQ4[32,16];
+ Rd_VPR128.8H[48,16] = TMPQ2[48,16] + TMPQ4[48,16];
+ Rd_VPR128.8H[64,16] = TMPQ2[64,16] + TMPQ4[64,16];
+ Rd_VPR128.8H[80,16] = TMPQ2[80,16] + TMPQ4[80,16];
+ Rd_VPR128.8H[96,16] = TMPQ2[96,16] + TMPQ4[96,16];
+ Rd_VPR128.8H[112,16] = TMPQ2[112,16] + TMPQ4[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.348 UADDL, UADDL2 page C7-2819 line 164702 MATCH x2e200000/mask=xbf20fc00
+# CONSTRUCT x2ea00000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@4:16 ARG3 $zext@4:16 =$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddl/2@4
+# AUNIT --inst x2ea00000/mask=xffe0fc00 --status pass --comment "ext"
+
+:uaddl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x0 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);
+ # simd resize TMPQ2 = zext(Rm_VPR64.2S) (lane size 4 to 8)
+ TMPQ2[0,64] = zext(Rm_VPR64.2S[0,32]);
+ TMPQ2[64,64] = zext(Rm_VPR64.2S[32,32]);
+ # simd infix Rd_VPR128.2D = TMPQ1 + TMPQ2 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ1[0,64] + TMPQ2[0,64];
+ Rd_VPR128.2D[64,64] = TMPQ1[64,64] + TMPQ2[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.348 UADDL, UADDL2 page C7-2819 line 164702 MATCH x2e200000/mask=xbf20fc00
+# CONSTRUCT x2e600000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@2:16 ARG3 $zext@2:16 =$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddl/2@2
+# AUNIT --inst x2e600000/mask=xffe0fc00 --status pass --comment "ext"
+
+:uaddl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x0 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);
+ # simd resize TMPQ2 = zext(Rm_VPR64.4H) (lane size 2 to 4)
+ TMPQ2[0,32] = zext(Rm_VPR64.4H[0,16]);
+ TMPQ2[32,32] = zext(Rm_VPR64.4H[16,16]);
+ TMPQ2[64,32] = zext(Rm_VPR64.4H[32,16]);
+ TMPQ2[96,32] = zext(Rm_VPR64.4H[48,16]);
+ # simd infix Rd_VPR128.4S = TMPQ1 + TMPQ2 on lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ1[0,32] + TMPQ2[0,32];
+ Rd_VPR128.4S[32,32] = TMPQ1[32,32] + TMPQ2[32,32];
+ Rd_VPR128.4S[64,32] = TMPQ1[64,32] + TMPQ2[64,32];
+ Rd_VPR128.4S[96,32] = TMPQ1[96,32] + TMPQ2[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.348 UADDL, UADDL2 page C7-2819 line 164702 MATCH x2e200000/mask=xbf20fc00
+# CONSTRUCT x2e200000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@1:16 ARG3 $zext@1:16 =$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddl/2@1
+# AUNIT --inst x2e200000/mask=xffe0fc00 --status pass --comment "ext"
+
+:uaddl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x0 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2)
+ TMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]);
+ TMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]);
+ TMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]);
+ TMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]);
+ TMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]);
+ TMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]);
+ TMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]);
+ TMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]);
+ # simd resize TMPQ2 = zext(Rm_VPR64.8B) (lane size 1 to 2)
+ TMPQ2[0,16] = zext(Rm_VPR64.8B[0,8]);
+ TMPQ2[16,16] = zext(Rm_VPR64.8B[8,8]);
+ TMPQ2[32,16] = zext(Rm_VPR64.8B[16,8]);
+ TMPQ2[48,16] = zext(Rm_VPR64.8B[24,8]);
+ TMPQ2[64,16] = zext(Rm_VPR64.8B[32,8]);
+ TMPQ2[80,16] = zext(Rm_VPR64.8B[40,8]);
+ TMPQ2[96,16] = zext(Rm_VPR64.8B[48,8]);
+ TMPQ2[112,16] = zext(Rm_VPR64.8B[56,8]);
+ # simd infix Rd_VPR128.8H = TMPQ1 + TMPQ2 on lane size 2
+ Rd_VPR128.8H[0,16] = TMPQ1[0,16] + TMPQ2[0,16];
+ Rd_VPR128.8H[16,16] = TMPQ1[16,16] + TMPQ2[16,16];
+ Rd_VPR128.8H[32,16] = TMPQ1[32,16] + TMPQ2[32,16];
+ Rd_VPR128.8H[48,16] = TMPQ1[48,16] + TMPQ2[48,16];
+ Rd_VPR128.8H[64,16] = TMPQ1[64,16] + TMPQ2[64,16];
+ Rd_VPR128.8H[80,16] = TMPQ1[80,16] + TMPQ2[80,16];
+ Rd_VPR128.8H[96,16] = TMPQ1[96,16] + TMPQ2[96,16];
+ Rd_VPR128.8H[112,16] = TMPQ1[112,16] + TMPQ2[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.349 UADDLP page C7-2821 line 164825 MATCH x2e202800/mask=xbf3ffc00
+# CONSTRUCT x2e202800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =var =#u+@1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlp/1@1
+# AUNIT --inst x2e202800/mask=xfffffc00 --status pass --comment "ext"
+# Vector variant when size = 00 , Q = 0 s=16 e1=1 e2=2 Ta=VPR64.4H Tb=VPR64.8B
+
+:uaddlp Rd_VPR64.4H, Rn_VPR64.8B
+is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000001010 & Rd_VPR64.4H & Rn_VPR64.8B & Zd
+{
+ TMPD1 = Rn_VPR64.8B;
+ # sipd infix Rd_VPR64.4H = +(TMPD1) on pairs lane size (1 to 2)
+ local tmp2 = TMPD1[0,8];
+ local tmp4 = zext(tmp2);
+ local tmp3 = TMPD1[8,8];
+ local tmp5 = zext(tmp3);
+ Rd_VPR64.4H[0,16] = tmp4 + tmp5;
+ tmp2 = TMPD1[16,8];
+ tmp4 = zext(tmp2);
+ tmp3 = TMPD1[24,8];
+ tmp5 = zext(tmp3);
+ Rd_VPR64.4H[16,16] = tmp4 + tmp5;
+ tmp2 = TMPD1[32,8];
+ tmp4 = zext(tmp2);
+ tmp3 = TMPD1[40,8];
+ tmp5 = zext(tmp3);
+ Rd_VPR64.4H[32,16] = tmp4 + tmp5;
+ tmp2 = TMPD1[48,8];
+ tmp4 = zext(tmp2);
+ tmp3 = TMPD1[56,8];
+ tmp5 = zext(tmp3);
+ Rd_VPR64.4H[48,16] = tmp4 + tmp5;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.349 UADDLP page C7-2821 line 164825 MATCH x2e202800/mask=xbf3ffc00
+# CONSTRUCT x6e202800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =var =#u+@1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlp/1@1
+# AUNIT --inst x6e202800/mask=xfffffc00 --status pass --comment "ext"
+# Vector variant when size = 00 , Q = 1 s=32 e1=1 e2=2 Ta=VPR128.8H Tb=VPR128.16B
+
+:uaddlp Rd_VPR128.8H, Rn_VPR128.16B
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000001010 & Rd_VPR128.8H & Rn_VPR128.16B & Zd
+{
+ TMPQ1 = Rn_VPR128.16B;
+ # sipd infix Rd_VPR128.8H = +(TMPQ1) on pairs lane size (1 to 2)
+ local tmp2 = TMPQ1[0,8];
+ local tmp4 = zext(tmp2);
+ local tmp3 = TMPQ1[8,8];
+ local tmp5 = zext(tmp3);
+ Rd_VPR128.8H[0,16] = tmp4 + tmp5;
+ tmp2 = TMPQ1[16,8];
+ tmp4 = zext(tmp2);
+ tmp3 = TMPQ1[24,8];
+ tmp5 = zext(tmp3);
+ Rd_VPR128.8H[16,16] = tmp4 + tmp5;
+ tmp2 = TMPQ1[32,8];
+ tmp4 = zext(tmp2);
+ tmp3 = TMPQ1[40,8];
+ tmp5 = zext(tmp3);
+ Rd_VPR128.8H[32,16] = tmp4 + tmp5;
+ tmp2 = TMPQ1[48,8];
+ tmp4 = zext(tmp2);
+ tmp3 = TMPQ1[56,8];
+ tmp5 = zext(tmp3);
+ Rd_VPR128.8H[48,16] = tmp4 + tmp5;
+ tmp2 = TMPQ1[64,8];
+ tmp4 = zext(tmp2);
+ tmp3 = TMPQ1[72,8];
+ tmp5 = zext(tmp3);
+ Rd_VPR128.8H[64,16] = tmp4 + tmp5;
+ tmp2 = TMPQ1[80,8];
+ tmp4 = zext(tmp2);
+ tmp3 = TMPQ1[88,8];
+ tmp5 = zext(tmp3);
+ Rd_VPR128.8H[80,16] = tmp4 + tmp5;
+ tmp2 = TMPQ1[96,8];
+ tmp4 = zext(tmp2);
+ tmp3 = TMPQ1[104,8];
+ tmp5 = zext(tmp3);
+ Rd_VPR128.8H[96,16] = tmp4 + tmp5;
+ tmp2 = TMPQ1[112,8];
+ tmp4 = zext(tmp2);
+ tmp3 = TMPQ1[120,8];
+ tmp5 = zext(tmp3);
+ Rd_VPR128.8H[112,16] = tmp4 + tmp5;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.349 UADDLP page C7-2821 line 164825 MATCH x2e202800/mask=xbf3ffc00
+# CONSTRUCT x2e602800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =var =#u+@2
+# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlp/1@2
+# AUNIT --inst x2e602800/mask=xfffffc00 --status pass --comment "ext"
+# Vector variant when size = 01 , Q = 0 s=16 e1=2 e2=4 Ta=VPR64.2S Tb=VPR64.4H
+
+:uaddlp Rd_VPR64.2S, Rn_VPR64.4H
+is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000001010 & Rd_VPR64.2S & Rn_VPR64.4H & Zd
+{
+ TMPD1 = Rn_VPR64.4H;
+ # sipd infix Rd_VPR64.2S = +(TMPD1) on pairs lane size (2 to 4)
+ local tmp2 = TMPD1[0,16];
+ local tmp4 = zext(tmp2);
+ local tmp3 = TMPD1[16,16];
+ local tmp5 = zext(tmp3);
+ Rd_VPR64.2S[0,32] = tmp4 + tmp5;
+ tmp2 = TMPD1[32,16];
+ tmp4 = zext(tmp2);
+ tmp3 = TMPD1[48,16];
+ tmp5 = zext(tmp3);
+ Rd_VPR64.2S[32,32] = tmp4 + tmp5;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.349 UADDLP page C7-2821 line 164825 MATCH x2e202800/mask=xbf3ffc00
+# CONSTRUCT x6e602800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =var =#u+@2
+# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlp/1@2
+# AUNIT --inst x6e602800/mask=xfffffc00 --status pass --comment "ext"
+# Vector variant when size = 01 , Q = 1 s=32 e1=2 e2=4 Ta=VPR128.4S Tb=VPR128.8H
+
+:uaddlp Rd_VPR128.4S, Rn_VPR128.8H
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000001010 & Rd_VPR128.4S & Rn_VPR128.8H & Zd
+{
+ TMPQ1 = Rn_VPR128.8H;
+ # sipd infix Rd_VPR128.4S = +(TMPQ1) on pairs lane size (2 to 4)
+ local tmp2 = TMPQ1[0,16];
+ local tmp4 = zext(tmp2);
+ local tmp3 = TMPQ1[16,16];
+ local tmp5 = zext(tmp3);
+ Rd_VPR128.4S[0,32] = tmp4 + tmp5;
+ tmp2 = TMPQ1[32,16];
+ tmp4 = zext(tmp2);
+ tmp3 = TMPQ1[48,16];
+ tmp5 = zext(tmp3);
+ Rd_VPR128.4S[32,32] = tmp4 + tmp5;
+ tmp2 = TMPQ1[64,16];
+ tmp4 = zext(tmp2);
+ tmp3 = TMPQ1[80,16];
+ tmp5 = zext(tmp3);
+ Rd_VPR128.4S[64,32] = tmp4 + tmp5;
+ tmp2 = TMPQ1[96,16];
+ tmp4 = zext(tmp2);
+ tmp3 = TMPQ1[112,16];
+ tmp5 = zext(tmp3);
+ Rd_VPR128.4S[96,32] = tmp4 + tmp5;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.349 UADDLP page C7-2821 line 164825 MATCH x2e202800/mask=xbf3ffc00
+# CONSTRUCT x2ea02800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =var =#u+@4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlp/1@4
+# AUNIT --inst x2ea02800/mask=xfffffc00 --status pass --comment "ext"
+# Vector variant when size = 10 , Q = 0 s=16 e1=4 e2=8 Ta=VPR64.1D Tb=VPR64.2S
+
+:uaddlp Rd_VPR64.1D, Rn_VPR64.2S
+is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000001010 & Rd_VPR64.1D & Rn_VPR64.2S & Zd
+{
+ TMPD1 = Rn_VPR64.2S;
+ # sipd infix Rd_VPR64.1D = +(TMPD1) on pairs lane size (4 to 8)
+ local tmp2 = TMPD1[0,32];
+ local tmp4 = zext(tmp2);
+ local tmp3 = TMPD1[32,32];
+ local tmp5 = zext(tmp3);
+ Rd_VPR64.1D = tmp4 + tmp5;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.349 UADDLP page C7-2821 line 164825 MATCH x2e202800/mask=xbf3ffc00
+# CONSTRUCT x6ea02800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =var =#u+@4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlp/1@4
+# AUNIT --inst x6ea02800/mask=xfffffc00 --status pass --comment "ext"
+# Vector variant when size = 10 , Q = 1 s=32 e1=4 e2=8 Ta=VPR128.2D Tb=VPR128.4S
+
+:uaddlp Rd_VPR128.2D, Rn_VPR128.4S
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000001010 & Rd_VPR128.2D & Rn_VPR128.4S & Zd
+{
+ TMPQ1 = Rn_VPR128.4S;
+ # sipd infix Rd_VPR128.2D = +(TMPQ1) on pairs lane size (4 to 8)
+ local tmp2 = TMPQ1[0,32];
+ local tmp4 = zext(tmp2);
+ local tmp3 = TMPQ1[32,32];
+ local tmp5 = zext(tmp3);
+ Rd_VPR128.2D[0,64] = tmp4 + tmp5;
+ tmp2 = TMPQ1[64,32];
+ tmp4 = zext(tmp2);
+ tmp3 = TMPQ1[96,32];
+ tmp5 = zext(tmp3);
+ Rd_VPR128.2D[64,64] = tmp4 + tmp5;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.350 UADDLV page C7-2823 line 164935 MATCH x2e303800/mask=xbf3ffc00
+# CONSTRUCT x6eb03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlv/1@4
+# AUNIT --inst x6eb03800/mask=xfffffc00 --status nopcodeop --comment "ext"
+
+:uaddlv Rd_FPR64, Rn_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR128.4S & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_uaddlv(Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.350 UADDLV page C7-2823 line 164935 MATCH x2e303800/mask=xbf3ffc00
+# CONSTRUCT x6e303800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlv/1@1
+# AUNIT --inst x6e303800/mask=xfffffc00 --status nopcodeop --comment "ext"
+
+:uaddlv Rd_FPR16, Rn_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR128.16B & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_uaddlv(Rn_VPR128.16B, 1:1);
+}
+
+# C7.2.350 UADDLV page C7-2823 line 164935 MATCH x2e303800/mask=xbf3ffc00
+# CONSTRUCT x2e303800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlv/1@1
+# AUNIT --inst x2e303800/mask=xfffffc00 --status nopcodeop --comment "ext"
+
+:uaddlv Rd_FPR16, Rn_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR64.8B & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_uaddlv(Rn_VPR64.8B, 1:1);
+}
+
+# C7.2.350 UADDLV page C7-2823 line 164935 MATCH x2e303800/mask=xbf3ffc00
+# CONSTRUCT x2e703800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlv/1@2
+# AUNIT --inst x2e703800/mask=xfffffc00 --status nopcodeop --comment "ext"
+
+:uaddlv Rd_FPR32, Rn_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR64.4H & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_uaddlv(Rn_VPR64.4H, 2:1);
+}
+
+# C7.2.350 UADDLV page C7-2823 line 164935 MATCH x2e303800/mask=xbf3ffc00
+# CONSTRUCT x6e703800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_uaddlv/1@2
+# AUNIT --inst x6e703800/mask=xfffffc00 --status nopcodeop --comment "ext"
+
+:uaddlv Rd_FPR32, Rn_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x3 & b_1011=2 & Rn_VPR128.8H & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_uaddlv(Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.351 UADDW, UADDW2 page C7-2825 line 165035 MATCH x2e201000/mask=xbf20fc00
+# CONSTRUCT x6ea01000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3[1]:8 $zext@4:16 =$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddw2/2@4
+# AUNIT --inst x6ea01000/mask=xffe0fc00 --status pass --comment "ext"
+
+:uaddw2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x1 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rm_VPR128.4S[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = zext(TMPD1[0,32]);
+ TMPQ2[64,64] = zext(TMPD1[32,32]);
+ # simd infix Rd_VPR128.2D = Rn_VPR128.2D + TMPQ2 on lane size 8
+ Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] + TMPQ2[0,64];
+ Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] + TMPQ2[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.351 UADDW, UADDW2 page C7-2825 line 165035 MATCH x2e201000/mask=xbf20fc00
+# CONSTRUCT x6e601000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3[1]:8 $zext@2:16 =$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddw2/2@2
+# AUNIT --inst x6e601000/mask=xffe0fc00 --status pass --comment "ext"
+
+:uaddw2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x1 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rm_VPR128.8H[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = zext(TMPD1[0,16]);
+ TMPQ2[32,32] = zext(TMPD1[16,16]);
+ TMPQ2[64,32] = zext(TMPD1[32,16]);
+ TMPQ2[96,32] = zext(TMPD1[48,16]);
+ # simd infix Rd_VPR128.4S = Rn_VPR128.4S + TMPQ2 on lane size 4
+ Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] + TMPQ2[0,32];
+ Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] + TMPQ2[32,32];
+ Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] + TMPQ2[64,32];
+ Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] + TMPQ2[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.351 UADDW, UADDW2 page C7-2825 line 165035 MATCH x2e201000/mask=xbf20fc00
+# CONSTRUCT x6e201000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3[1]:8 $zext@1:16 =$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddw2/2@1
+# AUNIT --inst x6e201000/mask=xffe0fc00 --status pass --comment "ext"
+
+:uaddw2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x1 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ TMPD1 = Rm_VPR128.16B[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)
+ TMPQ2[0,16] = zext(TMPD1[0,8]);
+ TMPQ2[16,16] = zext(TMPD1[8,8]);
+ TMPQ2[32,16] = zext(TMPD1[16,8]);
+ TMPQ2[48,16] = zext(TMPD1[24,8]);
+ TMPQ2[64,16] = zext(TMPD1[32,8]);
+ TMPQ2[80,16] = zext(TMPD1[40,8]);
+ TMPQ2[96,16] = zext(TMPD1[48,8]);
+ TMPQ2[112,16] = zext(TMPD1[56,8]);
+ # simd infix Rd_VPR128.8H = Rn_VPR128.8H + TMPQ2 on lane size 2
+ Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] + TMPQ2[0,16];
+ Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] + TMPQ2[16,16];
+ Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] + TMPQ2[32,16];
+ Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] + TMPQ2[48,16];
+ Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] + TMPQ2[64,16];
+ Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] + TMPQ2[80,16];
+ Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] + TMPQ2[96,16];
+ Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] + TMPQ2[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.351 UADDW, UADDW2 page C7-2825 line 165035 MATCH x2e201000/mask=xbf20fc00
+# CONSTRUCT x2ea01000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $zext@4:16 =$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddw/2@4
+# AUNIT --inst x2ea01000/mask=xffe0fc00 --status pass --comment "ext"
+
+:uaddw Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x1 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = zext(Rm_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = zext(Rm_VPR64.2S[0,32]);
+ TMPQ1[64,64] = zext(Rm_VPR64.2S[32,32]);
+ # simd infix Rd_VPR128.2D = Rn_VPR128.2D + TMPQ1 on lane size 8
+ Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] + TMPQ1[0,64];
+ Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] + TMPQ1[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.351 UADDW, UADDW2 page C7-2825 line 165035 MATCH x2e201000/mask=xbf20fc00
+# CONSTRUCT x2e601000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $zext@2:16 =$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddw/2@2
+# AUNIT --inst x2e601000/mask=xffe0fc00 --status pass --comment "ext"
+
+:uaddw Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x1 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = zext(Rm_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = zext(Rm_VPR64.4H[0,16]);
+ TMPQ1[32,32] = zext(Rm_VPR64.4H[16,16]);
+ TMPQ1[64,32] = zext(Rm_VPR64.4H[32,16]);
+ TMPQ1[96,32] = zext(Rm_VPR64.4H[48,16]);
+ # simd infix Rd_VPR128.4S = Rn_VPR128.4S + TMPQ1 on lane size 4
+ Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] + TMPQ1[0,32];
+ Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] + TMPQ1[32,32];
+ Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] + TMPQ1[64,32];
+ Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] + TMPQ1[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.351 UADDW, UADDW2 page C7-2825 line 165035 MATCH x2e201000/mask=xbf20fc00
+# CONSTRUCT x2e201000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $zext@1:16 =$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uaddw/2@1
+# AUNIT --inst x2e201000/mask=xffe0fc00 --status pass --comment "ext"
+
+:uaddw Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x1 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ # simd resize TMPQ1 = zext(Rm_VPR64.8B) (lane size 1 to 2)
+ TMPQ1[0,16] = zext(Rm_VPR64.8B[0,8]);
+ TMPQ1[16,16] = zext(Rm_VPR64.8B[8,8]);
+ TMPQ1[32,16] = zext(Rm_VPR64.8B[16,8]);
+ TMPQ1[48,16] = zext(Rm_VPR64.8B[24,8]);
+ TMPQ1[64,16] = zext(Rm_VPR64.8B[32,8]);
+ TMPQ1[80,16] = zext(Rm_VPR64.8B[40,8]);
+ TMPQ1[96,16] = zext(Rm_VPR64.8B[48,8]);
+ TMPQ1[112,16] = zext(Rm_VPR64.8B[56,8]);
+ # simd infix Rd_VPR128.8H = Rn_VPR128.8H + TMPQ1 on lane size 2
+ Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] + TMPQ1[0,16];
+ Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] + TMPQ1[16,16];
+ Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] + TMPQ1[32,16];
+ Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] + TMPQ1[48,16];
+ Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] + TMPQ1[64,16];
+ Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] + TMPQ1[80,16];
+ Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] + TMPQ1[96,16];
+ Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] + TMPQ1[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x7f00e400/mask=xff80fc00
+# CONSTRUCT x7f40e400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2
+# AUNIT --inst x7f40e400/mask=xffc0fc00 --status nopcodeop --comment "nofpround"
+
+:ucvtf Rd_FPR64, Rn_FPR64, Imm_shr_imm64
+is b_3031=1 & u=1 & b_2428=0x1f & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x1c & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_ucvtf(Rn_FPR64, Imm_shr_imm64:1);
+}
+
+# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x7f00e400/mask=xff80fc00
+# CONSTRUCT x7f20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2
+# AUNIT --inst x7f20e400/mask=xffe0fc00 --status nopcodeop --comment "nofpround"
+
+:ucvtf Rd_FPR32, Rn_FPR32, Imm_shr_imm32
+is b_3031=1 & u=1 & b_2428=0x1f & b_2123=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_ucvtf(Rn_FPR32, Imm_shr_imm32:1);
+}
+
+# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x7f00e400/mask=xff80fc00
+# CONSTRUCT x7f10e400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2
+# AUNIT --inst x7f10e400/mask=xfff0fc00 --status noqemu --comment "nofpround"
+
+:ucvtf Rd_FPR16, Rn_FPR16, Imm_shr_imm16
+is b_3031=1 & u=1 & b_2428=0x1f & b_2023=1 & Imm_shr_imm16 & b_1115=0x1c & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_ucvtf(Rn_FPR16, Imm_shr_imm16:1);
+}
+
+# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x2f00e400/mask=xbf80fc00
+# CONSTRUCT x6f40e400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2@8
+# AUNIT --inst x6f40e400/mask=xffc0fc00 --status nopcodeop --comment "nofpround"
+
+:ucvtf Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x1c & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_ucvtf(Rn_VPR128.2D, Imm_shr_imm64:1, 8:1);
+}
+
+# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x2f00e400/mask=xbf80fc00
+# CONSTRUCT x2f20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2@4
+# AUNIT --inst x2f20e400/mask=xffe0fc00 --status nopcodeop --comment "nofpround"
+
+:ucvtf Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_ucvtf(Rn_VPR64.2S, Imm_shr_imm32:1, 4:1);
+}
+
+# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x2f00e400/mask=xbf80fc00
+# CONSTRUCT x6f20e400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2@4
+# AUNIT --inst x6f20e400/mask=xffe0fc00 --status nopcodeop --comment "nofpround"
+
+:ucvtf Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_ucvtf(Rn_VPR128.4S, Imm_shr_imm32:1, 4:1);
+}
+
+# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x2f00e400/mask=xbf80fc00
+# CONSTRUCT x2f10e400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2@2
+# AUNIT --inst x2f10e400/mask=xfff0fc00 --status noqemu --comment "nofpround"
+
+:ucvtf Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm32
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_ucvtf(Rn_VPR64.4H, Imm_shr_imm32:1, 2:1);
+}
+
+# C7.2.352 UCVTF (vector, fixed-point) page C7-2827 line 165158 MATCH x2f00e400/mask=xbf80fc00
+# CONSTRUCT x6f10e400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ucvtf/2@2
+# AUNIT --inst x6f10e400/mask=xfff0fc00 --status noqemu --comment "nofpround"
+
+:ucvtf Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm32
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=1 & Imm_shr_imm32 & b_1115=0x1c & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_ucvtf(Rn_VPR128.8H, Imm_shr_imm32:1, 2:1);
+}
+
+# C7.2.353 UCVTF (vector, integer) page C7-2830 line 165313 MATCH x7e21d800/mask=xffbffc00
+# CONSTRUCT x7e21d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1
+# AUNIT --inst x7e21d800/mask=xfffffc00 --status nopcodeop --comment "nofpround"
+
+:ucvtf Rd_FPR32, Rn_FPR32
+is b_3031=1 & u=1 & b_2428=0x1e & size_high=0 & b_1722=0x10 & b_1216=0x1d & b_1011=2 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_ucvtf(Rn_FPR32);
+}
+
+# C7.2.353 UCVTF (vector, integer) page C7-2830 line 165313 MATCH x7e21d800/mask=xffbffc00
+# CONSTRUCT x7e61d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1
+# AUNIT --inst x7e61d800/mask=xfffffc00 --status nopcodeop --comment "nofpround"
+
+:ucvtf Rd_FPR64, Rn_FPR64
+is b_3031=1 & u=1 & b_2428=0x1e & size_high=0 & b_1722=0x30 & b_1216=0x1d & b_1011=2 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_ucvtf(Rn_FPR64);
+}
+
+# C7.2.353 UCVTF (vector, integer) page C7-2830 line 165313 MATCH x2e21d800/mask=xbfbffc00
+# CONSTRUCT x2e21d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1@4
+# AUNIT --inst x2e21d800/mask=xfffffc00 --status nopcodeop --comment "nofpround"
+
+:ucvtf Rd_VPR64.2S, Rn_VPR64.2S
+is sf=0 & q=0 & b_2929=1 & b_2428=0x0e & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x1d & b_1011=2 & Rd_VPR64.2S & Rn_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_ucvtf(Rn_VPR64.2S, 4:1);
+}
+
+# C7.2.353 UCVTF (vector, integer) page C7-2830 line 165313 MATCH x2e21d800/mask=xbfbffc00
+# CONSTRUCT x6e21d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1@4
+# AUNIT --inst x6e21d800/mask=xfffffc00 --status nopcodeop --comment "nofpround"
+
+:ucvtf Rd_VPR128.4S, Rn_VPR128.4S
+is sf=0 & q=1 & b_2929=1 & b_2428=0x0e & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x1d & b_1011=2 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_ucvtf(Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.353 UCVTF (vector, integer) page C7-2830 line 165313 MATCH x2e21d800/mask=xbfbffc00
+# CONSTRUCT x6e61d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1@8
+# AUNIT --inst x6e61d800/mask=xfffffc00 --status nopcodeop --comment "nofpround"
+
+:ucvtf Rd_VPR128.2D, Rn_VPR128.2D
+is sf=0 & q=1 & b_2929=1 & b_2428=0x0e & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x1d & b_1011=2 & Rd_VPR128.2D & Rn_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_ucvtf(Rn_VPR128.2D, 8:1);
+}
+
+# C7.2.353 UCVTF (vector, integer) page C7-2830 line 165313 MATCH x7e79d800/mask=xfffffc00
+# CONSTRUCT x7e79d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1
+# AUNIT --inst x7e79d800/mask=xfffffc00 --status noqemu --comment "nofpround"
+# Scalar half precision variant
+
+:ucvtf Rd_FPR16, Rn_FPR16
+is b_1031=0b0111111001111001110110 & Rd_FPR16 & Rn_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_ucvtf(Rn_FPR16);
+}
+
+# C7.2.353 UCVTF (vector, integer) page C7-2830 line 165313 MATCH x2e79d800/mask=xbffffc00
+# CONSTRUCT x2e79d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1@2
+# AUNIT --inst x2e79d800/mask=xfffffc00 --status noqemu --comment "nofpround"
+# Vector half precision variant when Q=0 T=VPR64.4H
+
+:ucvtf Rd_VPR64.4H, Rn_VPR64.4H
+is b_31=0 & b_30=0 & b_1029=0b10111001111001110110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_ucvtf(Rn_VPR64.4H, 2:1);
+}
+
+# C7.2.353 UCVTF (vector, integer) page C7-2830 line 165313 MATCH x2e79d800/mask=xbffffc00
+# CONSTRUCT x6e79d800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1@2
+# AUNIT --inst x6e79d800/mask=xfffffc00 --status noqemu --comment "nofpround"
+# Vector half precision variant when Q=1 T=VPR128.8H
+
+:ucvtf Rd_VPR128.8H, Rn_VPR128.8H
+is b_31=0 & b_30=1 & b_1029=0b10111001111001110110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_ucvtf(Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.354 UCVTF (scalar, fixed-point) page C7-2833 line 165497 MATCH x1e030000/mask=x7f3f0000
+# CONSTRUCT x1ec38000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 zext:8 int2float:2 FBits16 =f/
+# SMACRO(pseudo) ARG1 ARG2 FBits16 =NEON_ucvtf/2
+# AUNIT --inst x1ec38000/mask=xffff8000 --status noqemu --comment "nofpround"
+# if sf == '0' && scale<5> == '0' then UnallocatedEncoding();
+
+:ucvtf Rd_FPR16, Rn_GPR32, FBitsOp
+is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=0 & mode=0 & fpOpcode=3 & b_15=1 & FBitsOp & FBits16 & Rn_GPR32 & Rd_FPR16 & Zd
+{
+ local tmp1:8 = zext(Rn_GPR32);
+ local tmp2:2 = int2float(tmp1);
+ Rd_FPR16 = tmp2 f/ FBits16;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.354 UCVTF (scalar, fixed-point) page C7-2833 line 165497 MATCH x1e030000/mask=x7f3f0000
+# CONSTRUCT x9ec30000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 zext:9 int2float:2 FBits16 =f/
+# SMACRO(pseudo) ARG1 ARG2 FBits16 =NEON_ucvtf/2
+# AUNIT --inst x9ec30000/mask=xffff0000 --status noqemu --comment "nofpround"
+
+:ucvtf Rd_FPR16, Rn_GPR64, FBitsOp
+is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=0 & mode=0 & fpOpcode=3 & FBitsOp & FBits16 & Rn_GPR64 & Rd_FPR16 & Zd
+{
+ local tmp1:9 = zext(Rn_GPR64);
+ local tmp2:2 = int2float(tmp1);
+ Rd_FPR16 = tmp2 f/ FBits16;
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.354 UCVTF (scalar, fixed-point) page C7-2833 line 165497 MATCH x1e030000/mask=x7f3f0000
+# CONSTRUCT x1e438000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 zext:8 int2float:8 FBits64 =f/
+# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_ucvtf/2
+# AUNIT --inst x1e438000/mask=xffff8000 --status pass --comment "nofpround"
+# if sf == '0' && scale<5> == '0' then UnallocatedEncoding();
+
+:ucvtf Rd_FPR64, Rn_GPR32, FBitsOp
+is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=0 & mode=0 & fpOpcode=3 & b_15=1 & FBitsOp & FBits64 & Rn_GPR32 & Rd_FPR64 & Zd
+{
+ local tmp1:8 = zext(Rn_GPR32);
+ local tmp2:8 = int2float(tmp1);
+ Rd_FPR64 = tmp2 f/ FBits64;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.354 UCVTF (scalar, fixed-point) page C7-2833 line 165497 MATCH x1e030000/mask=x7f3f0000
+# CONSTRUCT x9e430000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 zext:9 int2float:8 FBits64 =f/
+# SMACRO(pseudo) ARG1 ARG2 FBits64 =NEON_ucvtf/2
+# AUNIT --inst x9e430000/mask=xffff0000 --status fail --comment "nofpround"
+# The zext:9 naively force unsigned int before conversion
+
+:ucvtf Rd_FPR64, Rn_GPR64, FBitsOp
+is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=0 & mode=0 & fpOpcode=3 & FBitsOp & FBits64 & Rn_GPR64 & Rd_FPR64 & Zd
+{
+ local tmp1:9 = zext(Rn_GPR64);
+ local tmp2:8 = int2float(tmp1);
+ Rd_FPR64 = tmp2 f/ FBits64;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.354 UCVTF (scalar, fixed-point) page C7-2833 line 165497 MATCH x1e030000/mask=x7f3f0000
+# CONSTRUCT x1e038000/mask=xffff8000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 zext:8 int2float:4 FBits32 =f/
+# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_ucvtf/2
+# AUNIT --inst x1e038000/mask=xffff8000 --status fail --comment "nofpround"
+# if sf == '0' && scale<5> == '0' then UnallocatedEncoding();
+
+:ucvtf Rd_FPR32, Rn_GPR32, FBitsOp
+is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=0 & mode=0 & fpOpcode=3 & b_15=1 & FBitsOp & FBits32 & Rn_GPR32 & Rd_FPR32 & Zd
+{
+ local tmp1:8 = zext(Rn_GPR32);
+ local tmp2:4 = int2float(tmp1);
+ Rd_FPR32 = tmp2 f/ FBits32;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.354 UCVTF (scalar, fixed-point) page C7-2833 line 165497 MATCH x1e030000/mask=x7f3f0000
+# CONSTRUCT x9e030000/mask=xffff0000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 zext:9 int2float:4 FBits32 =f/
+# SMACRO(pseudo) ARG1 ARG2 FBits32 =NEON_ucvtf/2
+# AUNIT --inst x9e030000/mask=xffff0000 --status fail --comment "nofpround"
+
+:ucvtf Rd_FPR32, Rn_GPR64, FBitsOp
+is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=0 & mode=0 & fpOpcode=3 & FBitsOp & FBits32 & Rn_GPR64 & Rd_FPR32 & Zd
+{
+ local tmp1:9 = zext(Rn_GPR64);
+ local tmp2:4 = int2float(tmp1);
+ Rd_FPR32 = tmp2 f/ FBits32;
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.355 UCVTF (scalar, integer) page C7-2835 line 165632 MATCH x1e230000/mask=x7f3ffc00
+# CONSTRUCT x1ee30000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 zext:8 =int2float
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1
+# AUNIT --inst x1ee30000/mask=xfffffc00 --status noqemu --comment "nofpround"
+
+:ucvtf Rd_FPR16, Rn_GPR32
+is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & rmode=0 & fpOpcode=3 & b_1015=0x0 & Rn_GPR32 & Rd_FPR16 & Zd
+{
+ local tmp1:8 = zext(Rn_GPR32);
+ Rd_FPR16 = int2float(tmp1);
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.355 UCVTF (scalar, integer) page C7-2835 line 165632 MATCH x1e230000/mask=x7f3ffc00
+# CONSTRUCT x9ee30000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 zext:9 =int2float
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1
+# AUNIT --inst x9ee30000/mask=xfffffc00 --status noqemu --comment "nofpround"
+
+:ucvtf Rd_FPR16, Rn_GPR64
+is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=3 & b_2121=1 & rmode=0 & fpOpcode=3 & b_1015=0x0 & Rn_GPR64 & Rd_FPR16 & Zd
+{
+ local tmp1:9 = zext(Rn_GPR64);
+ Rd_FPR16 = int2float(tmp1);
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.355 UCVTF (scalar, integer) page C7-2835 line 165632 MATCH x1e230000/mask=x7f3ffc00
+# CONSTRUCT x1e630000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 zext:8 =int2float
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1
+# AUNIT --inst x1e630000/mask=xfffffc00 --status pass --comment "nofpround"
+
+:ucvtf Rd_FPR64, Rn_GPR32
+is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & rmode=0 & fpOpcode=3 & b_1015=0x0 & Rn_GPR32 & Rd_FPR64 & Zd
+{
+ local tmp1:8 = zext(Rn_GPR32);
+ Rd_FPR64 = int2float(tmp1);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.355 UCVTF (scalar, integer) page C7-2835 line 165632 MATCH x1e230000/mask=x7f3ffc00
+# CONSTRUCT x9e630000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 zext:9 =int2float
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1
+# AUNIT --inst x9e630000/mask=xfffffc00 --status fail --comment "nofpround"
+
+:ucvtf Rd_FPR64, Rn_GPR64
+is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=1 & b_2121=1 & rmode=0 & fpOpcode=3 & b_1015=0x0 & Rn_GPR64 & Rd_FPR64 & Zd
+{
+ local tmp1:9 = zext(Rn_GPR64);
+ Rd_FPR64 = int2float(tmp1);
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.355 UCVTF (scalar, integer) page C7-2835 line 165632 MATCH x1e230000/mask=x7f3ffc00
+# CONSTRUCT x1e230000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 zext:8 =int2float
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1
+# AUNIT --inst x1e230000/mask=xfffffc00 --status fail --comment "nofpround"
+
+:ucvtf Rd_FPR32, Rn_GPR32
+is sf=0 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & rmode=0 & fpOpcode=3 & b_1015=0x0 & Rn_GPR32 & Rd_FPR32 & Zd
+{
+ local tmp1:8 = zext(Rn_GPR32);
+ Rd_FPR32 = int2float(tmp1);
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.355 UCVTF (scalar, integer) page C7-2835 line 165632 MATCH x1e230000/mask=x7f3ffc00
+# CONSTRUCT x9e230000/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 zext:9 =int2float
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ucvtf/1
+# AUNIT --inst x9e230000/mask=xfffffc00 --status fail --comment "nofpround"
+
+:ucvtf Rd_FPR32, Rn_GPR64
+is sf=1 & b_3030=0 & s=0 & b_2428=0x1e & ftype=0 & b_2121=1 & rmode=0 & fpOpcode=3 & b_1015=0x0 & Rn_GPR64 & Rd_FPR32 & Zd
+{
+ local tmp1:9 = zext(Rn_GPR64);
+ Rd_FPR32 = int2float(tmp1);
+ zext_zs(Zd); # zero upper 28 bytes of Zd
+}
+
+# C7.2.356 UDOT (by element) page C7-2837 line 165760 MATCH x2f00e000/mask=xbf00f400
+# CONSTRUCT x2f80e000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 Re_VPR128.S.vIndex =NEON_udot/2@1
+# AUNIT --inst x2f80e000/mask=xffc0f400 --status noqemu
+# Vector variant when Q=0 Ta=VPR64.2S Tb=VPR64.8B
+
+:udot Rd_VPR64.2S, Rn_VPR64.8B, Re_VPR128.B.vIndex
+is b_31=0 & b_30=0 & b_2429=0b101111 & b_2223=0b10 & b_1215=0b1110 & b_10=0 & Rd_VPR64.2S & Rn_VPR64.8B & Re_VPR128.B.vIndex & Re_VPR128.S & vIndex & Zd
+{
+ local tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1);
+ Rd_VPR64.2S = NEON_udot(Rn_VPR64.8B, tmp1, 1:1);
+}
+
+# C7.2.356 UDOT (by element) page C7-2837 line 165760 MATCH x2f00e000/mask=xbf00f400
+# CONSTRUCT x6f80e000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 Re_VPR128.S.vIndex =NEON_udot/2@1
+# AUNIT --inst x6f80e000/mask=xffc0f400 --status noqemu
+# Vector variant when Q=1 Ta=VPR128.4S Tb=VPR128.16B
+
+:udot Rd_VPR128.4S, Rn_VPR128.16B, Re_VPR128.B.vIndex
+is b_31=0 & b_30=1 & b_2429=0b101111 & b_2223=0b10 & b_1215=0b1110 & b_10=0 & Rd_VPR128.4S & Rn_VPR128.16B & Re_VPR128.B.vIndex & Re_VPR128.S & vIndex & Zd
+{
+ local tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1);
+ Rd_VPR128.4S = NEON_udot(Rn_VPR128.16B, tmp1, 1:1);
+}
+
+# C7.2.357 UDOT (vector) page C7-2839 line 165862 MATCH x2e009400/mask=xbf20fc00
+# CONSTRUCT x2e809400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_udot/2@1
+# AUNIT --inst x2e809400/mask=xffe0fc00 --status noqemu
+# Three registers of the same type variant when Q=0 Ta=VPR64.2S Tb=VPR64.8B
+
+:udot Rd_VPR64.2S, Rn_VPR64.8B, Rm_VPR64.8B
+is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_21=0 & b_1015=0b100101 & Rd_VPR64.2S & Rn_VPR64.8B & Rm_VPR64.8B & Zd
+{
+ Rd_VPR64.2S = NEON_udot(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.357 UDOT (vector) page C7-2839 line 165862 MATCH x2e009400/mask=xbf20fc00
+# CONSTRUCT x6e809400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_udot/2@1
+# AUNIT --inst x6e809400/mask=xffe0fc00 --status noqemu
+# Three registers of the same type variant when Q=1 Ta=VPR128.4S Tb=VPR128.16B
+
+:udot Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_21=0 & b_1015=0b100101 & Rd_VPR128.4S & Rn_VPR128.16B & Rm_VPR128.16B & Zd
+{
+ Rd_VPR128.4S = NEON_udot(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.358 UHADD page C7-2841 line 165961 MATCH x2e200400/mask=xbf20fc00
+# CONSTRUCT x6e200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhadd/2@1
+# AUNIT --inst x6e200400/mask=xffe0fc00 --status nopcodeop
+
+:uhadd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x0 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_uhadd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.358 UHADD page C7-2841 line 165961 MATCH x2e200400/mask=xbf20fc00
+# CONSTRUCT x2ea00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhadd/2@4
+# AUNIT --inst x2ea00400/mask=xffe0fc00 --status nopcodeop
+
+:uhadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x0 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_uhadd(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.358 UHADD page C7-2841 line 165961 MATCH x2e200400/mask=xbf20fc00
+# CONSTRUCT x2e600400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhadd/2@2
+# AUNIT --inst x2e600400/mask=xffe0fc00 --status nopcodeop
+
+:uhadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x0 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_uhadd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.358 UHADD page C7-2841 line 165961 MATCH x2e200400/mask=xbf20fc00
+# CONSTRUCT x6ea00400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhadd/2@4
+# AUNIT --inst x6ea00400/mask=xffe0fc00 --status nopcodeop
+
+:uhadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x0 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_uhadd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.358 UHADD page C7-2841 line 165961 MATCH x2e200400/mask=xbf20fc00
+# CONSTRUCT x2e200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhadd/2@1
+# AUNIT --inst x2e200400/mask=xffe0fc00 --status nopcodeop
+
+:uhadd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x0 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_uhadd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.358 UHADD page C7-2841 line 165961 MATCH x2e200400/mask=xbf20fc00
+# CONSTRUCT x6e600400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhadd/2@2
+# AUNIT --inst x6e600400/mask=xffe0fc00 --status nopcodeop
+
+:uhadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x0 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_uhadd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.359 UHSUB page C7-2843 line 166063 MATCH x2e202400/mask=xbf20fc00
+# CONSTRUCT x6e202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhsub/2@1
+# AUNIT --inst x6e202400/mask=xffe0fc00 --status nopcodeop
+
+:uhsub Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x4 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_uhsub(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.359 UHSUB page C7-2843 line 166063 MATCH x2e202400/mask=xbf20fc00
+# CONSTRUCT x2ea02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhsub/2@4
+# AUNIT --inst x2ea02400/mask=xffe0fc00 --status nopcodeop
+
+:uhsub Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x4 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_uhsub(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.359 UHSUB page C7-2843 line 166063 MATCH x2e202400/mask=xbf20fc00
+# CONSTRUCT x2e602400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhsub/2@2
+# AUNIT --inst x2e602400/mask=xffe0fc00 --status nopcodeop
+
+:uhsub Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x4 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_uhsub(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.359 UHSUB page C7-2843 line 166063 MATCH x2e202400/mask=xbf20fc00
+# CONSTRUCT x6ea02400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhsub/2@4
+# AUNIT --inst x6ea02400/mask=xffe0fc00 --status nopcodeop
+
+:uhsub Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x4 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_uhsub(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.359 UHSUB page C7-2843 line 166063 MATCH x2e202400/mask=xbf20fc00
+# CONSTRUCT x2e202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhsub/2@1
+# AUNIT --inst x2e202400/mask=xffe0fc00 --status nopcodeop
+
+:uhsub Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x4 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_uhsub(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.359 UHSUB page C7-2843 line 166063 MATCH x2e202400/mask=xbf20fc00
+# CONSTRUCT x6e602400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uhsub/2@2
+# AUNIT --inst x6e602400/mask=xffe0fc00 --status nopcodeop
+
+:uhsub Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x4 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_uhsub(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.360 UMAX page C7-2845 line 166163 MATCH x2e206400/mask=xbf20fc00
+# CONSTRUCT x6e206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umax/2@1
+# AUNIT --inst x6e206400/mask=xffe0fc00 --status nopcodeop
+
+:umax Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xc & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_umax(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.360 UMAX page C7-2845 line 166163 MATCH x2e206400/mask=xbf20fc00
+# CONSTRUCT x2ea06400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umax/2@4
+# AUNIT --inst x2ea06400/mask=xffe0fc00 --status nopcodeop
+
+:umax Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xc & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_umax(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.360 UMAX page C7-2845 line 166163 MATCH x2e206400/mask=xbf20fc00
+# CONSTRUCT x2e606400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umax/2@2
+# AUNIT --inst x2e606400/mask=xffe0fc00 --status nopcodeop
+
+:umax Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xc & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_umax(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.360 UMAX page C7-2845 line 166163 MATCH x2e206400/mask=xbf20fc00
+# CONSTRUCT x6ea06400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umax/2@4
+# AUNIT --inst x6ea06400/mask=xffe0fc00 --status nopcodeop
+
+:umax Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xc & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_umax(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.360 UMAX page C7-2845 line 166163 MATCH x2e206400/mask=xbf20fc00
+# CONSTRUCT x2e206400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umax/2@1
+# AUNIT --inst x2e206400/mask=xffe0fc00 --status nopcodeop
+
+:umax Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xc & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_umax(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.360 UMAX page C7-2845 line 166163 MATCH x2e206400/mask=xbf20fc00
+# CONSTRUCT x6e606400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umax/2@2
+# AUNIT --inst x6e606400/mask=xffe0fc00 --status nopcodeop
+
+:umax Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xc & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_umax(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.361 UMAXP page C7-2847 line 166265 MATCH x2e20a400/mask=xbf20fc00
+# CONSTRUCT x6e20a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umaxp/2@1
+# AUNIT --inst x6e20a400/mask=xffe0fc00 --status nopcodeop
+
+:umaxp Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x14 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_umaxp(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.361 UMAXP page C7-2847 line 166265 MATCH x2e20a400/mask=xbf20fc00
+# CONSTRUCT x2ea0a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umaxp/2@4
+# AUNIT --inst x2ea0a400/mask=xffe0fc00 --status nopcodeop
+
+:umaxp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x14 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_umaxp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.361 UMAXP page C7-2847 line 166265 MATCH x2e20a400/mask=xbf20fc00
+# CONSTRUCT x2e60a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umaxp/2@2
+# AUNIT --inst x2e60a400/mask=xffe0fc00 --status nopcodeop
+
+:umaxp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x14 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_umaxp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.361 UMAXP page C7-2847 line 166265 MATCH x2e20a400/mask=xbf20fc00
+# CONSTRUCT x6ea0a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umaxp/2@4
+# AUNIT --inst x6ea0a400/mask=xffe0fc00 --status nopcodeop
+
+:umaxp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x14 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_umaxp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.361 UMAXP page C7-2847 line 166265 MATCH x2e20a400/mask=xbf20fc00
+# CONSTRUCT x2e20a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umaxp/2@1
+# AUNIT --inst x2e20a400/mask=xffe0fc00 --status nopcodeop
+
+:umaxp Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x14 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_umaxp(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.361 UMAXP page C7-2847 line 166265 MATCH x2e20a400/mask=xbf20fc00
+# CONSTRUCT x6e60a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umaxp/2@2
+# AUNIT --inst x6e60a400/mask=xffe0fc00 --status nopcodeop
+
+:umaxp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x14 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_umaxp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.362 UMAXV page C7-2849 line 166369 MATCH x2e30a800/mask=xbf3ffc00
+# CONSTRUCT x6e30a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_umaxv/1@1
+# AUNIT --inst x6e30a800/mask=xfffffc00 --status nopcodeop
+
+:umaxv Rd_FPR8, Rn_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.16B & Rd_FPR8 & Zd
+{
+ Rd_FPR8 = NEON_umaxv(Rn_VPR128.16B, 1:1);
+}
+
+# C7.2.362 UMAXV page C7-2849 line 166369 MATCH x2e30a800/mask=xbf3ffc00
+# CONSTRUCT x2e30a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_umaxv/1@1
+# AUNIT --inst x2e30a800/mask=xfffffc00 --status nopcodeop
+
+:umaxv Rd_FPR8, Rn_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR64.8B & Rd_FPR8 & Zd
+{
+ Rd_FPR8 = NEON_umaxv(Rn_VPR64.8B, 1:1);
+}
+
+# C7.2.362 UMAXV page C7-2849 line 166369 MATCH x2e30a800/mask=xbf3ffc00
+# CONSTRUCT x2e70a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_umaxv/1@2
+# AUNIT --inst x2e70a800/mask=xfffffc00 --status nopcodeop
+
+:umaxv Rd_FPR16, Rn_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR64.4H & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_umaxv(Rn_VPR64.4H, 2:1);
+}
+
+# C7.2.362 UMAXV page C7-2849 line 166369 MATCH x2e30a800/mask=xbf3ffc00
+# CONSTRUCT x6e70a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_umaxv/1@2
+# AUNIT --inst x6e70a800/mask=xfffffc00 --status nopcodeop
+
+:umaxv Rd_FPR16, Rn_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.8H & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_umaxv(Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.362 UMAXV page C7-2849 line 166369 MATCH x2e30a800/mask=xbf3ffc00
+# CONSTRUCT x6eb0a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_umaxv/1@4
+# AUNIT --inst x6eb0a800/mask=xfffffc00 --status nopcodeop
+
+:umaxv Rd_FPR32, Rn_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0xa & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_umaxv(Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.363 UMIN page C7-2851 line 166472 MATCH x2e206c00/mask=xbf20fc00
+# CONSTRUCT x6e206c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umin/2@1
+# AUNIT --inst x6e206c00/mask=xffe0fc00 --status nopcodeop
+
+:umin Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xd & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_umin(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.363 UMIN page C7-2851 line 166472 MATCH x2e206c00/mask=xbf20fc00
+# CONSTRUCT x2ea06c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umin/2@4
+# AUNIT --inst x2ea06c00/mask=xffe0fc00 --status nopcodeop
+
+:umin Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xd & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_umin(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.363 UMIN page C7-2851 line 166472 MATCH x2e206c00/mask=xbf20fc00
+# CONSTRUCT x2e606c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umin/2@2
+# AUNIT --inst x2e606c00/mask=xffe0fc00 --status nopcodeop
+
+:umin Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xd & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_umin(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.363 UMIN page C7-2851 line 166472 MATCH x2e206c00/mask=xbf20fc00
+# CONSTRUCT x6ea06c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umin/2@4
+# AUNIT --inst x6ea06c00/mask=xffe0fc00 --status nopcodeop
+
+:umin Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xd & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_umin(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.363 UMIN page C7-2851 line 166472 MATCH x2e206c00/mask=xbf20fc00
+# CONSTRUCT x2e206c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umin/2@1
+# AUNIT --inst x2e206c00/mask=xffe0fc00 --status nopcodeop
+
+:umin Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xd & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_umin(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.363 UMIN page C7-2851 line 166472 MATCH x2e206c00/mask=xbf20fc00
+# CONSTRUCT x6e606c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umin/2@2
+# AUNIT --inst x6e606c00/mask=xffe0fc00 --status nopcodeop
+
+:umin Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xd & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_umin(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.364 UMINP page C7-2853 line 166574 MATCH x2e20ac00/mask=xbf20fc00
+# CONSTRUCT x6e20ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uminp/2@1
+# AUNIT --inst x6e20ac00/mask=xffe0fc00 --status nopcodeop
+
+:uminp Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x15 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_uminp(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.364 UMINP page C7-2853 line 166574 MATCH x2e20ac00/mask=xbf20fc00
+# CONSTRUCT x2ea0ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uminp/2@4
+# AUNIT --inst x2ea0ac00/mask=xffe0fc00 --status nopcodeop
+
+:uminp Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x15 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_uminp(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.364 UMINP page C7-2853 line 166574 MATCH x2e20ac00/mask=xbf20fc00
+# CONSTRUCT x2e60ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uminp/2@2
+# AUNIT --inst x2e60ac00/mask=xffe0fc00 --status nopcodeop
+
+:uminp Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x15 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_uminp(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.364 UMINP page C7-2853 line 166574 MATCH x2e20ac00/mask=xbf20fc00
+# CONSTRUCT x6ea0ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uminp/2@4
+# AUNIT --inst x6ea0ac00/mask=xffe0fc00 --status nopcodeop
+
+:uminp Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x15 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_uminp(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.364 UMINP page C7-2853 line 166574 MATCH x2e20ac00/mask=xbf20fc00
+# CONSTRUCT x2e20ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uminp/2@1
+# AUNIT --inst x2e20ac00/mask=xffe0fc00 --status nopcodeop
+
+:uminp Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x15 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_uminp(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.364 UMINP page C7-2853 line 166574 MATCH x2e20ac00/mask=xbf20fc00
+# CONSTRUCT x6e60ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uminp/2@2
+# AUNIT --inst x6e60ac00/mask=xffe0fc00 --status nopcodeop
+
+:uminp Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x15 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_uminp(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.365 UMINV page C7-2855 line 166678 MATCH x2e31a800/mask=xbf3ffc00
+# CONSTRUCT x6e31a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_uminv/1@1
+# AUNIT --inst x6e31a800/mask=xfffffc00 --status nopcodeop
+
+:uminv Rd_FPR8, Rn_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.16B & Rd_FPR8 & Zd
+{
+ Rd_FPR8 = NEON_uminv(Rn_VPR128.16B, 1:1);
+}
+
+# C7.2.365 UMINV page C7-2855 line 166678 MATCH x2e31a800/mask=xbf3ffc00
+# CONSTRUCT x2e31a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_uminv/1@1
+# AUNIT --inst x2e31a800/mask=xfffffc00 --status nopcodeop
+
+:uminv Rd_FPR8, Rn_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR64.8B & Rd_FPR8 & Zd
+{
+ Rd_FPR8 = NEON_uminv(Rn_VPR64.8B, 1:1);
+}
+
+# C7.2.365 UMINV page C7-2855 line 166678 MATCH x2e31a800/mask=xbf3ffc00
+# CONSTRUCT x2e71a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_uminv/1@2
+# AUNIT --inst x2e71a800/mask=xfffffc00 --status nopcodeop
+
+:uminv Rd_FPR16, Rn_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR64.4H & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_uminv(Rn_VPR64.4H, 2:1);
+}
+
+# C7.2.365 UMINV page C7-2855 line 166678 MATCH x2e31a800/mask=xbf3ffc00
+# CONSTRUCT x6e71a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_uminv/1@2
+# AUNIT --inst x6e71a800/mask=xfffffc00 --status nopcodeop
+
+:uminv Rd_FPR16, Rn_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.8H & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_uminv(Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.365 UMINV page C7-2855 line 166678 MATCH x2e31a800/mask=xbf3ffc00
+# CONSTRUCT x6eb1a800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_uminv/1@4
+# AUNIT --inst x6eb1a800/mask=xfffffc00 --status nopcodeop
+
+:uminv Rd_FPR32, Rn_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x1a & b_1011=2 & Rn_VPR128.4S & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_uminv(Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.366 UMLAL, UMLAL2 (by element) page C7-2857 line 166781 MATCH x2f002000/mask=xbf00f400
+# CONSTRUCT x2f802000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@4:16 ARG3 zext:8 $* &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal/3@4
+# AUNIT --inst x2f802000/mask=xffc0f400 --status pass --comment "ext"
+
+:umlal Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x2 & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp2:4 = Re_VPR128.S.vIndex;
+ local tmp3:8 = zext(tmp2);
+ # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8
+ TMPQ2[0,64] = TMPQ1[0,64] * tmp3;
+ TMPQ2[64,64] = TMPQ1[64,64] * tmp3;
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ2 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ2[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ2[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.366 UMLAL, UMLAL2 (by element) page C7-2857 line 166781 MATCH x2f002000/mask=xbf00f400
+# CONSTRUCT x6f802000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3 zext:8 $* &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal/3@4
+# AUNIT --inst x6f802000/mask=xffc0f400 --status pass --comment "ext"
+
+:umlal2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x2 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = zext(TMPD1[0,32]);
+ TMPQ2[64,64] = zext(TMPD1[32,32]);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp3:4 = Re_VPR128.S.vIndex;
+ local tmp4:8 = zext(tmp3);
+ # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8
+ TMPQ3[0,64] = TMPQ2[0,64] * tmp4;
+ TMPQ3[64,64] = TMPQ2[64,64] * tmp4;
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ3 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ3[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ3[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.366 UMLAL, UMLAL2 (by element) page C7-2857 line 166781 MATCH x2f002000/mask=xbf00f400
+# CONSTRUCT x2f402000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@2:16 ARG3 zext:4 $* &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal/3@2
+# AUNIT --inst x2f402000/mask=xffc0f400 --status pass --comment "ext"
+
+:umlal Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x2 & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp3:4 = zext(tmp2);
+ # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4
+ TMPQ2[0,32] = TMPQ1[0,32] * tmp3;
+ TMPQ2[32,32] = TMPQ1[32,32] * tmp3;
+ TMPQ2[64,32] = TMPQ1[64,32] * tmp3;
+ TMPQ2[96,32] = TMPQ1[96,32] * tmp3;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ2 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ2[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ2[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ2[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ2[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.366 UMLAL, UMLAL2 (by element) page C7-2857 line 166781 MATCH x2f002000/mask=xbf00f400
+# CONSTRUCT x6f402000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3 zext:4 $* &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal2/3@2
+# AUNIT --inst x6f402000/mask=xffc0f400 --status pass --comment "ext"
+
+:umlal2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x2 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = zext(TMPD1[0,16]);
+ TMPQ2[32,32] = zext(TMPD1[16,16]);
+ TMPQ2[64,32] = zext(TMPD1[32,16]);
+ TMPQ2[96,32] = zext(TMPD1[48,16]);
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp3:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp4:4 = zext(tmp3);
+ # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4
+ TMPQ3[0,32] = TMPQ2[0,32] * tmp4;
+ TMPQ3[32,32] = TMPQ2[32,32] * tmp4;
+ TMPQ3[64,32] = TMPQ2[64,32] * tmp4;
+ TMPQ3[96,32] = TMPQ2[96,32] * tmp4;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.367 UMLAL, UMLAL2 (vector) page C7-2860 line 166945 MATCH x2e208000/mask=xbf20fc00
+# CONSTRUCT x6ea08000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 $*@8 &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal2/3@4
+# AUNIT --inst x6ea08000/mask=xffe0fc00 --status pass --comment "ext"
+
+:umlal2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x8 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = zext(TMPD1[0,32]);
+ TMPQ2[64,64] = zext(TMPD1[32,32]);
+ TMPD3 = Rm_VPR128.4S[64,64];
+ # simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8)
+ TMPQ4[0,64] = zext(TMPD3[0,32]);
+ TMPQ4[64,64] = zext(TMPD3[32,32]);
+ # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8
+ TMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64];
+ TMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64];
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ5 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ5[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ5[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.367 UMLAL, UMLAL2 (vector) page C7-2860 line 166945 MATCH x2e208000/mask=xbf20fc00
+# CONSTRUCT x6e608000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 $*@4 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal2/3@2
+# AUNIT --inst x6e608000/mask=xffe0fc00 --status pass --comment "ext"
+
+:umlal2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x8 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = zext(TMPD1[0,16]);
+ TMPQ2[32,32] = zext(TMPD1[16,16]);
+ TMPQ2[64,32] = zext(TMPD1[32,16]);
+ TMPQ2[96,32] = zext(TMPD1[48,16]);
+ TMPD3 = Rm_VPR128.8H[64,64];
+ # simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4)
+ TMPQ4[0,32] = zext(TMPD3[0,16]);
+ TMPQ4[32,32] = zext(TMPD3[16,16]);
+ TMPQ4[64,32] = zext(TMPD3[32,16]);
+ TMPQ4[96,32] = zext(TMPD3[48,16]);
+ # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4
+ TMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32];
+ TMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32];
+ TMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32];
+ TMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32];
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ5 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ5[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ5[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ5[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ5[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.367 UMLAL, UMLAL2 (vector) page C7-2860 line 166945 MATCH x2e208000/mask=xbf20fc00
+# CONSTRUCT x6e208000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 $*@2 &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal2/3@1
+# AUNIT --inst x6e208000/mask=xffe0fc00 --status pass --comment "ext"
+
+:umlal2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x8 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
+{
+ TMPD1 = Rn_VPR128.16B[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)
+ TMPQ2[0,16] = zext(TMPD1[0,8]);
+ TMPQ2[16,16] = zext(TMPD1[8,8]);
+ TMPQ2[32,16] = zext(TMPD1[16,8]);
+ TMPQ2[48,16] = zext(TMPD1[24,8]);
+ TMPQ2[64,16] = zext(TMPD1[32,8]);
+ TMPQ2[80,16] = zext(TMPD1[40,8]);
+ TMPQ2[96,16] = zext(TMPD1[48,8]);
+ TMPQ2[112,16] = zext(TMPD1[56,8]);
+ TMPD3 = Rm_VPR128.16B[64,64];
+ # simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2)
+ TMPQ4[0,16] = zext(TMPD3[0,8]);
+ TMPQ4[16,16] = zext(TMPD3[8,8]);
+ TMPQ4[32,16] = zext(TMPD3[16,8]);
+ TMPQ4[48,16] = zext(TMPD3[24,8]);
+ TMPQ4[64,16] = zext(TMPD3[32,8]);
+ TMPQ4[80,16] = zext(TMPD3[40,8]);
+ TMPQ4[96,16] = zext(TMPD3[48,8]);
+ TMPQ4[112,16] = zext(TMPD3[56,8]);
+ # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 2
+ TMPQ5[0,16] = TMPQ2[0,16] * TMPQ4[0,16];
+ TMPQ5[16,16] = TMPQ2[16,16] * TMPQ4[16,16];
+ TMPQ5[32,16] = TMPQ2[32,16] * TMPQ4[32,16];
+ TMPQ5[48,16] = TMPQ2[48,16] * TMPQ4[48,16];
+ TMPQ5[64,16] = TMPQ2[64,16] * TMPQ4[64,16];
+ TMPQ5[80,16] = TMPQ2[80,16] * TMPQ4[80,16];
+ TMPQ5[96,16] = TMPQ2[96,16] * TMPQ4[96,16];
+ TMPQ5[112,16] = TMPQ2[112,16] * TMPQ4[112,16];
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ5 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ5[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ5[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ5[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ5[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ5[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ5[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ5[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ5[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.367 UMLAL, UMLAL2 (vector) page C7-2860 line 166945 MATCH x2e208000/mask=xbf20fc00
+# CONSTRUCT x2ea08000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@4:16 ARG3 $zext@4:16 $*@8 &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal/3@4
+# AUNIT --inst x2ea08000/mask=xffe0fc00 --status pass --comment "ext"
+
+:umlal Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x8 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);
+ # simd resize TMPQ2 = zext(Rm_VPR64.2S) (lane size 4 to 8)
+ TMPQ2[0,64] = zext(Rm_VPR64.2S[0,32]);
+ TMPQ2[64,64] = zext(Rm_VPR64.2S[32,32]);
+ # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 8
+ TMPQ3[0,64] = TMPQ1[0,64] * TMPQ2[0,64];
+ TMPQ3[64,64] = TMPQ1[64,64] * TMPQ2[64,64];
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ3 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ3[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ3[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.367 UMLAL, UMLAL2 (vector) page C7-2860 line 166945 MATCH x2e208000/mask=xbf20fc00
+# CONSTRUCT x2e608000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@2:16 ARG3 $zext@2:16 $*@4 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal/3@2
+# AUNIT --inst x2e608000/mask=xffe0fc00 --status pass --comment "ext"
+
+:umlal Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x8 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);
+ # simd resize TMPQ2 = zext(Rm_VPR64.4H) (lane size 2 to 4)
+ TMPQ2[0,32] = zext(Rm_VPR64.4H[0,16]);
+ TMPQ2[32,32] = zext(Rm_VPR64.4H[16,16]);
+ TMPQ2[64,32] = zext(Rm_VPR64.4H[32,16]);
+ TMPQ2[96,32] = zext(Rm_VPR64.4H[48,16]);
+ # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 4
+ TMPQ3[0,32] = TMPQ1[0,32] * TMPQ2[0,32];
+ TMPQ3[32,32] = TMPQ1[32,32] * TMPQ2[32,32];
+ TMPQ3[64,32] = TMPQ1[64,32] * TMPQ2[64,32];
+ TMPQ3[96,32] = TMPQ1[96,32] * TMPQ2[96,32];
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ3 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ3[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ3[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ3[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ3[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.367 UMLAL, UMLAL2 (vector) page C7-2860 line 166945 MATCH x2e208000/mask=xbf20fc00
+# CONSTRUCT x2e208000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@1:16 ARG3 $zext@1:16 $*@2 &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlal/3@1
+# AUNIT --inst x2e208000/mask=xffe0fc00 --status pass --comment "ext"
+
+:umlal Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x8 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2)
+ TMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]);
+ TMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]);
+ TMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]);
+ TMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]);
+ TMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]);
+ TMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]);
+ TMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]);
+ TMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]);
+ # simd resize TMPQ2 = zext(Rm_VPR64.8B) (lane size 1 to 2)
+ TMPQ2[0,16] = zext(Rm_VPR64.8B[0,8]);
+ TMPQ2[16,16] = zext(Rm_VPR64.8B[8,8]);
+ TMPQ2[32,16] = zext(Rm_VPR64.8B[16,8]);
+ TMPQ2[48,16] = zext(Rm_VPR64.8B[24,8]);
+ TMPQ2[64,16] = zext(Rm_VPR64.8B[32,8]);
+ TMPQ2[80,16] = zext(Rm_VPR64.8B[40,8]);
+ TMPQ2[96,16] = zext(Rm_VPR64.8B[48,8]);
+ TMPQ2[112,16] = zext(Rm_VPR64.8B[56,8]);
+ # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 2
+ TMPQ3[0,16] = TMPQ1[0,16] * TMPQ2[0,16];
+ TMPQ3[16,16] = TMPQ1[16,16] * TMPQ2[16,16];
+ TMPQ3[32,16] = TMPQ1[32,16] * TMPQ2[32,16];
+ TMPQ3[48,16] = TMPQ1[48,16] * TMPQ2[48,16];
+ TMPQ3[64,16] = TMPQ1[64,16] * TMPQ2[64,16];
+ TMPQ3[80,16] = TMPQ1[80,16] * TMPQ2[80,16];
+ TMPQ3[96,16] = TMPQ1[96,16] * TMPQ2[96,16];
+ TMPQ3[112,16] = TMPQ1[112,16] * TMPQ2[112,16];
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ3 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ3[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ3[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ3[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ3[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ3[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ3[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ3[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ3[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.368 UMLSL, UMLSL2 (by element) page C7-2862 line 167069 MATCH x2f006000/mask=xbf00f400
+# CONSTRUCT x2f806000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@4:16 ARG3 zext:8 $*@8 &=$-@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl/3@4
+# AUNIT --inst x2f806000/mask=xffc0f400 --status pass --comment "ext"
+
+:umlsl Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x6 & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp2:4 = Re_VPR128.S.vIndex;
+ local tmp3:8 = zext(tmp2);
+ # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 8
+ TMPQ2[0,64] = TMPQ1[0,64] * tmp3;
+ TMPQ2[64,64] = TMPQ1[64,64] * tmp3;
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ2 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ2[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ2[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.368 UMLSL, UMLSL2 (by element) page C7-2862 line 167069 MATCH x2f006000/mask=xbf00f400
+# CONSTRUCT x6f806000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3 zext:8 $*@8 &=$-@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl2/3@4
+# AUNIT --inst x6f806000/mask=xffc0f400 --status pass --comment "ext"
+
+:umlsl2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0x6 & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = zext(TMPD1[0,32]);
+ TMPQ2[64,64] = zext(TMPD1[32,32]);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp3:4 = Re_VPR128.S.vIndex;
+ local tmp4:8 = zext(tmp3);
+ # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 8
+ TMPQ3[0,64] = TMPQ2[0,64] * tmp4;
+ TMPQ3[64,64] = TMPQ2[64,64] * tmp4;
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ3 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ3[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ3[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.368 UMLSL, UMLSL2 (by element) page C7-2862 line 167069 MATCH x2f006000/mask=xbf00f400
+# CONSTRUCT x2f406000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@2:16 ARG3 zext:4 $*@4 &=$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl/3@2
+# AUNIT --inst x2f406000/mask=xffc0f400 --status pass --comment "ext"
+
+:umlsl Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x6 & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp3:4 = zext(tmp2);
+ # simd infix TMPQ2 = TMPQ1 * tmp3 on lane size 4
+ TMPQ2[0,32] = TMPQ1[0,32] * tmp3;
+ TMPQ2[32,32] = TMPQ1[32,32] * tmp3;
+ TMPQ2[64,32] = TMPQ1[64,32] * tmp3;
+ TMPQ2[96,32] = TMPQ1[96,32] * tmp3;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ2 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ2[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ2[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ2[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ2[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.368 UMLSL, UMLSL2 (by element) page C7-2862 line 167069 MATCH x2f006000/mask=xbf00f400
+# CONSTRUCT x6f406000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3 zext:4 $*@4 &=$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl2/3@2
+# AUNIT --inst x6f406000/mask=xffc0f400 --status pass --comment "ext"
+
+:umlsl2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0x6 & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = zext(TMPD1[0,16]);
+ TMPQ2[32,32] = zext(TMPD1[16,16]);
+ TMPQ2[64,32] = zext(TMPD1[32,16]);
+ TMPQ2[96,32] = zext(TMPD1[48,16]);
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp3:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp4:4 = zext(tmp3);
+ # simd infix TMPQ3 = TMPQ2 * tmp4 on lane size 4
+ TMPQ3[0,32] = TMPQ2[0,32] * tmp4;
+ TMPQ3[32,32] = TMPQ2[32,32] * tmp4;
+ TMPQ3[64,32] = TMPQ2[64,32] * tmp4;
+ TMPQ3[96,32] = TMPQ2[96,32] * tmp4;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.369 UMLSL, UMLSL2 (vector) page C7-2865 line 167233 MATCH x2e20a000/mask=xbf20fc00
+# CONSTRUCT x6ea0a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 $*@8 &=$-@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl2/3@4
+# AUNIT --inst x6ea0a000/mask=xffe0fc00 --status pass --comment "ext"
+
+:umlsl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0xa & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = zext(TMPD1[0,32]);
+ TMPQ2[64,64] = zext(TMPD1[32,32]);
+ TMPD3 = Rm_VPR128.4S[64,64];
+ # simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8)
+ TMPQ4[0,64] = zext(TMPD3[0,32]);
+ TMPQ4[64,64] = zext(TMPD3[32,32]);
+ # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 8
+ TMPQ5[0,64] = TMPQ2[0,64] * TMPQ4[0,64];
+ TMPQ5[64,64] = TMPQ2[64,64] * TMPQ4[64,64];
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ5 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ5[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ5[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.369 UMLSL, UMLSL2 (vector) page C7-2865 line 167233 MATCH x2e20a000/mask=xbf20fc00
+# CONSTRUCT x6e60a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 $*@4 &=$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl2/3@2
+# AUNIT --inst x6e60a000/mask=xffe0fc00 --status pass --comment "ext"
+
+:umlsl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0xa & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = zext(TMPD1[0,16]);
+ TMPQ2[32,32] = zext(TMPD1[16,16]);
+ TMPQ2[64,32] = zext(TMPD1[32,16]);
+ TMPQ2[96,32] = zext(TMPD1[48,16]);
+ TMPD3 = Rm_VPR128.8H[64,64];
+ # simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4)
+ TMPQ4[0,32] = zext(TMPD3[0,16]);
+ TMPQ4[32,32] = zext(TMPD3[16,16]);
+ TMPQ4[64,32] = zext(TMPD3[32,16]);
+ TMPQ4[96,32] = zext(TMPD3[48,16]);
+ # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 4
+ TMPQ5[0,32] = TMPQ2[0,32] * TMPQ4[0,32];
+ TMPQ5[32,32] = TMPQ2[32,32] * TMPQ4[32,32];
+ TMPQ5[64,32] = TMPQ2[64,32] * TMPQ4[64,32];
+ TMPQ5[96,32] = TMPQ2[96,32] * TMPQ4[96,32];
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ5 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ5[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ5[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ5[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ5[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.369 UMLSL, UMLSL2 (vector) page C7-2865 line 167233 MATCH x2e20a000/mask=xbf20fc00
+# CONSTRUCT x6e20a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 $*@2 &=$-@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl2/3@1
+# AUNIT --inst x6e20a000/mask=xffe0fc00 --status pass --comment "ext"
+
+:umlsl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0xa & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
+{
+ TMPD1 = Rn_VPR128.16B[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)
+ TMPQ2[0,16] = zext(TMPD1[0,8]);
+ TMPQ2[16,16] = zext(TMPD1[8,8]);
+ TMPQ2[32,16] = zext(TMPD1[16,8]);
+ TMPQ2[48,16] = zext(TMPD1[24,8]);
+ TMPQ2[64,16] = zext(TMPD1[32,8]);
+ TMPQ2[80,16] = zext(TMPD1[40,8]);
+ TMPQ2[96,16] = zext(TMPD1[48,8]);
+ TMPQ2[112,16] = zext(TMPD1[56,8]);
+ TMPD3 = Rm_VPR128.16B[64,64];
+ # simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2)
+ TMPQ4[0,16] = zext(TMPD3[0,8]);
+ TMPQ4[16,16] = zext(TMPD3[8,8]);
+ TMPQ4[32,16] = zext(TMPD3[16,8]);
+ TMPQ4[48,16] = zext(TMPD3[24,8]);
+ TMPQ4[64,16] = zext(TMPD3[32,8]);
+ TMPQ4[80,16] = zext(TMPD3[40,8]);
+ TMPQ4[96,16] = zext(TMPD3[48,8]);
+ TMPQ4[112,16] = zext(TMPD3[56,8]);
+ # simd infix TMPQ5 = TMPQ2 * TMPQ4 on lane size 2
+ TMPQ5[0,16] = TMPQ2[0,16] * TMPQ4[0,16];
+ TMPQ5[16,16] = TMPQ2[16,16] * TMPQ4[16,16];
+ TMPQ5[32,16] = TMPQ2[32,16] * TMPQ4[32,16];
+ TMPQ5[48,16] = TMPQ2[48,16] * TMPQ4[48,16];
+ TMPQ5[64,16] = TMPQ2[64,16] * TMPQ4[64,16];
+ TMPQ5[80,16] = TMPQ2[80,16] * TMPQ4[80,16];
+ TMPQ5[96,16] = TMPQ2[96,16] * TMPQ4[96,16];
+ TMPQ5[112,16] = TMPQ2[112,16] * TMPQ4[112,16];
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H - TMPQ5 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] - TMPQ5[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] - TMPQ5[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] - TMPQ5[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] - TMPQ5[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] - TMPQ5[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] - TMPQ5[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] - TMPQ5[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] - TMPQ5[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.369 UMLSL, UMLSL2 (vector) page C7-2865 line 167233 MATCH x2e20a000/mask=xbf20fc00
+# CONSTRUCT x2ea0a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@4:16 ARG3 $zext@4:16 $*@8 &=$-@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl/3@4
+# AUNIT --inst x2ea0a000/mask=xffe0fc00 --status pass --comment "ext"
+
+:umlsl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0xa & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);
+ # simd resize TMPQ2 = zext(Rm_VPR64.2S) (lane size 4 to 8)
+ TMPQ2[0,64] = zext(Rm_VPR64.2S[0,32]);
+ TMPQ2[64,64] = zext(Rm_VPR64.2S[32,32]);
+ # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 8
+ TMPQ3[0,64] = TMPQ1[0,64] * TMPQ2[0,64];
+ TMPQ3[64,64] = TMPQ1[64,64] * TMPQ2[64,64];
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D - TMPQ3 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] - TMPQ3[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] - TMPQ3[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.369 UMLSL, UMLSL2 (vector) page C7-2865 line 167233 MATCH x2e20a000/mask=xbf20fc00
+# CONSTRUCT x2e60a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@2:16 ARG3 $zext@2:16 $*@4 &=$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl/3@2
+# AUNIT --inst x2e60a000/mask=xffe0fc00 --status pass --comment "ext"
+
+:umlsl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0xa & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Rd_VPR128 & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);
+ # simd resize TMPQ2 = zext(Rm_VPR64.4H) (lane size 2 to 4)
+ TMPQ2[0,32] = zext(Rm_VPR64.4H[0,16]);
+ TMPQ2[32,32] = zext(Rm_VPR64.4H[16,16]);
+ TMPQ2[64,32] = zext(Rm_VPR64.4H[32,16]);
+ TMPQ2[96,32] = zext(Rm_VPR64.4H[48,16]);
+ # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 4
+ TMPQ3[0,32] = TMPQ1[0,32] * TMPQ2[0,32];
+ TMPQ3[32,32] = TMPQ1[32,32] * TMPQ2[32,32];
+ TMPQ3[64,32] = TMPQ1[64,32] * TMPQ2[64,32];
+ TMPQ3[96,32] = TMPQ1[96,32] * TMPQ2[96,32];
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S - TMPQ3 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] - TMPQ3[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] - TMPQ3[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] - TMPQ3[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] - TMPQ3[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.369 UMLSL, UMLSL2 (vector) page C7-2865 line 167233 MATCH x2e20a000/mask=xbf20fc00
+# CONSTRUCT x2e20a000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@1:16 ARG3 $zext@1:16 $*@2 &=$-@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_umlsl/3@1
+# AUNIT --inst x2e20a000/mask=xffe0fc00 --status pass --comment "ext"
+
+:umlsl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0xa & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Rd_VPR128 & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2)
+ TMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]);
+ TMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]);
+ TMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]);
+ TMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]);
+ TMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]);
+ TMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]);
+ TMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]);
+ TMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]);
+ # simd resize TMPQ2 = zext(Rm_VPR64.8B) (lane size 1 to 2)
+ TMPQ2[0,16] = zext(Rm_VPR64.8B[0,8]);
+ TMPQ2[16,16] = zext(Rm_VPR64.8B[8,8]);
+ TMPQ2[32,16] = zext(Rm_VPR64.8B[16,8]);
+ TMPQ2[48,16] = zext(Rm_VPR64.8B[24,8]);
+ TMPQ2[64,16] = zext(Rm_VPR64.8B[32,8]);
+ TMPQ2[80,16] = zext(Rm_VPR64.8B[40,8]);
+ TMPQ2[96,16] = zext(Rm_VPR64.8B[48,8]);
+ TMPQ2[112,16] = zext(Rm_VPR64.8B[56,8]);
+ # simd infix TMPQ3 = TMPQ1 * TMPQ2 on lane size 2
+ TMPQ3[0,16] = TMPQ1[0,16] * TMPQ2[0,16];
+ TMPQ3[16,16] = TMPQ1[16,16] * TMPQ2[16,16];
+ TMPQ3[32,16] = TMPQ1[32,16] * TMPQ2[32,16];
+ TMPQ3[48,16] = TMPQ1[48,16] * TMPQ2[48,16];
+ TMPQ3[64,16] = TMPQ1[64,16] * TMPQ2[64,16];
+ TMPQ3[80,16] = TMPQ1[80,16] * TMPQ2[80,16];
+ TMPQ3[96,16] = TMPQ1[96,16] * TMPQ2[96,16];
+ TMPQ3[112,16] = TMPQ1[112,16] * TMPQ2[112,16];
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H - TMPQ3 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] - TMPQ3[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] - TMPQ3[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] - TMPQ3[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] - TMPQ3[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] - TMPQ3[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] - TMPQ3[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] - TMPQ3[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] - TMPQ3[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.371 UMOV page C7-2868 line 167415 MATCH x0e003c00/mask=xbfe0fc00
+# CONSTRUCT x0e013c00/mask=xffe1fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =zext:4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_umov/1
+# AUNIT --inst x0e013c00/mask=xffe1fc00 --status pass
+
+:umov Rd_GPR32, Rn_VPR128.B.imm_neon_uimm4
+is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.B.imm_neon_uimm4 & b_1616=1 & b_1515=0 & imm4=0x7 & b_1010=1 & Rn_VPR128 & Rd_GPR32 & Rd_GPR64
+{
+ # simd element Rn_VPR128[imm_neon_uimm4] lane size 1
+ local tmp1:1 = Rn_VPR128.B.imm_neon_uimm4;
+ Rd_GPR32 = zext(tmp1);
+ zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
+}
+
+# C7.2.371 UMOV page C7-2868 line 167415 MATCH x0e003c00/mask=xbfe0fc00
+# CONSTRUCT x0e023c00/mask=xffe3fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =zext:4
+# SMACRO(pseudo) ARG1 ARG2 =NEON_umov/1
+# AUNIT --inst x0e023c00/mask=xffe3fc00 --status pass
+
+:umov Rd_GPR32, Rn_VPR128.H.imm_neon_uimm3
+is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.H.imm_neon_uimm3 & b_1617=2 & b_1515=0 & imm4=0x7 & b_1010=1 & Rn_VPR128 & Rd_GPR32 & Rd_GPR64 & Rd_VPR128
+{
+ # simd element Rn_VPR128[imm_neon_uimm3] lane size 2
+ local tmp1:2 = Rn_VPR128.H.imm_neon_uimm3;
+ Rd_GPR32 = zext(tmp1);
+ zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
+}
+
+# C7.2.372 UMULL, UMULL2 (by element) page C7-2870 line 167549 MATCH x2f00a000/mask=xbf00f400
+# CONSTRUCT x6f80a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3 zext:8 =$*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull2/2@4
+# AUNIT --inst x6f80a000/mask=xffc0f400 --status pass --comment "ext"
+
+:umull2 Rd_VPR128.2D, Rn_VPR128.4S, Re_VPR128.S.vIndex
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xa & b_1010=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = zext(TMPD1[0,32]);
+ TMPQ2[64,64] = zext(TMPD1[32,32]);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp3:4 = Re_VPR128.S.vIndex;
+ local tmp4:8 = zext(tmp3);
+ # simd infix Rd_VPR128.2D = TMPQ2 * tmp4 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ2[0,64] * tmp4;
+ Rd_VPR128.2D[64,64] = TMPQ2[64,64] * tmp4;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.372 UMULL, UMULL2 (by element) page C7-2870 line 167549 MATCH x2f00a000/mask=xbf00f400
+# CONSTRUCT x6f40a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3 zext:4 =$*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull2/2@2
+# AUNIT --inst x6f40a000/mask=xffc0f400 --status pass --comment "ext"
+
+:umull2 Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xa & b_1010=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = zext(TMPD1[0,16]);
+ TMPQ2[32,32] = zext(TMPD1[16,16]);
+ TMPQ2[64,32] = zext(TMPD1[32,16]);
+ TMPQ2[96,32] = zext(TMPD1[48,16]);
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp3:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp4:4 = zext(tmp3);
+ # simd infix Rd_VPR128.4S = TMPQ2 * tmp4 on lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ2[0,32] * tmp4;
+ Rd_VPR128.4S[32,32] = TMPQ2[32,32] * tmp4;
+ Rd_VPR128.4S[64,32] = TMPQ2[64,32] * tmp4;
+ Rd_VPR128.4S[96,32] = TMPQ2[96,32] * tmp4;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.372 UMULL, UMULL2 (by element) page C7-2870 line 167549 MATCH x2f00a000/mask=xbf00f400
+# CONSTRUCT x2f80a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@4:16 ARG3 zext:8 =$*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull/2@4
+# AUNIT --inst x2f80a000/mask=xffc0f400 --status pass --comment "ext"
+
+:umull Rd_VPR128.2D, Rn_VPR64.2S, Re_VPR128.S.vIndex
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re_VPR128.S & vIndex & b_1215=0xa & b_1010=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);
+ # simd element Re_VPR128.S[vIndex] lane size 4
+ local tmp2:4 = Re_VPR128.S.vIndex;
+ local tmp3:8 = zext(tmp2);
+ # simd infix Rd_VPR128.2D = TMPQ1 * tmp3 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ1[0,64] * tmp3;
+ Rd_VPR128.2D[64,64] = TMPQ1[64,64] * tmp3;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.372 UMULL, UMULL2 (by element) page C7-2870 line 167549 MATCH x2f00a000/mask=xbf00f400
+# CONSTRUCT x2f40a000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@2:16 ARG3 zext:4 =$*
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull/2@2
+# AUNIT --inst x2f40a000/mask=xffc0f400 --status pass --comment "ext"
+
+:umull Rd_VPR128.4S, Rn_VPR64.4H, Re_VPR128Lo.H.vIndexHLM
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & advSIMD3.size=1 & Re_VPR128Lo.H.vIndexHLM & Re_VPR128Lo.H & vIndexHLM & b_1215=0xa & b_1010=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);
+ # simd element Re_VPR128Lo.H[vIndexHLM] lane size 2
+ local tmp2:2 = Re_VPR128Lo.H.vIndexHLM;
+ local tmp3:4 = zext(tmp2);
+ # simd infix Rd_VPR128.4S = TMPQ1 * tmp3 on lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ1[0,32] * tmp3;
+ Rd_VPR128.4S[32,32] = TMPQ1[32,32] * tmp3;
+ Rd_VPR128.4S[64,32] = TMPQ1[64,32] * tmp3;
+ Rd_VPR128.4S[96,32] = TMPQ1[96,32] * tmp3;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.373 UMULL, UMULL2 (vector) page C7-2873 line 167705 MATCH x2e20c000/mask=xbf20fc00
+# CONSTRUCT x6ea0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 =$*@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull2/2@4
+# AUNIT --inst x6ea0c000/mask=xffe0fc00 --status pass --comment "ext"
+
+:umull2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0xc & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = zext(TMPD1[0,32]);
+ TMPQ2[64,64] = zext(TMPD1[32,32]);
+ TMPD3 = Rm_VPR128.4S[64,64];
+ # simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8)
+ TMPQ4[0,64] = zext(TMPD3[0,32]);
+ TMPQ4[64,64] = zext(TMPD3[32,32]);
+ # simd infix Rd_VPR128.2D = TMPQ2 * TMPQ4 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ2[0,64] * TMPQ4[0,64];
+ Rd_VPR128.2D[64,64] = TMPQ2[64,64] * TMPQ4[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.373 UMULL, UMULL2 (vector) page C7-2873 line 167705 MATCH x2e20c000/mask=xbf20fc00
+# CONSTRUCT x6e60c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 =$*@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull2/2@2
+# AUNIT --inst x6e60c000/mask=xffe0fc00 --status pass --comment "ext"
+
+:umull2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0xc & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = zext(TMPD1[0,16]);
+ TMPQ2[32,32] = zext(TMPD1[16,16]);
+ TMPQ2[64,32] = zext(TMPD1[32,16]);
+ TMPQ2[96,32] = zext(TMPD1[48,16]);
+ TMPD3 = Rm_VPR128.8H[64,64];
+ # simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4)
+ TMPQ4[0,32] = zext(TMPD3[0,16]);
+ TMPQ4[32,32] = zext(TMPD3[16,16]);
+ TMPQ4[64,32] = zext(TMPD3[32,16]);
+ TMPQ4[96,32] = zext(TMPD3[48,16]);
+ # simd infix Rd_VPR128.4S = TMPQ2 * TMPQ4 on lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ2[0,32] * TMPQ4[0,32];
+ Rd_VPR128.4S[32,32] = TMPQ2[32,32] * TMPQ4[32,32];
+ Rd_VPR128.4S[64,32] = TMPQ2[64,32] * TMPQ4[64,32];
+ Rd_VPR128.4S[96,32] = TMPQ2[96,32] * TMPQ4[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.373 UMULL, UMULL2 (vector) page C7-2873 line 167705 MATCH x2e20c000/mask=xbf20fc00
+# CONSTRUCT x6e20c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 =$*@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull2/2@1
+# AUNIT --inst x6e20c000/mask=xffe0fc00 --status pass --comment "ext"
+
+:umull2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0xc & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
+{
+ TMPD1 = Rn_VPR128.16B[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)
+ TMPQ2[0,16] = zext(TMPD1[0,8]);
+ TMPQ2[16,16] = zext(TMPD1[8,8]);
+ TMPQ2[32,16] = zext(TMPD1[16,8]);
+ TMPQ2[48,16] = zext(TMPD1[24,8]);
+ TMPQ2[64,16] = zext(TMPD1[32,8]);
+ TMPQ2[80,16] = zext(TMPD1[40,8]);
+ TMPQ2[96,16] = zext(TMPD1[48,8]);
+ TMPQ2[112,16] = zext(TMPD1[56,8]);
+ TMPD3 = Rm_VPR128.16B[64,64];
+ # simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2)
+ TMPQ4[0,16] = zext(TMPD3[0,8]);
+ TMPQ4[16,16] = zext(TMPD3[8,8]);
+ TMPQ4[32,16] = zext(TMPD3[16,8]);
+ TMPQ4[48,16] = zext(TMPD3[24,8]);
+ TMPQ4[64,16] = zext(TMPD3[32,8]);
+ TMPQ4[80,16] = zext(TMPD3[40,8]);
+ TMPQ4[96,16] = zext(TMPD3[48,8]);
+ TMPQ4[112,16] = zext(TMPD3[56,8]);
+ # simd infix Rd_VPR128.8H = TMPQ2 * TMPQ4 on lane size 2
+ Rd_VPR128.8H[0,16] = TMPQ2[0,16] * TMPQ4[0,16];
+ Rd_VPR128.8H[16,16] = TMPQ2[16,16] * TMPQ4[16,16];
+ Rd_VPR128.8H[32,16] = TMPQ2[32,16] * TMPQ4[32,16];
+ Rd_VPR128.8H[48,16] = TMPQ2[48,16] * TMPQ4[48,16];
+ Rd_VPR128.8H[64,16] = TMPQ2[64,16] * TMPQ4[64,16];
+ Rd_VPR128.8H[80,16] = TMPQ2[80,16] * TMPQ4[80,16];
+ Rd_VPR128.8H[96,16] = TMPQ2[96,16] * TMPQ4[96,16];
+ Rd_VPR128.8H[112,16] = TMPQ2[112,16] * TMPQ4[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.373 UMULL, UMULL2 (vector) page C7-2873 line 167705 MATCH x2e20c000/mask=xbf20fc00
+# CONSTRUCT x2ea0c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull/2@4
+# AUNIT --inst x2ea0c000/mask=xffe0fc00 --status nopcodeop --comment "ext"
+
+:umull Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0xc & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_umull(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.373 UMULL, UMULL2 (vector) page C7-2873 line 167705 MATCH x2e20c000/mask=xbf20fc00
+# CONSTRUCT x2e60c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull/2@2
+# AUNIT --inst x2e60c000/mask=xffe0fc00 --status nopcodeop --comment "ext"
+
+:umull Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0xc & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_umull(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.373 UMULL, UMULL2 (vector) page C7-2873 line 167705 MATCH x2e20c000/mask=xbf20fc00
+# CONSTRUCT x2e20c000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_umull/2@1
+# AUNIT --inst x2e20c000/mask=xffe0fc00 --status nopcodeop --comment "ext"
+
+:umull Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0xc & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_umull(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.374 UQADD page C7-2875 line 167821 MATCH x7e200c00/mask=xff20fc00
+# CONSTRUCT x7e200c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2
+# AUNIT --inst x7e200c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:uqadd Rd_FPR8, Rn_FPR8, Rm_FPR8
+is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0x1 & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd
+{
+ Rd_FPR8 = NEON_uqadd(Rn_FPR8, Rm_FPR8);
+}
+
+# C7.2.374 UQADD page C7-2875 line 167821 MATCH x7e200c00/mask=xff20fc00
+# CONSTRUCT x7ee00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2
+# AUNIT --inst x7ee00c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:uqadd Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x1 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_uqadd(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.374 UQADD page C7-2875 line 167821 MATCH x7e200c00/mask=xff20fc00
+# CONSTRUCT x7e600c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2
+# AUNIT --inst x7e600c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:uqadd Rd_FPR16, Rn_FPR16, Rm_FPR16
+is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x1 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_uqadd(Rn_FPR16, Rm_FPR16);
+}
+
+# C7.2.374 UQADD page C7-2875 line 167821 MATCH x7e200c00/mask=xff20fc00
+# CONSTRUCT x7ea00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2
+# AUNIT --inst x7ea00c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:uqadd Rd_FPR32, Rn_FPR32, Rm_FPR32
+is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x1 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_uqadd(Rn_FPR32, Rm_FPR32);
+}
+
+# C7.2.374 UQADD page C7-2875 line 167821 MATCH x2e200c00/mask=xbf20fc00
+# CONSTRUCT x6e200c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@1
+# AUNIT --inst x6e200c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:uqadd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x1 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_uqadd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.374 UQADD page C7-2875 line 167821 MATCH x2e200c00/mask=xbf20fc00
+# CONSTRUCT x6ee00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@8
+# AUNIT --inst x6ee00c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:uqadd Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x1 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_uqadd(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.374 UQADD page C7-2875 line 167821 MATCH x2e200c00/mask=xbf20fc00
+# CONSTRUCT x2ea00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@4
+# AUNIT --inst x2ea00c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:uqadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x1 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_uqadd(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.374 UQADD page C7-2875 line 167821 MATCH x2e200c00/mask=xbf20fc00
+# CONSTRUCT x2e600c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@2
+# AUNIT --inst x2e600c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:uqadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x1 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_uqadd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.374 UQADD page C7-2875 line 167821 MATCH x2e200c00/mask=xbf20fc00
+# CONSTRUCT x6ea00c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@4
+# AUNIT --inst x6ea00c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:uqadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x1 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_uqadd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.374 UQADD page C7-2875 line 167821 MATCH x2e200c00/mask=xbf20fc00
+# CONSTRUCT x2e200c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@1
+# AUNIT --inst x2e200c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:uqadd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x1 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_uqadd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.374 UQADD page C7-2875 line 167821 MATCH x2e200c00/mask=xbf20fc00
+# CONSTRUCT x6e600c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqadd/2@2
+# AUNIT --inst x6e600c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:uqadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x1 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_uqadd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x7e205c00/mask=xff20fc00
+# CONSTRUCT x7e205c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2
+# AUNIT --inst x7e205c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqrshl Rd_FPR8, Rn_FPR8, Rm_FPR8
+is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0xb & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd
+{
+ Rd_FPR8 = NEON_uqrshl(Rn_FPR8, Rm_FPR8);
+}
+
+# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x7e205c00/mask=xff20fc00
+# CONSTRUCT x7ee05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2
+# AUNIT --inst x7ee05c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqrshl Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0xb & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_uqrshl(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x7e205c00/mask=xff20fc00
+# CONSTRUCT x7e605c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2
+# AUNIT --inst x7e605c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqrshl Rd_FPR16, Rn_FPR16, Rm_FPR16
+is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0xb & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_uqrshl(Rn_FPR16, Rm_FPR16);
+}
+
+# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x7e205c00/mask=xff20fc00
+# CONSTRUCT x7ea05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2
+# AUNIT --inst x7ea05c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqrshl Rd_FPR32, Rn_FPR32, Rm_FPR32
+is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0xb & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_uqrshl(Rn_FPR32, Rm_FPR32);
+}
+
+# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x2e205c00/mask=xbf20fc00
+# CONSTRUCT x6e205c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@1
+# AUNIT --inst x6e205c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqrshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xb & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_uqrshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x2e205c00/mask=xbf20fc00
+# CONSTRUCT x6ee05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@8
+# AUNIT --inst x6ee05c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqrshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0xb & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_uqrshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x2e205c00/mask=xbf20fc00
+# CONSTRUCT x2ea05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@4
+# AUNIT --inst x2ea05c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqrshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xb & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_uqrshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x2e205c00/mask=xbf20fc00
+# CONSTRUCT x2e605c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@2
+# AUNIT --inst x2e605c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqrshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xb & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_uqrshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x2e205c00/mask=xbf20fc00
+# CONSTRUCT x6ea05c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@4
+# AUNIT --inst x6ea05c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqrshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xb & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_uqrshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x2e205c00/mask=xbf20fc00
+# CONSTRUCT x2e205c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@1
+# AUNIT --inst x2e205c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqrshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xb & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_uqrshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.375 UQRSHL page C7-2877 line 167948 MATCH x2e205c00/mask=xbf20fc00
+# CONSTRUCT x6e605c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqrshl/2@2
+# AUNIT --inst x6e605c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqrshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xb & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_uqrshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x2f009c00/mask=xbf80fc00
+# CONSTRUCT x6f089c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn2/2@2
+# AUNIT --inst x6f089c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat"
+
+:uqrshrn2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x13 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_uqrshrn2(Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
+}
+
+# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x2f009c00/mask=xbf80fc00
+# CONSTRUCT x2f209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2@8
+# AUNIT --inst x2f209c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:uqrshrn Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x13 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_uqrshrn(Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
+}
+
+# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x2f009c00/mask=xbf80fc00
+# CONSTRUCT x2f109c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2@4
+# AUNIT --inst x2f109c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:uqrshrn Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x13 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_uqrshrn(Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
+}
+
+# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x2f009c00/mask=xbf80fc00
+# CONSTRUCT x6f209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2@8
+# AUNIT --inst x6f209c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:uqrshrn2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x13 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_uqrshrn(Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
+}
+
+# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x2f009c00/mask=xbf80fc00
+# CONSTRUCT x2f089c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2@2
+# AUNIT --inst x2f089c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat"
+
+:uqrshrn Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x13 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_uqrshrn(Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
+}
+
+# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x2f009c00/mask=xbf80fc00
+# CONSTRUCT x6f109c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn2/2@4
+# AUNIT --inst x6f109c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat"
+
+:uqrshrn2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x13 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_uqrshrn2(Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
+}
+
+# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x7f009c00/mask=xff80fc00
+# CONSTRUCT x7f089c00/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2
+# AUNIT --inst x7f089c00/mask=xfff8fc00 --status nopcodeop --comment "nointround nointsat"
+# Scalar variant when immh=0001 Va=FPR16 Vb=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001
+
+:uqrshrn Rd_FPR8, Rn_FPR16, Imm_shr_imm8
+is b_2331=0b011111110 & b_1922=0b0001 & b_1015=0b100111 & Rd_FPR8 & Rn_FPR16 & Imm_shr_imm8 & Zd
+{
+ Rd_FPR8 = NEON_uqrshrn(Rn_FPR16, Imm_shr_imm8:1);
+}
+
+# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x7f009c00/mask=xff80fc00
+# CONSTRUCT x7f109c00/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2
+# AUNIT --inst x7f109c00/mask=xfff0fc00 --status nopcodeop --comment "nointround nointsat"
+# Scalar variant when immh=001x Va=FPR32 Vb=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001
+
+:uqrshrn Rd_FPR16, Rn_FPR32, Imm_shr_imm16
+is b_2331=0b011111110 & b_2022=0b001 & b_1015=0b100111 & Rd_FPR16 & Rn_FPR32 & Imm_shr_imm16 & Zd
+{
+ Rd_FPR16 = NEON_uqrshrn(Rn_FPR32, Imm_shr_imm16:1);
+}
+
+# C7.2.376 UQRSHRN, UQRSHRN2 page C7-2879 line 168091 MATCH x7f009c00/mask=xff80fc00
+# CONSTRUCT x7f209c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqrshrn/2
+# AUNIT --inst x7f209c00/mask=xffe0fc00 --status nopcodeop --comment "nointround nointsat"
+# Scalar variant when immh=01xx Va=FPR64 Vb=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01
+
+:uqrshrn Rd_FPR32, Rn_FPR64, Imm_shr_imm32
+is b_2331=0b011111110 & b_2122=0b01 & b_1015=0b100111 & Rd_FPR32 & Rn_FPR64 & Imm_shr_imm32 & Zd
+{
+ Rd_FPR32 = NEON_uqrshrn(Rn_FPR64, Imm_shr_imm32:1);
+}
+
+# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00
+# CONSTRUCT x6f087400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@1
+# AUNIT --inst x6f087400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
+
+:uqshl Rd_VPR128.16B, Rn_VPR128.16B, Imm_uimm3
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xe & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_uqshl(Rn_VPR128.16B, Imm_uimm3:1, 1:1);
+}
+
+# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00
+# CONSTRUCT x6f407400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@8
+# AUNIT --inst x6f407400/mask=xffc0fc00 --status nopcodeop --comment "nointsat"
+
+:uqshl Rd_VPR128.2D, Rn_VPR128.2D, Imm_imm0_63
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_imm0_63 & b_1115=0xe & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_uqshl(Rn_VPR128.2D, Imm_imm0_63:1, 8:1);
+}
+
+# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00
+# CONSTRUCT x2f207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@4
+# AUNIT --inst x2f207400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqshl Rd_VPR64.2S, Rn_VPR64.2S, Imm_uimm5
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xe & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_uqshl(Rn_VPR64.2S, Imm_uimm5:1, 4:1);
+}
+
+# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00
+# CONSTRUCT x2f107400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@2
+# AUNIT --inst x2f107400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
+
+:uqshl Rd_VPR64.4H, Rn_VPR64.4H, Imm_uimm4
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xe & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_uqshl(Rn_VPR64.4H, Imm_uimm4:1, 2:1);
+}
+
+# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00
+# CONSTRUCT x6f207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@4
+# AUNIT --inst x6f207400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqshl Rd_VPR128.4S, Rn_VPR128.4S, Imm_uimm5
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0xe & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_uqshl(Rn_VPR128.4S, Imm_uimm5:1, 4:1);
+}
+
+# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00
+# CONSTRUCT x2f087400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@1
+# AUNIT --inst x2f087400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
+
+:uqshl Rd_VPR64.8B, Rn_VPR64.8B, Imm_uimm3
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0xe & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_uqshl(Rn_VPR64.8B, Imm_uimm3:1, 1:1);
+}
+
+# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x2f007400/mask=xbf80fc00
+# CONSTRUCT x6f107400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2@2
+# AUNIT --inst x6f107400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
+
+:uqshl Rd_VPR128.8H, Rn_VPR128.8H, Imm_uimm4
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0xe & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_uqshl(Rn_VPR128.8H, Imm_uimm4:1, 2:1);
+}
+
+# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x7f007400/mask=xff80fc00
+# CONSTRUCT x7f087400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2
+# AUNIT --inst x7f087400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when immh=0001 V=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001
+
+:uqshl Rd_FPR8, Rn_FPR8, Imm_shr_imm8
+is b_2331=0b011111110 & b_1922=0b0001 & b_1015=0b011101 & Rd_FPR8 & Rn_FPR8 & Imm_shr_imm8 & Zd
+{
+ Rd_FPR8 = NEON_uqshl(Rn_FPR8, Imm_shr_imm8:1);
+}
+
+# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x7f007400/mask=xff80fc00
+# CONSTRUCT x7f107400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2
+# AUNIT --inst x7f107400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when immh=001x V=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001
+
+:uqshl Rd_FPR16, Rn_FPR16, Imm_shr_imm16
+is b_2331=0b011111110 & b_2022=0b001 & b_1015=0b011101 & Rd_FPR16 & Rn_FPR16 & Imm_shr_imm16 & Zd
+{
+ Rd_FPR16 = NEON_uqshl(Rn_FPR16, Imm_shr_imm16:1);
+}
+
+# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x7f007400/mask=xff80fc00
+# CONSTRUCT x7f207400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2
+# AUNIT --inst x7f207400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when immh=01xx V=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01
+
+:uqshl Rd_FPR32, Rn_FPR32, Imm_shr_imm32
+is b_2331=0b011111110 & b_2122=0b01 & b_1015=0b011101 & Rd_FPR32 & Rn_FPR32 & Imm_shr_imm32 & Zd
+{
+ Rd_FPR32 = NEON_uqshl(Rn_FPR32, Imm_shr_imm32:1);
+}
+
+# C7.2.377 UQSHL (immediate) page C7-2882 line 168276 MATCH x7f007400/mask=xff80fc00
+# CONSTRUCT x7f407400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_uqshl/2
+# AUNIT --inst x7f407400/mask=xffc0fc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when immh=1xxx V=FPR64 imm=Imm_shr_imm64 bb=b_22 aa=1
+
+:uqshl Rd_FPR64, Rn_FPR64, Imm_shr_imm64
+is b_2331=0b011111110 & b_22=1 & b_1015=0b011101 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd
+{
+ Rd_FPR64 = NEON_uqshl(Rn_FPR64, Imm_shr_imm64:1);
+}
+
+# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x7e204c00/mask=xff20fc00
+# CONSTRUCT x7e204c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2
+# AUNIT --inst x7e204c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqshl Rd_FPR8, Rn_FPR8, Rm_FPR8
+is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0x9 & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd
+{
+ Rd_FPR8 = NEON_uqshl(Rn_FPR8, Rm_FPR8);
+}
+
+# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x7e204c00/mask=xff20fc00
+# CONSTRUCT x7ee04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2
+# AUNIT --inst x7ee04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqshl Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x9 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_uqshl(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x7e204c00/mask=xff20fc00
+# CONSTRUCT x7e604c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2
+# AUNIT --inst x7e604c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqshl Rd_FPR16, Rn_FPR16, Rm_FPR16
+is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x9 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_uqshl(Rn_FPR16, Rm_FPR16);
+}
+
+# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x7e204c00/mask=xff20fc00
+# CONSTRUCT x7ea04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2
+# AUNIT --inst x7ea04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqshl Rd_FPR32, Rn_FPR32, Rm_FPR32
+is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x9 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_uqshl(Rn_FPR32, Rm_FPR32);
+}
+
+# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x2e204c00/mask=xbf20fc00
+# CONSTRUCT x6e204c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@1
+# AUNIT --inst x6e204c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x9 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_uqshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x2e204c00/mask=xbf20fc00
+# CONSTRUCT x6ee04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@8
+# AUNIT --inst x6ee04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x9 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_uqshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x2e204c00/mask=xbf20fc00
+# CONSTRUCT x2ea04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@4
+# AUNIT --inst x2ea04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x9 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_uqshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x2e204c00/mask=xbf20fc00
+# CONSTRUCT x2e604c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@2
+# AUNIT --inst x2e604c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x9 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_uqshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x2e204c00/mask=xbf20fc00
+# CONSTRUCT x6ea04c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@4
+# AUNIT --inst x6ea04c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x9 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_uqshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x2e204c00/mask=xbf20fc00
+# CONSTRUCT x2e204c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@1
+# AUNIT --inst x2e204c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x9 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_uqshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.378 UQSHL (register) page C7-2885 line 168441 MATCH x2e204c00/mask=xbf20fc00
+# CONSTRUCT x6e604c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqshl/2@2
+# AUNIT --inst x6e604c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x9 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_uqshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x2f009400/mask=xbf80fc00
+# CONSTRUCT x6f089400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn2/3@2
+# AUNIT --inst x6f089400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
+
+:uqshrn2 Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x12 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_uqshrn2(Rd_VPR128.16B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
+}
+
+# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x2f009400/mask=xbf80fc00
+# CONSTRUCT x2f209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn/3@8
+# AUNIT --inst x2f209400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqshrn Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x12 & b_1010=1 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_uqshrn(Rd_VPR64.2S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
+}
+
+# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x2f009400/mask=xbf80fc00
+# CONSTRUCT x2f109400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn/3@4
+# AUNIT --inst x2f109400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
+
+:uqshrn Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x12 & b_1010=1 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_uqshrn(Rd_VPR64.4H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
+}
+
+# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x2f009400/mask=xbf80fc00
+# CONSTRUCT x6f209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn2/3@8
+# AUNIT --inst x6f209400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqshrn2 Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x12 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_uqshrn2(Rd_VPR128.4S, Rn_VPR128.2D, Imm_shr_imm32:1, 8:1);
+}
+
+# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x2f009400/mask=xbf80fc00
+# CONSTRUCT x2f089400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn/3@2
+# AUNIT --inst x2f089400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
+
+:uqshrn Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x12 & b_1010=1 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_uqshrn(Rd_VPR64.8B, Rn_VPR128.8H, Imm_shr_imm8:1, 2:1);
+}
+
+# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x2f009400/mask=xbf80fc00
+# CONSTRUCT x6f109400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn2/3@4
+# AUNIT --inst x6f109400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
+
+:uqshrn2 Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x12 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_uqshrn2(Rd_VPR128.8H, Rn_VPR128.4S, Imm_shr_imm16:1, 4:1);
+}
+
+# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x7f009400/mask=xff80fc00
+# CONSTRUCT x7f089400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn/3
+# AUNIT --inst x7f089400/mask=xfff8fc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when immh=0001 Va=FPR16 Vb=FPR8 imm=Imm_shr_imm8 bb=b_1922 aa=0b0001
+
+:uqshrn Rd_FPR8, Rn_FPR16, Imm_shr_imm8
+is b_2331=0b011111110 & b_1922=0b0001 & b_1015=0b100101 & Rd_FPR8 & Rn_FPR16 & Imm_shr_imm8 & Zd
+{
+ Rd_FPR8 = NEON_uqshrn(Rd_FPR8, Rn_FPR16, Imm_shr_imm8:1);
+}
+
+# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x7f009400/mask=xff80fc00
+# CONSTRUCT x7f109400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn/3
+# AUNIT --inst x7f109400/mask=xfff0fc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when immh=001x Va=FPR32 Vb=FPR16 imm=Imm_shr_imm16 bb=b_2022 aa=0b001
+
+:uqshrn Rd_FPR16, Rn_FPR32, Imm_shr_imm16
+is b_2331=0b011111110 & b_2022=0b001 & b_1015=0b100101 & Rd_FPR16 & Rn_FPR32 & Imm_shr_imm16 & Zd
+{
+ Rd_FPR16 = NEON_uqshrn(Rd_FPR16, Rn_FPR32, Imm_shr_imm16:1);
+}
+
+# C7.2.379 UQSHRN, UQSHRN2 page C7-2887 line 168584 MATCH x7f009400/mask=xff80fc00
+# CONSTRUCT x7f209400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_uqshrn/3
+# AUNIT --inst x7f209400/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when immh=01xx Va=FPR64 Vb=FPR32 imm=Imm_shr_imm32 bb=b_2122 aa=0b01
+
+:uqshrn Rd_FPR32, Rn_FPR64, Imm_shr_imm32
+is b_2331=0b011111110 & b_2122=0b01 & b_1015=0b100101 & Rd_FPR32 & Rn_FPR64 & Imm_shr_imm32 & Zd
+{
+ Rd_FPR32 = NEON_uqshrn(Rd_FPR32, Rn_FPR64, Imm_shr_imm32:1);
+}
+
+# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x7e202c00/mask=xff20fc00
+# CONSTRUCT x7e202c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2
+# AUNIT --inst x7e202c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqsub Rd_FPR8, Rn_FPR8, Rm_FPR8
+is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=0 & b_2121=1 & Rm_FPR8 & b_1115=0x5 & b_1010=1 & Rn_FPR8 & Rd_FPR8 & Zd
+{
+ Rd_FPR8 = NEON_uqsub(Rn_FPR8, Rm_FPR8);
+}
+
+# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x7e202c00/mask=xff20fc00
+# CONSTRUCT x7ee02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2
+# AUNIT --inst x7ee02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqsub Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x5 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_uqsub(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x7e202c00/mask=xff20fc00
+# CONSTRUCT x7e602c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2
+# AUNIT --inst x7e602c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqsub Rd_FPR16, Rn_FPR16, Rm_FPR16
+is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=1 & b_2121=1 & Rm_FPR16 & b_1115=0x5 & b_1010=1 & Rn_FPR16 & Rd_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_uqsub(Rn_FPR16, Rm_FPR16);
+}
+
+# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x7e202c00/mask=xff20fc00
+# CONSTRUCT x7ea02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2
+# AUNIT --inst x7ea02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqsub Rd_FPR32, Rn_FPR32, Rm_FPR32
+is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=2 & b_2121=1 & Rm_FPR32 & b_1115=0x5 & b_1010=1 & Rn_FPR32 & Rd_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_uqsub(Rn_FPR32, Rm_FPR32);
+}
+
+# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x2e202c00/mask=xbf20fc00
+# CONSTRUCT x6e202c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@1
+# AUNIT --inst x6e202c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqsub Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x5 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_uqsub(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x2e202c00/mask=xbf20fc00
+# CONSTRUCT x6ee02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@8
+# AUNIT --inst x6ee02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqsub Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x5 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_uqsub(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x2e202c00/mask=xbf20fc00
+# CONSTRUCT x2ea02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@4
+# AUNIT --inst x2ea02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqsub Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x5 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_uqsub(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x2e202c00/mask=xbf20fc00
+# CONSTRUCT x2e602c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@2
+# AUNIT --inst x2e602c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqsub Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x5 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_uqsub(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x2e202c00/mask=xbf20fc00
+# CONSTRUCT x6ea02c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@4
+# AUNIT --inst x6ea02c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqsub Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x5 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_uqsub(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x2e202c00/mask=xbf20fc00
+# CONSTRUCT x2e202c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@1
+# AUNIT --inst x2e202c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqsub Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x5 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_uqsub(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.380 UQSUB page C7-2890 line 168769 MATCH x2e202c00/mask=xbf20fc00
+# CONSTRUCT x6e602c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uqsub/2@2
+# AUNIT --inst x6e602c00/mask=xffe0fc00 --status nopcodeop --comment "nointsat"
+
+:uqsub Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x5 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_uqsub(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x7e214800/mask=xff3ffc00
+# CONSTRUCT x7e214800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn/2
+# AUNIT --inst x7e214800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when size=00 Q=1 bb=1 mnemonic=uqxtn Ta=FPR16 Tb=FPR8
+
+:uqxtn Rd_FPR8, Rn_FPR16
+is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b00 & b_1021=0b100001010010 & Rd_FPR8 & Rn_FPR16 & Zd
+{
+ Rd_FPR8 = NEON_uqxtn(Rd_FPR8, Rn_FPR16);
+}
+
+# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x7e214800/mask=xff3ffc00
+# CONSTRUCT x7e614800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn/2
+# AUNIT --inst x7e614800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when size=01 Q=1 bb=1 mnemonic=uqxtn Ta=FPR32 Tb=FPR16
+
+:uqxtn Rd_FPR16, Rn_FPR32
+is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b01 & b_1021=0b100001010010 & Rd_FPR16 & Rn_FPR32 & Zd
+{
+ Rd_FPR16 = NEON_uqxtn(Rd_FPR16, Rn_FPR32);
+}
+
+# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x7e214800/mask=xff3ffc00
+# CONSTRUCT x7ea14800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn/2
+# AUNIT --inst x7ea14800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when size=10 Q=1 bb=1 mnemonic=uqxtn Ta=FPR64 Tb=FPR32
+
+:uqxtn Rd_FPR32, Rn_FPR64
+is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b10 & b_1021=0b100001010010 & Rd_FPR32 & Rn_FPR64 & Zd
+{
+ Rd_FPR32 = NEON_uqxtn(Rd_FPR32, Rn_FPR64);
+}
+
+# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x2e214800/mask=xbf3ffc00
+# CONSTRUCT x2e214800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn/2@2
+# AUNIT --inst x2e214800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Vector variant when size=00 Q=0 bb=0 mnemonic=uqxtn e=2 Ta=VPR128.8H Tb=VPR64.8B
+
+:uqxtn Rd_VPR64.8B, Rn_VPR128.8H
+is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100001010010 & Rd_VPR64.8B & Rn_VPR128.8H & Zd
+{
+ Rd_VPR64.8B = NEON_uqxtn(Rd_VPR64.8B, Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x2e214800/mask=xbf3ffc00
+# CONSTRUCT x6e214800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn2/2@2
+# AUNIT --inst x6e214800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Vector variant when size=00 Q=1 bb=0 mnemonic=uqxtn2 e=2 Ta=VPR128.8H Tb=VPR128.16B
+
+:uqxtn2 Rd_VPR128.16B, Rn_VPR128.8H
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100001010010 & Rd_VPR128.16B & Rn_VPR128.8H & Zd
+{
+ Rd_VPR128.16B = NEON_uqxtn2(Rd_VPR128.16B, Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x2e214800/mask=xbf3ffc00
+# CONSTRUCT x2e614800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn/2@4
+# AUNIT --inst x2e614800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Vector variant when size=01 Q=0 bb=0 mnemonic=uqxtn e=4 Ta=VPR128.4S Tb=VPR64.4H
+
+:uqxtn Rd_VPR64.4H, Rn_VPR128.4S
+is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100001010010 & Rd_VPR64.4H & Rn_VPR128.4S & Zd
+{
+ Rd_VPR64.4H = NEON_uqxtn(Rd_VPR64.4H, Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x2e214800/mask=xbf3ffc00
+# CONSTRUCT x6e614800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn2/2@4
+# AUNIT --inst x6e614800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Vector variant when size=01 Q=1 bb=0 mnemonic=uqxtn2 e=4 Ta=VPR128.4S Tb=VPR128.8H
+
+:uqxtn2 Rd_VPR128.8H, Rn_VPR128.4S
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100001010010 & Rd_VPR128.8H & Rn_VPR128.4S & Zd
+{
+ Rd_VPR128.8H = NEON_uqxtn2(Rd_VPR128.8H, Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x2e214800/mask=xbf3ffc00
+# CONSTRUCT x2ea14800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn/2@8
+# AUNIT --inst x2ea14800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Vector variant when size=10 Q=0 bb=0 mnemonic=uqxtn e=8 Ta=VPR128.2D Tb=VPR64.2S
+
+:uqxtn Rd_VPR64.2S, Rn_VPR128.2D
+is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100001010010 & Rd_VPR64.2S & Rn_VPR128.2D & Zd
+{
+ Rd_VPR64.2S = NEON_uqxtn(Rd_VPR64.2S, Rn_VPR128.2D, 8:1);
+}
+
+# C7.2.381 UQXTN, UQXTN2 page C7-2892 line 168897 MATCH x2e214800/mask=xbf3ffc00
+# CONSTRUCT x6ea14800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_uqxtn2/2@8
+# AUNIT --inst x6ea14800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Vector variant when size=10 Q=1 bb=0 mnemonic=uqxtn2 e=8 Ta=VPR128.2D Tb=VPR128.4S
+
+:uqxtn2 Rd_VPR128.4S, Rn_VPR128.2D
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100001010010 & Rd_VPR128.4S & Rn_VPR128.2D & Zd
+{
+ Rd_VPR128.4S = NEON_uqxtn2(Rd_VPR128.4S, Rn_VPR128.2D, 8:1);
+}
+
+# C7.2.382 URECPE page C7-2895 line 169051 MATCH x0ea1c800/mask=xbfbffc00
+# CONSTRUCT x0ea1c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_urecpe/1@4
+# AUNIT --inst x0ea1c800/mask=xfffffc00 --status nopcodeop
+# Vector variant when Q=0 T=VPR64.2S
+
+:urecpe Rd_VPR64.2S, Rn_VPR64.2S
+is b_31=0 & b_30=0 & b_2329=0b0011101 & b_22=0 & b_1021=0b100001110010 & Rd_VPR64.2S & Rn_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_urecpe(Rn_VPR64.2S, 4:1);
+}
+
+# C7.2.382 URECPE page C7-2895 line 169051 MATCH x0ea1c800/mask=xbfbffc00
+# CONSTRUCT x4ea1c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_urecpe/1@4
+# AUNIT --inst x4ea1c800/mask=xfffffc00 --status nopcodeop
+# Vector variant when Q=1 T=VPR128.4S
+
+:urecpe Rd_VPR128.4S, Rn_VPR128.4S
+is b_31=0 & b_30=1 & b_2329=0b0011101 & b_22=0 & b_1021=0b100001110010 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_urecpe(Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.383 URHADD page C7-2896 line 169117 MATCH x2e201400/mask=xbf20fc00
+# CONSTRUCT x6e201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urhadd/2@1
+# AUNIT --inst x6e201400/mask=xffe0fc00 --status nopcodeop
+
+:urhadd Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x2 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_urhadd(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.383 URHADD page C7-2896 line 169117 MATCH x2e201400/mask=xbf20fc00
+# CONSTRUCT x2ea01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urhadd/2@2
+# AUNIT --inst x2ea01400/mask=xffe0fc00 --status nopcodeop
+
+:urhadd Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x2 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_urhadd(Rn_VPR64.2S, Rm_VPR64.2S, 2:1);
+}
+
+# C7.2.383 URHADD page C7-2896 line 169117 MATCH x2e201400/mask=xbf20fc00
+# CONSTRUCT x2e601400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urhadd/2@2
+# AUNIT --inst x2e601400/mask=xffe0fc00 --status nopcodeop
+
+:urhadd Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x2 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_urhadd(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.383 URHADD page C7-2896 line 169117 MATCH x2e201400/mask=xbf20fc00
+# CONSTRUCT x6ea01400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urhadd/2@4
+# AUNIT --inst x6ea01400/mask=xffe0fc00 --status nopcodeop
+
+:urhadd Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x2 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_urhadd(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.383 URHADD page C7-2896 line 169117 MATCH x2e201400/mask=xbf20fc00
+# CONSTRUCT x2e201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urhadd/2@1
+# AUNIT --inst x2e201400/mask=xffe0fc00 --status nopcodeop
+
+:urhadd Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x2 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_urhadd(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.383 URHADD page C7-2896 line 169117 MATCH x2e201400/mask=xbf20fc00
+# CONSTRUCT x6e601400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urhadd/2@2
+# AUNIT --inst x6e601400/mask=xffe0fc00 --status nopcodeop
+
+:urhadd Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x2 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_urhadd(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.384 URSHL page C7-2898 line 169205 MATCH x7e205400/mask=xff20fc00
+# CONSTRUCT x7ee05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2
+# AUNIT --inst x7ee05400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:urshl Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0xa & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_urshl(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.384 URSHL page C7-2898 line 169205 MATCH x2e205400/mask=xbf20fc00
+# CONSTRUCT x6e205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@1
+# AUNIT --inst x6e205400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:urshl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0xa & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_urshl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.384 URSHL page C7-2898 line 169205 MATCH x2e205400/mask=xbf20fc00
+# CONSTRUCT x6ee05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@8
+# AUNIT --inst x6ee05400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:urshl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0xa & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_urshl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.384 URSHL page C7-2898 line 169205 MATCH x2e205400/mask=xbf20fc00
+# CONSTRUCT x2ea05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@4
+# AUNIT --inst x2ea05400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:urshl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0xa & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_urshl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.384 URSHL page C7-2898 line 169205 MATCH x2e205400/mask=xbf20fc00
+# CONSTRUCT x2e605400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@2
+# AUNIT --inst x2e605400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:urshl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0xa & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_urshl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.384 URSHL page C7-2898 line 169205 MATCH x2e205400/mask=xbf20fc00
+# CONSTRUCT x6ea05400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@4
+# AUNIT --inst x6ea05400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:urshl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0xa & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_urshl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.384 URSHL page C7-2898 line 169205 MATCH x2e205400/mask=xbf20fc00
+# CONSTRUCT x2e205400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@1
+# AUNIT --inst x2e205400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:urshl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0xa & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_urshl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.384 URSHL page C7-2898 line 169205 MATCH x2e205400/mask=xbf20fc00
+# CONSTRUCT x6e605400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_urshl/2@2
+# AUNIT --inst x6e605400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:urshl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0xa & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_urshl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00
+# CONSTRUCT x6f082400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@1
+# AUNIT --inst x6f082400/mask=xfff8fc00 --status nopcodeop --comment "nointround"
+
+:urshr Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x4 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_urshr(Rn_VPR128.16B, Imm_shr_imm8:1, 1:1);
+}
+
+# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00
+# CONSTRUCT x6f402400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@8
+# AUNIT --inst x6f402400/mask=xffc0fc00 --status nopcodeop --comment "nointround"
+
+:urshr Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x4 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_urshr(Rn_VPR128.2D, Imm_shr_imm64:1, 8:1);
+}
+
+# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00
+# CONSTRUCT x2f202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@4
+# AUNIT --inst x2f202400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:urshr Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x4 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_urshr(Rn_VPR64.2S, Imm_shr_imm32:1, 4:1);
+}
+
+# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00
+# CONSTRUCT x2f102400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@2
+# AUNIT --inst x2f102400/mask=xfff0fc00 --status nopcodeop --comment "nointround"
+
+:urshr Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x4 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_urshr(Rn_VPR64.4H, Imm_shr_imm16:1, 2:1);
+}
+
+# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00
+# CONSTRUCT x6f202400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@4
+# AUNIT --inst x6f202400/mask=xffe0fc00 --status nopcodeop --comment "nointround"
+
+:urshr Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x4 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_urshr(Rn_VPR128.4S, Imm_shr_imm32:1, 4:1);
+}
+
+# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00
+# CONSTRUCT x2f082400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@1
+# AUNIT --inst x2f082400/mask=xfff8fc00 --status nopcodeop --comment "nointround"
+
+:urshr Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x4 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_urshr(Rn_VPR64.8B, Imm_shr_imm8:1, 1:1);
+}
+
+# C7.2.385 URSHR page C7-2900 line 169341 MATCH x2f002400/mask=xbf80fc00
+# CONSTRUCT x6f102400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2@2
+# AUNIT --inst x6f102400/mask=xfff0fc00 --status nopcodeop --comment "nointround"
+
+:urshr Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x4 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_urshr(Rn_VPR128.8H, Imm_shr_imm16:1, 2:1);
+}
+
+# C7.2.385 URSHR page C7-2900 line 169341 MATCH x7f002400/mask=xff80fc00
+# CONSTRUCT x7f402400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_urshr/2
+# AUNIT --inst x7f402400/mask=xffc0fc00 --status nopcodeop --comment "nointround"
+# Scalar variant
+
+:urshr Rd_FPR64, Rn_FPR64, Imm_shr_imm32
+is b_2331=0b011111110 & b_22=1 & b_1015=0b001001 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm32 & Zd
+{
+ Rd_FPR64 = NEON_urshr(Rn_FPR64, Imm_shr_imm32:1);
+}
+
+# C7.2.386 URSQRTE page C7-2903 line 169492 MATCH x2ea1c800/mask=xbfbffc00
+# CONSTRUCT x2ea1c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ursqrte/1@4
+# AUNIT --inst x2ea1c800/mask=xfffffc00 --status nopcodeop
+# Vector variant when Q=0 T=VPR64.2S
+
+:ursqrte Rd_VPR64.2S, Rn_VPR64.2S
+is b_31=0 & b_30=0 & b_2329=0b1011101 & b_22=0 & b_1021=0b100001110010 & Rd_VPR64.2S & Rn_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_ursqrte(Rn_VPR64.2S, 4:1);
+}
+
+# C7.2.386 URSQRTE page C7-2903 line 169492 MATCH x2ea1c800/mask=xbfbffc00
+# CONSTRUCT x6ea1c800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 =NEON_ursqrte/1@4
+# AUNIT --inst x6ea1c800/mask=xfffffc00 --status nopcodeop
+# Vector variant when Q=0 T=VPR128.4S
+
+:ursqrte Rd_VPR128.4S, Rn_VPR128.4S
+is b_31=0 & b_30=1 & b_2329=0b1011101 & b_22=0 & b_1021=0b100001110010 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_ursqrte(Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00
+# CONSTRUCT x6f083400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:1 $>>@1 &=$+@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@1
+# AUNIT --inst x6f083400/mask=xfff8fc00 --status fail --comment "nointround"
+
+:ursra Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x6 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.16B >> Imm_shr_imm8:1 on lane size 1
+ TMPQ1[0,8] = Rn_VPR128.16B[0,8] >> Imm_shr_imm8:1;
+ TMPQ1[8,8] = Rn_VPR128.16B[8,8] >> Imm_shr_imm8:1;
+ TMPQ1[16,8] = Rn_VPR128.16B[16,8] >> Imm_shr_imm8:1;
+ TMPQ1[24,8] = Rn_VPR128.16B[24,8] >> Imm_shr_imm8:1;
+ TMPQ1[32,8] = Rn_VPR128.16B[32,8] >> Imm_shr_imm8:1;
+ TMPQ1[40,8] = Rn_VPR128.16B[40,8] >> Imm_shr_imm8:1;
+ TMPQ1[48,8] = Rn_VPR128.16B[48,8] >> Imm_shr_imm8:1;
+ TMPQ1[56,8] = Rn_VPR128.16B[56,8] >> Imm_shr_imm8:1;
+ TMPQ1[64,8] = Rn_VPR128.16B[64,8] >> Imm_shr_imm8:1;
+ TMPQ1[72,8] = Rn_VPR128.16B[72,8] >> Imm_shr_imm8:1;
+ TMPQ1[80,8] = Rn_VPR128.16B[80,8] >> Imm_shr_imm8:1;
+ TMPQ1[88,8] = Rn_VPR128.16B[88,8] >> Imm_shr_imm8:1;
+ TMPQ1[96,8] = Rn_VPR128.16B[96,8] >> Imm_shr_imm8:1;
+ TMPQ1[104,8] = Rn_VPR128.16B[104,8] >> Imm_shr_imm8:1;
+ TMPQ1[112,8] = Rn_VPR128.16B[112,8] >> Imm_shr_imm8:1;
+ TMPQ1[120,8] = Rn_VPR128.16B[120,8] >> Imm_shr_imm8:1;
+ # simd infix Rd_VPR128.16B = Rd_VPR128.16B + TMPQ1 on lane size 1
+ Rd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] + TMPQ1[0,8];
+ Rd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] + TMPQ1[8,8];
+ Rd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] + TMPQ1[16,8];
+ Rd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] + TMPQ1[24,8];
+ Rd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] + TMPQ1[32,8];
+ Rd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] + TMPQ1[40,8];
+ Rd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] + TMPQ1[48,8];
+ Rd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] + TMPQ1[56,8];
+ Rd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] + TMPQ1[64,8];
+ Rd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] + TMPQ1[72,8];
+ Rd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] + TMPQ1[80,8];
+ Rd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] + TMPQ1[88,8];
+ Rd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] + TMPQ1[96,8];
+ Rd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] + TMPQ1[104,8];
+ Rd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] + TMPQ1[112,8];
+ Rd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] + TMPQ1[120,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00
+# CONSTRUCT x6f403400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 zext:8 $>>@8 &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@8
+# AUNIT --inst x6f403400/mask=xffc0fc00 --status fail --comment "nointround"
+
+:ursra Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x6 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ local tmp1:8 = zext(Imm_shr_imm64);
+ # simd infix TMPQ1 = Rn_VPR128.2D >> tmp1 on lane size 8
+ TMPQ1[0,64] = Rn_VPR128.2D[0,64] >> tmp1;
+ TMPQ1[64,64] = Rn_VPR128.2D[64,64] >> tmp1;
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ1 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ1[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ1[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00
+# CONSTRUCT x2f203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =var:4 $>>@4 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@4
+# AUNIT --inst x2f203400/mask=xffe0fc00 --status fail --comment "nointround"
+
+:ursra Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x6 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ local tmp1:4 = Imm_shr_imm32;
+ # simd infix TMPD1 = Rn_VPR64.2S >> tmp1 on lane size 4
+ TMPD1[0,32] = Rn_VPR64.2S[0,32] >> tmp1;
+ TMPD1[32,32] = Rn_VPR64.2S[32,32] >> tmp1;
+ # simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4
+ Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32];
+ Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00
+# CONSTRUCT x2f103400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:2 $>>@2 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@2
+# AUNIT --inst x2f103400/mask=xfff0fc00 --status fail --comment "nointround"
+
+:ursra Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x6 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ # simd infix TMPD1 = Rn_VPR64.4H >> Imm_shr_imm16:2 on lane size 2
+ TMPD1[0,16] = Rn_VPR64.4H[0,16] >> Imm_shr_imm16:2;
+ TMPD1[16,16] = Rn_VPR64.4H[16,16] >> Imm_shr_imm16:2;
+ TMPD1[32,16] = Rn_VPR64.4H[32,16] >> Imm_shr_imm16:2;
+ TMPD1[48,16] = Rn_VPR64.4H[48,16] >> Imm_shr_imm16:2;
+ # simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 4
+ Rd_VPR64.4H[0,32] = Rd_VPR64.4H[0,32] + TMPD1[0,32];
+ Rd_VPR64.4H[32,32] = Rd_VPR64.4H[32,32] + TMPD1[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00
+# CONSTRUCT x6f203400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =var:4 $>>@4 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@4
+# AUNIT --inst x6f203400/mask=xffe0fc00 --status fail --comment "nointround"
+
+:ursra Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x6 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ local tmp1:4 = Imm_shr_imm32;
+ # simd infix TMPQ1 = Rn_VPR128.4S >> tmp1 on lane size 4
+ TMPQ1[0,32] = Rn_VPR128.4S[0,32] >> tmp1;
+ TMPQ1[32,32] = Rn_VPR128.4S[32,32] >> tmp1;
+ TMPQ1[64,32] = Rn_VPR128.4S[64,32] >> tmp1;
+ TMPQ1[96,32] = Rn_VPR128.4S[96,32] >> tmp1;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00
+# CONSTRUCT x2f083400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:1 $>>@1 &=$+@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@1
+# AUNIT --inst x2f083400/mask=xfff8fc00 --status fail --comment "nointround"
+
+:ursra Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x6 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ # simd infix TMPD1 = Rn_VPR64.8B >> Imm_shr_imm8:1 on lane size 1
+ TMPD1[0,8] = Rn_VPR64.8B[0,8] >> Imm_shr_imm8:1;
+ TMPD1[8,8] = Rn_VPR64.8B[8,8] >> Imm_shr_imm8:1;
+ TMPD1[16,8] = Rn_VPR64.8B[16,8] >> Imm_shr_imm8:1;
+ TMPD1[24,8] = Rn_VPR64.8B[24,8] >> Imm_shr_imm8:1;
+ TMPD1[32,8] = Rn_VPR64.8B[32,8] >> Imm_shr_imm8:1;
+ TMPD1[40,8] = Rn_VPR64.8B[40,8] >> Imm_shr_imm8:1;
+ TMPD1[48,8] = Rn_VPR64.8B[48,8] >> Imm_shr_imm8:1;
+ TMPD1[56,8] = Rn_VPR64.8B[56,8] >> Imm_shr_imm8:1;
+ # simd infix Rd_VPR64.8B = Rd_VPR64.8B + TMPD1 on lane size 1
+ Rd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] + TMPD1[0,8];
+ Rd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] + TMPD1[8,8];
+ Rd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] + TMPD1[16,8];
+ Rd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] + TMPD1[24,8];
+ Rd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] + TMPD1[32,8];
+ Rd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] + TMPD1[40,8];
+ Rd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] + TMPD1[48,8];
+ Rd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] + TMPD1[56,8];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.387 URSRA page C7-2904 line 169558 MATCH x2f003400/mask=xbf80fc00
+# CONSTRUCT x6f103400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:2 $>>@2 &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3@2
+# AUNIT --inst x6f103400/mask=xfff0fc00 --status fail --comment "nointround"
+
+:ursra Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x6 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.8H >> Imm_shr_imm16:2 on lane size 2
+ TMPQ1[0,16] = Rn_VPR128.8H[0,16] >> Imm_shr_imm16:2;
+ TMPQ1[16,16] = Rn_VPR128.8H[16,16] >> Imm_shr_imm16:2;
+ TMPQ1[32,16] = Rn_VPR128.8H[32,16] >> Imm_shr_imm16:2;
+ TMPQ1[48,16] = Rn_VPR128.8H[48,16] >> Imm_shr_imm16:2;
+ TMPQ1[64,16] = Rn_VPR128.8H[64,16] >> Imm_shr_imm16:2;
+ TMPQ1[80,16] = Rn_VPR128.8H[80,16] >> Imm_shr_imm16:2;
+ TMPQ1[96,16] = Rn_VPR128.8H[96,16] >> Imm_shr_imm16:2;
+ TMPQ1[112,16] = Rn_VPR128.8H[112,16] >> Imm_shr_imm16:2;
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.387 URSRA page C7-2904 line 169558 MATCH x7f003400/mask=xff80fc00
+# CONSTRUCT x7f403400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 zext:8 >> &=+
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_ursra/3
+# AUNIT --inst x7f403400/mask=xffc0fc00 --status fail --comment "nointround"
+# Scalar variant when immh=1xxx
+
+:ursra Rd_FPR64, Rn_FPR64, Imm_shr_imm64
+is b_2331=0b011111110 & b_22=1 & b_1015=0b001101 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd
+{
+ local tmp1:8 = zext(Imm_shr_imm64);
+ local tmp2:8 = Rn_FPR64 >> tmp1;
+ Rd_FPR64 = Rd_FPR64 + tmp2;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.390 USHL page C7-2911 line 169885 MATCH x7e204400/mask=xff20fc00
+# CONSTRUCT x7ee04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2
+# AUNIT --inst x7ee04400/mask=xffe0fc00 --status nopcodeop
+
+:ushl Rd_FPR64, Rn_FPR64, Rm_FPR64
+is b_3031=1 & u=1 & b_2428=0x1e & advSIMD3.size=3 & b_2121=1 & Rm_FPR64 & b_1115=0x8 & b_1010=1 & Rn_FPR64 & Rd_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_ushl(Rn_FPR64, Rm_FPR64);
+}
+
+# C7.2.390 USHL page C7-2911 line 169885 MATCH x2e204400/mask=xbf20fc00
+# CONSTRUCT x6e204400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@1
+# AUNIT --inst x6e204400/mask=xffe0fc00 --status nopcodeop
+
+:ushl Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1115=0x8 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_ushl(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.390 USHL page C7-2911 line 169885 MATCH x2e204400/mask=xbf20fc00
+# CONSTRUCT x6ee04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@8
+# AUNIT --inst x6ee04400/mask=xffe0fc00 --status nopcodeop
+
+:ushl Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=3 & b_2121=1 & Rm_VPR128.2D & b_1115=0x8 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_ushl(Rn_VPR128.2D, Rm_VPR128.2D, 8:1);
+}
+
+# C7.2.390 USHL page C7-2911 line 169885 MATCH x2e204400/mask=xbf20fc00
+# CONSTRUCT x2ea04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@4
+# AUNIT --inst x2ea04400/mask=xffe0fc00 --status nopcodeop
+
+:ushl Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1115=0x8 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_ushl(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
+}
+
+# C7.2.390 USHL page C7-2911 line 169885 MATCH x2e204400/mask=xbf20fc00
+# CONSTRUCT x2e604400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@2
+# AUNIT --inst x2e604400/mask=xffe0fc00 --status nopcodeop
+
+:ushl Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1115=0x8 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_ushl(Rn_VPR64.4H, Rm_VPR64.4H, 2:1);
+}
+
+# C7.2.390 USHL page C7-2911 line 169885 MATCH x2e204400/mask=xbf20fc00
+# CONSTRUCT x6ea04400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@4
+# AUNIT --inst x6ea04400/mask=xffe0fc00 --status nopcodeop
+
+:ushl Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1115=0x8 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_ushl(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
+}
+
+# C7.2.390 USHL page C7-2911 line 169885 MATCH x2e204400/mask=xbf20fc00
+# CONSTRUCT x2e204400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@1
+# AUNIT --inst x2e204400/mask=xffe0fc00 --status nopcodeop
+
+:ushl Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1115=0x8 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_ushl(Rn_VPR64.8B, Rm_VPR64.8B, 1:1);
+}
+
+# C7.2.390 USHL page C7-2911 line 169885 MATCH x2e204400/mask=xbf20fc00
+# CONSTRUCT x6e604400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_ushl/2@2
+# AUNIT --inst x6e604400/mask=xffe0fc00 --status nopcodeop
+
+:ushl Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1115=0x8 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_ushl(Rn_VPR128.8H, Rm_VPR128.8H, 2:1);
+}
+
+# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00
+# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00
+# CONSTRUCT x6f08a400/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3 =var:2 =$<<@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushll2/2@1
+# AUNIT --inst x6f08a400/mask=xfff8fc00 --status pass --comment "ext"
+
+:ushll2 Rd_VPR128.8H, Rn_VPR128.16B, Imm_uimm3
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0x14 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
+{
+ TMPD1 = Rn_VPR128.16B[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)
+ TMPQ2[0,16] = zext(TMPD1[0,8]);
+ TMPQ2[16,16] = zext(TMPD1[8,8]);
+ TMPQ2[32,16] = zext(TMPD1[16,8]);
+ TMPQ2[48,16] = zext(TMPD1[24,8]);
+ TMPQ2[64,16] = zext(TMPD1[32,8]);
+ TMPQ2[80,16] = zext(TMPD1[40,8]);
+ TMPQ2[96,16] = zext(TMPD1[48,8]);
+ TMPQ2[112,16] = zext(TMPD1[56,8]);
+ local tmp3:2 = Imm_uimm3;
+ # simd infix Rd_VPR128.8H = TMPQ2 << tmp3 on lane size 2
+ Rd_VPR128.8H[0,16] = TMPQ2[0,16] << tmp3;
+ Rd_VPR128.8H[16,16] = TMPQ2[16,16] << tmp3;
+ Rd_VPR128.8H[32,16] = TMPQ2[32,16] << tmp3;
+ Rd_VPR128.8H[48,16] = TMPQ2[48,16] << tmp3;
+ Rd_VPR128.8H[64,16] = TMPQ2[64,16] << tmp3;
+ Rd_VPR128.8H[80,16] = TMPQ2[80,16] << tmp3;
+ Rd_VPR128.8H[96,16] = TMPQ2[96,16] << tmp3;
+ Rd_VPR128.8H[112,16] = TMPQ2[112,16] << tmp3;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00
+# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00
+# CONSTRUCT x2f20a400/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@4:16 ARG3 =var:8 =$<<@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushll/2@4
+# AUNIT --inst x2f20a400/mask=xffe0fc00 --status pass --comment "ext"
+
+:ushll Rd_VPR128.2D, Rn_VPR64.2S, Imm_uimm5
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0x14 & b_1010=1 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);
+ local tmp2:8 = Imm_uimm5;
+ # simd infix Rd_VPR128.2D = TMPQ1 << tmp2 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ1[0,64] << tmp2;
+ Rd_VPR128.2D[64,64] = TMPQ1[64,64] << tmp2;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00
+# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00
+# CONSTRUCT x2f10a400/mask=xfff0fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@2:16 ARG3 =var:4 =$<<@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushll/2@2
+# AUNIT --inst x2f10a400/mask=xfff0fc00 --status pass --comment "ext"
+
+:ushll Rd_VPR128.4S, Rn_VPR64.4H, Imm_uimm4
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0x14 & b_1010=1 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);
+ local tmp2:4 = Imm_uimm4;
+ # simd infix Rd_VPR128.4S = TMPQ1 << tmp2 on lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ1[0,32] << tmp2;
+ Rd_VPR128.4S[32,32] = TMPQ1[32,32] << tmp2;
+ Rd_VPR128.4S[64,32] = TMPQ1[64,32] << tmp2;
+ Rd_VPR128.4S[96,32] = TMPQ1[96,32] << tmp2;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00
+# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00
+# CONSTRUCT x6f20a400/mask=xffe0fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3 =var:8 =$<<@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushll2/2@4
+# AUNIT --inst x6f20a400/mask=xffe0fc00 --status pass --comment "ext"
+
+:ushll2 Rd_VPR128.2D, Rn_VPR128.4S, Imm_uimm5
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5 & b_1115=0x14 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = zext(TMPD1[0,32]);
+ TMPQ2[64,64] = zext(TMPD1[32,32]);
+ local tmp3:8 = Imm_uimm5;
+ # simd infix Rd_VPR128.2D = TMPQ2 << tmp3 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ2[0,64] << tmp3;
+ Rd_VPR128.2D[64,64] = TMPQ2[64,64] << tmp3;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00
+# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00
+# CONSTRUCT x2f08a400/mask=xfff8fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@1:16 ARG3 =var:2 =$<<@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushll/2@1
+# AUNIT --inst x2f08a400/mask=xfff8fc00 --status pass --comment "ext"
+
+:ushll Rd_VPR128.8H, Rn_VPR64.8B, Imm_uimm3
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3 & b_1115=0x14 & b_1010=1 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2)
+ TMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]);
+ TMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]);
+ TMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]);
+ TMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]);
+ TMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]);
+ TMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]);
+ TMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]);
+ TMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]);
+ local tmp2:2 = Imm_uimm3;
+ # simd infix Rd_VPR128.8H = TMPQ1 << tmp2 on lane size 2
+ Rd_VPR128.8H[0,16] = TMPQ1[0,16] << tmp2;
+ Rd_VPR128.8H[16,16] = TMPQ1[16,16] << tmp2;
+ Rd_VPR128.8H[32,16] = TMPQ1[32,16] << tmp2;
+ Rd_VPR128.8H[48,16] = TMPQ1[48,16] << tmp2;
+ Rd_VPR128.8H[64,16] = TMPQ1[64,16] << tmp2;
+ Rd_VPR128.8H[80,16] = TMPQ1[80,16] << tmp2;
+ Rd_VPR128.8H[96,16] = TMPQ1[96,16] << tmp2;
+ Rd_VPR128.8H[112,16] = TMPQ1[112,16] << tmp2;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00
+# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00
+# CONSTRUCT x6f10a400/mask=xfff0fc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3 =var:4 =$<<@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushll2/2@2
+# AUNIT --inst x6f10a400/mask=xfff0fc00 --status pass --comment "ext"
+
+:ushll2 Rd_VPR128.4S, Rn_VPR128.8H, Imm_uimm4
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4 & b_1115=0x14 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = zext(TMPD1[0,16]);
+ TMPQ2[32,32] = zext(TMPD1[16,16]);
+ TMPQ2[64,32] = zext(TMPD1[32,16]);
+ TMPQ2[96,32] = zext(TMPD1[48,16]);
+ local tmp3:4 = Imm_uimm4;
+ # simd infix Rd_VPR128.4S = TMPQ2 << tmp3 on lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ2[0,32] << tmp3;
+ Rd_VPR128.4S[32,32] = TMPQ2[32,32] << tmp3;
+ Rd_VPR128.4S[64,32] = TMPQ2[64,32] << tmp3;
+ Rd_VPR128.4S[96,32] = TMPQ2[96,32] << tmp3;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00
+# CONSTRUCT x6f080400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:1 =$>>@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@1
+# AUNIT --inst x6f080400/mask=xfff8fc00 --status pass
+
+:ushr Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x0 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ # simd infix Rd_VPR128.16B = Rn_VPR128.16B >> Imm_shr_imm8:1 on lane size 1
+ Rd_VPR128.16B[0,8] = Rn_VPR128.16B[0,8] >> Imm_shr_imm8:1;
+ Rd_VPR128.16B[8,8] = Rn_VPR128.16B[8,8] >> Imm_shr_imm8:1;
+ Rd_VPR128.16B[16,8] = Rn_VPR128.16B[16,8] >> Imm_shr_imm8:1;
+ Rd_VPR128.16B[24,8] = Rn_VPR128.16B[24,8] >> Imm_shr_imm8:1;
+ Rd_VPR128.16B[32,8] = Rn_VPR128.16B[32,8] >> Imm_shr_imm8:1;
+ Rd_VPR128.16B[40,8] = Rn_VPR128.16B[40,8] >> Imm_shr_imm8:1;
+ Rd_VPR128.16B[48,8] = Rn_VPR128.16B[48,8] >> Imm_shr_imm8:1;
+ Rd_VPR128.16B[56,8] = Rn_VPR128.16B[56,8] >> Imm_shr_imm8:1;
+ Rd_VPR128.16B[64,8] = Rn_VPR128.16B[64,8] >> Imm_shr_imm8:1;
+ Rd_VPR128.16B[72,8] = Rn_VPR128.16B[72,8] >> Imm_shr_imm8:1;
+ Rd_VPR128.16B[80,8] = Rn_VPR128.16B[80,8] >> Imm_shr_imm8:1;
+ Rd_VPR128.16B[88,8] = Rn_VPR128.16B[88,8] >> Imm_shr_imm8:1;
+ Rd_VPR128.16B[96,8] = Rn_VPR128.16B[96,8] >> Imm_shr_imm8:1;
+ Rd_VPR128.16B[104,8] = Rn_VPR128.16B[104,8] >> Imm_shr_imm8:1;
+ Rd_VPR128.16B[112,8] = Rn_VPR128.16B[112,8] >> Imm_shr_imm8:1;
+ Rd_VPR128.16B[120,8] = Rn_VPR128.16B[120,8] >> Imm_shr_imm8:1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00
+# CONSTRUCT x6f400400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 zext:8 =$>>@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@8
+# AUNIT --inst x6f400400/mask=xffc0fc00 --status pass
+
+:ushr Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x0 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ local tmp1:8 = zext(Imm_shr_imm64);
+ # simd infix Rd_VPR128.2D = Rn_VPR128.2D >> tmp1 on lane size 8
+ Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] >> tmp1;
+ Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] >> tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00
+# CONSTRUCT x2f200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =var:4 =$>>@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@4
+# AUNIT --inst x2f200400/mask=xffe0fc00 --status pass
+
+:ushr Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x0 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ local tmp1:4 = Imm_shr_imm32;
+ # simd infix Rd_VPR64.2S = Rn_VPR64.2S >> tmp1 on lane size 4
+ Rd_VPR64.2S[0,32] = Rn_VPR64.2S[0,32] >> tmp1;
+ Rd_VPR64.2S[32,32] = Rn_VPR64.2S[32,32] >> tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00
+# CONSTRUCT x2f100400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:2 =$>>@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@2
+# AUNIT --inst x2f100400/mask=xfff0fc00 --status pass
+
+:ushr Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x0 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ # simd infix Rd_VPR64.4H = Rn_VPR64.4H >> Imm_shr_imm16:2 on lane size 2
+ Rd_VPR64.4H[0,16] = Rn_VPR64.4H[0,16] >> Imm_shr_imm16:2;
+ Rd_VPR64.4H[16,16] = Rn_VPR64.4H[16,16] >> Imm_shr_imm16:2;
+ Rd_VPR64.4H[32,16] = Rn_VPR64.4H[32,16] >> Imm_shr_imm16:2;
+ Rd_VPR64.4H[48,16] = Rn_VPR64.4H[48,16] >> Imm_shr_imm16:2;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00
+# CONSTRUCT x6f200400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =var:4 =$>>@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@4
+# AUNIT --inst x6f200400/mask=xffe0fc00 --status pass
+
+:ushr Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x0 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ local tmp1:4 = Imm_shr_imm32;
+ # simd infix Rd_VPR128.4S = Rn_VPR128.4S >> tmp1 on lane size 4
+ Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] >> tmp1;
+ Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] >> tmp1;
+ Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] >> tmp1;
+ Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] >> tmp1;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00
+# CONSTRUCT x2f080400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:1 =$>>@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@1
+# AUNIT --inst x2f080400/mask=xfff8fc00 --status pass
+
+:ushr Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x0 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ # simd infix Rd_VPR64.8B = Rn_VPR64.8B >> Imm_shr_imm8:1 on lane size 1
+ Rd_VPR64.8B[0,8] = Rn_VPR64.8B[0,8] >> Imm_shr_imm8:1;
+ Rd_VPR64.8B[8,8] = Rn_VPR64.8B[8,8] >> Imm_shr_imm8:1;
+ Rd_VPR64.8B[16,8] = Rn_VPR64.8B[16,8] >> Imm_shr_imm8:1;
+ Rd_VPR64.8B[24,8] = Rn_VPR64.8B[24,8] >> Imm_shr_imm8:1;
+ Rd_VPR64.8B[32,8] = Rn_VPR64.8B[32,8] >> Imm_shr_imm8:1;
+ Rd_VPR64.8B[40,8] = Rn_VPR64.8B[40,8] >> Imm_shr_imm8:1;
+ Rd_VPR64.8B[48,8] = Rn_VPR64.8B[48,8] >> Imm_shr_imm8:1;
+ Rd_VPR64.8B[56,8] = Rn_VPR64.8B[56,8] >> Imm_shr_imm8:1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.392 USHR page C7-2916 line 170174 MATCH x2f000400/mask=xbf80fc00
+# CONSTRUCT x6f100400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:2 =$>>@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2@2
+# AUNIT --inst x6f100400/mask=xfff0fc00 --status pass
+
+:ushr Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x0 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ # simd infix Rd_VPR128.8H = Rn_VPR128.8H >> Imm_shr_imm16:2 on lane size 2
+ Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] >> Imm_shr_imm16:2;
+ Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] >> Imm_shr_imm16:2;
+ Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] >> Imm_shr_imm16:2;
+ Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] >> Imm_shr_imm16:2;
+ Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] >> Imm_shr_imm16:2;
+ Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] >> Imm_shr_imm16:2;
+ Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] >> Imm_shr_imm16:2;
+ Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] >> Imm_shr_imm16:2;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.392 USHR page C7-2916 line 170174 MATCH x7f000400/mask=xff80fc00
+# CONSTRUCT x7f400400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 zext:8 =>>
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 =NEON_ushr/2
+# AUNIT --inst x7f400400/mask=xffc0fc00 --status pass
+# Scalar variant when immh=1xxx
+
+:ushr Rd_FPR64, Rn_FPR64, Imm_shr_imm64
+is b_2331=0b011111110 & b_22=1 & b_1015=0b000001 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd
+{
+ local tmp1:8 = zext(Imm_shr_imm64);
+ Rd_FPR64 = Rn_FPR64 >> tmp1;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.394 USQADD page C7-2920 line 170396 MATCH x7e203800/mask=xff3ffc00
+# CONSTRUCT x7e203800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2
+# AUNIT --inst x7e203800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when size=00 Q=1 bb=1 T=FPR8
+
+:usqadd Rd_FPR8, Rn_FPR8
+is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b00 & b_1021=0b100000001110 & Rd_FPR8 & Rn_FPR8 & Zd
+{
+ Rd_FPR8 = NEON_usqadd(Rd_FPR8, Rn_FPR8);
+}
+
+# C7.2.394 USQADD page C7-2920 line 170396 MATCH x7e203800/mask=xff3ffc00
+# CONSTRUCT x7e603800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2
+# AUNIT --inst x7e603800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when size=01 Q=1 bb=1 T=FPR16
+
+:usqadd Rd_FPR16, Rn_FPR16
+is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b01 & b_1021=0b100000001110 & Rd_FPR16 & Rn_FPR16 & Zd
+{
+ Rd_FPR16 = NEON_usqadd(Rd_FPR16, Rn_FPR16);
+}
+
+# C7.2.394 USQADD page C7-2920 line 170396 MATCH x7e203800/mask=xff3ffc00
+# CONSTRUCT x7ea03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2
+# AUNIT --inst x7ea03800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when size=10 Q=1 bb=1 T=FPR32
+
+:usqadd Rd_FPR32, Rn_FPR32
+is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b10 & b_1021=0b100000001110 & Rd_FPR32 & Rn_FPR32 & Zd
+{
+ Rd_FPR32 = NEON_usqadd(Rd_FPR32, Rn_FPR32);
+}
+
+# C7.2.394 USQADD page C7-2920 line 170396 MATCH x7e203800/mask=xff3ffc00
+# CONSTRUCT x7ee03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2
+# AUNIT --inst x7ee03800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Scalar variant when size=11 Q=1 bb=1 T=FPR64
+
+:usqadd Rd_FPR64, Rn_FPR64
+is b_31=0 & b_30=1 & b_2429=0b111110 & b_2223=0b11 & b_1021=0b100000001110 & Rd_FPR64 & Rn_FPR64 & Zd
+{
+ Rd_FPR64 = NEON_usqadd(Rd_FPR64, Rn_FPR64);
+}
+
+# C7.2.394 USQADD page C7-2920 line 170396 MATCH x2e203800/mask=xbf3ffc00
+# CONSTRUCT x2e203800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@1
+# AUNIT --inst x2e203800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Vector variant when size=00 Q=0 bb=0 e=1 T=VPR64.8B
+
+:usqadd Rd_VPR64.8B, Rn_VPR64.8B
+is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000001110 & Rd_VPR64.8B & Rn_VPR64.8B & Zd
+{
+ Rd_VPR64.8B = NEON_usqadd(Rd_VPR64.8B, Rn_VPR64.8B, 1:1);
+}
+
+# C7.2.394 USQADD page C7-2920 line 170396 MATCH x2e203800/mask=xbf3ffc00
+# CONSTRUCT x6e203800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@1
+# AUNIT --inst x6e203800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Vector variant when size=00 Q=1 bb=0 e=1 T=VPR128.16B
+
+:usqadd Rd_VPR128.16B, Rn_VPR128.16B
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b00 & b_1021=0b100000001110 & Rd_VPR128.16B & Rn_VPR128.16B & Zd
+{
+ Rd_VPR128.16B = NEON_usqadd(Rd_VPR128.16B, Rn_VPR128.16B, 1:1);
+}
+
+# C7.2.394 USQADD page C7-2920 line 170396 MATCH x2e203800/mask=xbf3ffc00
+# CONSTRUCT x2e603800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@2
+# AUNIT --inst x2e603800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Vector variant when size=01 Q=0 bb=0 e=2 T=VPR64.4H
+
+:usqadd Rd_VPR64.4H, Rn_VPR64.4H
+is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000001110 & Rd_VPR64.4H & Rn_VPR64.4H & Zd
+{
+ Rd_VPR64.4H = NEON_usqadd(Rd_VPR64.4H, Rn_VPR64.4H, 2:1);
+}
+
+# C7.2.394 USQADD page C7-2920 line 170396 MATCH x2e203800/mask=xbf3ffc00
+# CONSTRUCT x6e603800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@2
+# AUNIT --inst x6e603800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Vector variant when size=01 Q=1 bb=0 e=2 T=VPR128.8H
+
+:usqadd Rd_VPR128.8H, Rn_VPR128.8H
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b01 & b_1021=0b100000001110 & Rd_VPR128.8H & Rn_VPR128.8H & Zd
+{
+ Rd_VPR128.8H = NEON_usqadd(Rd_VPR128.8H, Rn_VPR128.8H, 2:1);
+}
+
+# C7.2.394 USQADD page C7-2920 line 170396 MATCH x2e203800/mask=xbf3ffc00
+# CONSTRUCT x2ea03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@4
+# AUNIT --inst x2ea03800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Vector variant when size=10 Q=0 bb=0 e=4 T=VPR64.2S
+
+:usqadd Rd_VPR64.2S, Rn_VPR64.2S
+is b_31=0 & b_30=0 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000001110 & Rd_VPR64.2S & Rn_VPR64.2S & Zd
+{
+ Rd_VPR64.2S = NEON_usqadd(Rd_VPR64.2S, Rn_VPR64.2S, 4:1);
+}
+
+# C7.2.394 USQADD page C7-2920 line 170396 MATCH x2e203800/mask=xbf3ffc00
+# CONSTRUCT x6ea03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@4
+# AUNIT --inst x6ea03800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Vector variant when size=10 Q=1 bb=0 e=4 T=VPR128.4S
+
+:usqadd Rd_VPR128.4S, Rn_VPR128.4S
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b10 & b_1021=0b100000001110 & Rd_VPR128.4S & Rn_VPR128.4S & Zd
+{
+ Rd_VPR128.4S = NEON_usqadd(Rd_VPR128.4S, Rn_VPR128.4S, 4:1);
+}
+
+# C7.2.394 USQADD page C7-2920 line 170396 MATCH x2e203800/mask=xbf3ffc00
+# CONSTRUCT x6ee03800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_usqadd/2@8
+# AUNIT --inst x6ee03800/mask=xfffffc00 --status nopcodeop --comment "nointsat"
+# Vector variant when size=11 Q=1 bb=0 e=8 T=VPR128.2D
+
+:usqadd Rd_VPR128.2D, Rn_VPR128.2D
+is b_31=0 & b_30=1 & b_2429=0b101110 & b_2223=0b11 & b_1021=0b100000001110 & Rd_VPR128.2D & Rn_VPR128.2D & Zd
+{
+ Rd_VPR128.2D = NEON_usqadd(Rd_VPR128.2D, Rn_VPR128.2D, 8:1);
+}
+
+# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00
+# CONSTRUCT x6f081400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:1 $>>@1 &=$+@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@1
+# AUNIT --inst x6f081400/mask=xfff8fc00 --status pass
+
+:usra Rd_VPR128.16B, Rn_VPR128.16B, Imm_shr_imm8
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x2 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.16B >> Imm_shr_imm8:1 on lane size 1
+ TMPQ1[0,8] = Rn_VPR128.16B[0,8] >> Imm_shr_imm8:1;
+ TMPQ1[8,8] = Rn_VPR128.16B[8,8] >> Imm_shr_imm8:1;
+ TMPQ1[16,8] = Rn_VPR128.16B[16,8] >> Imm_shr_imm8:1;
+ TMPQ1[24,8] = Rn_VPR128.16B[24,8] >> Imm_shr_imm8:1;
+ TMPQ1[32,8] = Rn_VPR128.16B[32,8] >> Imm_shr_imm8:1;
+ TMPQ1[40,8] = Rn_VPR128.16B[40,8] >> Imm_shr_imm8:1;
+ TMPQ1[48,8] = Rn_VPR128.16B[48,8] >> Imm_shr_imm8:1;
+ TMPQ1[56,8] = Rn_VPR128.16B[56,8] >> Imm_shr_imm8:1;
+ TMPQ1[64,8] = Rn_VPR128.16B[64,8] >> Imm_shr_imm8:1;
+ TMPQ1[72,8] = Rn_VPR128.16B[72,8] >> Imm_shr_imm8:1;
+ TMPQ1[80,8] = Rn_VPR128.16B[80,8] >> Imm_shr_imm8:1;
+ TMPQ1[88,8] = Rn_VPR128.16B[88,8] >> Imm_shr_imm8:1;
+ TMPQ1[96,8] = Rn_VPR128.16B[96,8] >> Imm_shr_imm8:1;
+ TMPQ1[104,8] = Rn_VPR128.16B[104,8] >> Imm_shr_imm8:1;
+ TMPQ1[112,8] = Rn_VPR128.16B[112,8] >> Imm_shr_imm8:1;
+ TMPQ1[120,8] = Rn_VPR128.16B[120,8] >> Imm_shr_imm8:1;
+ # simd infix Rd_VPR128.16B = Rd_VPR128.16B + TMPQ1 on lane size 1
+ Rd_VPR128.16B[0,8] = Rd_VPR128.16B[0,8] + TMPQ1[0,8];
+ Rd_VPR128.16B[8,8] = Rd_VPR128.16B[8,8] + TMPQ1[8,8];
+ Rd_VPR128.16B[16,8] = Rd_VPR128.16B[16,8] + TMPQ1[16,8];
+ Rd_VPR128.16B[24,8] = Rd_VPR128.16B[24,8] + TMPQ1[24,8];
+ Rd_VPR128.16B[32,8] = Rd_VPR128.16B[32,8] + TMPQ1[32,8];
+ Rd_VPR128.16B[40,8] = Rd_VPR128.16B[40,8] + TMPQ1[40,8];
+ Rd_VPR128.16B[48,8] = Rd_VPR128.16B[48,8] + TMPQ1[48,8];
+ Rd_VPR128.16B[56,8] = Rd_VPR128.16B[56,8] + TMPQ1[56,8];
+ Rd_VPR128.16B[64,8] = Rd_VPR128.16B[64,8] + TMPQ1[64,8];
+ Rd_VPR128.16B[72,8] = Rd_VPR128.16B[72,8] + TMPQ1[72,8];
+ Rd_VPR128.16B[80,8] = Rd_VPR128.16B[80,8] + TMPQ1[80,8];
+ Rd_VPR128.16B[88,8] = Rd_VPR128.16B[88,8] + TMPQ1[88,8];
+ Rd_VPR128.16B[96,8] = Rd_VPR128.16B[96,8] + TMPQ1[96,8];
+ Rd_VPR128.16B[104,8] = Rd_VPR128.16B[104,8] + TMPQ1[104,8];
+ Rd_VPR128.16B[112,8] = Rd_VPR128.16B[112,8] + TMPQ1[112,8];
+ Rd_VPR128.16B[120,8] = Rd_VPR128.16B[120,8] + TMPQ1[120,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00
+# CONSTRUCT x6f401400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 zext:8 $>>@8 &=$+@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@8
+# AUNIT --inst x6f401400/mask=xffc0fc00 --status pass
+
+:usra Rd_VPR128.2D, Rn_VPR128.2D, Imm_shr_imm64
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2223=0b01 & Imm_shr_imm64 & b_1115=0x2 & b_1010=1 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ local tmp1:8 = zext(Imm_shr_imm64);
+ # simd infix TMPQ1 = Rn_VPR128.2D >> tmp1 on lane size 8
+ TMPQ1[0,64] = Rn_VPR128.2D[0,64] >> tmp1;
+ TMPQ1[64,64] = Rn_VPR128.2D[64,64] >> tmp1;
+ # simd infix Rd_VPR128.2D = Rd_VPR128.2D + TMPQ1 on lane size 8
+ Rd_VPR128.2D[0,64] = Rd_VPR128.2D[0,64] + TMPQ1[0,64];
+ Rd_VPR128.2D[64,64] = Rd_VPR128.2D[64,64] + TMPQ1[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00
+# CONSTRUCT x2f201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =var:4 $>>@4 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@4
+# AUNIT --inst x2f201400/mask=xffe0fc00 --status pass
+
+:usra Rd_VPR64.2S, Rn_VPR64.2S, Imm_shr_imm32
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x2 & b_1010=1 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ local tmp1:4 = Imm_shr_imm32;
+ # simd infix TMPD1 = Rn_VPR64.2S >> tmp1 on lane size 4
+ TMPD1[0,32] = Rn_VPR64.2S[0,32] >> tmp1;
+ TMPD1[32,32] = Rn_VPR64.2S[32,32] >> tmp1;
+ # simd infix Rd_VPR64.2S = Rd_VPR64.2S + TMPD1 on lane size 4
+ Rd_VPR64.2S[0,32] = Rd_VPR64.2S[0,32] + TMPD1[0,32];
+ Rd_VPR64.2S[32,32] = Rd_VPR64.2S[32,32] + TMPD1[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00
+# CONSTRUCT x2f101400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:2 $>>@2 &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@2
+# AUNIT --inst x2f101400/mask=xfff0fc00 --status pass
+
+:usra Rd_VPR64.4H, Rn_VPR64.4H, Imm_shr_imm16
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x2 & b_1010=1 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ # simd infix TMPD1 = Rn_VPR64.4H >> Imm_shr_imm16:2 on lane size 2
+ TMPD1[0,16] = Rn_VPR64.4H[0,16] >> Imm_shr_imm16:2;
+ TMPD1[16,16] = Rn_VPR64.4H[16,16] >> Imm_shr_imm16:2;
+ TMPD1[32,16] = Rn_VPR64.4H[32,16] >> Imm_shr_imm16:2;
+ TMPD1[48,16] = Rn_VPR64.4H[48,16] >> Imm_shr_imm16:2;
+ # simd infix Rd_VPR64.4H = Rd_VPR64.4H + TMPD1 on lane size 2
+ Rd_VPR64.4H[0,16] = Rd_VPR64.4H[0,16] + TMPD1[0,16];
+ Rd_VPR64.4H[16,16] = Rd_VPR64.4H[16,16] + TMPD1[16,16];
+ Rd_VPR64.4H[32,16] = Rd_VPR64.4H[32,16] + TMPD1[32,16];
+ Rd_VPR64.4H[48,16] = Rd_VPR64.4H[48,16] + TMPD1[48,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00
+# CONSTRUCT x6f201400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 =var:4 $>>@4 &=$+@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@4
+# AUNIT --inst x6f201400/mask=xffe0fc00 --status pass
+
+:usra Rd_VPR128.4S, Rn_VPR128.4S, Imm_shr_imm32
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_shr_imm32 & b_1115=0x2 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ local tmp1:4 = Imm_shr_imm32;
+ # simd infix TMPQ1 = Rn_VPR128.4S >> tmp1 on lane size 4
+ TMPQ1[0,32] = Rn_VPR128.4S[0,32] >> tmp1;
+ TMPQ1[32,32] = Rn_VPR128.4S[32,32] >> tmp1;
+ TMPQ1[64,32] = Rn_VPR128.4S[64,32] >> tmp1;
+ TMPQ1[96,32] = Rn_VPR128.4S[96,32] >> tmp1;
+ # simd infix Rd_VPR128.4S = Rd_VPR128.4S + TMPQ1 on lane size 4
+ Rd_VPR128.4S[0,32] = Rd_VPR128.4S[0,32] + TMPQ1[0,32];
+ Rd_VPR128.4S[32,32] = Rd_VPR128.4S[32,32] + TMPQ1[32,32];
+ Rd_VPR128.4S[64,32] = Rd_VPR128.4S[64,32] + TMPQ1[64,32];
+ Rd_VPR128.4S[96,32] = Rd_VPR128.4S[96,32] + TMPQ1[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00
+# CONSTRUCT x2f081400/mask=xfff8fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:1 $>>@1 &=$+@1
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@1
+# AUNIT --inst x2f081400/mask=xfff8fc00 --status pass
+
+:usra Rd_VPR64.8B, Rn_VPR64.8B, Imm_shr_imm8
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_shr_imm8 & b_1115=0x2 & b_1010=1 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ # simd infix TMPD1 = Rn_VPR64.8B >> Imm_shr_imm8:1 on lane size 1
+ TMPD1[0,8] = Rn_VPR64.8B[0,8] >> Imm_shr_imm8:1;
+ TMPD1[8,8] = Rn_VPR64.8B[8,8] >> Imm_shr_imm8:1;
+ TMPD1[16,8] = Rn_VPR64.8B[16,8] >> Imm_shr_imm8:1;
+ TMPD1[24,8] = Rn_VPR64.8B[24,8] >> Imm_shr_imm8:1;
+ TMPD1[32,8] = Rn_VPR64.8B[32,8] >> Imm_shr_imm8:1;
+ TMPD1[40,8] = Rn_VPR64.8B[40,8] >> Imm_shr_imm8:1;
+ TMPD1[48,8] = Rn_VPR64.8B[48,8] >> Imm_shr_imm8:1;
+ TMPD1[56,8] = Rn_VPR64.8B[56,8] >> Imm_shr_imm8:1;
+ # simd infix Rd_VPR64.8B = Rd_VPR64.8B + TMPD1 on lane size 1
+ Rd_VPR64.8B[0,8] = Rd_VPR64.8B[0,8] + TMPD1[0,8];
+ Rd_VPR64.8B[8,8] = Rd_VPR64.8B[8,8] + TMPD1[8,8];
+ Rd_VPR64.8B[16,8] = Rd_VPR64.8B[16,8] + TMPD1[16,8];
+ Rd_VPR64.8B[24,8] = Rd_VPR64.8B[24,8] + TMPD1[24,8];
+ Rd_VPR64.8B[32,8] = Rd_VPR64.8B[32,8] + TMPD1[32,8];
+ Rd_VPR64.8B[40,8] = Rd_VPR64.8B[40,8] + TMPD1[40,8];
+ Rd_VPR64.8B[48,8] = Rd_VPR64.8B[48,8] + TMPD1[48,8];
+ Rd_VPR64.8B[56,8] = Rd_VPR64.8B[56,8] + TMPD1[56,8];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.395 USRA page C7-2922 line 170519 MATCH x2f001400/mask=xbf80fc00
+# CONSTRUCT x6f101400/mask=xfff0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3:2 $>>@2 &=$+@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3@2
+# AUNIT --inst x6f101400/mask=xfff0fc00 --status pass
+
+:usra Rd_VPR128.8H, Rn_VPR128.8H, Imm_shr_imm16
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_shr_imm16 & b_1115=0x2 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.8H >> Imm_shr_imm16:2 on lane size 2
+ TMPQ1[0,16] = Rn_VPR128.8H[0,16] >> Imm_shr_imm16:2;
+ TMPQ1[16,16] = Rn_VPR128.8H[16,16] >> Imm_shr_imm16:2;
+ TMPQ1[32,16] = Rn_VPR128.8H[32,16] >> Imm_shr_imm16:2;
+ TMPQ1[48,16] = Rn_VPR128.8H[48,16] >> Imm_shr_imm16:2;
+ TMPQ1[64,16] = Rn_VPR128.8H[64,16] >> Imm_shr_imm16:2;
+ TMPQ1[80,16] = Rn_VPR128.8H[80,16] >> Imm_shr_imm16:2;
+ TMPQ1[96,16] = Rn_VPR128.8H[96,16] >> Imm_shr_imm16:2;
+ TMPQ1[112,16] = Rn_VPR128.8H[112,16] >> Imm_shr_imm16:2;
+ # simd infix Rd_VPR128.8H = Rd_VPR128.8H + TMPQ1 on lane size 2
+ Rd_VPR128.8H[0,16] = Rd_VPR128.8H[0,16] + TMPQ1[0,16];
+ Rd_VPR128.8H[16,16] = Rd_VPR128.8H[16,16] + TMPQ1[16,16];
+ Rd_VPR128.8H[32,16] = Rd_VPR128.8H[32,16] + TMPQ1[32,16];
+ Rd_VPR128.8H[48,16] = Rd_VPR128.8H[48,16] + TMPQ1[48,16];
+ Rd_VPR128.8H[64,16] = Rd_VPR128.8H[64,16] + TMPQ1[64,16];
+ Rd_VPR128.8H[80,16] = Rd_VPR128.8H[80,16] + TMPQ1[80,16];
+ Rd_VPR128.8H[96,16] = Rd_VPR128.8H[96,16] + TMPQ1[96,16];
+ Rd_VPR128.8H[112,16] = Rd_VPR128.8H[112,16] + TMPQ1[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.395 USRA page C7-2922 line 170519 MATCH x7f001400/mask=xff80fc00
+# CONSTRUCT x7f401400/mask=xffc0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 zext:8 >> &=+
+# SMACRO(pseudo) ARG1 ARG2 ARG3:1 &=NEON_usra/3
+# AUNIT --inst x7f401400/mask=xffc0fc00 --status pass
+# Scalar variant when immh=1xxx
+
+:usra Rd_FPR64, Rn_FPR64, Imm_shr_imm64
+is b_2331=0b011111110 & b_22=1 & b_1015=0b000101 & Rd_FPR64 & Rn_FPR64 & Imm_shr_imm64 & Zd
+{
+ local tmp1:8 = zext(Imm_shr_imm64);
+ local tmp2:8 = Rn_FPR64 >> tmp1;
+ Rd_FPR64 = Rd_FPR64 + tmp2;
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.396 USUBL, USUBL2 page C7-2925 line 170683 MATCH x2e202000/mask=xbf20fc00
+# CONSTRUCT x6ea02000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@4:16 ARG3[1]:8 $zext@4:16 =$-@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubl2/2@4
+# AUNIT --inst x6ea02000/mask=xffe0fc00 --status pass --comment "ext"
+
+:usubl2 Rd_VPR128.2D, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x2 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = zext(TMPD1[0,32]);
+ TMPQ2[64,64] = zext(TMPD1[32,32]);
+ TMPD3 = Rm_VPR128.4S[64,64];
+ # simd resize TMPQ4 = zext(TMPD3) (lane size 4 to 8)
+ TMPQ4[0,64] = zext(TMPD3[0,32]);
+ TMPQ4[64,64] = zext(TMPD3[32,32]);
+ # simd infix Rd_VPR128.2D = TMPQ2 - TMPQ4 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ2[0,64] - TMPQ4[0,64];
+ Rd_VPR128.2D[64,64] = TMPQ2[64,64] - TMPQ4[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.396 USUBL, USUBL2 page C7-2925 line 170683 MATCH x2e202000/mask=xbf20fc00
+# CONSTRUCT x6e602000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@2:16 ARG3[1]:8 $zext@2:16 =$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubl2/2@2
+# AUNIT --inst x6e602000/mask=xffe0fc00 --status pass --comment "ext"
+
+:usubl2 Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x2 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = zext(TMPD1[0,16]);
+ TMPQ2[32,32] = zext(TMPD1[16,16]);
+ TMPQ2[64,32] = zext(TMPD1[32,16]);
+ TMPQ2[96,32] = zext(TMPD1[48,16]);
+ TMPD3 = Rm_VPR128.8H[64,64];
+ # simd resize TMPQ4 = zext(TMPD3) (lane size 2 to 4)
+ TMPQ4[0,32] = zext(TMPD3[0,16]);
+ TMPQ4[32,32] = zext(TMPD3[16,16]);
+ TMPQ4[64,32] = zext(TMPD3[32,16]);
+ TMPQ4[96,32] = zext(TMPD3[48,16]);
+ # simd infix Rd_VPR128.4S = TMPQ2 - TMPQ4 on lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ2[0,32] - TMPQ4[0,32];
+ Rd_VPR128.4S[32,32] = TMPQ2[32,32] - TMPQ4[32,32];
+ Rd_VPR128.4S[64,32] = TMPQ2[64,32] - TMPQ4[64,32];
+ Rd_VPR128.4S[96,32] = TMPQ2[96,32] - TMPQ4[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.396 USUBL, USUBL2 page C7-2925 line 170683 MATCH x2e202000/mask=xbf20fc00
+# CONSTRUCT x6e202000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 $zext@1:16 ARG3[1]:8 $zext@1:16 =$-@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubl2/2@1
+# AUNIT --inst x6e202000/mask=xffe0fc00 --status pass --comment "ext"
+
+:usubl2 Rd_VPR128.8H, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x2 & b_1011=0 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
+{
+ TMPD1 = Rn_VPR128.16B[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)
+ TMPQ2[0,16] = zext(TMPD1[0,8]);
+ TMPQ2[16,16] = zext(TMPD1[8,8]);
+ TMPQ2[32,16] = zext(TMPD1[16,8]);
+ TMPQ2[48,16] = zext(TMPD1[24,8]);
+ TMPQ2[64,16] = zext(TMPD1[32,8]);
+ TMPQ2[80,16] = zext(TMPD1[40,8]);
+ TMPQ2[96,16] = zext(TMPD1[48,8]);
+ TMPQ2[112,16] = zext(TMPD1[56,8]);
+ TMPD3 = Rm_VPR128.16B[64,64];
+ # simd resize TMPQ4 = zext(TMPD3) (lane size 1 to 2)
+ TMPQ4[0,16] = zext(TMPD3[0,8]);
+ TMPQ4[16,16] = zext(TMPD3[8,8]);
+ TMPQ4[32,16] = zext(TMPD3[16,8]);
+ TMPQ4[48,16] = zext(TMPD3[24,8]);
+ TMPQ4[64,16] = zext(TMPD3[32,8]);
+ TMPQ4[80,16] = zext(TMPD3[40,8]);
+ TMPQ4[96,16] = zext(TMPD3[48,8]);
+ TMPQ4[112,16] = zext(TMPD3[56,8]);
+ # simd infix Rd_VPR128.8H = TMPQ2 - TMPQ4 on lane size 2
+ Rd_VPR128.8H[0,16] = TMPQ2[0,16] - TMPQ4[0,16];
+ Rd_VPR128.8H[16,16] = TMPQ2[16,16] - TMPQ4[16,16];
+ Rd_VPR128.8H[32,16] = TMPQ2[32,16] - TMPQ4[32,16];
+ Rd_VPR128.8H[48,16] = TMPQ2[48,16] - TMPQ4[48,16];
+ Rd_VPR128.8H[64,16] = TMPQ2[64,16] - TMPQ4[64,16];
+ Rd_VPR128.8H[80,16] = TMPQ2[80,16] - TMPQ4[80,16];
+ Rd_VPR128.8H[96,16] = TMPQ2[96,16] - TMPQ4[96,16];
+ Rd_VPR128.8H[112,16] = TMPQ2[112,16] - TMPQ4[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.396 USUBL, USUBL2 page C7-2925 line 170683 MATCH x2e202000/mask=xbf20fc00
+# CONSTRUCT x2ea02000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@4:16 ARG3 $zext@4:16 =$-@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubl/2@4
+# AUNIT --inst x2ea02000/mask=xffe0fc00 --status pass --comment "ext"
+
+:usubl Rd_VPR128.2D, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x2 & b_1011=0 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = zext(Rn_VPR64.2S[0,32]);
+ TMPQ1[64,64] = zext(Rn_VPR64.2S[32,32]);
+ # simd resize TMPQ2 = zext(Rm_VPR64.2S) (lane size 4 to 8)
+ TMPQ2[0,64] = zext(Rm_VPR64.2S[0,32]);
+ TMPQ2[64,64] = zext(Rm_VPR64.2S[32,32]);
+ # simd infix Rd_VPR128.2D = TMPQ1 - TMPQ2 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ1[0,64] - TMPQ2[0,64];
+ Rd_VPR128.2D[64,64] = TMPQ1[64,64] - TMPQ2[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.396 USUBL, USUBL2 page C7-2925 line 170683 MATCH x2e202000/mask=xbf20fc00
+# CONSTRUCT x2e602000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@2:16 ARG3 $zext@2:16 =$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubl/2@2
+# AUNIT --inst x2e602000/mask=xffe0fc00 --status pass --comment "ext"
+
+:usubl Rd_VPR128.4S, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x2 & b_1011=0 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = zext(Rn_VPR64.4H[0,16]);
+ TMPQ1[32,32] = zext(Rn_VPR64.4H[16,16]);
+ TMPQ1[64,32] = zext(Rn_VPR64.4H[32,16]);
+ TMPQ1[96,32] = zext(Rn_VPR64.4H[48,16]);
+ # simd resize TMPQ2 = zext(Rm_VPR64.4H) (lane size 2 to 4)
+ TMPQ2[0,32] = zext(Rm_VPR64.4H[0,16]);
+ TMPQ2[32,32] = zext(Rm_VPR64.4H[16,16]);
+ TMPQ2[64,32] = zext(Rm_VPR64.4H[32,16]);
+ TMPQ2[96,32] = zext(Rm_VPR64.4H[48,16]);
+ # simd infix Rd_VPR128.4S = TMPQ1 - TMPQ2 on lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ1[0,32] - TMPQ2[0,32];
+ Rd_VPR128.4S[32,32] = TMPQ1[32,32] - TMPQ2[32,32];
+ Rd_VPR128.4S[64,32] = TMPQ1[64,32] - TMPQ2[64,32];
+ Rd_VPR128.4S[96,32] = TMPQ1[96,32] - TMPQ2[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.396 USUBL, USUBL2 page C7-2925 line 170683 MATCH x2e202000/mask=xbf20fc00
+# CONSTRUCT x2e202000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@1:16 ARG3 $zext@1:16 =$-@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubl/2@1
+# AUNIT --inst x2e202000/mask=xffe0fc00 --status pass --comment "ext"
+
+:usubl Rd_VPR128.8H, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x2 & b_1011=0 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
+{
+ # simd resize TMPQ1 = zext(Rn_VPR64.8B) (lane size 1 to 2)
+ TMPQ1[0,16] = zext(Rn_VPR64.8B[0,8]);
+ TMPQ1[16,16] = zext(Rn_VPR64.8B[8,8]);
+ TMPQ1[32,16] = zext(Rn_VPR64.8B[16,8]);
+ TMPQ1[48,16] = zext(Rn_VPR64.8B[24,8]);
+ TMPQ1[64,16] = zext(Rn_VPR64.8B[32,8]);
+ TMPQ1[80,16] = zext(Rn_VPR64.8B[40,8]);
+ TMPQ1[96,16] = zext(Rn_VPR64.8B[48,8]);
+ TMPQ1[112,16] = zext(Rn_VPR64.8B[56,8]);
+ # simd resize TMPQ2 = zext(Rm_VPR64.8B) (lane size 1 to 2)
+ TMPQ2[0,16] = zext(Rm_VPR64.8B[0,8]);
+ TMPQ2[16,16] = zext(Rm_VPR64.8B[8,8]);
+ TMPQ2[32,16] = zext(Rm_VPR64.8B[16,8]);
+ TMPQ2[48,16] = zext(Rm_VPR64.8B[24,8]);
+ TMPQ2[64,16] = zext(Rm_VPR64.8B[32,8]);
+ TMPQ2[80,16] = zext(Rm_VPR64.8B[40,8]);
+ TMPQ2[96,16] = zext(Rm_VPR64.8B[48,8]);
+ TMPQ2[112,16] = zext(Rm_VPR64.8B[56,8]);
+ # simd infix Rd_VPR128.8H = TMPQ1 - TMPQ2 on lane size 2
+ Rd_VPR128.8H[0,16] = TMPQ1[0,16] - TMPQ2[0,16];
+ Rd_VPR128.8H[16,16] = TMPQ1[16,16] - TMPQ2[16,16];
+ Rd_VPR128.8H[32,16] = TMPQ1[32,16] - TMPQ2[32,16];
+ Rd_VPR128.8H[48,16] = TMPQ1[48,16] - TMPQ2[48,16];
+ Rd_VPR128.8H[64,16] = TMPQ1[64,16] - TMPQ2[64,16];
+ Rd_VPR128.8H[80,16] = TMPQ1[80,16] - TMPQ2[80,16];
+ Rd_VPR128.8H[96,16] = TMPQ1[96,16] - TMPQ2[96,16];
+ Rd_VPR128.8H[112,16] = TMPQ1[112,16] - TMPQ2[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.397 USUBW, USUBW2 page C7-2927 line 170806 MATCH x2e203000/mask=xbf20fc00
+# CONSTRUCT x6ea03000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3[1]:8 $zext@4:16 =$-@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubw2/2@4
+# AUNIT --inst x6ea03000/mask=xffe0fc00 --status pass --comment "ext"
+
+:usubw2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S & b_1215=0x3 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rm_VPR128.4S[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 4 to 8)
+ TMPQ2[0,64] = zext(TMPD1[0,32]);
+ TMPQ2[64,64] = zext(TMPD1[32,32]);
+ # simd infix Rd_VPR128.2D = Rn_VPR128.2D - TMPQ2 on lane size 8
+ Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] - TMPQ2[0,64];
+ Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] - TMPQ2[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.397 USUBW, USUBW2 page C7-2927 line 170806 MATCH x2e203000/mask=xbf20fc00
+# CONSTRUCT x6e603000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3[1]:8 $zext@2:16 =$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubw2/2@2
+# AUNIT --inst x6e603000/mask=xffe0fc00 --status pass --comment "ext"
+
+:usubw2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR128.8H & b_1215=0x3 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rm_VPR128.8H[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 2 to 4)
+ TMPQ2[0,32] = zext(TMPD1[0,16]);
+ TMPQ2[32,32] = zext(TMPD1[16,16]);
+ TMPQ2[64,32] = zext(TMPD1[32,16]);
+ TMPQ2[96,32] = zext(TMPD1[48,16]);
+ # simd infix Rd_VPR128.4S = Rn_VPR128.4S - TMPQ2 on lane size 4
+ Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] - TMPQ2[0,32];
+ Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] - TMPQ2[32,32];
+ Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] - TMPQ2[64,32];
+ Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] - TMPQ2[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.397 USUBW, USUBW2 page C7-2927 line 170806 MATCH x2e203000/mask=xbf20fc00
+# CONSTRUCT x6e203000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3[1]:8 $zext@1:16 =$-@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubw2/2@1
+# AUNIT --inst x6e203000/mask=xffe0fc00 --status pass --comment "ext"
+
+:usubw2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16B & b_1215=0x3 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ TMPD1 = Rm_VPR128.16B[64,64];
+ # simd resize TMPQ2 = zext(TMPD1) (lane size 1 to 2)
+ TMPQ2[0,16] = zext(TMPD1[0,8]);
+ TMPQ2[16,16] = zext(TMPD1[8,8]);
+ TMPQ2[32,16] = zext(TMPD1[16,8]);
+ TMPQ2[48,16] = zext(TMPD1[24,8]);
+ TMPQ2[64,16] = zext(TMPD1[32,8]);
+ TMPQ2[80,16] = zext(TMPD1[40,8]);
+ TMPQ2[96,16] = zext(TMPD1[48,8]);
+ TMPQ2[112,16] = zext(TMPD1[56,8]);
+ # simd infix Rd_VPR128.8H = Rn_VPR128.8H - TMPQ2 on lane size 2
+ Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] - TMPQ2[0,16];
+ Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] - TMPQ2[16,16];
+ Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] - TMPQ2[32,16];
+ Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] - TMPQ2[48,16];
+ Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] - TMPQ2[64,16];
+ Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] - TMPQ2[80,16];
+ Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] - TMPQ2[96,16];
+ Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] - TMPQ2[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.397 USUBW, USUBW2 page C7-2927 line 170806 MATCH x2e203000/mask=xbf20fc00
+# CONSTRUCT x2ea03000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $zext@4:16 =$-@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubw/2@4
+# AUNIT --inst x2ea03000/mask=xffe0fc00 --status pass --comment "ext"
+
+:usubw Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S & b_1215=0x3 & b_1011=0 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ # simd resize TMPQ1 = zext(Rm_VPR64.2S) (lane size 4 to 8)
+ TMPQ1[0,64] = zext(Rm_VPR64.2S[0,32]);
+ TMPQ1[64,64] = zext(Rm_VPR64.2S[32,32]);
+ # simd infix Rd_VPR128.2D = Rn_VPR128.2D - TMPQ1 on lane size 8
+ Rd_VPR128.2D[0,64] = Rn_VPR128.2D[0,64] - TMPQ1[0,64];
+ Rd_VPR128.2D[64,64] = Rn_VPR128.2D[64,64] - TMPQ1[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.397 USUBW, USUBW2 page C7-2927 line 170806 MATCH x2e203000/mask=xbf20fc00
+# CONSTRUCT x2e603000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $zext@2:16 =$-@4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubw/2@2
+# AUNIT --inst x2e603000/mask=xffe0fc00 --status pass --comment "ext"
+
+:usubw Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=1 & b_2121=1 & Rm_VPR64.4H & b_1215=0x3 & b_1011=0 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPQ1 = zext(Rm_VPR64.4H) (lane size 2 to 4)
+ TMPQ1[0,32] = zext(Rm_VPR64.4H[0,16]);
+ TMPQ1[32,32] = zext(Rm_VPR64.4H[16,16]);
+ TMPQ1[64,32] = zext(Rm_VPR64.4H[32,16]);
+ TMPQ1[96,32] = zext(Rm_VPR64.4H[48,16]);
+ # simd infix Rd_VPR128.4S = Rn_VPR128.4S - TMPQ1 on lane size 4
+ Rd_VPR128.4S[0,32] = Rn_VPR128.4S[0,32] - TMPQ1[0,32];
+ Rd_VPR128.4S[32,32] = Rn_VPR128.4S[32,32] - TMPQ1[32,32];
+ Rd_VPR128.4S[64,32] = Rn_VPR128.4S[64,32] - TMPQ1[64,32];
+ Rd_VPR128.4S[96,32] = Rn_VPR128.4S[96,32] - TMPQ1[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.397 USUBW, USUBW2 page C7-2927 line 170806 MATCH x2e203000/mask=xbf20fc00
+# CONSTRUCT x2e203000/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $zext@1:16 =$-@2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_usubw/2@1
+# AUNIT --inst x2e203000/mask=xffe0fc00 --status pass --comment "ext"
+
+:usubw Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR64.8B & b_1215=0x3 & b_1011=0 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ # simd resize TMPQ1 = zext(Rm_VPR64.8B) (lane size 1 to 2)
+ TMPQ1[0,16] = zext(Rm_VPR64.8B[0,8]);
+ TMPQ1[16,16] = zext(Rm_VPR64.8B[8,8]);
+ TMPQ1[32,16] = zext(Rm_VPR64.8B[16,8]);
+ TMPQ1[48,16] = zext(Rm_VPR64.8B[24,8]);
+ TMPQ1[64,16] = zext(Rm_VPR64.8B[32,8]);
+ TMPQ1[80,16] = zext(Rm_VPR64.8B[40,8]);
+ TMPQ1[96,16] = zext(Rm_VPR64.8B[48,8]);
+ TMPQ1[112,16] = zext(Rm_VPR64.8B[56,8]);
+ # simd infix Rd_VPR128.8H = Rn_VPR128.8H - TMPQ1 on lane size 2
+ Rd_VPR128.8H[0,16] = Rn_VPR128.8H[0,16] - TMPQ1[0,16];
+ Rd_VPR128.8H[16,16] = Rn_VPR128.8H[16,16] - TMPQ1[16,16];
+ Rd_VPR128.8H[32,16] = Rn_VPR128.8H[32,16] - TMPQ1[32,16];
+ Rd_VPR128.8H[48,16] = Rn_VPR128.8H[48,16] - TMPQ1[48,16];
+ Rd_VPR128.8H[64,16] = Rn_VPR128.8H[64,16] - TMPQ1[64,16];
+ Rd_VPR128.8H[80,16] = Rn_VPR128.8H[80,16] - TMPQ1[80,16];
+ Rd_VPR128.8H[96,16] = Rn_VPR128.8H[96,16] - TMPQ1[96,16];
+ Rd_VPR128.8H[112,16] = Rn_VPR128.8H[112,16] - TMPQ1[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00
+# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00
+# CONSTRUCT x6f08a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 =$zext@1:16
+# SMACRO(pseudo) ARG1 ARG2 =NEON_uxtl2/1@1
+# AUNIT --inst x6f08a400/mask=xfffffc00 --status pass --comment "ext"
+
+:uxtl2 Rd_VPR128.8H, Rn_VPR128.16B
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3=0 & b_1115=0x14 & b_1010=1 & Rn_VPR128.16B & Rd_VPR128.8H & Zd
+{
+ TMPD1 = Rn_VPR128.16B[64,64];
+ # simd resize Rd_VPR128.8H = zext(TMPD1) (lane size 1 to 2)
+ Rd_VPR128.8H[0,16] = zext(TMPD1[0,8]);
+ Rd_VPR128.8H[16,16] = zext(TMPD1[8,8]);
+ Rd_VPR128.8H[32,16] = zext(TMPD1[16,8]);
+ Rd_VPR128.8H[48,16] = zext(TMPD1[24,8]);
+ Rd_VPR128.8H[64,16] = zext(TMPD1[32,8]);
+ Rd_VPR128.8H[80,16] = zext(TMPD1[40,8]);
+ Rd_VPR128.8H[96,16] = zext(TMPD1[48,8]);
+ Rd_VPR128.8H[112,16] = zext(TMPD1[56,8]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00
+# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00
+# CONSTRUCT x2f20a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =var =$zext@4:16
+# SMACRO(pseudo) ARG1 ARG2 =NEON_uxtl/1@4
+# AUNIT --inst x2f20a400/mask=xfffffc00 --status pass --comment "ext"
+
+:uxtl Rd_VPR128.2D, Rn_VPR64.2S
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5=0 & b_1115=0x14 & b_1010=1 & Rn_VPR64.2S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR64.2S;
+ # simd resize Rd_VPR128.2D = zext(TMPD1) (lane size 4 to 8)
+ Rd_VPR128.2D[0,64] = zext(TMPD1[0,32]);
+ Rd_VPR128.2D[64,64] = zext(TMPD1[32,32]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00
+# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00
+# CONSTRUCT x2f10a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =var =$zext@2:16
+# SMACRO(pseudo) ARG1 ARG2 =NEON_uxtl/1@2
+# AUNIT --inst x2f10a400/mask=xfffffc00 --status pass --comment "ext"
+
+:uxtl Rd_VPR128.4S, Rn_VPR64.4H
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4=0 & b_1115=0x14 & b_1010=1 & Rn_VPR64.4H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR64.4H;
+ # simd resize Rd_VPR128.4S = zext(TMPD1) (lane size 2 to 4)
+ Rd_VPR128.4S[0,32] = zext(TMPD1[0,16]);
+ Rd_VPR128.4S[32,32] = zext(TMPD1[16,16]);
+ Rd_VPR128.4S[64,32] = zext(TMPD1[32,16]);
+ Rd_VPR128.4S[96,32] = zext(TMPD1[48,16]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00
+# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00
+# CONSTRUCT x6f20a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 =$zext@4:16
+# SMACRO(pseudo) ARG1 ARG2 =NEON_uxtl2/1@4
+# AUNIT --inst x6f20a400/mask=xfffffc00 --status pass --comment "ext"
+
+:uxtl2 Rd_VPR128.2D, Rn_VPR128.4S
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2123=1 & Imm_uimm5=0 & b_1115=0x14 & b_1010=1 & Rn_VPR128.4S & Rd_VPR128.2D & Zd
+{
+ TMPD1 = Rn_VPR128.4S[64,64];
+ # simd resize Rd_VPR128.2D = zext(TMPD1) (lane size 4 to 8)
+ Rd_VPR128.2D[0,64] = zext(TMPD1[0,32]);
+ Rd_VPR128.2D[64,64] = zext(TMPD1[32,32]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00
+# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00
+# CONSTRUCT x2f08a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 =var =$zext@1:16
+# SMACRO(pseudo) ARG1 ARG2 =NEON_uxtl/1@1
+# AUNIT --inst x2f08a400/mask=xfffffc00 --status pass --comment "ext"
+
+:uxtl Rd_VPR128.8H, Rn_VPR64.8B
+is b_3131=0 & q=0 & u=1 & b_2428=0xf & b_1923=0x1 & Imm_uimm3=0 & b_1115=0x14 & b_1010=1 & Rn_VPR64.8B & Rd_VPR128.8H & Zd
+{
+ TMPD1 = Rn_VPR64.8B;
+ # simd resize Rd_VPR128.8H = zext(TMPD1) (lane size 1 to 2)
+ Rd_VPR128.8H[0,16] = zext(TMPD1[0,8]);
+ Rd_VPR128.8H[16,16] = zext(TMPD1[8,8]);
+ Rd_VPR128.8H[32,16] = zext(TMPD1[16,8]);
+ Rd_VPR128.8H[48,16] = zext(TMPD1[24,8]);
+ Rd_VPR128.8H[64,16] = zext(TMPD1[32,8]);
+ Rd_VPR128.8H[80,16] = zext(TMPD1[40,8]);
+ Rd_VPR128.8H[96,16] = zext(TMPD1[48,8]);
+ Rd_VPR128.8H[112,16] = zext(TMPD1[56,8]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.398 UXTL, UXTL2 page C7-2929 line 170931 MATCH x2f00a400/mask=xbf87fc00
+# C7.2.391 USHLL, USHLL2 page C7-2914 line 170042 MATCH x2f00a400/mask=xbf80fc00
+# CONSTRUCT x6f10a400/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2[1]:8 =$zext@2:16
+# SMACRO(pseudo) ARG1 ARG2 =NEON_uxtl2/1@2
+# AUNIT --inst x6f10a400/mask=xfffffc00 --status pass --comment "ext"
+
+:uxtl2 Rd_VPR128.4S, Rn_VPR128.8H
+is b_3131=0 & q=1 & u=1 & b_2428=0xf & b_2023=0x1 & Imm_uimm4=0 & b_1115=0x14 & b_1010=1 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPD1 = Rn_VPR128.8H[64,64];
+ # simd resize Rd_VPR128.4S = zext(TMPD1) (lane size 2 to 4)
+ Rd_VPR128.4S[0,32] = zext(TMPD1[0,16]);
+ Rd_VPR128.4S[32,32] = zext(TMPD1[16,16]);
+ Rd_VPR128.4S[64,32] = zext(TMPD1[32,16]);
+ Rd_VPR128.4S[96,32] = zext(TMPD1[48,16]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.399 UZP1 page C7-2931 line 171030 MATCH x0e001800/mask=xbf20fc00
+# CONSTRUCT x4e001800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-1@4-2@6-3@8-4@10-5@12-6@14-7:1 swap &=$shuffle@0-8@2-9@4-10@6-11@8-12@10-13@12-14@14-15:1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@1
+# AUNIT --inst x4e001800/mask=xffe0fc00 --status pass
+
+:uzp1 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ TMPQ2 = Rm_VPR128.16B;
+ TMPQ1 = Rn_VPR128.16B;
+ # simd shuffle Rd_VPR128.16B = TMPQ1 (@0-0@2-1@4-2@6-3@8-4@10-5@12-6@14-7) lane size 1
+ Rd_VPR128.16B[0,8] = TMPQ1[0,8];
+ Rd_VPR128.16B[8,8] = TMPQ1[16,8];
+ Rd_VPR128.16B[16,8] = TMPQ1[32,8];
+ Rd_VPR128.16B[24,8] = TMPQ1[48,8];
+ Rd_VPR128.16B[32,8] = TMPQ1[64,8];
+ Rd_VPR128.16B[40,8] = TMPQ1[80,8];
+ Rd_VPR128.16B[48,8] = TMPQ1[96,8];
+ Rd_VPR128.16B[56,8] = TMPQ1[112,8];
+ # simd shuffle Rd_VPR128.16B = TMPQ2 (@0-8@2-9@4-10@6-11@8-12@10-13@12-14@14-15) lane size 1
+ Rd_VPR128.16B[64,8] = TMPQ2[0,8];
+ Rd_VPR128.16B[72,8] = TMPQ2[16,8];
+ Rd_VPR128.16B[80,8] = TMPQ2[32,8];
+ Rd_VPR128.16B[88,8] = TMPQ2[48,8];
+ Rd_VPR128.16B[96,8] = TMPQ2[64,8];
+ Rd_VPR128.16B[104,8] = TMPQ2[80,8];
+ Rd_VPR128.16B[112,8] = TMPQ2[96,8];
+ Rd_VPR128.16B[120,8] = TMPQ2[112,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.399 UZP1 page C7-2931 line 171030 MATCH x0e001800/mask=xbf20fc00
+# CONSTRUCT x4ec01800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0:8 swap &=$shuffle@0-1:8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@8
+# AUNIT --inst x4ec01800/mask=xffe0fc00 --status pass
+
+:uzp1 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=3 & b_2121=0 & Rm_VPR128.2D & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ TMPQ2 = Rm_VPR128.2D;
+ TMPQ1 = Rn_VPR128.2D;
+ # simd shuffle Rd_VPR128.2D = TMPQ1 (@0-0) lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ1[0,64];
+ # simd shuffle Rd_VPR128.2D = TMPQ2 (@0-1) lane size 8
+ Rd_VPR128.2D[64,64] = TMPQ2[0,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.399 UZP1 page C7-2931 line 171030 MATCH x0e001800/mask=xbf20fc00
+# CONSTRUCT x0e801800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0:4 swap &=$shuffle@0-1:4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@4
+# AUNIT --inst x0e801800/mask=xffe0fc00 --status pass
+
+:uzp1 Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR64.2S & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ TMPD2 = Rm_VPR64.2S;
+ TMPD1 = Rn_VPR64.2S;
+ # simd shuffle Rd_VPR64.2S = TMPD1 (@0-0) lane size 4
+ Rd_VPR64.2S[0,32] = TMPD1[0,32];
+ # simd shuffle Rd_VPR64.2S = TMPD2 (@0-1) lane size 4
+ Rd_VPR64.2S[32,32] = TMPD2[0,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.399 UZP1 page C7-2931 line 171030 MATCH x0e001800/mask=xbf20fc00
+# CONSTRUCT x0e401800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-1:2 swap &=$shuffle@0-2@2-3:2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@2
+# AUNIT --inst x0e401800/mask=xffe0fc00 --status pass
+
+:uzp1 Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR64.4H & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ TMPD2 = Rm_VPR64.4H;
+ TMPD1 = Rn_VPR64.4H;
+ # simd shuffle Rd_VPR64.4H = TMPD1 (@0-0@2-1) lane size 2
+ Rd_VPR64.4H[0,16] = TMPD1[0,16];
+ Rd_VPR64.4H[16,16] = TMPD1[32,16];
+ # simd shuffle Rd_VPR64.4H = TMPD2 (@0-2@2-3) lane size 2
+ Rd_VPR64.4H[32,16] = TMPD2[0,16];
+ Rd_VPR64.4H[48,16] = TMPD2[32,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.399 UZP1 page C7-2931 line 171030 MATCH x0e001800/mask=xbf20fc00
+# CONSTRUCT x4e801800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-1:4 swap &=$shuffle@0-2@2-3:4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@4
+# AUNIT --inst x4e801800/mask=xffe0fc00 --status pass
+
+:uzp1 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR128.4S & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ TMPQ2 = Rm_VPR128.4S;
+ TMPQ1 = Rn_VPR128.4S;
+ # simd shuffle Rd_VPR128.4S = TMPQ1 (@0-0@2-1) lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ1[0,32];
+ Rd_VPR128.4S[32,32] = TMPQ1[64,32];
+ # simd shuffle Rd_VPR128.4S = TMPQ2 (@0-2@2-3) lane size 4
+ Rd_VPR128.4S[64,32] = TMPQ2[0,32];
+ Rd_VPR128.4S[96,32] = TMPQ2[64,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.399 UZP1 page C7-2931 line 171030 MATCH x0e001800/mask=xbf20fc00
+# CONSTRUCT x0e001800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-1@4-2@6-3:1 swap &=$shuffle@0-4@2-5@4-6@6-7:1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@1
+# AUNIT --inst x0e001800/mask=xffe0fc00 --status pass
+
+:uzp1 Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR64.8B & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ TMPD2 = Rm_VPR64.8B;
+ TMPD1 = Rn_VPR64.8B;
+ # simd shuffle Rd_VPR64.8B = TMPD1 (@0-0@2-1@4-2@6-3) lane size 1
+ Rd_VPR64.8B[0,8] = TMPD1[0,8];
+ Rd_VPR64.8B[8,8] = TMPD1[16,8];
+ Rd_VPR64.8B[16,8] = TMPD1[32,8];
+ Rd_VPR64.8B[24,8] = TMPD1[48,8];
+ # simd shuffle Rd_VPR64.8B = TMPD2 (@0-4@2-5@4-6@6-7) lane size 1
+ Rd_VPR64.8B[32,8] = TMPD2[0,8];
+ Rd_VPR64.8B[40,8] = TMPD2[16,8];
+ Rd_VPR64.8B[48,8] = TMPD2[32,8];
+ Rd_VPR64.8B[56,8] = TMPD2[48,8];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.399 UZP1 page C7-2931 line 171030 MATCH x0e001800/mask=xbf20fc00
+# CONSTRUCT x4e401800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@2-1@4-2@6-3:2 swap &=$shuffle@0-4@2-5@4-6@6-7:2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp1/2@2
+# AUNIT --inst x4e401800/mask=xffe0fc00 --status pass
+
+:uzp1 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR128.8H & b_1515=0 & b_1214=1 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ TMPQ2 = Rm_VPR128.8H;
+ TMPQ1 = Rn_VPR128.8H;
+ # simd shuffle Rd_VPR128.8H = TMPQ1 (@0-0@2-1@4-2@6-3) lane size 2
+ Rd_VPR128.8H[0,16] = TMPQ1[0,16];
+ Rd_VPR128.8H[16,16] = TMPQ1[32,16];
+ Rd_VPR128.8H[32,16] = TMPQ1[64,16];
+ Rd_VPR128.8H[48,16] = TMPQ1[96,16];
+ # simd shuffle Rd_VPR128.8H = TMPQ2 (@0-4@2-5@4-6@6-7) lane size 2
+ Rd_VPR128.8H[64,16] = TMPQ2[0,16];
+ Rd_VPR128.8H[80,16] = TMPQ2[32,16];
+ Rd_VPR128.8H[96,16] = TMPQ2[64,16];
+ Rd_VPR128.8H[112,16] = TMPQ2[96,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.400 UZP2 page C7-2933 line 171142 MATCH x0e005800/mask=xbf20fc00
+# CONSTRUCT x4e005800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7:1 swap &=$shuffle@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15:1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@1
+# AUNIT --inst x4e005800/mask=xffe0fc00 --status pass
+
+:uzp2 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ TMPQ2 = Rm_VPR128.16B;
+ TMPQ1 = Rn_VPR128.16B;
+ # simd shuffle Rd_VPR128.16B = TMPQ1 (@1-0@3-1@5-2@7-3@9-4@11-5@13-6@15-7) lane size 1
+ Rd_VPR128.16B[0,8] = TMPQ1[8,8];
+ Rd_VPR128.16B[8,8] = TMPQ1[24,8];
+ Rd_VPR128.16B[16,8] = TMPQ1[40,8];
+ Rd_VPR128.16B[24,8] = TMPQ1[56,8];
+ Rd_VPR128.16B[32,8] = TMPQ1[72,8];
+ Rd_VPR128.16B[40,8] = TMPQ1[88,8];
+ Rd_VPR128.16B[48,8] = TMPQ1[104,8];
+ Rd_VPR128.16B[56,8] = TMPQ1[120,8];
+ # simd shuffle Rd_VPR128.16B = TMPQ2 (@1-8@3-9@5-10@7-11@9-12@11-13@13-14@15-15) lane size 1
+ Rd_VPR128.16B[64,8] = TMPQ2[8,8];
+ Rd_VPR128.16B[72,8] = TMPQ2[24,8];
+ Rd_VPR128.16B[80,8] = TMPQ2[40,8];
+ Rd_VPR128.16B[88,8] = TMPQ2[56,8];
+ Rd_VPR128.16B[96,8] = TMPQ2[72,8];
+ Rd_VPR128.16B[104,8] = TMPQ2[88,8];
+ Rd_VPR128.16B[112,8] = TMPQ2[104,8];
+ Rd_VPR128.16B[120,8] = TMPQ2[120,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.400 UZP2 page C7-2933 line 171142 MATCH x0e005800/mask=xbf20fc00
+# CONSTRUCT x4ec05800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0:8 swap &=$shuffle@1-1:8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@8
+# AUNIT --inst x4ec05800/mask=xffe0fc00 --status pass
+
+:uzp2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=3 & b_2121=0 & Rm_VPR128.2D & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ TMPQ2 = Rm_VPR128.2D;
+ TMPQ1 = Rn_VPR128.2D;
+ # simd shuffle Rd_VPR128.2D = TMPQ1 (@1-0) lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ1[64,64];
+ # simd shuffle Rd_VPR128.2D = TMPQ2 (@1-1) lane size 8
+ Rd_VPR128.2D[64,64] = TMPQ2[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.400 UZP2 page C7-2933 line 171142 MATCH x0e005800/mask=xbf20fc00
+# CONSTRUCT x0e805800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0:4 swap &=$shuffle@1-1:4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@4
+# AUNIT --inst x0e805800/mask=xffe0fc00 --status pass
+
+:uzp2 Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR64.2S & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ TMPD2 = Rm_VPR64.2S;
+ TMPD1 = Rn_VPR64.2S;
+ # simd shuffle Rd_VPR64.2S = TMPD1 (@1-0) lane size 4
+ Rd_VPR64.2S[0,32] = TMPD1[32,32];
+ # simd shuffle Rd_VPR64.2S = TMPD2 (@1-1) lane size 4
+ Rd_VPR64.2S[32,32] = TMPD2[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.400 UZP2 page C7-2933 line 171142 MATCH x0e005800/mask=xbf20fc00
+# CONSTRUCT x0e405800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-1:2 swap &=$shuffle@1-2@3-3:2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@2
+# AUNIT --inst x0e405800/mask=xffe0fc00 --status pass
+
+:uzp2 Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR64.4H & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ TMPD2 = Rm_VPR64.4H;
+ TMPD1 = Rn_VPR64.4H;
+ # simd shuffle Rd_VPR64.4H = TMPD1 (@1-0@3-1) lane size 2
+ Rd_VPR64.4H[0,16] = TMPD1[16,16];
+ Rd_VPR64.4H[16,16] = TMPD1[48,16];
+ # simd shuffle Rd_VPR64.4H = TMPD2 (@1-2@3-3) lane size 2
+ Rd_VPR64.4H[32,16] = TMPD2[16,16];
+ Rd_VPR64.4H[48,16] = TMPD2[48,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.400 UZP2 page C7-2933 line 171142 MATCH x0e005800/mask=xbf20fc00
+# CONSTRUCT x4e805800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-1:4 swap &=$shuffle@1-2@3-3:4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@4
+# AUNIT --inst x4e805800/mask=xffe0fc00 --status pass
+
+:uzp2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR128.4S & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ TMPQ2 = Rm_VPR128.4S;
+ TMPQ1 = Rn_VPR128.4S;
+ # simd shuffle Rd_VPR128.4S = TMPQ1 (@1-0@3-1) lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ1[32,32];
+ Rd_VPR128.4S[32,32] = TMPQ1[96,32];
+ # simd shuffle Rd_VPR128.4S = TMPQ2 (@1-2@3-3) lane size 4
+ Rd_VPR128.4S[64,32] = TMPQ2[32,32];
+ Rd_VPR128.4S[96,32] = TMPQ2[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.400 UZP2 page C7-2933 line 171142 MATCH x0e005800/mask=xbf20fc00
+# CONSTRUCT x0e005800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-1@5-2@7-3:1 swap &=$shuffle@1-4@3-5@5-6@7-7:1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@1
+# AUNIT --inst x0e005800/mask=xffe0fc00 --status pass
+
+:uzp2 Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR64.8B & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ TMPD2 = Rm_VPR64.8B;
+ TMPD1 = Rn_VPR64.8B;
+ # simd shuffle Rd_VPR64.8B = TMPD1 (@1-0@3-1@5-2@7-3) lane size 1
+ Rd_VPR64.8B[0,8] = TMPD1[8,8];
+ Rd_VPR64.8B[8,8] = TMPD1[24,8];
+ Rd_VPR64.8B[16,8] = TMPD1[40,8];
+ Rd_VPR64.8B[24,8] = TMPD1[56,8];
+ # simd shuffle Rd_VPR64.8B = TMPD2 (@1-4@3-5@5-6@7-7) lane size 1
+ Rd_VPR64.8B[32,8] = TMPD2[8,8];
+ Rd_VPR64.8B[40,8] = TMPD2[24,8];
+ Rd_VPR64.8B[48,8] = TMPD2[40,8];
+ Rd_VPR64.8B[56,8] = TMPD2[56,8];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.400 UZP2 page C7-2933 line 171142 MATCH x0e005800/mask=xbf20fc00
+# CONSTRUCT x4e405800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0@3-1@5-2@7-3:2 swap &=$shuffle@1-4@3-5@5-6@7-7:2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_uzp2/2@2
+# AUNIT --inst x4e405800/mask=xffe0fc00 --status pass
+
+:uzp2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR128.8H & b_1515=0 & b_1214=5 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ TMPQ2 = Rm_VPR128.8H;
+ TMPQ1 = Rn_VPR128.8H;
+ # simd shuffle Rd_VPR128.8H = TMPQ1 (@1-0@3-1@5-2@7-3) lane size 2
+ Rd_VPR128.8H[0,16] = TMPQ1[16,16];
+ Rd_VPR128.8H[16,16] = TMPQ1[48,16];
+ Rd_VPR128.8H[32,16] = TMPQ1[80,16];
+ Rd_VPR128.8H[48,16] = TMPQ1[112,16];
+ # simd shuffle Rd_VPR128.8H = TMPQ2 (@1-4@3-5@5-6@7-7) lane size 2
+ Rd_VPR128.8H[64,16] = TMPQ2[16,16];
+ Rd_VPR128.8H[80,16] = TMPQ2[48,16];
+ Rd_VPR128.8H[96,16] = TMPQ2[80,16];
+ Rd_VPR128.8H[112,16] = TMPQ2[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.401 XAR page C7-2935 line 171254 MATCH xce800000/mask=xffe00000
+# CONSTRUCT xce800000/mask=xffe00000 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 ARG3 $|@8 ARG4 =var:8 =$>>@8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 ARG4 =NEON_xar/3@8
+# AUNIT --inst xce800000/mask=xffe00000 --status noqemu
+# Advanced SIMD variant
+
+:xar Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D, LSB_bitfield64_imm
+is b_2131=0b11001110100 & Rd_VPR128.2D & Rn_VPR128.2D & Rm_VPR128.2D & LSB_bitfield64_imm & Zd
+{
+ # simd infix TMPQ1 = Rn_VPR128.2D | Rm_VPR128.2D on lane size 8
+ TMPQ1[0,64] = Rn_VPR128.2D[0,64] | Rm_VPR128.2D[0,64];
+ TMPQ1[64,64] = Rn_VPR128.2D[64,64] | Rm_VPR128.2D[64,64];
+ local tmp2:8 = LSB_bitfield64_imm;
+ # simd infix Rd_VPR128.2D = TMPQ1 >> tmp2 on lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ1[0,64] >> tmp2;
+ Rd_VPR128.2D[64,64] = TMPQ1[64,64] >> tmp2;
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.402 XTN, XTN2 page C7-2936 line 171324 MATCH x0e212800/mask=xbf3ffc00
+# CONSTRUCT x0ea12800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@8:8 &=$shuffle@0-0@1-1:4
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_xtn/2@8
+# AUNIT --inst x0ea12800/mask=xfffffc00 --status pass --comment "ext"
+
+:xtn Rd_VPR64.2S, Rn_VPR128.2D
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x12 & b_1011=2 & Rn_VPR128.2D & Rd_VPR64.2S & Zd
+{
+ # simd resize TMPD1 = zext(Rn_VPR128.2D) (lane size 8 to 4)
+ TMPD1[0,32] = Rn_VPR128.2D[0,32];
+ TMPD1[32,32] = Rn_VPR128.2D[64,32];
+ # simd shuffle Rd_VPR64.2S = TMPD1 (@0-0@1-1) lane size 4
+ Rd_VPR64.2S[0,32] = TMPD1[0,32];
+ Rd_VPR64.2S[32,32] = TMPD1[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.402 XTN, XTN2 page C7-2936 line 171324 MATCH x0e212800/mask=xbf3ffc00
+# CONSTRUCT x4ea12800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@8:8 &=$shuffle@0-2@1-3:4
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_xtn2/2@8
+# AUNIT --inst x4ea12800/mask=xfffffc00 --status pass --comment "ext"
+
+:xtn2 Rd_VPR128.4S, Rn_VPR128.2D
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x10 & b_1216=0x12 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.4S & Zd
+{
+ # simd resize TMPD1 = zext(Rn_VPR128.2D) (lane size 8 to 4)
+ TMPD1[0,32] = Rn_VPR128.2D[0,32];
+ TMPD1[32,32] = Rn_VPR128.2D[64,32];
+ # simd shuffle Rd_VPR128.4S = TMPD1 (@0-2@1-3) lane size 4
+ Rd_VPR128.4S[64,32] = TMPD1[0,32];
+ Rd_VPR128.4S[96,32] = TMPD1[32,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.402 XTN, XTN2 page C7-2936 line 171324 MATCH x0e212800/mask=xbf3ffc00
+# CONSTRUCT x0e612800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@4:8 &=$shuffle@0-0@1-1@2-2@3-3:2
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_xtn/2@4
+# AUNIT --inst x0e612800/mask=xfffffc00 --status pass --comment "ext"
+
+:xtn Rd_VPR64.4H, Rn_VPR128.4S
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x12 & b_1011=2 & Rn_VPR128.4S & Rd_VPR64.4H & Zd
+{
+ # simd resize TMPD1 = zext(Rn_VPR128.4S) (lane size 4 to 2)
+ TMPD1[0,16] = Rn_VPR128.4S[0,16];
+ TMPD1[16,16] = Rn_VPR128.4S[32,16];
+ TMPD1[32,16] = Rn_VPR128.4S[64,16];
+ TMPD1[48,16] = Rn_VPR128.4S[96,16];
+ # simd shuffle Rd_VPR64.4H = TMPD1 (@0-0@1-1@2-2@3-3) lane size 2
+ Rd_VPR64.4H[0,16] = TMPD1[0,16];
+ Rd_VPR64.4H[16,16] = TMPD1[16,16];
+ Rd_VPR64.4H[32,16] = TMPD1[32,16];
+ Rd_VPR64.4H[48,16] = TMPD1[48,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.402 XTN, XTN2 page C7-2936 line 171324 MATCH x0e212800/mask=xbf3ffc00
+# CONSTRUCT x4e612800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@4:8 &=$shuffle@0-4@1-5@2-6@3-7:2
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_xtn2/2@4
+# AUNIT --inst x4e612800/mask=xfffffc00 --status pass --comment "ext"
+
+:xtn2 Rd_VPR128.8H, Rn_VPR128.4S
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=1 & b_1721=0x10 & b_1216=0x12 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.8H & Zd
+{
+ # simd resize TMPD1 = zext(Rn_VPR128.4S) (lane size 4 to 2)
+ TMPD1[0,16] = Rn_VPR128.4S[0,16];
+ TMPD1[16,16] = Rn_VPR128.4S[32,16];
+ TMPD1[32,16] = Rn_VPR128.4S[64,16];
+ TMPD1[48,16] = Rn_VPR128.4S[96,16];
+ # simd shuffle Rd_VPR128.8H = TMPD1 (@0-4@1-5@2-6@3-7) lane size 2
+ Rd_VPR128.8H[64,16] = TMPD1[0,16];
+ Rd_VPR128.8H[80,16] = TMPD1[16,16];
+ Rd_VPR128.8H[96,16] = TMPD1[32,16];
+ Rd_VPR128.8H[112,16] = TMPD1[48,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.402 XTN, XTN2 page C7-2936 line 171324 MATCH x0e212800/mask=xbf3ffc00
+# CONSTRUCT x0e212800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@2:8 &=$shuffle@0-0@1-1@2-2@3-3@4-4@5-5@6-6@7-7:1
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_xtn/2@2
+# AUNIT --inst x0e212800/mask=xfffffc00 --status pass --comment "ext"
+
+:xtn Rd_VPR64.8B, Rn_VPR128.8H
+is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x12 & b_1011=2 & Rn_VPR128.8H & Rd_VPR64.8B & Zd
+{
+ # simd resize TMPD1 = zext(Rn_VPR128.8H) (lane size 2 to 1)
+ TMPD1[0,8] = Rn_VPR128.8H[0,8];
+ TMPD1[8,8] = Rn_VPR128.8H[16,8];
+ TMPD1[16,8] = Rn_VPR128.8H[32,8];
+ TMPD1[24,8] = Rn_VPR128.8H[48,8];
+ TMPD1[32,8] = Rn_VPR128.8H[64,8];
+ TMPD1[40,8] = Rn_VPR128.8H[80,8];
+ TMPD1[48,8] = Rn_VPR128.8H[96,8];
+ TMPD1[56,8] = Rn_VPR128.8H[112,8];
+ # simd shuffle Rd_VPR64.8B = TMPD1 (@0-0@1-1@2-2@3-3@4-4@5-5@6-6@7-7) lane size 1
+ Rd_VPR64.8B[0,8] = TMPD1[0,8];
+ Rd_VPR64.8B[8,8] = TMPD1[8,8];
+ Rd_VPR64.8B[16,8] = TMPD1[16,8];
+ Rd_VPR64.8B[24,8] = TMPD1[24,8];
+ Rd_VPR64.8B[32,8] = TMPD1[32,8];
+ Rd_VPR64.8B[40,8] = TMPD1[40,8];
+ Rd_VPR64.8B[48,8] = TMPD1[48,8];
+ Rd_VPR64.8B[56,8] = TMPD1[56,8];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.402 XTN, XTN2 page C7-2936 line 171324 MATCH x0e212800/mask=xbf3ffc00
+# CONSTRUCT x4e212800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG1 ARG2 $zext@2:8 &=$shuffle@0-8@1-9@2-10@3-11@4-12@5-13@6-14@7-15:1
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_xtn2/2@2
+# AUNIT --inst x4e212800/mask=xfffffc00 --status pass --comment "ext"
+
+:xtn2 Rd_VPR128.16B, Rn_VPR128.8H
+is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_1721=0x10 & b_1216=0x12 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.16B & Zd
+{
+ # simd resize TMPD1 = zext(Rn_VPR128.8H) (lane size 2 to 1)
+ TMPD1[0,8] = Rn_VPR128.8H[0,8];
+ TMPD1[8,8] = Rn_VPR128.8H[16,8];
+ TMPD1[16,8] = Rn_VPR128.8H[32,8];
+ TMPD1[24,8] = Rn_VPR128.8H[48,8];
+ TMPD1[32,8] = Rn_VPR128.8H[64,8];
+ TMPD1[40,8] = Rn_VPR128.8H[80,8];
+ TMPD1[48,8] = Rn_VPR128.8H[96,8];
+ TMPD1[56,8] = Rn_VPR128.8H[112,8];
+ # simd shuffle Rd_VPR128.16B = TMPD1 (@0-8@1-9@2-10@3-11@4-12@5-13@6-14@7-15) lane size 1
+ Rd_VPR128.16B[64,8] = TMPD1[0,8];
+ Rd_VPR128.16B[72,8] = TMPD1[8,8];
+ Rd_VPR128.16B[80,8] = TMPD1[16,8];
+ Rd_VPR128.16B[88,8] = TMPD1[24,8];
+ Rd_VPR128.16B[96,8] = TMPD1[32,8];
+ Rd_VPR128.16B[104,8] = TMPD1[40,8];
+ Rd_VPR128.16B[112,8] = TMPD1[48,8];
+ Rd_VPR128.16B[120,8] = TMPD1[56,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.403 ZIP1 page C7-2938 line 171432 MATCH x0e003800/mask=xbf20fc00
+# CONSTRUCT x4e003800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@1-2@2-4@3-6@4-8@5-10@6-12@7-14:1 swap &=$shuffle@0-1@1-3@2-5@3-7@4-9@5-11@6-13@7-15:1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@1
+# AUNIT --inst x4e003800/mask=xffe0fc00 --status pass
+
+:zip1 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ TMPQ2 = Rm_VPR128.16B;
+ TMPQ1 = Rn_VPR128.16B;
+ # simd shuffle Rd_VPR128.16B = TMPQ1 (@0-0@1-2@2-4@3-6@4-8@5-10@6-12@7-14) lane size 1
+ Rd_VPR128.16B[0,8] = TMPQ1[0,8];
+ Rd_VPR128.16B[16,8] = TMPQ1[8,8];
+ Rd_VPR128.16B[32,8] = TMPQ1[16,8];
+ Rd_VPR128.16B[48,8] = TMPQ1[24,8];
+ Rd_VPR128.16B[64,8] = TMPQ1[32,8];
+ Rd_VPR128.16B[80,8] = TMPQ1[40,8];
+ Rd_VPR128.16B[96,8] = TMPQ1[48,8];
+ Rd_VPR128.16B[112,8] = TMPQ1[56,8];
+ # simd shuffle Rd_VPR128.16B = TMPQ2 (@0-1@1-3@2-5@3-7@4-9@5-11@6-13@7-15) lane size 1
+ Rd_VPR128.16B[8,8] = TMPQ2[0,8];
+ Rd_VPR128.16B[24,8] = TMPQ2[8,8];
+ Rd_VPR128.16B[40,8] = TMPQ2[16,8];
+ Rd_VPR128.16B[56,8] = TMPQ2[24,8];
+ Rd_VPR128.16B[72,8] = TMPQ2[32,8];
+ Rd_VPR128.16B[88,8] = TMPQ2[40,8];
+ Rd_VPR128.16B[104,8] = TMPQ2[48,8];
+ Rd_VPR128.16B[120,8] = TMPQ2[56,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.403 ZIP1 page C7-2938 line 171432 MATCH x0e003800/mask=xbf20fc00
+# CONSTRUCT x4ec03800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0:8 swap &=$shuffle@0-1:8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@8
+# AUNIT --inst x4ec03800/mask=xffe0fc00 --status pass
+
+:zip1 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=3 & b_2121=0 & Rm_VPR128.2D & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ TMPQ2 = Rm_VPR128.2D;
+ TMPQ1 = Rn_VPR128.2D;
+ # simd shuffle Rd_VPR128.2D = TMPQ1 (@0-0) lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ1[0,64];
+ # simd shuffle Rd_VPR128.2D = TMPQ2 (@0-1) lane size 8
+ Rd_VPR128.2D[64,64] = TMPQ2[0,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.403 ZIP1 page C7-2938 line 171432 MATCH x0e003800/mask=xbf20fc00
+# CONSTRUCT x0e803800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0:4 swap &=$shuffle@0-1:4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@4
+# AUNIT --inst x0e803800/mask=xffe0fc00 --status pass
+
+:zip1 Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR64.2S & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ TMPD2 = Rm_VPR64.2S;
+ TMPD1 = Rn_VPR64.2S;
+ # simd shuffle Rd_VPR64.2S = TMPD1 (@0-0) lane size 4
+ Rd_VPR64.2S[0,32] = TMPD1[0,32];
+ # simd shuffle Rd_VPR64.2S = TMPD2 (@0-1) lane size 4
+ Rd_VPR64.2S[32,32] = TMPD2[0,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.403 ZIP1 page C7-2938 line 171432 MATCH x0e003800/mask=xbf20fc00
+# CONSTRUCT x0e403800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@1-2:2 swap &=$shuffle@0-1@1-3:2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@2
+# AUNIT --inst x0e403800/mask=xffe0fc00 --status pass
+
+:zip1 Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR64.4H & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ TMPD2 = Rm_VPR64.4H;
+ TMPD1 = Rn_VPR64.4H;
+ # simd shuffle Rd_VPR64.4H = TMPD1 (@0-0@1-2) lane size 2
+ Rd_VPR64.4H[0,16] = TMPD1[0,16];
+ Rd_VPR64.4H[32,16] = TMPD1[16,16];
+ # simd shuffle Rd_VPR64.4H = TMPD2 (@0-1@1-3) lane size 2
+ Rd_VPR64.4H[16,16] = TMPD2[0,16];
+ Rd_VPR64.4H[48,16] = TMPD2[16,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.403 ZIP1 page C7-2938 line 171432 MATCH x0e003800/mask=xbf20fc00
+# CONSTRUCT x4e803800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@1-2:4 swap &=$shuffle@0-1@1-3:4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@4
+# AUNIT --inst x4e803800/mask=xffe0fc00 --status pass
+
+:zip1 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR128.4S & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ TMPQ2 = Rm_VPR128.4S;
+ TMPQ1 = Rn_VPR128.4S;
+ # simd shuffle Rd_VPR128.4S = TMPQ1 (@0-0@1-2) lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ1[0,32];
+ Rd_VPR128.4S[64,32] = TMPQ1[32,32];
+ # simd shuffle Rd_VPR128.4S = TMPQ2 (@0-1@1-3) lane size 4
+ Rd_VPR128.4S[32,32] = TMPQ2[0,32];
+ Rd_VPR128.4S[96,32] = TMPQ2[32,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.403 ZIP1 page C7-2938 line 171432 MATCH x0e003800/mask=xbf20fc00
+# CONSTRUCT x0e003800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@1-2@2-4@3-6:1 swap &=$shuffle@0-1@1-3@2-5@3-7:1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@1
+# AUNIT --inst x0e003800/mask=xffe0fc00 --status pass
+
+:zip1 Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR64.8B & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ TMPD2 = Rm_VPR64.8B;
+ TMPD1 = Rn_VPR64.8B;
+ # simd shuffle Rd_VPR64.8B = TMPD1 (@0-0@1-2@2-4@3-6) lane size 1
+ Rd_VPR64.8B[0,8] = TMPD1[0,8];
+ Rd_VPR64.8B[16,8] = TMPD1[8,8];
+ Rd_VPR64.8B[32,8] = TMPD1[16,8];
+ Rd_VPR64.8B[48,8] = TMPD1[24,8];
+ # simd shuffle Rd_VPR64.8B = TMPD2 (@0-1@1-3@2-5@3-7) lane size 1
+ Rd_VPR64.8B[8,8] = TMPD2[0,8];
+ Rd_VPR64.8B[24,8] = TMPD2[8,8];
+ Rd_VPR64.8B[40,8] = TMPD2[16,8];
+ Rd_VPR64.8B[56,8] = TMPD2[24,8];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.403 ZIP1 page C7-2938 line 171432 MATCH x0e003800/mask=xbf20fc00
+# CONSTRUCT x4e403800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@0-0@1-2@2-4@3-6:2 swap &=$shuffle@0-1@1-3@2-5@3-7:2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip1/2@2
+# AUNIT --inst x4e403800/mask=xffe0fc00 --status pass
+
+:zip1 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR128.8H & b_1515=0 & b_1214=3 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ TMPQ2 = Rm_VPR128.8H;
+ TMPQ1 = Rn_VPR128.8H;
+ # simd shuffle Rd_VPR128.8H = TMPQ1 (@0-0@1-2@2-4@3-6) lane size 2
+ Rd_VPR128.8H[0,16] = TMPQ1[0,16];
+ Rd_VPR128.8H[32,16] = TMPQ1[16,16];
+ Rd_VPR128.8H[64,16] = TMPQ1[32,16];
+ Rd_VPR128.8H[96,16] = TMPQ1[48,16];
+ # simd shuffle Rd_VPR128.8H = TMPQ2 (@0-1@1-3@2-5@3-7) lane size 2
+ Rd_VPR128.8H[16,16] = TMPQ2[0,16];
+ Rd_VPR128.8H[48,16] = TMPQ2[16,16];
+ Rd_VPR128.8H[80,16] = TMPQ2[32,16];
+ Rd_VPR128.8H[112,16] = TMPQ2[48,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.404 ZIP2 page C7-2940 line 171547 MATCH x0e007800/mask=xbf20fc00
+# CONSTRUCT x4e007800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@8-0@9-2@10-4@11-6@12-8@13-10@14-12@15-14:1 swap &=$shuffle@8-1@9-3@10-5@11-7@12-9@13-11@14-13@15-15:1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@1
+# AUNIT --inst x4e007800/mask=xffe0fc00 --status pass
+
+:zip2 Rd_VPR128.16B, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR128.16B & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR128.16B & Rd_VPR128.16B & Zd
+{
+ TMPQ2 = Rm_VPR128.16B;
+ TMPQ1 = Rn_VPR128.16B;
+ # simd shuffle Rd_VPR128.16B = TMPQ1 (@8-0@9-2@10-4@11-6@12-8@13-10@14-12@15-14) lane size 1
+ Rd_VPR128.16B[0,8] = TMPQ1[64,8];
+ Rd_VPR128.16B[16,8] = TMPQ1[72,8];
+ Rd_VPR128.16B[32,8] = TMPQ1[80,8];
+ Rd_VPR128.16B[48,8] = TMPQ1[88,8];
+ Rd_VPR128.16B[64,8] = TMPQ1[96,8];
+ Rd_VPR128.16B[80,8] = TMPQ1[104,8];
+ Rd_VPR128.16B[96,8] = TMPQ1[112,8];
+ Rd_VPR128.16B[112,8] = TMPQ1[120,8];
+ # simd shuffle Rd_VPR128.16B = TMPQ2 (@8-1@9-3@10-5@11-7@12-9@13-11@14-13@15-15) lane size 1
+ Rd_VPR128.16B[8,8] = TMPQ2[64,8];
+ Rd_VPR128.16B[24,8] = TMPQ2[72,8];
+ Rd_VPR128.16B[40,8] = TMPQ2[80,8];
+ Rd_VPR128.16B[56,8] = TMPQ2[88,8];
+ Rd_VPR128.16B[72,8] = TMPQ2[96,8];
+ Rd_VPR128.16B[88,8] = TMPQ2[104,8];
+ Rd_VPR128.16B[104,8] = TMPQ2[112,8];
+ Rd_VPR128.16B[120,8] = TMPQ2[120,8];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.404 ZIP2 page C7-2940 line 171547 MATCH x0e007800/mask=xbf20fc00
+# CONSTRUCT x4ec07800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0:8 swap &=$shuffle@1-1:8
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@8
+# AUNIT --inst x4ec07800/mask=xffe0fc00 --status pass
+
+:zip2 Rd_VPR128.2D, Rn_VPR128.2D, Rm_VPR128.2D
+is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=3 & b_2121=0 & Rm_VPR128.2D & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR128.2D & Rd_VPR128.2D & Zd
+{
+ TMPQ2 = Rm_VPR128.2D;
+ TMPQ1 = Rn_VPR128.2D;
+ # simd shuffle Rd_VPR128.2D = TMPQ1 (@1-0) lane size 8
+ Rd_VPR128.2D[0,64] = TMPQ1[64,64];
+ # simd shuffle Rd_VPR128.2D = TMPQ2 (@1-1) lane size 8
+ Rd_VPR128.2D[64,64] = TMPQ2[64,64];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.404 ZIP2 page C7-2940 line 171547 MATCH x0e007800/mask=xbf20fc00
+# CONSTRUCT x0e807800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@1-0:4 swap &=$shuffle@1-1:4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@4
+# AUNIT --inst x0e807800/mask=xffe0fc00 --status pass
+
+:zip2 Rd_VPR64.2S, Rn_VPR64.2S, Rm_VPR64.2S
+is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR64.2S & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR64.2S & Rd_VPR64.2S & Zd
+{
+ TMPD2 = Rm_VPR64.2S;
+ TMPD1 = Rn_VPR64.2S;
+ # simd shuffle Rd_VPR64.2S = TMPD1 (@1-0) lane size 4
+ Rd_VPR64.2S[0,32] = TMPD1[32,32];
+ # simd shuffle Rd_VPR64.2S = TMPD2 (@1-1) lane size 4
+ Rd_VPR64.2S[32,32] = TMPD2[32,32];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.404 ZIP2 page C7-2940 line 171547 MATCH x0e007800/mask=xbf20fc00
+# CONSTRUCT x0e407800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@2-0@3-2:2 swap &=$shuffle@2-1@3-3:2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@2
+# AUNIT --inst x0e407800/mask=xffe0fc00 --status pass
+
+:zip2 Rd_VPR64.4H, Rn_VPR64.4H, Rm_VPR64.4H
+is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR64.4H & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR64.4H & Rd_VPR64.4H & Zd
+{
+ TMPD2 = Rm_VPR64.4H;
+ TMPD1 = Rn_VPR64.4H;
+ # simd shuffle Rd_VPR64.4H = TMPD1 (@2-0@3-2) lane size 2
+ Rd_VPR64.4H[0,16] = TMPD1[32,16];
+ Rd_VPR64.4H[32,16] = TMPD1[48,16];
+ # simd shuffle Rd_VPR64.4H = TMPD2 (@2-1@3-3) lane size 2
+ Rd_VPR64.4H[16,16] = TMPD2[32,16];
+ Rd_VPR64.4H[48,16] = TMPD2[48,16];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.404 ZIP2 page C7-2940 line 171547 MATCH x0e007800/mask=xbf20fc00
+# CONSTRUCT x4e807800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@2-0@3-2:4 swap &=$shuffle@2-1@3-3:4
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@4
+# AUNIT --inst x4e807800/mask=xffe0fc00 --status pass
+
+:zip2 Rd_VPR128.4S, Rn_VPR128.4S, Rm_VPR128.4S
+is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=2 & b_2121=0 & Rm_VPR128.4S & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR128.4S & Rd_VPR128.4S & Zd
+{
+ TMPQ2 = Rm_VPR128.4S;
+ TMPQ1 = Rn_VPR128.4S;
+ # simd shuffle Rd_VPR128.4S = TMPQ1 (@2-0@3-2) lane size 4
+ Rd_VPR128.4S[0,32] = TMPQ1[64,32];
+ Rd_VPR128.4S[64,32] = TMPQ1[96,32];
+ # simd shuffle Rd_VPR128.4S = TMPQ2 (@2-1@3-3) lane size 4
+ Rd_VPR128.4S[32,32] = TMPQ2[64,32];
+ Rd_VPR128.4S[96,32] = TMPQ2[96,32];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.404 ZIP2 page C7-2940 line 171547 MATCH x0e007800/mask=xbf20fc00
+# CONSTRUCT x0e007800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@4-0@5-2@6-4@7-6:1 swap &=$shuffle@4-1@5-3@6-5@7-7:1
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@1
+# AUNIT --inst x0e007800/mask=xffe0fc00 --status pass
+
+:zip2 Rd_VPR64.8B, Rn_VPR64.8B, Rm_VPR64.8B
+is b_3131=0 & q=0 & b_2429=0xe & advSIMD3.size=0 & b_2121=0 & Rm_VPR64.8B & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR64.8B & Rd_VPR64.8B & Zd
+{
+ TMPD2 = Rm_VPR64.8B;
+ TMPD1 = Rn_VPR64.8B;
+ # simd shuffle Rd_VPR64.8B = TMPD1 (@4-0@5-2@6-4@7-6) lane size 1
+ Rd_VPR64.8B[0,8] = TMPD1[32,8];
+ Rd_VPR64.8B[16,8] = TMPD1[40,8];
+ Rd_VPR64.8B[32,8] = TMPD1[48,8];
+ Rd_VPR64.8B[48,8] = TMPD1[56,8];
+ # simd shuffle Rd_VPR64.8B = TMPD2 (@4-1@5-3@6-5@7-7) lane size 1
+ Rd_VPR64.8B[8,8] = TMPD2[32,8];
+ Rd_VPR64.8B[24,8] = TMPD2[40,8];
+ Rd_VPR64.8B[40,8] = TMPD2[48,8];
+ Rd_VPR64.8B[56,8] = TMPD2[56,8];
+ zext_zd(Zd); # zero upper 24 bytes of Zd
+}
+
+# C7.2.404 ZIP2 page C7-2940 line 171547 MATCH x0e007800/mask=xbf20fc00
+# CONSTRUCT x4e407800/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO ARG3 =var ARG1 ARG2 =var &=$shuffle@4-0@5-2@6-4@7-6:2 swap &=$shuffle@4-1@5-3@6-5@7-7:2
+# SMACRO(pseudo) ARG1 ARG2 ARG3 =NEON_zip2/2@2
+# AUNIT --inst x4e407800/mask=xffe0fc00 --status pass
+
+:zip2 Rd_VPR128.8H, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0 & q=1 & b_2429=0xe & advSIMD3.size=1 & b_2121=0 & Rm_VPR128.8H & b_1515=0 & b_1214=7 & b_1011=2 & Rn_VPR128.8H & Rd_VPR128.8H & Zd
+{
+ TMPQ2 = Rm_VPR128.8H;
+ TMPQ1 = Rn_VPR128.8H;
+ # simd shuffle Rd_VPR128.8H = TMPQ1 (@4-0@5-2@6-4@7-6) lane size 2
+ Rd_VPR128.8H[0,16] = TMPQ1[64,16];
+ Rd_VPR128.8H[32,16] = TMPQ1[80,16];
+ Rd_VPR128.8H[64,16] = TMPQ1[96,16];
+ Rd_VPR128.8H[96,16] = TMPQ1[112,16];
+ # simd shuffle Rd_VPR128.8H = TMPQ2 (@4-1@5-3@6-5@7-7) lane size 2
+ Rd_VPR128.8H[16,16] = TMPQ2[64,16];
+ Rd_VPR128.8H[48,16] = TMPQ2[80,16];
+ Rd_VPR128.8H[80,16] = TMPQ2[96,16];
+ Rd_VPR128.8H[112,16] = TMPQ2[112,16];
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+
+# C7.2.13 BFCVT page C7-2037 line 118954 MATCH x1e634000/mask=xfffffc00
+# C7.2.69 FCVT page C7-2172 line 126762 MATCH x1e224000/mask=xff3e7c00
+# CONSTRUCT x1e634000/mask=xfffffc00 MATCHED 2 DOCUMENTED OPCODES
+# x1e634000/mask=xfffffc00 NOT MATCHED BY ANY CONSTRUCTOR
+# SMACRO ARG1 ARG2 =float2float/1
+# SMACRO(pseudo) ARG1 ARG2 =NEON_bfcvt/1
+# b_0031=0001111001100011010000..........
+:bfcvt Rd_FPR16, Rn_FPR32
+is b_1031=0b0001111001100011010000 & Rd_FPR16 & Rn_FPR32 & Zd
+{
+ Rd_FPR16 = float2float(Rn_FPR32);
+ zext_zh(Zd); # zero upper 30 bytes of Zd
+}
+
+# C7.2.14 BFCVTN, BFCVTN2 page C7-2038 line 119011 MATCH x0ea16800/mask=xbffffc00
+# CONSTRUCT x0ea16800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# x0ea16800/mask=xbffffc00 NOT MATCHED BY ANY CONSTRUCTOR
+# SMACRO ARG1 ARG2 =var =$float2float@4:8
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtn/2@4
+# b_0031=0.00111010100001011010..........
+
+:bfcvtn Rd_VPR128.4S, Rn_VPR128.4H
+is b_3131=0b0 & Q=0 & b_1029=0b00111010100001011010 & Rn_VPR128.4H & Rd_VPR128.4S & Zd
+{
+ TMPQ1 = Rn_VPR128.4H;
+ # simd resize Rd_VPR128.4S = float2float(TMPQ1) (lane size 4 to 4)
+ Rd_VPR128.4S[0,32] = float2float(TMPQ1[0,32]);
+ Rd_VPR128.4S[32,32] = float2float(TMPQ1[32,32]);
+ Rd_VPR128.4S[64,32] = float2float(TMPQ1[64,32]);
+ Rd_VPR128.4S[96,32] = float2float(TMPQ1[96,32]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.14 BFCVTN, BFCVTN2 page C7-2038 line 119011 MATCH x0ea16800/mask=xbffffc00
+# CONSTRUCT x4ea16800/mask=xfffffc00 MATCHED 1 DOCUMENTED OPCODES
+# x0ea16800/mask=xbffffc00 NOT MATCHED BY ANY CONSTRUCTOR
+# SMACRO ARG1 ARG2 =var =$float2float@4:8
+# SMACRO(pseudo) ARG1 ARG2 &=NEON_fcvtn/2@4
+
+:bfcvtn2 Rd_VPR128.4S, Rn_VPR128.8H
+is b_3131=0b0 & Q=1 & b_1029=0b00111010100001011010 & Rn_VPR128.8H & Rd_VPR128.4S & Zd
+{
+ TMPQ1 = Rn_VPR128.8H;
+ # simd resize Rd_VPR128.4S = float2float(TMPQ1) (lane size 4 to 4)
+ Rd_VPR128.4S[0,32] = float2float(TMPQ1[0,32]);
+ Rd_VPR128.4S[32,32] = float2float(TMPQ1[32,32]);
+ Rd_VPR128.4S[64,32] = float2float(TMPQ1[64,32]);
+ Rd_VPR128.4S[96,32] = float2float(TMPQ1[96,32]);
+ zext_zq(Zd); # zero upper 16 bytes of Zd
+}
+
+# C7.2.15 BFDOT (by element) page C7-2039 line 119080 MATCH x0f40f000/mask=xbfc0f400
+# CONSTRUCT x0f40f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# x0f40f000/mask=xbfc0f400 NOT MATCHED BY ANY CONSTRUCTOR
+# b_0031=0.00111101......1111.0..........
+
+:bfdot Rd_VPR128.2S, Rn_VPR128.4H, , Re_VPR128.H.vIndexHL
+is b_3131=0b0 & Q=0 & b_2229=0b00111101 & Re_VPR128.H.vIndexHL & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.4H & Rd_VPR128.2S
+{
+ Rd_VPR128.2S = NEON_bfdot(Rn_VPR128.4H, Re_VPR128.H.vIndexHL);
+}
+
+# C7.2.15 BFDOT (by element) page C7-2039 line 119080 MATCH x0f40f000/mask=xbfc0f400
+# CONSTRUCT x4f40f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+
+:bfdot Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128.H.vIndexHL
+is b_3131=0b0 & Q=1 & b_2229=0b00111101 & Re_VPR128.H.vIndexHL & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.8H & Rd_VPR128.4S
+{
+ Rd_VPR128.4S = NEON_bfdot(Rn_VPR128.8H, Re_VPR128.H.vIndexHL);
+}
+
+# C7.2.16 BFDOT (vector) page C7-2041 line 119201 MATCH x2e40fc00/mask=xbfe0fc00
+# CONSTRUCT x2e40fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# x2e40fc00/mask=xbfe0fc00 NOT MATCHED BY ANY CONSTRUCTOR
+# b_0031=0.101110010.....111111..........
+
+:bfdot Rd_VPR128.2S, Rn_VPR128.4H, Rm_VPR128.4H
+is b_3131=0b0 & Q=0 & b_2129=0b101110010 & Rm_VPR128.4H & b_1015=0b111111 & Rn_VPR128.4H & Rd_VPR128.2S
+{
+ Rd_VPR128.2S = NEON_bfdot(Rn_VPR128.4H, Rm_VPR128.4H);
+}
+
+# C7.2.16 BFDOT (vector) page C7-2041 line 119201 MATCH x2e40fc00/mask=xbfe0fc00
+# CONSTRUCT x6e40fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+
+:bfdot Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0b0 & Q=1 & b_2129=0b101110010 & Rm_VPR128.8H & b_1015=0b111111 & Rn_VPR128.8H & Rd_VPR128.4S
+{
+ Rd_VPR128.4S = NEON_bfdot(Rn_VPR128.8H, Rm_VPR128.8H);
+}
+
+# C7.2.17 BFMLALB, BFMLALT (by element) page C7-2043 line 119316 MATCH x0fc0f000/mask=xbfc0f400
+# CONSTRUCT x0fc0f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# x0fc0f000/mask=xbfc0f400 NOT MATCHED BY ANY CONSTRUCTOR
+# b_0031=0.00111111......1111.0..........
+
+:bfmlalb Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
+is b_3131=0b0 & Q=0 & b_2229=0b00111111 & Re_VPR128Lo.H.vIndexHLM & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.8H & Rd_VPR128.4S
+{
+ Rd_VPR128.4S = NEON_bfmlalb(Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM);
+}
+
+# C7.2.17 BFMLALB, BFMLALT (by element) page C7-2043 line 119316 MATCH x0fc0f000/mask=xbfc0f400
+# CONSTRUCT x4fc0f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+
+:bfmlalt Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM
+is b_3131=0b0 & Q=1 & b_2229=0b00111111 & Re_VPR128Lo.H.vIndexHLM & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.8H & Rd_VPR128.4S
+{
+ Rd_VPR128.4S = NEON_bfmlalt(Rd_VPR128.4S, Rn_VPR128.8H, Re_VPR128Lo.H.vIndexHLM);
+}
+
+# C7.2.18 BFMLALB, BFMLALT (vector) page C7-2045 line 119401 MATCH x2ec0fc00/mask=xbfe0fc00
+# CONSTRUCT x2ec0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# x2ec0fc00/mask=xbfe0fc00 NOT MATCHED BY ANY CONSTRUCTOR
+# b_0031=0.101110110.....111111..........
+
+:bfmlalb Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0b0 & Q=0 & b_2129=0b101110110 & Rm_VPR128.8H & b_1015=0b111111 & Rn_VPR128.8H & Rd_VPR128.4S
+{
+ Rd_VPR128.4S = NEON_bfmlalb(Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H);
+}
+
+# C7.2.18 BFMLALB, BFMLALT (vector) page C7-2045 line 119401 MATCH x2ec0fc00/mask=xbfe0fc00
+# CONSTRUCT x6ec0fc00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+
+:bfmlalt Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
+is b_3131=0b0 & Q=1 & b_2129=0b101110110 & Rm_VPR128.8H & b_1015=0b111111 & Rn_VPR128.8H & Rd_VPR128.4S
+{
+ Rd_VPR128.4S = NEON_bfmlalt(Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H);
+}
+
+# C7.2.19 BFMMLA page C7-2046 line 119472 MATCH x6e40ec00/mask=xffe0fc00
+# CONSTRUCT x6e40ec00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# x6e40ec00/mask=xffe0fc00 NOT MATCHED BY ANY CONSTRUCTOR
+# b_0031=01101110010.....111011..........
+
+:bfmmla Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H
+is b_2131=0b01101110010 & Rm_VPR128.8H & b_1015=0b111011 & Rn_VPR128.8H & Rd_VPR128.4S
+{
+ Rd_VPR128.4S = NEON_bfmmla(Rd_VPR128.4S, Rn_VPR128.8H, Rm_VPR128.8H);
+}
+
+# C7.2.147 FRINT32X (vector) page C7-2353 line 137678 MATCH x2e21e800/mask=xbfbffc00
+# CONSTRUCT x2e21e800/mask=xbfbffc00 MATCHED 1 DOCUMENTED OPCODES
+# x2e21e800/mask=xbfbffc00 NOT MATCHED BY ANY CONSTRUCTOR
+# b_0031=0.1011100.100001111010..........
+
+:frint32x
+is b_3131=0b0 & Q & b_2329=0b1011100 & b_22 & b_1021=0b100001111010 & Rn & Rd
+unimpl
+
+# C7.2.148 FRINT32X (scalar) page C7-2355 line 137767 MATCH x1e28c000/mask=xffbffc00
+# CONSTRUCT x1e28c000/mask=xffbffc00 MATCHED 1 DOCUMENTED OPCODES
+# x1e28c000/mask=xffbffc00 NOT MATCHED BY ANY CONSTRUCTOR
+# b_0031=000111100.101000110000..........
+
+:frint32x
+is b_2331=0b000111100 & b_22 & b_1021=0b101000110000 & Rn & Rd
+unimpl
+
+# C7.2.149 FRINT32Z (vector) page C7-2357 line 137862 MATCH x0e21e800/mask=xbfbffc00
+# CONSTRUCT x0e21e800/mask=xbfbffc00 MATCHED 1 DOCUMENTED OPCODES
+# x0e21e800/mask=xbfbffc00 NOT MATCHED BY ANY CONSTRUCTOR
+# b_0031=0.0011100.100001111010..........
+
+:frint32z
+is b_3131=0b0 & Q & b_2329=0b0011100 & b_22 & b_1021=0b100001111010 & Rn & Rd
+unimpl
+
+# C7.2.150 FRINT32Z (scalar) page C7-2359 line 137950 MATCH x1e284000/mask=xffbffc00
+# CONSTRUCT x1e284000/mask=xffbffc00 MATCHED 1 DOCUMENTED OPCODES
+# x1e284000/mask=xffbffc00 NOT MATCHED BY ANY CONSTRUCTOR
+# b_0031=000111100.101000010000..........
+
+:frint32z
+is b_2331=0b000111100 & b_22 & b_1021=0b101000010000 & Rn & Rd
+unimpl
+
+# C7.2.151 FRINT64X (vector) page C7-2361 line 138043 MATCH x2e21f800/mask=xbfbffc00
+# CONSTRUCT x2e21f800/mask=xbfbffc00 MATCHED 1 DOCUMENTED OPCODES
+# x2e21f800/mask=xbfbffc00 NOT MATCHED BY ANY CONSTRUCTOR
+# b_0031=0.1011100.100001111110..........
+
+:frint64x
+is b_3131=0b0 & Q & b_2329=0b1011100 & b_22 & b_1021=0b100001111110 & Rn & Rd
+unimpl
+
+# C7.2.152 FRINT64X (scalar) page C7-2363 line 138132 MATCH x1e29c000/mask=xffbffc00
+# CONSTRUCT x1e29c000/mask=xffbffc00 MATCHED 1 DOCUMENTED OPCODES
+# x1e29c000/mask=xffbffc00 NOT MATCHED BY ANY CONSTRUCTOR
+# b_0031=000111100.101001110000..........
+
+:frint64x
+is b_2331=0b000111100 & b_22 & b_1021=0b101001110000 & Rn & Rd
+unimpl
+
+# C7.2.153 FRINT64Z (vector) page C7-2365 line 138227 MATCH x0e21f800/mask=xbfbffc00
+# CONSTRUCT x0e21f800/mask=xbfbffc00 MATCHED 1 DOCUMENTED OPCODES
+# x0e21f800/mask=xbfbffc00 NOT MATCHED BY ANY CONSTRUCTOR
+# b_0031=0.0011100.100001111110..........
+
+:frint64z
+is b_3131=0b0 & Q & b_2329=0b0011100 & b_22 & b_1021=0b100001111110 & Rn & Rd
+unimpl
+
+# C7.2.154 FRINT64Z (scalar) page C7-2367 line 138315 MATCH x1e294000/mask=xffbffc00
+# CONSTRUCT x1e294000/mask=xffbffc00 MATCHED 1 DOCUMENTED OPCODES
+# x1e294000/mask=xffbffc00 NOT MATCHED BY ANY CONSTRUCTOR
+# b_0031=000111100.101001010000..........
+
+:frint64z
+is b_2331=0b000111100 & b_22 & b_1021=0b101001010000 & Rn & Rd
+unimpl
+
+# C7.2.278 SMMLA (vector) page C7-2634 line 153703 MATCH x4e80a400/mask=xffe0fc00
+# CONSTRUCT x4e80a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# x4e80a400/mask=xffe0fc00 NOT MATCHED BY ANY CONSTRUCTOR
+# b_0031=01001110100.....101001..........
+
+:smmla Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B
+is b_2131=0b01001110100 & Rm_VPR128.16B & b_1015=0b101001 & Rn_VPR128.16B & Rd_VPR128.4S
+{
+ Rd_VPR128.4S = NEON_smmla(Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B);
+}
+
+# C7.2.336 SUDOT (by element) page C7-2795 line 163341 MATCH x0f00f000/mask=xbfc0f400
+# CONSTRUCT x0f00f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# x0f00f000/mask=xbfc0f400 NOT MATCHED BY ANY CONSTRUCTOR
+# b_0031=0.00111100......1111.0..........
+
+:sudot Rd_VPR128.2S, Rn_VPR128.8B, Re_VPR128.H.vIndexHL
+is b_3131=0b0 & Q=0 & b_2229=0b00111100 & Re_VPR128.H.vIndexHL & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.8B & Rd_VPR128.2S
+{
+ Rd_VPR128.2S = NEON_sudot(Rd_VPR128.2S, Rn_VPR128.8B, Re_VPR128.H.vIndexHL);
+}
+
+# C7.2.336 SUDOT (by element) page C7-2795 line 163341 MATCH x0f00f000/mask=xbfc0f400
+# CONSTRUCT x4f00f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+
+:sudot Rd_VPR128.4S, Rn_VPR128.16B, Re_VPR128.H.vIndexHL
+is b_3131=0b0 & Q=1 & b_2229=0b00111100 & Re_VPR128.H.vIndexHL & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.16B & Rd_VPR128.4S
+{
+ Rd_VPR128.4S = NEON_sudot(Rd_VPR128.4S, Rn_VPR128.16B, Re_VPR128.H.vIndexHL);
+}
+
+# C7.2.370 UMMLA (vector) page C7-2867 line 167357 MATCH x6e80a400/mask=xffe0fc00
+# CONSTRUCT x6e80a400/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# x6e80a400/mask=xffe0fc00 NOT MATCHED BY ANY CONSTRUCTOR
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_ummla/3@1
+# b_0031=01101110100.....101001..........
+:ummla Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B
+is b_2131=0b01101110100 & Rm_VPR128.16B & b_1015=0b101001 & Rn_VPR128.16B & Rd_VPR128.4S
+{
+ Rd_VPR128.4S = NEON_ummla(Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
+
+# C7.2.388 USDOT (vector) page C7-2907 line 169709 MATCH x0e809c00/mask=xbfe0fc00
+# CONSTRUCT x0e809c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# x0e809c00/mask=xbfe0fc00 NOT MATCHED BY ANY CONSTRUCTOR
+# b_0031=0.001110100.....100111..........
+
+:usdot Rd_VPR128.2S, Rn_VPR128.8B, Rm_VPR128.8B
+is b_3131=0b0 & Q=0 & b_2129=0b001110100 & Rm_VPR128.8B & b_1015=0b100111 & Rn_VPR128.8B & Rd_VPR128.2S
+{
+ Rd_VPR128.2S = NEON_usdot(Rd_VPR128.2S, Rn_VPR128.8B, Rm_VPR128.8B);
+}
+
+# C7.2.388 USDOT (vector) page C7-2907 line 169709 MATCH x0e809c00/mask=xbfe0fc00
+# CONSTRUCT x4e809c00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+
+:usdot Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B
+is b_3131=0b0 & Q=1 & b_2129=0b001110100 & Rn_VPR128.16B & b_1015=0b100111 & Rm_VPR128.16B & Rd_VPR128.4S
+{
+ Rd_VPR128.4S = NEON_usdot(Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B);
+}
+
+# C7.2.389 USDOT (by element) page C7-2909 line 169795 MATCH x0f80f000/mask=xbfc0f400
+# CONSTRUCT x0f80f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+# x0f80f000/mask=xbfc0f400 NOT MATCHED BY ANY CONSTRUCTOR
+# b_0031=0.00111110......1111.0..........
+
+:usdot Rd_VPR128.2S, Rn_VPR128.8B, Re_VPR128.H.vIndexHL
+is b_3131=0b0 & Q=0 & b_2229=0b00111110 & Re_VPR128.H.vIndexHL & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.8B & Rd_VPR128.2S
+{
+ Rd_VPR128.2S = NEON_usdot(Rd_VPR128.2S, Rn_VPR128.8B, Re_VPR128.H.vIndexHL);
+}
+
+# C7.2.389 USDOT (by element) page C7-2909 line 169795 MATCH x0f80f000/mask=xbfc0f400
+# CONSTRUCT x4f80f000/mask=xffc0f400 MATCHED 1 DOCUMENTED OPCODES
+
+:usdot Rd_VPR128.4S, Rn_VPR128.16B, Re_VPR128.H.vIndexHL
+is b_3131=0b0 & Q=1 & b_2229=0b00111110 & Re_VPR128.H.vIndexHL & b_1215=0b1111 & b_1010=0b0 & Rn_VPR128.16B & Rd_VPR128.4S
+{
+ Rd_VPR128.4S = NEON_usdot(Rd_VPR128.4S, Rn_VPR128.16B, Re_VPR128.H.vIndexHL);
+}
+
+# C7.2.393 USMMLA (vector) page C7-2919 line 170338 MATCH x4e80ac00/mask=xffe0fc00
+# CONSTRUCT x4e80ac00/mask=xffe0fc00 MATCHED 1 DOCUMENTED OPCODES
+# SMACRO(pseudo) ARG1 ARG2 ARG3 &=NEON_usmmla/3@1
+# x4e80ac00/mask=xffe0fc00 NOT MATCHED BY ANY CONSTRUCTOR
+# b_0031=01001110100.....101011..........
+:usmmla Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B
+is b_2131=0b01001110100 & Rm_VPR128.16B & b_1015=0b101011 & Rn_VPR128.16B & Rd_VPR128.4S
+{
+ Rd_VPR128.4S = NEON_usmmla(Rd_VPR128.4S, Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
+}
diff --git a/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64sve.sinc b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64sve.sinc
new file mode 100644
index 0000000..958b466
--- /dev/null
+++ b/python/icicle/Ghidra/Processors/AARCH64/data/languages/AARCH64sve.sinc
@@ -0,0 +1,7405 @@
+# INFO This file automatically generated by andre on Mon Apr 30 14:51:39 2018
+# INFO Direct edits to this file may be lost in future updates
+# INFO Command line arguments: ['../../../ProcessorTest/test/andre/scrape/sveit.py', '--sinc']
+
+# abs_z_p_z.xml: ABS variant SVE
+# PATTERN x0416a000/mask=xff3fe000
+
+:abs Zd.T, Pg3_m, Zn.T
+is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m
+{
+ Zd.T = SVE_abs(Zd.T, Pg3_m, Zn.T);
+}
+
+# add_z_p_zz.xml: ADD (vectors, predicated) variant SVE
+# PATTERN x04000000/mask=xff3fe000
+
+:add Zd.T, Pg3_m, Zd.T_2, Zn.T
+is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m
+{
+ Zd.T = SVE_add(Zd.T, Pg3_m, Zd.T_2, Zn.T);
+}
+
+# add_z_zi.xml: ADD (immediate) variant SVE
+# PATTERN x2520c000/mask=xff3fc000
+
+:add Zd.T, Zd.T_2, sve_shf8_1_0to255
+is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b100 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1415=0b11 & sve_sh_13 & sve_imm8_0512 & sve_zdn_0004 & sve_shift_13 & Zd.T & Zd.T_2 & sve_imm8_1_0to255 & sve_shf8_1_0to255
+{
+ Zd.T = SVE_add(Zd.T, Zd.T_2, sve_shf8_1_0to255, sve_shift_13:1);
+}
+
+# add_z_zz.xml: ADD (vectors, unpredicated) variant SVE
+# PATTERN x04200000/mask=xff20fc00
+
+:add Zd.T, Zn.T, Zm.T
+is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b00 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T
+{
+ Zd.T = SVE_add(Zd.T, Zn.T, Zm.T);
+}
+
+# addpl_r_ri.xml: ADDPL variant SVE
+# PATTERN x04605000/mask=xffe0f800
+
+:addpl Rd_GPR64xsp, Rm_GPR64xsp, "#"^sve_imm6_1_m32to31
+is sve_b_2331=0b000001000 & sve_b_22=1 & sve_b_21=1 & sve_rn_1620 & sve_b_1115=0b01010 & sve_imm6_0510 & sve_rd_0004 & Rd_GPR64xsp & Rm_GPR64xsp & sve_imm6_1_m32to31
+{
+ Rd_GPR64xsp = SVE_addpl(Rd_GPR64xsp, Rm_GPR64xsp, sve_imm6_1_m32to31:1);
+}
+
+# addvl_r_ri.xml: ADDVL variant SVE
+# PATTERN x04205000/mask=xffe0f800
+
+:addvl Rd_GPR64xsp, Rm_GPR64xsp, "#"^sve_imm6_1_m32to31
+is sve_b_2331=0b000001000 & sve_b_22=0 & sve_b_21=1 & sve_rn_1620 & sve_b_1115=0b01010 & sve_imm6_0510 & sve_rd_0004 & Rd_GPR64xsp & Rm_GPR64xsp & sve_imm6_1_m32to31
+{
+ Rd_GPR64xsp = SVE_addvl(Rd_GPR64xsp, Rm_GPR64xsp, sve_imm6_1_m32to31:1);
+}
+
+# adr_z_az.xml: ADR variant Packed offsets
+# PATTERN x04a0a000/mask=xffa0f000
+
+:adr Zd.T_sz, [Zn.T_sz, Zm.T_sz^sve_mod_amount]
+is sve_b_2431=0b00000100 & sve_b_23=1 & sve_sz_22 & sve_b_21=1 & sve_zm_1620 & sve_b_1215=0b1010 & sve_msz_1011 & sve_zn_0509 & sve_zd_0004 & sve_mod_amount & Zm.T_sz & Zd.T_sz & Zn.T_sz
+{
+ Zd.T_sz = SVE_adr(Zd.T_sz, Zn.T_sz, Zm.T_sz, sve_mod_amount:1);
+}
+
+# adr_z_az.xml: ADR variant Unpacked 32-bit signed offsets
+# PATTERN x0420a000/mask=xffe0f000
+
+:adr Zd.D, [Zn.D, Zm.D, "sxtw"^sve_msz_1011]
+is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_21=1 & sve_zm_1620 & sve_b_1215=0b1010 & sve_msz_1011 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Zm.D
+{
+ Zd.D = SVE_adr(Zd.D, Zn.D, Zm.D, sve_msz_1011:1);
+}
+
+# adr_z_az.xml: ADR variant Unpacked 32-bit unsigned offsets
+# PATTERN x0460a000/mask=xffe0f000
+
+:adr Zd.D, [Zn.D, Zm.D, "uxtw"^sve_msz_1011]
+is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_21=1 & sve_zm_1620 & sve_b_1215=0b1010 & sve_msz_1011 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Zm.D
+{
+ Zd.D = SVE_adr(Zd.D, Zn.D, Zm.D, sve_msz_1011:1);
+}
+
+# and_p_p_pp.xml: AND, ANDS (predicates) variant Flag setting
+# PATTERN x25404000/mask=xfff0c210
+
+:ands Pd.B, Pg_z, Pn.B, Pm.B
+is sve_b_2431=0b00100101 & sve_b_23=0 & sve_s_22=1 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B
+{
+ Pd.B = SVE_ands(Pd.B, Pg_z, Pn.B, Pm.B);
+}
+
+# and_p_p_pp.xml: AND, ANDS (predicates) variant Not flag setting
+# PATTERN x25004000/mask=xfff0c210
+
+:and Pd.B, Pg_z, Pn.B, Pm.B
+is sve_b_2431=0b00100101 & sve_b_23=0 & sve_s_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B
+{
+ Pd.B = SVE_and(Pd.B, Pg_z, Pn.B, Pm.B);
+}
+
+# and_z_p_zz.xml: AND (vectors, predicated) variant SVE
+# PATTERN x041a0000/mask=xff3fe000
+
+:and Zd.T, Pg3_m, Zd.T_2, Zn.T
+is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m
+{
+ Zd.T = SVE_and(Zd.T, Pg3_m, Zd.T_2, Zn.T);
+}
+
+# and_z_zi.xml: AND (immediate) variant SVE
+# PATTERN x05800000/mask=xfffc0000
+
+:and Zd.T_imm13, Zd.T_imm13_2, "#"^sve_decode_bit_mask
+is sve_b_2431=0b00000101 & sve_b_23=1 & sve_b_22=0 & sve_b_1821=0b0000 & sve_imm13_0517 & sve_zdn_0004 & sve_decode_bit_mask & Zd.T_imm13 & Zd.T_imm13_2
+{
+ Zd.T_imm13 = SVE_and(Zd.T_imm13, Zd.T_imm13_2, sve_decode_bit_mask:1);
+}
+
+# and_z_zz.xml: AND (vectors, unpredicated) variant SVE
+# PATTERN x04203000/mask=xffe0fc00
+
+:and Zd.D, Zn.D, Zm.D
+is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_21=1 & sve_zm_1620 & sve_b_1015=0b001100 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Zm.D
+{
+ Zd.D = SVE_and(Zd.D, Zn.D, Zm.D);
+}
+
+# andv_r_p_z.xml: ANDV variant SVE
+# PATTERN x041a2000/mask=xff3fe000
+
+:andv Rd_FPR8, Pg3, Zn.T
+is sve_b_2431=0b00000100 & sve_size_2223=0b00 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3
+{
+ Rd_FPR8 = SVE_andv(Rd_FPR8, Pg3, Zn.T);
+}
+
+# andv_r_p_z.xml: ANDV variant SVE
+# PATTERN x041a2000/mask=xff3fe000
+
+:andv Rd_FPR32, Pg3, Zn.T
+is sve_b_2431=0b00000100 & sve_size_2223=0b10 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3
+{
+ Rd_FPR32 = SVE_andv(Rd_FPR32, Pg3, Zn.T);
+}
+
+# andv_r_p_z.xml: ANDV variant SVE
+# PATTERN x041a2000/mask=xff3fe000
+
+:andv Rd_FPR16, Pg3, Zn.T
+is sve_b_2431=0b00000100 & sve_size_2223=0b01 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3
+{
+ Rd_FPR16 = SVE_andv(Rd_FPR16, Pg3, Zn.T);
+}
+
+# andv_r_p_z.xml: ANDV variant SVE
+# PATTERN x041a2000/mask=xff3fe000
+
+:andv Rd_FPR64, Pg3, Zn.T
+is sve_b_2431=0b00000100 & sve_size_2223=0b11 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3
+{
+ Rd_FPR64 = SVE_andv(Rd_FPR64, Pg3, Zn.T);
+}
+
+# asr_z_p_zi.xml: ASR (immediate, predicated) variant SVE
+# PATTERN x04008000/mask=xff3fe000
+
+:asr Zd.T_tszh, Pg3_m, Zd.T_tszh_2, "#"^sve_imm_shift
+is sve_b_2431=0b00000100 & sve_tszh_2223 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_tszl_0809 & sve_imm3_0507 & sve_zdn_0004 & sve_imm_shift & Zd.T_tszh & Zd.T_tszh_2 & Pg3_m
+{
+ Zd.T_tszh = SVE_asr(Zd.T_tszh, Pg3_m, Zd.T_tszh_2, sve_imm_shift:1);
+}
+
+# asr_z_p_zw.xml: ASR (wide elements, predicated) variant SVE
+# PATTERN x04188000/mask=xff3fe000
+
+:asr Zd.T, Pg3_m, Zd.T_2, Zn.D
+is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Pg3_m & Zn.D
+{
+ Zd.T = SVE_asr(Zd.T, Pg3_m, Zd.T_2, Zn.D);
+}
+
+# asr_z_p_zz.xml: ASR (vectors) variant SVE
+# PATTERN x04108000/mask=xff3fe000
+
+:asr Zd.T, Pg3_m, Zd.T_2, Zn.T
+is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m
+{
+ Zd.T = SVE_asr(Zd.T, Pg3_m, Zd.T_2, Zn.T);
+}
+
+# asr_z_zi.xml: ASR (immediate, unpredicated) variant SVE
+# PATTERN x04209000/mask=xff20fc00
+
+:asr Zd.T_tszh, Zn.T_tszh, "#"^sve_imm_shift
+is sve_b_2431=0b00000100 & sve_tszh_2223 & sve_b_21=1 & sve_tszl_1920 & sve_imm3_1618 & sve_b_1215=0b1001 & sve_b_11=0 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & sve_imm_shift & Zd.T_tszh & Zn.T_tszh
+{
+ Zd.T_tszh = SVE_asr(Zd.T_tszh, Zn.T_tszh, sve_imm_shift:1);
+}
+
+# asr_z_zw.xml: ASR (wide elements, unpredicated) variant SVE
+# PATTERN x04208000/mask=xff20fc00
+
+:asr Zd.T, Zn.T, Zm.D
+is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_1215=0b1000 & sve_b_11=0 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Zm.D
+{
+ Zd.T = SVE_asr(Zd.T, Zn.T, Zm.D);
+}
+
+# asrd_z_p_zi.xml: ASRD variant SVE
+# PATTERN x04048000/mask=xff3fe000
+
+:asrd Zd.T_tszh, Pg3_m, Zd.T_tszh_2, "#"^sve_imm_shift
+is sve_b_2431=0b00000100 & sve_tszh_2223 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_tszl_0809 & sve_imm3_0507 & sve_zdn_0004 & sve_imm_shift & Zd.T_tszh & Zd.T_tszh_2 & Pg3_m
+{
+ Zd.T_tszh = SVE_asrd(Zd.T_tszh, Pg3_m, Zd.T_tszh_2, sve_imm_shift:1);
+}
+
+# asrr_z_p_zz.xml: ASRR variant SVE
+# PATTERN x04148000/mask=xff3fe000
+
+:asrr Zd.T, Pg3_m, Zd.T_2, Zn.T
+is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b010 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m
+{
+ Zd.T = SVE_asrr(Zd.T, Pg3_m, Zd.T_2, Zn.T);
+}
+
+# bic_and_z_zi.xml: BIC (immediate) variant SVE
+# ALIASEDBY AND ., ., #(- - 1) if Never
+# PATTERN x05800000/mask=xfffc0000
+
+# SKIPPING bic_and_z_zi.xml because x05800000/mask=xfffc0000 has already been defined
+
+# bic_p_p_pp.xml: BIC, BICS (predicates) variant Flag setting
+# PATTERN x25404010/mask=xfff0c210
+
+:bics Pd.B, Pg_z, Pn.B, Pm.B
+is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=1 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B
+{
+ Pd.B = SVE_bics(Pd.B, Pg_z, Pn.B, Pm.B);
+}
+
+# bic_p_p_pp.xml: BIC, BICS (predicates) variant Not flag setting
+# PATTERN x25004010/mask=xfff0c210
+
+:bic Pd.B, Pg_z, Pn.B, Pm.B
+is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=1 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B
+{
+ Pd.B = SVE_bic(Pd.B, Pg_z, Pn.B, Pm.B);
+}
+
+# bic_z_p_zz.xml: BIC (vectors, predicated) variant SVE
+# PATTERN x041b0000/mask=xff3fe000
+
+:bic Zd.T, Pg3_m, Zd.T_2, Zn.T
+is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=1 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m
+{
+ Zd.T = SVE_bic(Zd.T, Pg3_m, Zd.T_2, Zn.T);
+}
+
+# bic_z_zz.xml: BIC (vectors, unpredicated) variant SVE
+# PATTERN x04e03000/mask=xffe0fc00
+
+:bic Zd.D, Zn.D, Zm.D
+is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_zm_1620 & sve_b_1015=0b001100 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Zm.D
+{
+ Zd.D = SVE_bic(Zd.D, Zn.D, Zm.D);
+}
+
+# brka_p_p_p.xml: BRKA, BRKAS variant Flag setting
+# PATTERN x25504000/mask=xffffc210
+
+:brkas Pd.B, Pg_z, Pn.B
+is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1421=0b01000001 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B
+{
+ Pd.B = SVE_brkas(Pd.B, Pg_z, Pn.B);
+}
+
+# brka_p_p_p.xml: BRKA, BRKAS variant Not flag setting
+# PATTERN x25104000/mask=xffffc200
+
+:brka Pd.B, Pg_zm, Pn.B
+is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=0 & sve_b_1421=0b01000001 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_m_04 & sve_pd_0003 & Pg_zm & Pd.B & Pn.B
+{
+ Pd.B = SVE_brka(Pd.B, Pg_zm, Pn.B);
+}
+
+# brkb_p_p_p.xml: BRKB, BRKBS variant Flag setting
+# PATTERN x25d04000/mask=xffffc210
+
+:brkbs Pd.B, Pg_z, Pn.B
+is sve_b_2431=0b00100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1421=0b01000001 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B
+{
+ Pd.B = SVE_brkbs(Pd.B, Pg_z, Pn.B);
+}
+
+# brkb_p_p_p.xml: BRKB, BRKBS variant Not flag setting
+# PATTERN x25904000/mask=xffffc200
+
+:brkb Pd.B, Pg_zm, Pn.B
+is sve_b_2431=0b00100101 & sve_b_23=1 & sve_b_22=0 & sve_b_1421=0b01000001 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_m_04 & sve_pd_0003 & Pg_zm & Pd.B & Pn.B
+{
+ Pd.B = SVE_brkb(Pd.B, Pg_zm, Pn.B);
+}
+
+# brkn_p_p_pp.xml: BRKN, BRKNS variant Flag setting
+# PATTERN x25584000/mask=xffffc210
+
+:brkns Pd.B, Pg_z, Pn.B, Pd.B_2
+is sve_b_2331=0b001001010 & sve_b_22=1 & sve_b_1421=0b01100001 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pdm_0003 & Pd.B & Pd.B_2 & Pg_z & Pn.B
+{
+ Pd.B = SVE_brkns(Pd.B, Pg_z, Pn.B, Pd.B_2);
+}
+
+# brkn_p_p_pp.xml: BRKN, BRKNS variant Not flag setting
+# PATTERN x25184000/mask=xffffc210
+
+:brkn Pd.B, Pg_z, Pn.B, Pd.B_2
+is sve_b_2331=0b001001010 & sve_b_22=0 & sve_b_1421=0b01100001 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pdm_0003 & Pd.B & Pd.B_2 & Pg_z & Pn.B
+{
+ Pd.B = SVE_brkn(Pd.B, Pg_z, Pn.B, Pd.B_2);
+}
+
+# brkpa_p_p_pp.xml: BRKPA, BRKPAS variant Flag setting
+# PATTERN x2540c000/mask=xfff0c210
+
+:brkpas Pd.B, Pg_z, Pn.B, Pm.B
+is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b11 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B
+{
+ Pd.B = SVE_brkpas(Pd.B, Pg_z, Pn.B, Pm.B);
+}
+
+# brkpa_p_p_pp.xml: BRKPA, BRKPAS variant Not flag setting
+# PATTERN x2500c000/mask=xfff0c210
+
+:brkpa Pd.B, Pg_z, Pn.B, Pm.B
+is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b11 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B
+{
+ Pd.B = SVE_brkpa(Pd.B, Pg_z, Pn.B, Pm.B);
+}
+
+# brkpb_p_p_pp.xml: BRKPB, BRKPBS variant Flag setting
+# PATTERN x2540c010/mask=xfff0c210
+
+:brkpbs Pd.B, Pg_z, Pn.B, Pm.B
+is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b11 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=1 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B
+{
+ Pd.B = SVE_brkpbs(Pd.B, Pg_z, Pn.B, Pm.B);
+}
+
+# brkpb_p_p_pp.xml: BRKPB, BRKPBS variant Not flag setting
+# PATTERN x2500c010/mask=xfff0c210
+
+:brkpb Pd.B, Pg_z, Pn.B, Pm.B
+is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b11 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_b_04=1 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B
+{
+ Pd.B = SVE_brkpb(Pd.B, Pg_z, Pn.B, Pm.B);
+}
+
+# clasta_r_p_z.xml: CLASTA (scalar) variant SVE
+# PATTERN x0530a000/mask=xff3fe000
+
+:clasta Rd_GPR64, Pg3, Rd_GPR64_2, Zn.T
+is sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1721=0b11000 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zm_0509 & sve_rdn_0004 & Zn.T & Rd_GPR64 & Rd_GPR64_2 & Pg3
+{
+ Rd_GPR64 = SVE_clasta(Rd_GPR64, Pg3, Rd_GPR64_2, Zn.T);
+}
+
+# clasta_r_p_z.xml: CLASTA (scalar) variant SVE
+# PATTERN x0530a000/mask=xff3fe000
+
+:clasta Rd_GPR32, Pg3, Rd_GPR32_2, Zn.T
+is sve_b_2431=0b00000101 & (b_23=0 | b_22=0) & sve_b_1721=0b11000 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zm_0509 & sve_rdn_0004 & Zn.T & Rd_GPR32 & Rd_GPR32_2 & Pg3
+{
+ Rd_GPR32 = SVE_clasta(Rd_GPR32, Pg3, Rd_GPR32_2, Zn.T);
+}
+
+# clasta_v_p_z.xml: CLASTA (SIMD&FP scalar) variant SVE
+# PATTERN x052a8000/mask=xff3fe000
+
+:clasta Rd_FPR8, Pg3, Rd_FPR8_2, Zn.T
+is sve_b_2431=0b00000101 & sve_size_2223=0b00 & sve_b_1721=0b10101 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR8 & Rd_FPR8_2 & Pg3
+{
+ Rd_FPR8 = SVE_clasta(Rd_FPR8, Pg3, Rd_FPR8_2, Zn.T);
+}
+
+# clasta_v_p_z.xml: CLASTA (SIMD&FP scalar) variant SVE
+# PATTERN x052a8000/mask=xff3fe000
+
+:clasta Rd_FPR32, Pg3, Rd_FPR32_2, Zn.T
+is sve_b_2431=0b00000101 & sve_size_2223=0b10 & sve_b_1721=0b10101 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR32 & Rd_FPR32_2 & Pg3
+{
+ Rd_FPR32 = SVE_clasta(Rd_FPR32, Pg3, Rd_FPR32_2, Zn.T);
+}
+
+# clasta_v_p_z.xml: CLASTA (SIMD&FP scalar) variant SVE
+# PATTERN x052a8000/mask=xff3fe000
+
+:clasta Rd_FPR16, Pg3, Rd_FPR16_2, Zn.T
+is sve_b_2431=0b00000101 & sve_size_2223=0b01 & sve_b_1721=0b10101 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR16 & Rd_FPR16_2 & Pg3
+{
+ Rd_FPR16 = SVE_clasta(Rd_FPR16, Pg3, Rd_FPR16_2, Zn.T);
+}
+
+# clasta_v_p_z.xml: CLASTA (SIMD&FP scalar) variant SVE
+# PATTERN x052a8000/mask=xff3fe000
+
+:clasta Rd_FPR64, Pg3, Rd_FPR64_2, Zn.T
+is sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1721=0b10101 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR64 & Rd_FPR64_2 & Pg3
+{
+ Rd_FPR64 = SVE_clasta(Rd_FPR64, Pg3, Rd_FPR64_2, Zn.T);
+}
+
+# clasta_z_p_zz.xml: CLASTA (vectors) variant SVE
+# PATTERN x05288000/mask=xff3fe000
+
+:clasta Zd.T, Pg3, Zd.T_2, Zn.T
+is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1721=0b10100 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3
+{
+ Zd.T = SVE_clasta(Zd.T, Pg3, Zd.T_2, Zn.T);
+}
+
+# clastb_r_p_z.xml: CLASTB (scalar) variant SVE
+# PATTERN x0531a000/mask=xff3fe000
+
+:clastb Rd_GPR64, Pg3, Rd_GPR64_2, Zn.T
+is sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1721=0b11000 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zm_0509 & sve_rdn_0004 & Zn.T & Rd_GPR64 & Rd_GPR64_2 & Pg3
+{
+ Rd_GPR64 = SVE_clastb(Rd_GPR64, Pg3, Rd_GPR64_2, Zn.T);
+}
+
+# clastb_r_p_z.xml: CLASTB (scalar) variant SVE
+# PATTERN x0531a000/mask=xff3fe000
+
+:clastb Rd_GPR32, Pg3, Rd_GPR32_2, Zn.T
+is sve_b_2431=0b00000101 & (b_23=0 | b_22=0) & sve_b_1721=0b11000 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zm_0509 & sve_rdn_0004 & Zn.T & Rd_GPR32 & Rd_GPR32_2 & Pg3
+{
+ Rd_GPR32 = SVE_clastb(Rd_GPR32, Pg3, Rd_GPR32_2, Zn.T);
+}
+
+# clastb_v_p_z.xml: CLASTB (SIMD&FP scalar) variant SVE
+# PATTERN x052b8000/mask=xff3fe000
+
+:clastb Rd_FPR8, Pg3, Rd_FPR8_2, Zn.T
+is sve_b_2431=0b00000101 & sve_size_2223=0b00 & sve_b_1721=0b10101 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR8 & Rd_FPR8_2 & Pg3
+{
+ Rd_FPR8 = SVE_clastb(Rd_FPR8, Pg3, Rd_FPR8_2, Zn.T);
+}
+
+# clastb_v_p_z.xml: CLASTB (SIMD&FP scalar) variant SVE
+# PATTERN x052b8000/mask=xff3fe000
+
+:clastb Rd_FPR32, Pg3, Rd_FPR32_2, Zn.T
+is sve_b_2431=0b00000101 & sve_size_2223=0b10 & sve_b_1721=0b10101 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR32 & Rd_FPR32_2 & Pg3
+{
+ Rd_FPR32 = SVE_clastb(Rd_FPR32, Pg3, Rd_FPR32_2, Zn.T);
+}
+
+# clastb_v_p_z.xml: CLASTB (SIMD&FP scalar) variant SVE
+# PATTERN x052b8000/mask=xff3fe000
+
+:clastb Rd_FPR16, Pg3, Rd_FPR16_2, Zn.T
+is sve_b_2431=0b00000101 & sve_size_2223=0b01 & sve_b_1721=0b10101 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR16 & Rd_FPR16_2 & Pg3
+{
+ Rd_FPR16 = SVE_clastb(Rd_FPR16, Pg3, Rd_FPR16_2, Zn.T);
+}
+
+# clastb_v_p_z.xml: CLASTB (SIMD&FP scalar) variant SVE
+# PATTERN x052b8000/mask=xff3fe000
+
+:clastb Rd_FPR64, Pg3, Rd_FPR64_2, Zn.T
+is sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1721=0b10101 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR64 & Rd_FPR64_2 & Pg3
+{
+ Rd_FPR64 = SVE_clastb(Rd_FPR64, Pg3, Rd_FPR64_2, Zn.T);
+}
+
+# clastb_z_p_zz.xml: CLASTB (vectors) variant SVE
+# PATTERN x05298000/mask=xff3fe000
+
+:clastb Zd.T, Pg3, Zd.T_2, Zn.T
+is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_1721=0b10100 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3
+{
+ Zd.T = SVE_clastb(Zd.T, Pg3, Zd.T_2, Zn.T);
+}
+
+# cls_z_p_z.xml: CLS variant SVE
+# PATTERN x0418a000/mask=xff3fe000
+
+:cls Zd.T, Pg3_m, Zn.T
+is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m
+{
+ Zd.T = SVE_cls(Zd.T, Pg3_m, Zn.T);
+}
+
+# clz_z_p_z.xml: CLZ variant SVE
+# PATTERN x0419a000/mask=xff3fe000
+
+:clz Zd.T, Pg3_m, Zn.T
+is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m
+{
+ Zd.T = SVE_clz(Zd.T, Pg3_m, Zn.T);
+}
+
+# cmpeq_p_p_zi.xml: CMP (immediate) variant Equal
+# PATTERN x25008000/mask=xff20e010
+
+:cmpeq Pd.T, Pg3_z, Zn.T, "#"^sve_imm5s_1620
+is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=0 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & sve_imm5s_1620
+{
+ Pd.T = SVE_cmpeq(Pd.T, Pg3_z, Zn.T, sve_imm5s_1620:1);
+}
+
+# cmpeq_p_p_zi.xml: CMP (immediate) variant Greater than
+# PATTERN x25000010/mask=xff20e010
+
+:cmpgt Pd.T, Pg3_z, Zn.T, "#"^sve_imm5s_1620
+is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=0 & sve_imm5_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & sve_imm5s_1620
+{
+ Pd.T = SVE_cmpgt(Pd.T, Pg3_z, Zn.T, sve_imm5s_1620:1);
+}
+
+# cmpeq_p_p_zi.xml: CMP (immediate) variant Greater than or equal
+# PATTERN x25000000/mask=xff20e010
+
+:cmpge Pd.T, Pg3_z, Zn.T, "#"^sve_imm5s_1620
+is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=0 & sve_imm5_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & sve_imm5s_1620
+{
+ Pd.T = SVE_cmpge(Pd.T, Pg3_z, Zn.T, sve_imm5s_1620:1);
+}
+
+# cmpeq_p_p_zi.xml: CMP (immediate) variant Higher
+# PATTERN x24200010/mask=xff202010
+
+:cmphi Pd.T, Pg3_z, Zn.T, "#"^sve_imm7_1420
+is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=1 & sve_imm7_1420 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z
+{
+ Pd.T = SVE_cmphi(Pd.T, Pg3_z, Zn.T, sve_imm7_1420:1);
+}
+
+# cmpeq_p_p_zi.xml: CMP (immediate) variant Higher or same
+# PATTERN x24200000/mask=xff202010
+
+:cmphs Pd.T, Pg3_z, Zn.T, "#"^sve_imm7_1420
+is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=1 & sve_imm7_1420 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z
+{
+ Pd.T = SVE_cmphs(Pd.T, Pg3_z, Zn.T, sve_imm7_1420:1);
+}
+
+# cmpeq_p_p_zi.xml: CMP (immediate) variant Less than
+# PATTERN x25002000/mask=xff20e010
+
+:cmplt Pd.T, Pg3_z, Zn.T, "#"^sve_imm5s_1620
+is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=0 & sve_imm5_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & sve_imm5s_1620
+{
+ Pd.T = SVE_cmplt(Pd.T, Pg3_z, Zn.T, sve_imm5s_1620:1);
+}
+
+# cmpeq_p_p_zi.xml: CMP (immediate) variant Less than or equal
+# PATTERN x25002010/mask=xff20e010
+
+:cmple Pd.T, Pg3_z, Zn.T, "#"^sve_imm5s_1620
+is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=0 & sve_imm5_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & sve_imm5s_1620
+{
+ Pd.T = SVE_cmple(Pd.T, Pg3_z, Zn.T, sve_imm5s_1620:1);
+}
+
+# cmpeq_p_p_zi.xml: CMP (immediate) variant Lower
+# PATTERN x24202000/mask=xff202010
+
+:cmplo Pd.T, Pg3_z, Zn.T, "#"^sve_imm7_1420
+is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=1 & sve_imm7_1420 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z
+{
+ Pd.T = SVE_cmplo(Pd.T, Pg3_z, Zn.T, sve_imm7_1420:1);
+}
+
+# cmpeq_p_p_zi.xml: CMP (immediate) variant Lower or same
+# PATTERN x24202010/mask=xff202010
+
+:cmpls Pd.T, Pg3_z, Zn.T, "#"^sve_imm7_1420
+is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=1 & sve_imm7_1420 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z
+{
+ Pd.T = SVE_cmpls(Pd.T, Pg3_z, Zn.T, sve_imm7_1420:1);
+}
+
+# cmpeq_p_p_zi.xml: CMP (immediate) variant Not equal
+# PATTERN x25008010/mask=xff20e010
+
+:cmpne Pd.T, Pg3_z, Zn.T, "#"^sve_imm5s_1620
+is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_21=0 & sve_imm5_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & sve_imm5s_1620
+{
+ Pd.T = SVE_cmpne(Pd.T, Pg3_z, Zn.T, sve_imm5s_1620:1);
+}
+
+# cmpeq_p_p_zw.xml: CMP (wide elements) variant Equal
+# PATTERN x24002000/mask=xff20e010
+
+:cmpeq Pd.T, Pg3_z, Zn.T, Zm.D
+is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D
+{
+ Pd.T = SVE_cmpeq(Pd.T, Pg3_z, Zn.T, Zm.D);
+}
+
+# cmpeq_p_p_zw.xml: CMP (wide elements) variant Greater than
+# PATTERN x24004010/mask=xff20e010
+
+:cmpgt Pd.T, Pg3_z, Zn.T, Zm.D
+is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D
+{
+ Pd.T = SVE_cmpgt(Pd.T, Pg3_z, Zn.T, Zm.D);
+}
+
+# cmpeq_p_p_zw.xml: CMP (wide elements) variant Greater than or equal
+# PATTERN x24004000/mask=xff20e010
+
+:cmpge Pd.T, Pg3_z, Zn.T, Zm.D
+is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D
+{
+ Pd.T = SVE_cmpge(Pd.T, Pg3_z, Zn.T, Zm.D);
+}
+
+# cmpeq_p_p_zw.xml: CMP (wide elements) variant Higher
+# PATTERN x2400c010/mask=xff20e010
+
+:cmphi Pd.T, Pg3_z, Zn.T, Zm.D
+is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D
+{
+ Pd.T = SVE_cmphi(Pd.T, Pg3_z, Zn.T, Zm.D);
+}
+
+# cmpeq_p_p_zw.xml: CMP (wide elements) variant Higher or same
+# PATTERN x2400c000/mask=xff20e010
+
+:cmphs Pd.T, Pg3_z, Zn.T, Zm.D
+is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D
+{
+ Pd.T = SVE_cmphs(Pd.T, Pg3_z, Zn.T, Zm.D);
+}
+
+# cmpeq_p_p_zw.xml: CMP (wide elements) variant Less than
+# PATTERN x24006000/mask=xff20e010
+
+:cmplt Pd.T, Pg3_z, Zn.T, Zm.D
+is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D
+{
+ Pd.T = SVE_cmplt(Pd.T, Pg3_z, Zn.T, Zm.D);
+}
+
+# cmpeq_p_p_zw.xml: CMP (wide elements) variant Less than or equal
+# PATTERN x24006010/mask=xff20e010
+
+:cmple Pd.T, Pg3_z, Zn.T, Zm.D
+is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D
+{
+ Pd.T = SVE_cmple(Pd.T, Pg3_z, Zn.T, Zm.D);
+}
+
+# cmpeq_p_p_zw.xml: CMP (wide elements) variant Lower
+# PATTERN x2400e000/mask=xff20e010
+
+:cmplo Pd.T, Pg3_z, Zn.T, Zm.D
+is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D
+{
+ Pd.T = SVE_cmplo(Pd.T, Pg3_z, Zn.T, Zm.D);
+}
+
+# cmpeq_p_p_zw.xml: CMP (wide elements) variant Lower or same
+# PATTERN x2400e010/mask=xff20e010
+
+:cmpls Pd.T, Pg3_z, Zn.T, Zm.D
+is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D
+{
+ Pd.T = SVE_cmpls(Pd.T, Pg3_z, Zn.T, Zm.D);
+}
+
+# cmpeq_p_p_zw.xml: CMP (wide elements) variant Not equal
+# PATTERN x24002010/mask=xff20e010
+
+:cmpne Pd.T, Pg3_z, Zn.T, Zm.D
+is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z & Zm.D
+{
+ Pd.T = SVE_cmpne(Pd.T, Pg3_z, Zn.T, Zm.D);
+}
+
+# cmpeq_p_p_zz.xml: CMP (vectors) variant Equal
+# PATTERN x2400a000/mask=xff20e010
+
+:cmpeq Pd.T, Pg3_z, Zn.T, Zm.T
+is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z
+{
+ Pd.T = SVE_cmpeq(Pd.T, Pg3_z, Zn.T, Zm.T);
+}
+
+# cmpeq_p_p_zz.xml: CMP (vectors) variant Greater than
+# PATTERN x24008010/mask=xff20e010
+
+:cmpgt Pd.T, Pg3_z, Zn.T, Zm.T
+is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z
+{
+ Pd.T = SVE_cmpgt(Pd.T, Pg3_z, Zn.T, Zm.T);
+}
+
+# cmpeq_p_p_zz.xml: CMP (vectors) variant Greater than or equal
+# PATTERN x24008000/mask=xff20e010
+
+:cmpge Pd.T, Pg3_z, Zn.T, Zm.T
+is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z
+{
+ Pd.T = SVE_cmpge(Pd.T, Pg3_z, Zn.T, Zm.T);
+}
+
+# cmpeq_p_p_zz.xml: CMP (vectors) variant Higher
+# PATTERN x24000010/mask=xff20e010
+
+:cmphi Pd.T, Pg3_z, Zn.T, Zm.T
+is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z
+{
+ Pd.T = SVE_cmphi(Pd.T, Pg3_z, Zn.T, Zm.T);
+}
+
+# cmpeq_p_p_zz.xml: CMP (vectors) variant Higher or same
+# PATTERN x24000000/mask=xff20e010
+
+:cmphs Pd.T, Pg3_z, Zn.T, Zm.T
+is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z
+{
+ Pd.T = SVE_cmphs(Pd.T, Pg3_z, Zn.T, Zm.T);
+}
+
+# cmpeq_p_p_zz.xml: CMP (vectors) variant Not equal
+# PATTERN x2400a010/mask=xff20e010
+
+:cmpne Pd.T, Pg3_z, Zn.T, Zm.T
+is sve_b_2431=0b00100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z
+{
+ Pd.T = SVE_cmpne(Pd.T, Pg3_z, Zn.T, Zm.T);
+}
+
+# cmple_cmpeq_p_p_zz.xml: CMPLE (vectors) variant Greater than or equal
+# ALIASEDBY CMPGE ., /Z, ., . if Never
+# PATTERN x24008000/mask=xff20e010
+
+# SKIPPING cmple_cmpeq_p_p_zz.xml because x24008000/mask=xff20e010 has already been defined
+
+# cmplo_cmpeq_p_p_zz.xml: CMPLO (vectors) variant Higher
+# ALIASEDBY CMPHI ., /Z, ., . if Never
+# PATTERN x24000010/mask=xff20e010
+
+# SKIPPING cmplo_cmpeq_p_p_zz.xml because x24000010/mask=xff20e010 has already been defined
+
+# cmpls_cmpeq_p_p_zz.xml: CMPLS (vectors) variant Higher or same
+# ALIASEDBY CMPHS ., /Z, ., . if Never
+# PATTERN x24000000/mask=xff20e010
+
+# SKIPPING cmpls_cmpeq_p_p_zz.xml because x24000000/mask=xff20e010 has already been defined
+
+# cmplt_cmpeq_p_p_zz.xml: CMPLT (vectors) variant Greater than
+# ALIASEDBY CMPGT ., /Z, ., . if Never
+# PATTERN x24008010/mask=xff20e010
+
+# SKIPPING cmplt_cmpeq_p_p_zz.xml because x24008010/mask=xff20e010 has already been defined
+
+# cnot_z_p_z.xml: CNOT variant SVE
+# PATTERN x041ba000/mask=xff3fe000
+
+:cnot Zd.T, Pg3_m, Zn.T
+is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m
+{
+ Zd.T = SVE_cnot(Zd.T, Pg3_m, Zn.T);
+}
+
+# cnt_z_p_z.xml: CNT variant SVE
+# PATTERN x041aa000/mask=xff3fe000
+
+:cnt Zd.T, Pg3_m, Zn.T
+is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b01 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m
+{
+ Zd.T = SVE_cnt(Zd.T, Pg3_m, Zn.T);
+}
+
+# cntb_r_s.xml: CNTB, CNTD, CNTH, CNTW variant Byte
+# PATTERN x0420e000/mask=xfff0fc00
+
+:cntb Rd_GPR64^sve_mul_pattern
+is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=0 & sve_pattern_0509 & sve_rd_0004 & sve_pattern & sve_imm4_1_1to16 & Rd_GPR64 & sve_mul_pattern
+{
+ Rd_GPR64 = SVE_cntb(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);
+}
+
+# cntb_r_s.xml: CNTB, CNTD, CNTH, CNTW variant Doubleword
+# PATTERN x04e0e000/mask=xfff0fc00
+
+:cntd Rd_GPR64^sve_mul_pattern
+is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=0 & sve_pattern_0509 & sve_rd_0004 & sve_pattern & sve_imm4_1_1to16 & Rd_GPR64 & sve_mul_pattern
+{
+ Rd_GPR64 = SVE_cntd(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);
+}
+
+# cntb_r_s.xml: CNTB, CNTD, CNTH, CNTW variant Halfword
+# PATTERN x0460e000/mask=xfff0fc00
+
+:cnth Rd_GPR64^sve_mul_pattern
+is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=0 & sve_pattern_0509 & sve_rd_0004 & sve_pattern & sve_imm4_1_1to16 & Rd_GPR64 & sve_mul_pattern
+{
+ Rd_GPR64 = SVE_cnth(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);
+}
+
+# cntb_r_s.xml: CNTB, CNTD, CNTH, CNTW variant Word
+# PATTERN x04a0e000/mask=xfff0fc00
+
+:cntw Rd_GPR64^sve_mul_pattern
+is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b10 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=0 & sve_pattern_0509 & sve_rd_0004 & sve_pattern & sve_imm4_1_1to16 & Rd_GPR64 & sve_mul_pattern
+{
+ Rd_GPR64 = SVE_cntw(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);
+}
+
+# cntp_r_p_p.xml: CNTP variant SVE
+# PATTERN x25208000/mask=xff3fc200
+
+:cntp Rd_GPR64, Pg, Pn.T
+is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b100 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1415=0b10 & sve_pg_1013 & sve_b_09=0 & sve_pn_0508 & sve_rd_0004 & Pn.T & Rd_GPR64 & Pg
+{
+ Rd_GPR64 = SVE_cntp(Rd_GPR64, Pn.T, Pg);
+}
+
+# compact_z_p_z.xml: COMPACT variant SVE
+# PATTERN x05a18000/mask=xffbfe000
+
+:compact Zd.T_sz, Pg3, Zn.T_sz
+is sve_b_2331=0b000001011 & sve_sz_22 & sve_b_1321=0b100001100 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T_sz & Zn.T_sz & Pg3
+{
+ Zd.T_sz = SVE_compact(Zd.T_sz, Pg3, Zn.T_sz);
+}
+
+# cpy_z_p_i.xml: CPY (immediate) variant SVE
+# PATTERN x05100000/mask=xff308000
+
+:cpy Zd.T, Pm_zm, sve_shf8_1_m128to127
+is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_2021=0b01 & sve_pg_1619 & sve_b_15=0 & sve_m_14 & sve_sh_13 & sve_imm8_0512 & sve_zd_0004 & sve_shift_13 & Pm_zm & Zd.T & sve_imm8_1_m128to127 & sve_shf8_1_m128to127
+{
+ Zd.T = SVE_cpy(Zd.T, Pm_zm, sve_shf8_1_m128to127, sve_shift_13:1);
+}
+
+# cpy_z_p_r.xml: CPY (scalar) variant SVE
+# PATTERN x0528a000/mask=xff3fe000
+
+:cpy Zd.T, Pg3_m, Rn_GPR64xsp
+is sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1321=0b101000101 & sve_pg_1012 & sve_rn_0509 & sve_zd_0004 & Rn_GPR64xsp & Zd.T & Pg3_m
+{
+ Zd.T = SVE_cpy(Zd.T, Pg3_m, Rn_GPR64xsp);
+}
+
+# cpy_z_p_r.xml: CPY (scalar) variant SVE
+# PATTERN x0528a000/mask=xff3fe000
+
+:cpy Zd.T, Pg3_m, Rn_GPR32xsp
+is sve_b_2431=0b00000101 & (b_23=0 | b_22=0) & sve_b_1321=0b101000101 & sve_pg_1012 & sve_rn_0509 & sve_zd_0004 & Rn_GPR32xsp & Zd.T & Pg3_m
+{
+ Zd.T = SVE_cpy(Zd.T, Pg3_m, Rn_GPR32xsp);
+}
+
+# cpy_z_p_v.xml: CPY (SIMD&FP scalar) variant SVE
+# PATTERN x05208000/mask=xff3fe000
+
+:cpy Zd.T, Pg3_m, Rn_FPR8
+is sve_b_2431=0b00000101 & sve_size_2223=0b00 & sve_b_1321=0b100000100 & sve_pg_1012 & sve_vn_0509 & sve_zd_0004 & Zd.T & Rn_FPR8 & Pg3_m
+{
+ Zd.T = SVE_cpy(Zd.T, Pg3_m, Rn_FPR8);
+}
+
+# cpy_z_p_v.xml: CPY (SIMD&FP scalar) variant SVE
+# PATTERN x05208000/mask=xff3fe000
+
+:cpy Zd.T, Pg3_m, Rn_FPR32
+is sve_b_2431=0b00000101 & sve_size_2223=0b10 & sve_b_1321=0b100000100 & sve_pg_1012 & sve_vn_0509 & sve_zd_0004 & Zd.T & Rn_FPR32 & Pg3_m
+{
+ Zd.T = SVE_cpy(Zd.T, Pg3_m, Rn_FPR32);
+}
+
+# cpy_z_p_v.xml: CPY (SIMD&FP scalar) variant SVE
+# PATTERN x05208000/mask=xff3fe000
+
+:cpy Zd.T, Pg3_m, Rn_FPR16
+is sve_b_2431=0b00000101 & sve_size_2223=0b01 & sve_b_1321=0b100000100 & sve_pg_1012 & sve_vn_0509 & sve_zd_0004 & Zd.T & Rn_FPR16 & Pg3_m
+{
+ Zd.T = SVE_cpy(Zd.T, Pg3_m, Rn_FPR16);
+}
+
+# cpy_z_p_v.xml: CPY (SIMD&FP scalar) variant SVE
+# PATTERN x05208000/mask=xff3fe000
+
+:cpy Zd.T, Pg3_m, Rn_FPR64
+is sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1321=0b100000100 & sve_pg_1012 & sve_vn_0509 & sve_zd_0004 & Zd.T & Rn_FPR64 & Pg3_m
+{
+ Zd.T = SVE_cpy(Zd.T, Pg3_m, Rn_FPR64);
+}
+
+# ctermeq_rr.xml: CTERMEQ, CTERMNE variant Equal
+# PATTERN x25a02000/mask=xffa0fc1f
+
+:ctermeq Rn_GPR64, Rm_GPR64
+is sve_b_3031=0b00 & sve_b_2429=0b100101 & sve_b_23=1 & sve_sz_22=1 & sve_b_21=1 & sve_rm_1620 & sve_b_1015=0b001000 & sve_rn_0509 & sve_b_04=0 & sve_b_03=0 & sve_b_02=0 & sve_b_0001=0b00 & Rn_GPR64 & Rm_GPR64
+{
+ SVE_ctermeq(Rn_GPR64, Rm_GPR64);
+}
+
+# ctermeq_rr.xml: CTERMEQ, CTERMNE variant Equal
+# PATTERN x25a02000/mask=xffa0fc1f
+
+:ctermeq Rn_GPR32, Rm_GPR32
+is sve_b_3031=0b00 & sve_b_2429=0b100101 & sve_b_23=1 & sve_sz_22=0 & sve_b_21=1 & sve_rm_1620 & sve_b_1015=0b001000 & sve_rn_0509 & sve_b_04=0 & sve_b_03=0 & sve_b_02=0 & sve_b_0001=0b00 & Rn_GPR32 & Rm_GPR32
+{
+ SVE_ctermeq(Rn_GPR32, Rm_GPR32);
+}
+
+# ctermeq_rr.xml: CTERMEQ, CTERMNE variant Not equal
+# PATTERN x25a02010/mask=xffa0fc1f
+
+:ctermne Rn_GPR64, Rm_GPR64
+is sve_b_3031=0b00 & sve_b_2429=0b100101 & sve_b_23=1 & sve_sz_22=1 & sve_b_21=1 & sve_rm_1620 & sve_b_1015=0b001000 & sve_rn_0509 & sve_b_04=1 & sve_b_03=0 & sve_b_02=0 & sve_b_0001=0b00 & Rn_GPR64 & Rm_GPR64
+{
+ SVE_ctermne(Rn_GPR64, Rm_GPR64);
+}
+
+# ctermeq_rr.xml: CTERMEQ, CTERMNE variant Not equal
+# PATTERN x25a02010/mask=xffa0fc1f
+
+:ctermne Rn_GPR32, Rm_GPR32
+is sve_b_3031=0b00 & sve_b_2429=0b100101 & sve_b_23=1 & sve_sz_22=0 & sve_b_21=1 & sve_rm_1620 & sve_b_1015=0b001000 & sve_rn_0509 & sve_b_04=1 & sve_b_03=0 & sve_b_02=0 & sve_b_0001=0b00 & Rn_GPR32 & Rm_GPR32
+{
+ SVE_ctermne(Rn_GPR32, Rm_GPR32);
+}
+
+# decb_r_rs.xml: DECB, DECD, DECH, DECW (scalar) variant Byte
+# PATTERN x0430e400/mask=xfff0fc00
+
+:decb Rd_GPR64^sve_mul_pattern
+is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern
+{
+ Rd_GPR64 = SVE_decb(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);
+}
+
+# decb_r_rs.xml: DECB, DECD, DECH, DECW (scalar) variant Doubleword
+# PATTERN x04f0e400/mask=xfff0fc00
+
+:decd Rd_GPR64^sve_mul_pattern
+is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern
+{
+ Rd_GPR64 = SVE_decd(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);
+}
+
+# decb_r_rs.xml: DECB, DECD, DECH, DECW (scalar) variant Halfword
+# PATTERN x0470e400/mask=xfff0fc00
+
+:dech Rd_GPR64^sve_mul_pattern
+is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern
+{
+ Rd_GPR64 = SVE_dech(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);
+}
+
+# decb_r_rs.xml: DECB, DECD, DECH, DECW (scalar) variant Word
+# PATTERN x04b0e400/mask=xfff0fc00
+
+:decw Rd_GPR64^sve_mul_pattern
+is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11100 & sve_b_10=1 & sve_pattern_0509 & sve_rdn_0004 & sve_pattern & Rd_GPR64 & sve_imm4_1_1to16 & sve_mul_pattern
+{
+ Rd_GPR64 = SVE_decw(Rd_GPR64, sve_mul_pattern, sve_imm4_1_1to16:1);
+}
+
+# decd_z_zs.xml: DECD, DECH, DECW (vector) variant Doubleword
+# PATTERN x04f0c400/mask=xfff0fc00
+
+:decd Zd.D^sve_mul_pattern
+is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=1 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11000 & sve_b_10=1 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.D & sve_imm4_1_1to16 & sve_mul_pattern
+{
+ Zd.D = SVE_decd(Zd.D, sve_mul_pattern, sve_imm4_1_1to16:1);
+}
+
+# decd_z_zs.xml: DECD, DECH, DECW (vector) variant Halfword
+# PATTERN x0470c400/mask=xfff0fc00
+
+:dech Zd.H^sve_mul_pattern
+is sve_b_2431=0b00000100 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11000 & sve_b_10=1 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.H & sve_imm4_1_1to16 & sve_mul_pattern
+{
+ Zd.H = SVE_dech(Zd.H, sve_mul_pattern, sve_imm4_1_1to16:1);
+}
+
+# decd_z_zs.xml: DECD, DECH, DECW (vector) variant Word
+# PATTERN x04b0c400/mask=xfff0fc00
+
+:decw Zd.S^sve_mul_pattern
+is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_2021=0b11 & sve_imm4_1619 & sve_b_1115=0b11000 & sve_b_10=1 & sve_pattern_0509 & sve_zdn_0004 & sve_pattern & Zd.S & sve_imm4_1_1to16 & sve_mul_pattern
+{
+ Zd.S = SVE_decw(Zd.S, sve_mul_pattern, sve_imm4_1_1to16:1);
+}
+
+# decp_r_p_r.xml: DECP (scalar) variant SVE
+# PATTERN x252d8800/mask=xff3ffe00
+
+:decp Rd_GPR64, Pn.T
+is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1011 & sve_b_17=0 & sve_b_16=1 & sve_b_1115=0b10001 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_rdn_0004 & Pn.T & Rd_GPR64
+{
+ Rd_GPR64 = SVE_decp(Rd_GPR64, Pn.T);
+}
+
+# decp_z_p_z.xml: DECP (vector) variant SVE
+# PATTERN x252d8000/mask=xff3ffe00
+
+:decp Zd.T, Pn
+is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1821=0b1011 & sve_b_17=0 & sve_b_16=1 & sve_b_1115=0b10000 & sve_b_10=0 & sve_b_09=0 & sve_pg_0508 & sve_zdn_0004 & Zd.T & Pn
+{
+ Zd.T = SVE_decp(Zd.T, Pn);
+}
+
+# dup_z_i.xml: DUP (immediate) variant SVE
+# PATTERN x2538c000/mask=xff3fc000
+
+:dup Zd.T, sve_shf8_1_m128to127
+is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b111 & sve_b_18=0 & sve_b_17=0 & sve_b_1416=0b011 & sve_sh_13 & sve_imm8_0512 & sve_zd_0004 & sve_shift_13 & Zd.T & sve_imm8_1_m128to127 & sve_shf8_1_m128to127
+{
+ Zd.T = SVE_dup(Zd.T, sve_shf8_1_m128to127, sve_shift_13:1);
+}
+
+# dup_z_r.xml: DUP (scalar) variant SVE
+# PATTERN x05203800/mask=xff3ffc00
+
+:dup Zd.T, Rn_GPR64xsp
+is sve_b_2431=0b00000101 & sve_size_2223=0b11 & sve_b_1021=0b100000001110 & sve_rn_0509 & sve_zd_0004 & Rn_GPR64xsp & Zd.T
+{
+ Zd.T = SVE_dup(Zd.T, Rn_GPR64xsp);
+}
+
+# dup_z_r.xml: DUP (scalar) variant SVE
+# PATTERN x05203800/mask=xff3ffc00
+
+:dup Zd.T, Rn_GPR32xsp
+is sve_b_2431=0b00000101 & (b_23=0 | b_22=0) & sve_b_1021=0b100000001110 & sve_rn_0509 & sve_zd_0004 & Rn_GPR32xsp & Zd.T
+{
+ Zd.T = SVE_dup(Zd.T, Rn_GPR32xsp);
+}
+
+# dup_z_zi.xml: DUP (indexed) variant SVE
+# PATTERN x05202000/mask=xff20fc00
+
+:dup Zd.T_tsz, Zn.T_tsz[sve_imm2_tsz]
+is sve_b_2431=0b00000101 & sve_imm2_2223 & sve_b_21=1 & sve_tsz_1620 & sve_b_1015=0b001000 & sve_zn_0509 & sve_zd_0004 & Zd.T_tsz & Zn.T_tsz & sve_imm2_tsz
+{
+ Zd.T_tsz = SVE_dup(Zd.T_tsz, Zn.T_tsz, sve_imm2_tsz:1);
+}
+
+# dupm_z_i.xml: DUPM variant SVE
+# PATTERN x05c00000/mask=xfffc0000
+
+:dupm Zd.T_imm13, "#"^sve_decode_bit_mask
+is sve_b_1831=0b00000101110000 & sve_imm13_0517 & sve_zd_0004 & sve_decode_bit_mask & Zd.T_imm13
+{
+ Zd.T_imm13 = SVE_dupm(Zd.T_imm13, sve_decode_bit_mask:1);
+}
+
+# eon_eor_z_zi.xml: EON variant SVE
+# ALIASEDBY EOR ., ., #(- - 1) if Never
+# PATTERN x05400000/mask=xfffc0000
+
+:eon Zd.T_imm13, Zd.T_imm13_2, "#"^sve_decode_bit_mask
+is sve_b_2431=0b00000101 & sve_b_23=0 & sve_b_22=1 & sve_b_1821=0b0000 & sve_imm13_0517 & sve_zdn_0004 & sve_decode_bit_mask & Zd.T_imm13 & Zd.T_imm13_2
+{
+ Zd.T_imm13 = SVE_eon(Zd.T_imm13, Zd.T_imm13_2, sve_decode_bit_mask:1);
+}
+
+# eor_p_p_pp.xml: EOR, EORS (predicates) variant Flag setting
+# PATTERN x25404200/mask=xfff0c210
+
+:eors Pd.B, Pg_z, Pn.B, Pm.B
+is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=1 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=1 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B
+{
+ Pd.B = SVE_eors(Pd.B, Pg_z, Pn.B, Pm.B);
+}
+
+# eor_p_p_pp.xml: EOR, EORS (predicates) variant Not flag setting
+# PATTERN x25004200/mask=xfff0c210
+
+:eor Pd.B, Pg_z, Pn.B, Pm.B
+is sve_b_2431=0b00100101 & sve_b_23=0 & sve_b_22=0 & sve_b_2021=0b00 & sve_pm_1619 & sve_b_1415=0b01 & sve_pg_1013 & sve_b_09=1 & sve_pn_0508 & sve_b_04=0 & sve_pd_0003 & Pd.B & Pg_z & Pn.B & Pm.B
+{
+ Pd.B = SVE_eor(Pd.B, Pg_z, Pn.B, Pm.B);
+}
+
+# eor_z_p_zz.xml: EOR (vectors, predicated) variant SVE
+# PATTERN x04190000/mask=xff3fe000
+
+:eor Zd.T, Pg3_m, Zd.T_2, Zn.T
+is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b000 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m
+{
+ Zd.T = SVE_eor(Zd.T, Pg3_m, Zd.T_2, Zn.T);
+}
+
+# eor_z_zi.xml: EOR (immediate) variant SVE
+# PATTERN x05400000/mask=xfffc0000
+
+# SKIPPING eor_z_zi.xml because x05400000/mask=xfffc0000 has already been defined
+
+# eor_z_zz.xml: EOR (vectors, unpredicated) variant SVE
+# PATTERN x04a03000/mask=xffe0fc00
+
+:eor Zd.D, Zn.D, Zm.D
+is sve_b_2431=0b00000100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_zm_1620 & sve_b_1015=0b001100 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Zm.D
+{
+ Zd.D = SVE_eor(Zd.D, Zn.D, Zm.D);
+}
+
+# eorv_r_p_z.xml: EORV variant SVE
+# PATTERN x04192000/mask=xff3fe000
+
+:eorv Rd_FPR8, Pg3, Zn.T
+is sve_b_2431=0b00000100 & sve_size_2223=0b00 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3
+{
+ Rd_FPR8 = SVE_eorv(Rd_FPR8, Pg3, Zn.T);
+}
+
+# eorv_r_p_z.xml: EORV variant SVE
+# PATTERN x04192000/mask=xff3fe000
+
+:eorv Rd_FPR32, Pg3, Zn.T
+is sve_b_2431=0b00000100 & sve_size_2223=0b10 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3
+{
+ Rd_FPR32 = SVE_eorv(Rd_FPR32, Pg3, Zn.T);
+}
+
+# eorv_r_p_z.xml: EORV variant SVE
+# PATTERN x04192000/mask=xff3fe000
+
+:eorv Rd_FPR16, Pg3, Zn.T
+is sve_b_2431=0b00000100 & sve_size_2223=0b01 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3
+{
+ Rd_FPR16 = SVE_eorv(Rd_FPR16, Pg3, Zn.T);
+}
+
+# eorv_r_p_z.xml: EORV variant SVE
+# PATTERN x04192000/mask=xff3fe000
+
+:eorv Rd_FPR64, Pg3, Zn.T
+is sve_b_2431=0b00000100 & sve_size_2223=0b11 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3
+{
+ Rd_FPR64 = SVE_eorv(Rd_FPR64, Pg3, Zn.T);
+}
+
+# ext_z_zi.xml: EXT variant SVE
+# PATTERN x05200000/mask=xffe0e000
+
+:ext Zd.B, Zd.B_2, Zn.B, "#"^sve_imm8_2_0to255
+is sve_b_2131=0b00000101001 & sve_imm8h_1620 & sve_b_1315=0b000 & sve_imm8l_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.B & Zd.B_2 & Zn.B & sve_imm8_2_0to255
+{
+ Zd.B = SVE_ext(Zd.B, Zd.B_2, Zn.B, sve_imm8_2_0to255:1);
+}
+
+# fabd_z_p_zz.xml: FABD variant SVE
+# PATTERN x65088000/mask=xff3fe000
+
+:fabd Zd.T, Pg3_m, Zd.T_2, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b100 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m
+{
+ Zd.T = SVE_fabd(Zd.T, Pg3_m, Zd.T_2, Zn.T);
+}
+
+# fabs_z_p_z.xml: FABS variant SVE
+# PATTERN x041ca000/mask=xff3fe000
+
+:fabs Zd.T, Pg3_m, Zn.T
+is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T & Pg3_m
+{
+ Zd.T = SVE_fabs(Zd.T, Pg3_m, Zn.T);
+}
+
+# facge_p_p_zz.xml: FAC variant Greater than
+# PATTERN x6500e010/mask=xff20e010
+
+:facgt Pd.T, Pg3_z, Zn.T, Zm.T
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z
+{
+ Pd.T = SVE_facgt(Pd.T, Pg3_z, Zn.T, Zm.T);
+}
+
+# facge_p_p_zz.xml: FAC variant Greater than or equal
+# PATTERN x6500c010/mask=xff20e010
+
+:facge Pd.T, Pg3_z, Zn.T, Zm.T
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z
+{
+ Pd.T = SVE_facge(Pd.T, Pg3_z, Zn.T, Zm.T);
+}
+
+# facle_facge_p_p_zz.xml: FACLE variant Greater than or equal
+# ALIASEDBY FACGE ., /Z, ., . if Never
+# PATTERN x6500c010/mask=xff20e010
+
+# SKIPPING facle_facge_p_p_zz.xml because x6500c010/mask=xff20e010 has already been defined
+
+# faclt_facge_p_p_zz.xml: FACLT variant Greater than
+# ALIASEDBY FACGT ., /Z, ., . if Never
+# PATTERN x6500e010/mask=xff20e010
+
+# SKIPPING faclt_facge_p_p_zz.xml because x6500e010/mask=xff20e010 has already been defined
+
+# fadd_z_p_zs.xml: FADD (immediate) variant SVE
+# PATTERN x65188000/mask=xff3fe3c0
+
+:fadd Zd.T, Pg3_m, Zd.T_2, sve_float_0510
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_b_0609=0b0000 & sve_i1_05 & sve_zdn_0004 & sve_float_0510 & Zd.T & Zd.T_2 & Pg3_m
+{
+ Zd.T = SVE_fadd(Zd.T, Pg3_m, Zd.T_2, sve_float_0510:1);
+}
+
+# fadd_z_p_zz.xml: FADD (vectors, predicated) variant SVE
+# PATTERN x65008000/mask=xff3fe000
+
+:fadd Zd.T, Pg3_m, Zd.T_2, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b000 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m
+{
+ Zd.T = SVE_fadd(Zd.T, Pg3_m, Zd.T_2, Zn.T);
+}
+
+# fadd_z_zz.xml: FADD (vectors, unpredicated) variant SVE
+# PATTERN x65000000/mask=xff20fc00
+
+:fadd Zd.T, Zn.T, Zm.T
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_1315=0b000 & sve_b_1112=0b00 & sve_b_10=0 & sve_zn_0509 & sve_zd_0004 & Zm.T & Zd.T & Zn.T
+{
+ Zd.T = SVE_fadd(Zd.T, Zn.T, Zm.T);
+}
+
+# fadda_v_p_z.xml: FADDA variant SVE
+# PATTERN x65182000/mask=xff3fe000
+
+:fadda Rd_FPR8, Pg3, Rd_FPR8_2, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223=0b00 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR8 & Rd_FPR8_2 & Pg3
+{
+ Rd_FPR8 = SVE_fadda(Rd_FPR8, Pg3, Rd_FPR8_2, Zn.T);
+}
+
+# fadda_v_p_z.xml: FADDA variant SVE
+# PATTERN x65182000/mask=xff3fe000
+
+:fadda Rd_FPR32, Pg3, Rd_FPR32_2, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223=0b10 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR32 & Rd_FPR32_2 & Pg3
+{
+ Rd_FPR32 = SVE_fadda(Rd_FPR32, Pg3, Rd_FPR32_2, Zn.T);
+}
+
+# fadda_v_p_z.xml: FADDA variant SVE
+# PATTERN x65182000/mask=xff3fe000
+
+:fadda Rd_FPR16, Pg3, Rd_FPR16_2, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223=0b01 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR16 & Rd_FPR16_2 & Pg3
+{
+ Rd_FPR16 = SVE_fadda(Rd_FPR16, Pg3, Rd_FPR16_2, Zn.T);
+}
+
+# fadda_v_p_z.xml: FADDA variant SVE
+# PATTERN x65182000/mask=xff3fe000
+
+:fadda Rd_FPR64, Pg3, Rd_FPR64_2, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223=0b11 & sve_b_1921=0b011 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zm_0509 & sve_vdn_0004 & Zn.T & Rd_FPR64 & Rd_FPR64_2 & Pg3
+{
+ Rd_FPR64 = SVE_fadda(Rd_FPR64, Pg3, Rd_FPR64_2, Zn.T);
+}
+
+# faddv_v_p_z.xml: FADDV variant SVE
+# PATTERN x65002000/mask=xff3fe000
+
+:faddv Rd_FPR8, Pg3, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223=0b00 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3
+{
+ Rd_FPR8 = SVE_faddv(Rd_FPR8, Pg3, Zn.T);
+}
+
+# faddv_v_p_z.xml: FADDV variant SVE
+# PATTERN x65002000/mask=xff3fe000
+
+:faddv Rd_FPR32, Pg3, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223=0b10 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3
+{
+ Rd_FPR32 = SVE_faddv(Rd_FPR32, Pg3, Zn.T);
+}
+
+# faddv_v_p_z.xml: FADDV variant SVE
+# PATTERN x65002000/mask=xff3fe000
+
+:faddv Rd_FPR16, Pg3, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223=0b01 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3
+{
+ Rd_FPR16 = SVE_faddv(Rd_FPR16, Pg3, Zn.T);
+}
+
+# faddv_v_p_z.xml: FADDV variant SVE
+# PATTERN x65002000/mask=xff3fe000
+
+:faddv Rd_FPR64, Pg3, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223=0b11 & sve_b_1921=0b000 & sve_b_1718=0b00 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3
+{
+ Rd_FPR64 = SVE_faddv(Rd_FPR64, Pg3, Zn.T);
+}
+
+# fcadd_z_p_zz.xml: FCADD variant SVE
+# PATTERN x64008000/mask=xff3ee000
+
+:fcadd Zd.T, Pg3_m, Zd.T_2, Zn.T, sve_rot_16
+is sve_b_2431=0b01100100 & sve_size_2223 & sve_b_1721=0b00000 & sve_rot_16 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m
+{
+ Zd.T = SVE_fcadd(Zd.T, Pg3_m, Zd.T_2, Zn.T, sve_rot_16:1);
+}
+
+# fcmeq_p_p_z0.xml: FCM (zero) variant Equal
+# PATTERN x65122000/mask=xff3fe010
+
+:fcmeq Pd.T, Pg3_z, Zn.T, "#0.0"
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1821=0b0100 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z
+{
+ Pd.T = SVE_fcmeq(Pd.T, Pg3_z, Zn.T);
+}
+
+# fcmeq_p_p_z0.xml: FCM (zero) variant Greater than
+# PATTERN x65102010/mask=xff3fe010
+
+:fcmgt Pd.T, Pg3_z, Zn.T, "#0.0"
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1821=0b0100 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z
+{
+ Pd.T = SVE_fcmgt(Pd.T, Pg3_z, Zn.T);
+}
+
+# fcmeq_p_p_z0.xml: FCM (zero) variant Greater than or equal
+# PATTERN x65102000/mask=xff3fe010
+
+:fcmge Pd.T, Pg3_z, Zn.T, "#0.0"
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1821=0b0100 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z
+{
+ Pd.T = SVE_fcmge(Pd.T, Pg3_z, Zn.T);
+}
+
+# fcmeq_p_p_z0.xml: FCM (zero) variant Less than
+# PATTERN x65112000/mask=xff3fe010
+
+:fcmlt Pd.T, Pg3_z, Zn.T, "#0.0"
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1821=0b0100 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z
+{
+ Pd.T = SVE_fcmlt(Pd.T, Pg3_z, Zn.T);
+}
+
+# fcmeq_p_p_z0.xml: FCM (zero) variant Less than or equal
+# PATTERN x65112010/mask=xff3fe010
+
+:fcmle Pd.T, Pg3_z, Zn.T, "#0.0"
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1821=0b0100 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z
+{
+ Pd.T = SVE_fcmle(Pd.T, Pg3_z, Zn.T);
+}
+
+# fcmeq_p_p_z0.xml: FCM (zero) variant Not equal
+# PATTERN x65132000/mask=xff3fe010
+
+:fcmne Pd.T, Pg3_z, Zn.T, "#0.0"
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1821=0b0100 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Pd.T & Zn.T & Pg3_z
+{
+ Pd.T = SVE_fcmne(Pd.T, Pg3_z, Zn.T);
+}
+
+# fcmeq_p_p_zz.xml: FCM (vectors) variant Equal
+# PATTERN x65006000/mask=xff20e010
+
+:fcmeq Pd.T, Pg3_z, Zn.T, Zm.T
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z
+{
+ Pd.T = SVE_fcmeq(Pd.T, Pg3_z, Zn.T, Zm.T);
+}
+
+# fcmeq_p_p_zz.xml: FCM (vectors) variant Greater than
+# PATTERN x65004010/mask=xff20e010
+
+:fcmgt Pd.T, Pg3_z, Zn.T, Zm.T
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z
+{
+ Pd.T = SVE_fcmgt(Pd.T, Pg3_z, Zn.T, Zm.T);
+}
+
+# fcmeq_p_p_zz.xml: FCM (vectors) variant Greater than or equal
+# PATTERN x65004000/mask=xff20e010
+
+:fcmge Pd.T, Pg3_z, Zn.T, Zm.T
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z
+{
+ Pd.T = SVE_fcmge(Pd.T, Pg3_z, Zn.T, Zm.T);
+}
+
+# fcmeq_p_p_zz.xml: FCM (vectors) variant Not equal
+# PATTERN x65006010/mask=xff20e010
+
+:fcmne Pd.T, Pg3_z, Zn.T, Zm.T
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_b_14=1 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_b_04=1 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z
+{
+ Pd.T = SVE_fcmne(Pd.T, Pg3_z, Zn.T, Zm.T);
+}
+
+# fcmeq_p_p_zz.xml: FCM (vectors) variant Unordered
+# PATTERN x6500c000/mask=xff20e010
+
+:fcmuo Pd.T, Pg3_z, Zn.T, Zm.T
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=1 & sve_b_14=1 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_b_04=0 & sve_pd_0003 & Zm.T & Pd.T & Zn.T & Pg3_z
+{
+ Pd.T = SVE_fcmuo(Pd.T, Pg3_z, Zn.T, Zm.T);
+}
+
+# fcmla_z_p_zzz.xml: FCMLA (vectors) variant SVE
+# PATTERN x64000000/mask=xff208000
+
+:fcmla Zd.T, Pg3_m, Zn.T, Zm.T, sve_rot_1314
+is sve_b_2431=0b01100100 & sve_size_2223 & sve_b_21=0 & sve_zm_1620 & sve_b_15=0 & sve_rot_1314 & sve_pg_1012 & sve_zn_0509 & sve_zda_0004 & Zd.T & Zm.T & Zn.T & Pg3_m
+{
+ Zd.T = SVE_fcmla(Zd.T, Pg3_m, Zn.T, Zm.T, sve_rot_1314:1);
+}
+
+# fcmla_z_zzzi.xml: FCMLA (indexed) variant Half-precision
+# PATTERN x64a01000/mask=xffe0f000
+
+:fcmla Zd.H, Zn.H, Zm3.H[sve_i2_1920], sve_rot_1011
+is sve_b_2431=0b01100100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_i2_1920 & sve_zm_1618 & sve_b_1215=0b0001 & sve_rot_1011 & sve_zn_0509 & sve_zda_0004 & Zd.H & Zn.H & Zm3.H
+{
+ Zd.H = SVE_fcmla(Zd.H, Zn.H, Zm3.H, sve_i2_1920:1, sve_rot_1011:1);
+}
+
+# fcmla_z_zzzi.xml: FCMLA (indexed) variant Single-precision
+# PATTERN x64e01000/mask=xffe0f000
+
+:fcmla Zd.S, Zn.S, Zm4.S[sve_i1_20], sve_rot_1011
+is sve_b_2431=0b01100100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_i1_20 & sve_zm_1619 & sve_b_1215=0b0001 & sve_rot_1011 & sve_zn_0509 & sve_zda_0004 & Zd.S & Zn.S & Zm4.S
+{
+ Zd.S = SVE_fcmla(Zd.S, Zn.S, Zm4.S, sve_i1_20:1, sve_rot_1011:1);
+}
+
+# fcmle_fcmeq_p_p_zz.xml: FCMLE (vectors) variant Greater than or equal
+# ALIASEDBY FCMGE ., /Z, ., . if Never
+# PATTERN x65004000/mask=xff20e010
+
+# SKIPPING fcmle_fcmeq_p_p_zz.xml because x65004000/mask=xff20e010 has already been defined
+
+# fcmlt_fcmeq_p_p_zz.xml: FCMLT (vectors) variant Greater than
+# ALIASEDBY FCMGT ., /Z, ., . if Never
+# PATTERN x65004010/mask=xff20e010
+
+# SKIPPING fcmlt_fcmeq_p_p_zz.xml because x65004010/mask=xff20e010 has already been defined
+
+# fcpy_z_p_i.xml: FCPY variant SVE
+# PATTERN x0510c000/mask=xff30e000
+
+:fcpy Zd.T, Pm_m, "#"^sve_float_imm8
+is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_2021=0b01 & sve_pg_1619 & sve_b_1315=0b110 & sve_imm8_0512 & sve_zd_0004 & sve_float_imm8 & Zd.T & Pm_m
+{
+ Zd.T = SVE_fcpy(Zd.T, Pm_m, sve_float_imm8:1);
+}
+
+# fcvt_z_p_z.xml: FCVT variant Half-precision to single-precision
+# PATTERN x6589a000/mask=xffffe000
+
+:fcvt Zd.S, Pg3_m, Zn.H
+is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=0 & sve_b_1821=0b0010 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.S & Pg3_m
+{
+ Zd.S = SVE_fcvt(Zd.S, Pg3_m, Zn.H);
+}
+
+# fcvt_z_p_z.xml: FCVT variant Half-precision to double-precision
+# PATTERN x65c9a000/mask=xffffe000
+
+:fcvt Zd.D, Pg3_m, Zn.H
+is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1821=0b0010 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.D & Pg3_m
+{
+ Zd.D = SVE_fcvt(Zd.D, Pg3_m, Zn.H);
+}
+
+# fcvt_z_p_z.xml: FCVT variant Single-precision to half-precision
+# PATTERN x6588a000/mask=xffffe000
+
+:fcvt Zd.H, Pg3_m, Zn.S
+is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=0 & sve_b_1821=0b0010 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.H & Pg3_m
+{
+ Zd.H = SVE_fcvt(Zd.H, Pg3_m, Zn.S);
+}
+
+# fcvt_z_p_z.xml: FCVT variant Single-precision to double-precision
+# PATTERN x65cba000/mask=xffffe000
+
+:fcvt Zd.D, Pg3_m, Zn.S
+is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1821=0b0010 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.D & Pg3_m
+{
+ Zd.D = SVE_fcvt(Zd.D, Pg3_m, Zn.S);
+}
+
+# fcvt_z_p_z.xml: FCVT variant Double-precision to half-precision
+# PATTERN x65c8a000/mask=xffffe000
+
+:fcvt Zd.H, Pg3_m, Zn.D
+is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1821=0b0010 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.H & Pg3_m
+{
+ Zd.H = SVE_fcvt(Zd.H, Pg3_m, Zn.D);
+}
+
+# fcvt_z_p_z.xml: FCVT variant Double-precision to single-precision
+# PATTERN x65caa000/mask=xffffe000
+
+:fcvt Zd.S, Pg3_m, Zn.D
+is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1821=0b0010 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.S & Pg3_m
+{
+ Zd.S = SVE_fcvt(Zd.S, Pg3_m, Zn.D);
+}
+
+# fcvtzs_z_p_z.xml: FCVTZS variant Half-precision to 16-bit
+# PATTERN x655aa000/mask=xffffe000
+
+:fcvtzs Zd.H, Pg3_m, Zn.H
+is sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=0 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.H & Pg3_m
+{
+ Zd.H = SVE_fcvtzs(Zd.H, Pg3_m, Zn.H);
+}
+
+# fcvtzs_z_p_z.xml: FCVTZS variant Half-precision to 32-bit
+# PATTERN x655ca000/mask=xffffe000
+
+:fcvtzs Zd.S, Pg3_m, Zn.H
+is sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.S & Pg3_m
+{
+ Zd.S = SVE_fcvtzs(Zd.S, Pg3_m, Zn.H);
+}
+
+# fcvtzs_z_p_z.xml: FCVTZS variant Half-precision to 64-bit
+# PATTERN x655ea000/mask=xffffe000
+
+:fcvtzs Zd.D, Pg3_m, Zn.H
+is sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.D & Pg3_m
+{
+ Zd.D = SVE_fcvtzs(Zd.D, Pg3_m, Zn.H);
+}
+
+# fcvtzs_z_p_z.xml: FCVTZS variant Single-precision to 32-bit
+# PATTERN x659ca000/mask=xffffe000
+
+:fcvtzs Zd.S, Pg3_m, Zn.S
+is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=0 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.S & Pg3_m
+{
+ Zd.S = SVE_fcvtzs(Zd.S, Pg3_m, Zn.S);
+}
+
+# fcvtzs_z_p_z.xml: FCVTZS variant Single-precision to 64-bit
+# PATTERN x65dca000/mask=xffffe000
+
+:fcvtzs Zd.D, Pg3_m, Zn.S
+is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.D & Pg3_m
+{
+ Zd.D = SVE_fcvtzs(Zd.D, Pg3_m, Zn.S);
+}
+
+# fcvtzs_z_p_z.xml: FCVTZS variant Double-precision to 32-bit
+# PATTERN x65d8a000/mask=xffffe000
+
+:fcvtzs Zd.S, Pg3_m, Zn.D
+is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=0 & sve_b_17=0 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.S & Pg3_m
+{
+ Zd.S = SVE_fcvtzs(Zd.S, Pg3_m, Zn.D);
+}
+
+# fcvtzs_z_p_z.xml: FCVTZS variant Double-precision to 64-bit
+# PATTERN x65dea000/mask=xffffe000
+
+:fcvtzs Zd.D, Pg3_m, Zn.D
+is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=1 & sve_b_16=0 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Pg3_m
+{
+ Zd.D = SVE_fcvtzs(Zd.D, Pg3_m, Zn.D);
+}
+
+# fcvtzu_z_p_z.xml: FCVTZU variant Half-precision to 16-bit
+# PATTERN x655ba000/mask=xffffe000
+
+:fcvtzu Zd.H, Pg3_m, Zn.H
+is sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=0 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.H & Pg3_m
+{
+ Zd.H = SVE_fcvtzu(Zd.H, Pg3_m, Zn.H);
+}
+
+# fcvtzu_z_p_z.xml: FCVTZU variant Half-precision to 32-bit
+# PATTERN x655da000/mask=xffffe000
+
+:fcvtzu Zd.S, Pg3_m, Zn.H
+is sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.S & Pg3_m
+{
+ Zd.S = SVE_fcvtzu(Zd.S, Pg3_m, Zn.H);
+}
+
+# fcvtzu_z_p_z.xml: FCVTZU variant Half-precision to 64-bit
+# PATTERN x655fa000/mask=xffffe000
+
+:fcvtzu Zd.D, Pg3_m, Zn.H
+is sve_b_2431=0b01100101 & sve_b_23=0 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.H & Zd.D & Pg3_m
+{
+ Zd.D = SVE_fcvtzu(Zd.D, Pg3_m, Zn.H);
+}
+
+# fcvtzu_z_p_z.xml: FCVTZU variant Single-precision to 32-bit
+# PATTERN x659da000/mask=xffffe000
+
+:fcvtzu Zd.S, Pg3_m, Zn.S
+is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=0 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.S & Pg3_m
+{
+ Zd.S = SVE_fcvtzu(Zd.S, Pg3_m, Zn.S);
+}
+
+# fcvtzu_z_p_z.xml: FCVTZU variant Single-precision to 64-bit
+# PATTERN x65dda000/mask=xffffe000
+
+:fcvtzu Zd.D, Pg3_m, Zn.S
+is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.S & Zd.D & Pg3_m
+{
+ Zd.D = SVE_fcvtzu(Zd.D, Pg3_m, Zn.S);
+}
+
+# fcvtzu_z_p_z.xml: FCVTZU variant Double-precision to 32-bit
+# PATTERN x65d9a000/mask=xffffe000
+
+:fcvtzu Zd.S, Pg3_m, Zn.D
+is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=0 & sve_b_17=0 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.S & Pg3_m
+{
+ Zd.S = SVE_fcvtzu(Zd.S, Pg3_m, Zn.D);
+}
+
+# fcvtzu_z_p_z.xml: FCVTZU variant Double-precision to 64-bit
+# PATTERN x65dfa000/mask=xffffe000
+
+:fcvtzu Zd.D, Pg3_m, Zn.D
+is sve_b_2431=0b01100101 & sve_b_23=1 & sve_b_22=1 & sve_b_1921=0b011 & sve_b_18=1 & sve_b_17=1 & sve_b_16=1 & sve_b_1315=0b101 & sve_pg_1012 & sve_zn_0509 & sve_zd_0004 & Zn.D & Zd.D & Pg3_m
+{
+ Zd.D = SVE_fcvtzu(Zd.D, Pg3_m, Zn.D);
+}
+
+# fdiv_z_p_zz.xml: FDIV variant SVE
+# PATTERN x650d8000/mask=xff3fe000
+
+:fdiv Zd.T, Pg3_m, Zd.T_2, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b110 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m
+{
+ Zd.T = SVE_fdiv(Zd.T, Pg3_m, Zd.T_2, Zn.T);
+}
+
+# fdivr_z_p_zz.xml: FDIVR variant SVE
+# PATTERN x650c8000/mask=xff3fe000
+
+:fdivr Zd.T, Pg3_m, Zd.T_2, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b110 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m
+{
+ Zd.T = SVE_fdivr(Zd.T, Pg3_m, Zd.T_2, Zn.T);
+}
+
+# fdup_z_i.xml: FDUP variant SVE
+# PATTERN x2539c000/mask=xff3fe000
+
+:fdup Zd.T, "#"^sve_float_imm8
+is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b111 & sve_b_18=0 & sve_b_17=0 & sve_b_1416=0b111 & sve_b_13=0 & sve_imm8_0512 & sve_zd_0004 & sve_float_imm8 & Zd.T
+{
+ Zd.T = SVE_fdup(Zd.T, sve_float_imm8:1);
+}
+
+# fexpa_z_z.xml: FEXPA variant SVE
+# PATTERN x0420b800/mask=xff3ffc00
+
+:fexpa Zd.T, Zn.T
+is sve_b_2431=0b00000100 & sve_size_2223 & sve_b_21=1 & sve_b_1720=0b0000 & sve_b_16=0 & sve_b_1015=0b101110 & sve_zn_0509 & sve_zd_0004 & Zd.T & Zn.T
+{
+ Zd.T = SVE_fexpa(Zd.T, Zn.T);
+}
+
+# fmad_z_p_zzz.xml: FMAD variant SVE
+# PATTERN x65208000/mask=xff20e000
+
+:fmad Zd.T, Pg3_m, Zn.T, Zm.T
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=1 & sve_za_1620 & sve_b_15=1 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zn.T & Zm.T & Pg3_m
+{
+ Zd.T = SVE_fmad(Zd.T, Pg3_m, Zn.T, Zm.T);
+}
+
+# fmax_z_p_zs.xml: FMAX (immediate) variant SVE
+# PATTERN x651e8000/mask=xff3fe3c0
+
+:fmax Zd.T, Pg3_m, Zd.T_2, sve_float_0010
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_b_0609=0b0000 & sve_i1_05 & sve_zdn_0004 & sve_float_0010 & Zd.T & Zd.T_2 & Pg3_m
+{
+ Zd.T = SVE_fmax(Zd.T, Pg3_m, Zd.T_2, sve_float_0010:1);
+}
+
+# fmax_z_p_zz.xml: FMAX (vectors) variant SVE
+# PATTERN x65068000/mask=xff3fe000
+
+:fmax Zd.T, Pg3_m, Zd.T_2, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b011 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m
+{
+ Zd.T = SVE_fmax(Zd.T, Pg3_m, Zd.T_2, Zn.T);
+}
+
+# fmaxnm_z_p_zs.xml: FMAXNM (immediate) variant SVE
+# PATTERN x651c8000/mask=xff3fe3c0
+
+:fmaxnm Zd.T, Pg3_m, Zd.T_2, sve_float_0010
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_b_0609=0b0000 & sve_i1_05 & sve_zdn_0004 & sve_float_0010 & Zd.T & Zd.T_2 & Pg3_m
+{
+ Zd.T = SVE_fmaxnm(Zd.T, Pg3_m, Zd.T_2, sve_float_0010:1);
+}
+
+# fmaxnm_z_p_zz.xml: FMAXNM (vectors) variant SVE
+# PATTERN x65048000/mask=xff3fe000
+
+:fmaxnm Zd.T, Pg3_m, Zd.T_2, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b010 & sve_b_16=0 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m
+{
+ Zd.T = SVE_fmaxnm(Zd.T, Pg3_m, Zd.T_2, Zn.T);
+}
+
+# fmaxnmv_v_p_z.xml: FMAXNMV variant SVE
+# PATTERN x65042000/mask=xff3fe000
+
+:fmaxnmv Rd_FPR8, Pg3, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223=0b00 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3
+{
+ Rd_FPR8 = SVE_fmaxnmv(Rd_FPR8, Pg3, Zn.T);
+}
+
+# fmaxnmv_v_p_z.xml: FMAXNMV variant SVE
+# PATTERN x65042000/mask=xff3fe000
+
+:fmaxnmv Rd_FPR32, Pg3, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223=0b10 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3
+{
+ Rd_FPR32 = SVE_fmaxnmv(Rd_FPR32, Pg3, Zn.T);
+}
+
+# fmaxnmv_v_p_z.xml: FMAXNMV variant SVE
+# PATTERN x65042000/mask=xff3fe000
+
+:fmaxnmv Rd_FPR16, Pg3, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223=0b01 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3
+{
+ Rd_FPR16 = SVE_fmaxnmv(Rd_FPR16, Pg3, Zn.T);
+}
+
+# fmaxnmv_v_p_z.xml: FMAXNMV variant SVE
+# PATTERN x65042000/mask=xff3fe000
+
+:fmaxnmv Rd_FPR64, Pg3, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223=0b11 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3
+{
+ Rd_FPR64 = SVE_fmaxnmv(Rd_FPR64, Pg3, Zn.T);
+}
+
+# fmaxv_v_p_z.xml: FMAXV variant SVE
+# PATTERN x65062000/mask=xff3fe000
+
+:fmaxv Rd_FPR8, Pg3, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223=0b00 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3
+{
+ Rd_FPR8 = SVE_fmaxv(Rd_FPR8, Pg3, Zn.T);
+}
+
+# fmaxv_v_p_z.xml: FMAXV variant SVE
+# PATTERN x65062000/mask=xff3fe000
+
+:fmaxv Rd_FPR32, Pg3, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223=0b10 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3
+{
+ Rd_FPR32 = SVE_fmaxv(Rd_FPR32, Pg3, Zn.T);
+}
+
+# fmaxv_v_p_z.xml: FMAXV variant SVE
+# PATTERN x65062000/mask=xff3fe000
+
+:fmaxv Rd_FPR16, Pg3, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223=0b01 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3
+{
+ Rd_FPR16 = SVE_fmaxv(Rd_FPR16, Pg3, Zn.T);
+}
+
+# fmaxv_v_p_z.xml: FMAXV variant SVE
+# PATTERN x65062000/mask=xff3fe000
+
+:fmaxv Rd_FPR64, Pg3, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223=0b11 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=0 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3
+{
+ Rd_FPR64 = SVE_fmaxv(Rd_FPR64, Pg3, Zn.T);
+}
+
+# fmin_z_p_zs.xml: FMIN (immediate) variant SVE
+# PATTERN x651f8000/mask=xff3fe3c0
+
+:fmin Zd.T, Pg3_m, Zd.T_2, sve_float_0010
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_b_0609=0b0000 & sve_i1_05 & sve_zdn_0004 & sve_float_0010 & Zd.T & Zd.T_2 & Pg3_m
+{
+ Zd.T = SVE_fmin(Zd.T, Pg3_m, Zd.T_2, sve_float_0010:1);
+}
+
+# fmin_z_p_zz.xml: FMIN (vectors) variant SVE
+# PATTERN x65078000/mask=xff3fe000
+
+:fmin Zd.T, Pg3_m, Zd.T_2, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b011 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m
+{
+ Zd.T = SVE_fmin(Zd.T, Pg3_m, Zd.T_2, Zn.T);
+}
+
+# fminnm_z_p_zs.xml: FMINNM (immediate) variant SVE
+# PATTERN x651d8000/mask=xff3fe3c0
+
+:fminnm Zd.T, Pg3_m, Zd.T_2, sve_float_0010
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_1921=0b011 & sve_b_1718=0b10 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_b_0609=0b0000 & sve_i1_05 & sve_zdn_0004 & sve_float_0010 & Zd.T & Zd.T_2 & Pg3_m
+{
+ Zd.T = SVE_fminnm(Zd.T, Pg3_m, Zd.T_2, sve_float_0010:1);
+}
+
+# fminnm_z_p_zz.xml: FMINNM (vectors) variant SVE
+# PATTERN x65058000/mask=xff3fe000
+
+:fminnm Zd.T, Pg3_m, Zd.T_2, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_2021=0b00 & sve_b_1719=0b010 & sve_b_16=1 & sve_b_1315=0b100 & sve_pg_1012 & sve_zm_0509 & sve_zdn_0004 & Zd.T & Zd.T_2 & Zn.T & Pg3_m
+{
+ Zd.T = SVE_fminnm(Zd.T, Pg3_m, Zd.T_2, Zn.T);
+}
+
+# fminnmv_v_p_z.xml: FMINNMV variant SVE
+# PATTERN x65052000/mask=xff3fe000
+
+:fminnmv Rd_FPR8, Pg3, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223=0b00 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3
+{
+ Rd_FPR8 = SVE_fminnmv(Rd_FPR8, Pg3, Zn.T);
+}
+
+# fminnmv_v_p_z.xml: FMINNMV variant SVE
+# PATTERN x65052000/mask=xff3fe000
+
+:fminnmv Rd_FPR32, Pg3, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223=0b10 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3
+{
+ Rd_FPR32 = SVE_fminnmv(Rd_FPR32, Pg3, Zn.T);
+}
+
+# fminnmv_v_p_z.xml: FMINNMV variant SVE
+# PATTERN x65052000/mask=xff3fe000
+
+:fminnmv Rd_FPR16, Pg3, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223=0b01 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3
+{
+ Rd_FPR16 = SVE_fminnmv(Rd_FPR16, Pg3, Zn.T);
+}
+
+# fminnmv_v_p_z.xml: FMINNMV variant SVE
+# PATTERN x65052000/mask=xff3fe000
+
+:fminnmv Rd_FPR64, Pg3, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223=0b11 & sve_b_1921=0b000 & sve_b_1718=0b10 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3
+{
+ Rd_FPR64 = SVE_fminnmv(Rd_FPR64, Pg3, Zn.T);
+}
+
+# fminv_v_p_z.xml: FMINV variant SVE
+# PATTERN x65072000/mask=xff3fe000
+
+:fminv Rd_FPR8, Pg3, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223=0b00 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR8 & Pg3
+{
+ Rd_FPR8 = SVE_fminv(Rd_FPR8, Pg3, Zn.T);
+}
+
+# fminv_v_p_z.xml: FMINV variant SVE
+# PATTERN x65072000/mask=xff3fe000
+
+:fminv Rd_FPR32, Pg3, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223=0b10 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR32 & Pg3
+{
+ Rd_FPR32 = SVE_fminv(Rd_FPR32, Pg3, Zn.T);
+}
+
+# fminv_v_p_z.xml: FMINV variant SVE
+# PATTERN x65072000/mask=xff3fe000
+
+:fminv Rd_FPR16, Pg3, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223=0b01 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR16 & Pg3
+{
+ Rd_FPR16 = SVE_fminv(Rd_FPR16, Pg3, Zn.T);
+}
+
+# fminv_v_p_z.xml: FMINV variant SVE
+# PATTERN x65072000/mask=xff3fe000
+
+:fminv Rd_FPR64, Pg3, Zn.T
+is sve_b_2431=0b01100101 & sve_size_2223=0b11 & sve_b_1921=0b000 & sve_b_1718=0b11 & sve_b_16=1 & sve_b_1315=0b001 & sve_pg_1012 & sve_zn_0509 & sve_vd_0004 & Zn.T & Rd_FPR64 & Pg3
+{
+ Rd_FPR64 = SVE_fminv(Rd_FPR64, Pg3, Zn.T);
+}
+
+# fmla_z_p_zzz.xml: FMLA (vectors) variant SVE
+# PATTERN x65200000/mask=xff20e000
+
+:fmla Zd.T, Pg3_m, Zn.T, Zm.T
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=0 & sve_pg_1012 & sve_zn_0509 & sve_zda_0004 & Zd.T & Zm.T & Zn.T & Pg3_m
+{
+ Zd.T = SVE_fmla(Zd.T, Pg3_m, Zn.T, Zm.T);
+}
+
+# fmla_z_zzzi.xml: FMLA (indexed) variant Half-precision
+# PATTERN x64200000/mask=xffa0fc00
+
+:fmla Zd.H, Zn.H, Zm3.H[sve_i3h_i3l]
+is sve_b_2431=0b01100100 & sve_b_23=0 & sve_i3h_22 & sve_b_21=1 & sve_i3l_1920 & sve_zm_1618 & sve_b_1115=0b00000 & sve_b_10=0 & sve_zn_0509 & sve_zda_0004 & Zd.H & Zn.H & Zm3.H & sve_i3h_i3l
+{
+ Zd.H = SVE_fmla(Zd.H, Zn.H, Zm3.H, sve_i3h_i3l:1);
+}
+
+# fmla_z_zzzi.xml: FMLA (indexed) variant Single-precision
+# PATTERN x64a00000/mask=xffe0fc00
+
+:fmla Zd.S, Zn.S, Zm3.S[sve_i2_1920]
+is sve_b_2431=0b01100100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_i2_1920 & sve_zm_1618 & sve_b_1115=0b00000 & sve_b_10=0 & sve_zn_0509 & sve_zda_0004 & Zd.S & Zn.S & Zm3.S
+{
+ Zd.S = SVE_fmla(Zd.S, Zn.S, Zm3.S, sve_i2_1920:1);
+}
+
+# fmla_z_zzzi.xml: FMLA (indexed) variant Double-precision
+# PATTERN x64e00000/mask=xffe0fc00
+
+:fmla Zd.D, Zn.D, Zm4.D[sve_i1_20]
+is sve_b_2431=0b01100100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_i1_20 & sve_zm_1619 & sve_b_1115=0b00000 & sve_b_10=0 & sve_zn_0509 & sve_zda_0004 & Zd.D & Zn.D & Zm4.D
+{
+ Zd.D = SVE_fmla(Zd.D, Zn.D, Zm4.D, sve_i1_20:1);
+}
+
+# fmls_z_p_zzz.xml: FMLS (vectors) variant SVE
+# PATTERN x65202000/mask=xff20e000
+
+:fmls Zd.T, Pg3_m, Zn.T, Zm.T
+is sve_b_2431=0b01100101 & sve_size_2223 & sve_b_21=1 & sve_zm_1620 & sve_b_15=0 & sve_b_14=0 & sve_b_13=1 & sve_pg_1012 & sve_zn_0509 & sve_zda_0004 & Zd.T & Zm.T & Zn.T & Pg3_m
+{
+ Zd.T = SVE_fmls(Zd.T, Pg3_m, Zn.T, Zm.T);
+}
+
+# fmls_z_zzzi.xml: FMLS (indexed) variant Half-precision
+# PATTERN x64200400/mask=xffa0fc00
+
+:fmls Zd.H, Zn.H, Zm3.H[sve_i3h_i3l]
+is sve_b_2431=0b01100100 & sve_b_23=0 & sve_i3h_22 & sve_b_21=1 & sve_i3l_1920 & sve_zm_1618 & sve_b_1115=0b00000 & sve_b_10=1 & sve_zn_0509 & sve_zda_0004 & Zd.H & Zn.H & Zm3.H & sve_i3h_i3l
+{
+ Zd.H = SVE_fmls(Zd.H, Zn.H, Zm3.H, sve_i3h_i3l:1);
+}
+
+# fmls_z_zzzi.xml: FMLS (indexed) variant Single-precision
+# PATTERN x64a00400/mask=xffe0fc00
+
+:fmls Zd.S, Zn.S, Zm3.S[sve_i2_1920]
+is sve_b_2431=0b01100100 & sve_b_23=1 & sve_b_22=0 & sve_b_21=1 & sve_i2_1920 & sve_zm_1618 & sve_b_1115=0b00000 & sve_b_10=1 & sve_zn_0509 & sve_zda_0004 & Zd.S & Zn.S & Zm3.S
+{
+ Zd.S = SVE_fmls(Zd.S, Zn.S, Zm3.S, sve_i2_1920:1);
+}
+
+# fmls_z_zzzi.xml: FMLS (indexed) variant Double-precision
+# PATTERN x64e00400/mask=xffe0fc00
+
+:fmls Zd.D, Zn.D, Zm4.D[sve_i1_20]
+is sve_b_2431=0b01100100 & sve_b_23=1 & sve_b_22=1 & sve_b_21=1 & sve_i1_20 & sve_zm_1619 & sve_b_1115=0b00000 & sve_b_10=1 & sve_zn_0509 & sve_zda_0004 & Zd.D & Zn.D & Zm4.D
+{
+ Zd.D = SVE_fmls(Zd.D, Zn.D, Zm4.D, sve_i1_20:1);
+}
+
+# fmov_cpy_z_p_i.xml: FMOV (zero, predicated) variant SVE
+# ALIASEDBY CPY ., /M, #0 if Never
+# PATTERN x05104000/mask=xff30ffe0
+
+:fmov Zd.T, Pm_m, "#0.0"
+is sve_b_2431=0b00000101 & sve_size_2223 & sve_b_2021=0b01 & sve_pg_1619 & sve_b_15=0 & sve_m_14=1 & sve_sh_13=0 & sve_imm8_0512=0b00000000 & sve_zd_0004 & Zd.T & Pm_m
+{
+ Zd.T = SVE_fmov(Zd.T, Pm_m);
+}
+
+# fmov_dup_z_i.xml: FMOV (zero, unpredicated) variant SVE
+# ALIASEDBY DUP ., #0 if Never
+# PATTERN x2538c000/mask=xff3fffe0
+
+:fmov Zd.T, "#0.0"
+is sve_b_2431=0b00100101 & sve_size_2223 & sve_b_1921=0b111 & sve_b_18=0 & sve_b_17=0 & sve_b_1416=0b011 & sve_sh_13=0 & sve_imm8_0512=0b00000000 & sve_zd_0004 & Zd.T
+{
+ Zd.T = SVE_fmov(Zd.T);
+}
+
+# fmov_fcpy_z_p_i.xml: FMOV (immediate, predicated) variant SVE
+# ALIASEDBY FCPY .